Mercurial > mplayer.hg
annotate drivers/mga_vid.c @ 3347:21af9f3d5372
Minor fixes
author | nick |
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date | Thu, 06 Dec 2001 10:21:02 +0000 |
parents | d62aa0b7fd68 |
children | 72d8a4d0de18 |
rev | line source |
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2345 | 1 //#define CRTC2 |
2 | |
1 | 3 // YUY2 support (see config.format) added by A'rpi/ESP-team |
57 | 4 // double buffering added by A'rpi/ESP-team |
5 | |
6 // Set this value, if autodetection fails! (video ram size in megabytes) | |
91 | 7 // #define MGA_MEMORY_SIZE 16 |
1 | 8 |
68 | 9 //#define MGA_ALLOW_IRQ |
10 | |
11 #define MGA_VSYNC_POS 2 | |
12 | |
1 | 13 /* |
14 * | |
15 * mga_vid.c | |
16 * | |
17 * Copyright (C) 1999 Aaron Holtzman | |
18 * | |
19 * Module skeleton based on gutted agpgart module by Jeff Hartmann | |
20 * <slicer@ionet.net> | |
21 * | |
22 * Matrox MGA G200/G400 YUV Video Interface module Version 0.1.0 | |
23 * | |
24 * BES == Back End Scaler | |
25 * | |
26 * This software has been released under the terms of the GNU Public | |
27 * license. See http://www.gnu.org/copyleft/gpl.html for details. | |
28 */ | |
29 | |
30 //It's entirely possible this major conflicts with something else | |
31 /* mknod /dev/mga_vid c 178 0 */ | |
32 | |
33 #include <linux/config.h> | |
34 #include <linux/version.h> | |
35 #include <linux/module.h> | |
36 #include <linux/types.h> | |
37 #include <linux/kernel.h> | |
38 #include <linux/sched.h> | |
39 #include <linux/mm.h> | |
40 #include <linux/string.h> | |
41 #include <linux/errno.h> | |
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42 |
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43 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,10) |
1 | 44 #include <linux/malloc.h> |
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45 #else |
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46 #include <linux/slab.h> |
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47 #endif |
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48 |
1 | 49 #include <linux/pci.h> |
63 | 50 #include <linux/ioport.h> |
1 | 51 #include <linux/init.h> |
52 | |
53 #include "mga_vid.h" | |
54 | |
55 #ifdef CONFIG_MTRR | |
56 #include <asm/mtrr.h> | |
57 #endif | |
58 | |
59 #include <asm/uaccess.h> | |
60 #include <asm/system.h> | |
61 #include <asm/io.h> | |
62 | |
63 #define TRUE 1 | |
64 #define FALSE 0 | |
65 | |
66 #define MGA_VID_MAJOR 178 | |
67 | |
57 | 68 //#define MGA_VIDMEM_SIZE mga_ram_size |
1 | 69 |
70 #ifndef PCI_DEVICE_ID_MATROX_G200_PCI | |
71 #define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520 | |
72 #endif | |
73 | |
74 #ifndef PCI_DEVICE_ID_MATROX_G200_AGP | |
75 #define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521 | |
76 #endif | |
77 | |
78 #ifndef PCI_DEVICE_ID_MATROX_G400 | |
79 #define PCI_DEVICE_ID_MATROX_G400 0x0525 | |
80 #endif | |
81 | |
1989 | 82 #ifndef PCI_DEVICE_ID_MATROX_G550 |
83 #define PCI_DEVICE_ID_MATROX_G550 0x2527 | |
84 #endif | |
85 | |
1 | 86 MODULE_AUTHOR("Aaron Holtzman <aholtzma@engr.uvic.ca>"); |
2262 | 87 #ifdef MODULE_LICENSE |
88 MODULE_LICENSE("GPL"); | |
89 #endif | |
1 | 90 |
91 typedef struct bes_registers_s | |
92 { | |
93 //BES Control | |
94 uint32_t besctl; | |
95 //BES Global control | |
96 uint32_t besglobctl; | |
97 //Luma control (brightness and contrast) | |
98 uint32_t beslumactl; | |
99 //Line pitch | |
100 uint32_t bespitch; | |
101 | |
102 //Buffer A-1 Chroma 3 plane org | |
103 uint32_t besa1c3org; | |
104 //Buffer A-1 Chroma org | |
105 uint32_t besa1corg; | |
106 //Buffer A-1 Luma org | |
107 uint32_t besa1org; | |
108 | |
109 //Buffer A-2 Chroma 3 plane org | |
110 uint32_t besa2c3org; | |
111 //Buffer A-2 Chroma org | |
112 uint32_t besa2corg; | |
113 //Buffer A-2 Luma org | |
114 uint32_t besa2org; | |
115 | |
116 //Buffer B-1 Chroma 3 plane org | |
117 uint32_t besb1c3org; | |
118 //Buffer B-1 Chroma org | |
119 uint32_t besb1corg; | |
120 //Buffer B-1 Luma org | |
121 uint32_t besb1org; | |
122 | |
123 //Buffer B-2 Chroma 3 plane org | |
124 uint32_t besb2c3org; | |
125 //Buffer B-2 Chroma org | |
126 uint32_t besb2corg; | |
127 //Buffer B-2 Luma org | |
128 uint32_t besb2org; | |
129 | |
130 //BES Horizontal coord | |
131 uint32_t beshcoord; | |
132 //BES Horizontal inverse scaling [5.14] | |
133 uint32_t beshiscal; | |
134 //BES Horizontal source start [10.14] (for scaling) | |
135 uint32_t beshsrcst; | |
136 //BES Horizontal source ending [10.14] (for scaling) | |
137 uint32_t beshsrcend; | |
138 //BES Horizontal source last | |
139 uint32_t beshsrclst; | |
140 | |
141 | |
142 //BES Vertical coord | |
143 uint32_t besvcoord; | |
144 //BES Vertical inverse scaling [5.14] | |
145 uint32_t besviscal; | |
146 //BES Field 1 vertical source last position | |
147 uint32_t besv1srclst; | |
148 //BES Field 1 weight start | |
149 uint32_t besv1wght; | |
150 //BES Field 2 vertical source last position | |
151 uint32_t besv2srclst; | |
152 //BES Field 2 weight start | |
153 uint32_t besv2wght; | |
154 | |
155 } bes_registers_t; | |
156 | |
157 static bes_registers_t regs; | |
2344 | 158 #ifdef CRTC2 |
159 typedef struct crtc2_registers_s | |
160 { | |
161 uint32_t c2ctl; | |
162 uint32_t c2datactl; | |
163 uint32_t c2misc; | |
164 uint32_t c2hparam; | |
165 uint32_t c2hsync; | |
166 uint32_t c2offset; | |
167 uint32_t c2pl2startadd0; | |
168 uint32_t c2pl2startadd1; | |
169 uint32_t c2pl3startadd0; | |
170 uint32_t c2pl3startadd1; | |
171 uint32_t c2preload; | |
172 uint32_t c2spicstartadd0; | |
173 uint32_t c2spicstartadd1; | |
174 uint32_t c2startadd0; | |
175 uint32_t c2startadd1; | |
176 uint32_t c2subpiclut; | |
177 uint32_t c2vcount; | |
178 uint32_t c2vparam; | |
179 uint32_t c2vsync; | |
180 } crtc2_registers_t; | |
181 static crtc2_registers_t cregs; | |
182 #endif | |
1 | 183 static uint32_t mga_vid_in_use = 0; |
184 static uint32_t is_g400 = 0; | |
185 static uint32_t vid_src_ready = 0; | |
186 static uint32_t vid_overlay_on = 0; | |
187 | |
188 static uint8_t *mga_mmio_base = 0; | |
189 static uint32_t mga_mem_base = 0; | |
190 | |
57 | 191 static int mga_src_base = 0; // YUV buffer position in video memory |
192 | |
193 static uint32_t mga_ram_size = 0; // how much megabytes videoram we have | |
1 | 194 |
95 | 195 //static int mga_force_memsize = 0; |
90 | 196 |
95 | 197 MODULE_PARM(mga_ram_size, "i"); |
90 | 198 |
1 | 199 static struct pci_dev *pci_dev; |
200 | |
201 static mga_vid_config_t mga_config; | |
202 | |
2086 | 203 static int colkey_saved=0; |
204 static int colkey_on=0; | |
205 static unsigned char colkey_color[4]; | |
206 static unsigned char colkey_mask[4]; | |
207 | |
48 | 208 static int mga_irq = -1; |
1 | 209 |
210 //All register offsets are converted to word aligned offsets (32 bit) | |
211 //because we want all our register accesses to be 32 bits | |
212 #define VCOUNT 0x1e20 | |
213 | |
214 #define PALWTADD 0x3c00 // Index register for X_DATAREG port | |
215 #define X_DATAREG 0x3c0a | |
216 | |
217 #define XMULCTRL 0x19 | |
218 #define BPP_8 0x00 | |
219 #define BPP_15 0x01 | |
220 #define BPP_16 0x02 | |
221 #define BPP_24 0x03 | |
222 #define BPP_32_DIR 0x04 | |
223 #define BPP_32_PAL 0x07 | |
224 | |
225 #define XCOLMSK 0x40 | |
226 #define X_COLKEY 0x42 | |
227 #define XKEYOPMODE 0x51 | |
228 #define XCOLMSK0RED 0x52 | |
229 #define XCOLMSK0GREEN 0x53 | |
230 #define XCOLMSK0BLUE 0x54 | |
231 #define XCOLKEY0RED 0x55 | |
232 #define XCOLKEY0GREEN 0x56 | |
233 #define XCOLKEY0BLUE 0x57 | |
234 | |
2344 | 235 #ifdef CRTC2 |
236 | |
237 /*CRTC2 registers*/ | |
238 #define XMISCCTRL 0x1e | |
239 #define C2CTL 0x3c10 | |
240 #define C2DATACTL 0x3c4c | |
241 #define C2MISC 0x3c44 | |
242 #define C2HPARAM 0x3c14 | |
243 #define C2HSYNC 0x3c18 | |
244 #define C2OFFSET 0x3c40 | |
245 #define C2PL2STARTADD0 0x3c30 // like BESA1CORG | |
246 #define C2PL2STARTADD1 0x3c34 // like BESA2CORG | |
247 #define C2PL3STARTADD0 0x3c38 // like BESA1C3ORG | |
248 #define C2PL3STARTADD1 0x3c3c // like BESA2C3ORG | |
249 #define C2PRELOAD 0x3c24 | |
250 #define C2SPICSTARTADD0 0x3c54 | |
251 #define C2SPICSTARTADD1 0x3c58 | |
252 #define C2STARTADD0 0x3c28 // like BESA1ORG | |
253 #define C2STARTADD1 0x3c2c // like BESA2ORG | |
254 #define C2SUBPICLUT 0x3c50 | |
255 #define C2VCOUNT 0x3c48 | |
256 #define C2VPARAM 0x3c1c | |
257 #define C2VSYNC 0x3c20 | |
258 | |
259 #endif | |
260 | |
1 | 261 // Backend Scaler registers |
262 #define BESCTL 0x3d20 | |
263 #define BESGLOBCTL 0x3dc0 | |
264 #define BESLUMACTL 0x3d40 | |
265 #define BESPITCH 0x3d24 | |
48 | 266 |
1 | 267 #define BESA1C3ORG 0x3d60 |
268 #define BESA1CORG 0x3d10 | |
269 #define BESA1ORG 0x3d00 | |
48 | 270 |
1 | 271 #define BESA2C3ORG 0x3d64 |
272 #define BESA2CORG 0x3d14 | |
273 #define BESA2ORG 0x3d04 | |
48 | 274 |
1 | 275 #define BESB1C3ORG 0x3d68 |
276 #define BESB1CORG 0x3d18 | |
277 #define BESB1ORG 0x3d08 | |
48 | 278 |
1 | 279 #define BESB2C3ORG 0x3d6C |
280 #define BESB2CORG 0x3d1C | |
281 #define BESB2ORG 0x3d0C | |
48 | 282 |
1 | 283 #define BESHCOORD 0x3d28 |
284 #define BESHISCAL 0x3d30 | |
285 #define BESHSRCEND 0x3d3C | |
286 #define BESHSRCLST 0x3d50 | |
287 #define BESHSRCST 0x3d38 | |
288 #define BESV1WGHT 0x3d48 | |
289 #define BESV2WGHT 0x3d4c | |
290 #define BESV1SRCLST 0x3d54 | |
291 #define BESV2SRCLST 0x3d58 | |
292 #define BESVISCAL 0x3d34 | |
293 #define BESVCOORD 0x3d2c | |
294 #define BESSTATUS 0x3dc4 | |
295 | |
48 | 296 #define CRTCX 0x1fd4 |
297 #define CRTCD 0x1fd5 | |
298 #define IEN 0x1e1c | |
299 #define ICLEAR 0x1e18 | |
300 #define STATUS 0x1e14 | |
301 | |
302 static int mga_next_frame=0; | |
1 | 303 |
2344 | 304 #ifdef CRTC2 |
305 static void crtc2_frame_sel(int frame) | |
306 { | |
307 switch(frame) { | |
308 case 0: | |
309 cregs.c2pl2startadd0=regs.besa1corg; | |
310 cregs.c2pl3startadd0=regs.besa1c3org; | |
311 cregs.c2startadd0=regs.besa1org; | |
312 break; | |
313 case 1: | |
314 cregs.c2pl2startadd0=regs.besa2corg; | |
315 cregs.c2pl3startadd0=regs.besa2c3org; | |
316 cregs.c2startadd0=regs.besa2org; | |
317 break; | |
318 case 2: | |
319 cregs.c2pl2startadd0=regs.besb1corg; | |
320 cregs.c2pl3startadd0=regs.besb1c3org; | |
321 cregs.c2startadd0=regs.besb1org; | |
322 break; | |
323 case 3: | |
324 cregs.c2pl2startadd0=regs.besb2corg; | |
325 cregs.c2pl3startadd0=regs.besb2c3org; | |
326 cregs.c2startadd0=regs.besb2org; | |
327 break; | |
328 } | |
329 writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0); | |
330 writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0); | |
331 writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0); | |
332 } | |
333 #endif | |
334 | |
1 | 335 static void mga_vid_frame_sel(int frame) |
336 { | |
48 | 337 if ( mga_irq != -1 ) { |
338 mga_next_frame=frame; | |
339 } else { | |
340 | |
1 | 341 //we don't need the vcount protection as we're only hitting |
342 //one register (and it doesn't seem to be double buffered) | |
343 regs.besctl = (regs.besctl & ~0x07000000) + (frame << 25); | |
344 writel( regs.besctl, mga_mmio_base + BESCTL ); | |
68 | 345 |
346 // writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), | |
347 writel( regs.besglobctl + (MGA_VSYNC_POS<<16), | |
348 mga_mmio_base + BESGLOBCTL); | |
2344 | 349 #ifdef CRTC2 |
350 crtc2_frame_sel(frame); | |
351 #endif | |
68 | 352 |
48 | 353 } |
1 | 354 } |
355 | |
356 | |
2086 | 357 static void mga_vid_write_regs(int restore) |
1 | 358 { |
359 //Make sure internal registers don't get updated until we're done | |
360 writel( (readl(mga_mmio_base + VCOUNT)-1)<<16, | |
361 mga_mmio_base + BESGLOBCTL); | |
362 | |
363 // color or coordinate keying | |
2086 | 364 |
365 if(restore && colkey_saved){ | |
366 // restore it | |
367 colkey_saved=0; | |
368 | |
369 printk("mga_vid: Restoring colorkey (ON: %d %02X:%02X:%02X)\n", | |
370 colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]); | |
371 | |
372 // Set color key registers: | |
373 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); | |
374 writeb( colkey_on, mga_mmio_base + X_DATAREG); | |
375 | |
376 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); | |
377 writeb( colkey_color[0], mga_mmio_base + X_DATAREG); | |
378 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); | |
379 writeb( colkey_color[1], mga_mmio_base + X_DATAREG); | |
380 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); | |
381 writeb( colkey_color[2], mga_mmio_base + X_DATAREG); | |
382 writeb( X_COLKEY, mga_mmio_base + PALWTADD); | |
383 writeb( colkey_color[3], mga_mmio_base + X_DATAREG); | |
384 | |
385 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); | |
386 writeb( colkey_mask[0], mga_mmio_base + X_DATAREG); | |
387 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); | |
388 writeb( colkey_mask[1], mga_mmio_base + X_DATAREG); | |
389 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); | |
390 writeb( colkey_mask[2], mga_mmio_base + X_DATAREG); | |
391 writeb( XCOLMSK, mga_mmio_base + PALWTADD); | |
392 writeb( colkey_mask[3], mga_mmio_base + X_DATAREG); | |
393 | |
394 } else if(!colkey_saved){ | |
395 // save it | |
396 colkey_saved=1; | |
397 // Get color key registers: | |
398 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); | |
399 colkey_on=(unsigned char)readb(mga_mmio_base + X_DATAREG) & 1; | |
400 | |
401 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); | |
402 colkey_color[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
403 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); | |
404 colkey_color[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
405 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); | |
406 colkey_color[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
407 writeb( X_COLKEY, mga_mmio_base + PALWTADD); | |
408 colkey_color[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
409 | |
410 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); | |
411 colkey_mask[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
412 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); | |
413 colkey_mask[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
414 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); | |
415 colkey_mask[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
416 writeb( XCOLMSK, mga_mmio_base + PALWTADD); | |
417 colkey_mask[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
418 | |
419 printk("mga_vid: Saved colorkey (ON: %d %02X:%02X:%02X)\n", | |
420 colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]); | |
421 | |
422 } | |
423 | |
424 if(!restore){ | |
1 | 425 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); |
426 writeb( mga_config.colkey_on, mga_mmio_base + X_DATAREG); | |
427 if ( mga_config.colkey_on ) | |
428 { | |
429 uint32_t r=0, g=0, b=0; | |
430 | |
431 writeb( XMULCTRL, mga_mmio_base + PALWTADD); | |
432 switch (readb (mga_mmio_base + X_DATAREG)) | |
433 { | |
434 case BPP_8: | |
435 /* Need to look up the color index, just using | |
436 color 0 for now. */ | |
437 break; | |
438 | |
439 case BPP_15: | |
440 r = mga_config.colkey_red >> 3; | |
441 g = mga_config.colkey_green >> 3; | |
442 b = mga_config.colkey_blue >> 3; | |
443 break; | |
444 | |
445 case BPP_16: | |
446 r = mga_config.colkey_red >> 3; | |
447 g = mga_config.colkey_green >> 2; | |
448 b = mga_config.colkey_blue >> 3; | |
449 break; | |
450 | |
451 case BPP_24: | |
452 case BPP_32_DIR: | |
453 case BPP_32_PAL: | |
454 r = mga_config.colkey_red; | |
455 g = mga_config.colkey_green; | |
456 b = mga_config.colkey_blue; | |
457 break; | |
458 } | |
459 | |
460 // Disable color keying on alpha channel | |
461 writeb( XCOLMSK, mga_mmio_base + PALWTADD); | |
462 writeb( 0x00, mga_mmio_base + X_DATAREG); | |
463 writeb( X_COLKEY, mga_mmio_base + PALWTADD); | |
464 writeb( 0x00, mga_mmio_base + X_DATAREG); | |
465 | |
2086 | 466 |
1 | 467 // Set up color key registers |
468 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); | |
469 writeb( r, mga_mmio_base + X_DATAREG); | |
470 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); | |
471 writeb( g, mga_mmio_base + X_DATAREG); | |
472 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); | |
473 writeb( b, mga_mmio_base + X_DATAREG); | |
474 | |
475 // Set up color key mask registers | |
476 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); | |
477 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
478 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); | |
479 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
480 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); | |
481 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
482 } | |
483 | |
2086 | 484 } |
485 | |
1 | 486 // Backend Scaler |
487 writel( regs.besctl, mga_mmio_base + BESCTL); | |
488 if(is_g400) | |
489 writel( regs.beslumactl, mga_mmio_base + BESLUMACTL); | |
490 writel( regs.bespitch, mga_mmio_base + BESPITCH); | |
491 | |
492 writel( regs.besa1org, mga_mmio_base + BESA1ORG); | |
493 writel( regs.besa1corg, mga_mmio_base + BESA1CORG); | |
48 | 494 writel( regs.besa2org, mga_mmio_base + BESA2ORG); |
495 writel( regs.besa2corg, mga_mmio_base + BESA2CORG); | |
1 | 496 writel( regs.besb1org, mga_mmio_base + BESB1ORG); |
497 writel( regs.besb1corg, mga_mmio_base + BESB1CORG); | |
48 | 498 writel( regs.besb2org, mga_mmio_base + BESB2ORG); |
499 writel( regs.besb2corg, mga_mmio_base + BESB2CORG); | |
1 | 500 if(is_g400) |
501 { | |
502 writel( regs.besa1c3org, mga_mmio_base + BESA1C3ORG); | |
48 | 503 writel( regs.besa2c3org, mga_mmio_base + BESA2C3ORG); |
1 | 504 writel( regs.besb1c3org, mga_mmio_base + BESB1C3ORG); |
48 | 505 writel( regs.besb2c3org, mga_mmio_base + BESB2C3ORG); |
1 | 506 } |
507 | |
508 writel( regs.beshcoord, mga_mmio_base + BESHCOORD); | |
509 writel( regs.beshiscal, mga_mmio_base + BESHISCAL); | |
510 writel( regs.beshsrcst, mga_mmio_base + BESHSRCST); | |
511 writel( regs.beshsrcend, mga_mmio_base + BESHSRCEND); | |
512 writel( regs.beshsrclst, mga_mmio_base + BESHSRCLST); | |
513 | |
514 writel( regs.besvcoord, mga_mmio_base + BESVCOORD); | |
515 writel( regs.besviscal, mga_mmio_base + BESVISCAL); | |
48 | 516 |
1 | 517 writel( regs.besv1srclst, mga_mmio_base + BESV1SRCLST); |
518 writel( regs.besv1wght, mga_mmio_base + BESV1WGHT); | |
48 | 519 writel( regs.besv2srclst, mga_mmio_base + BESV2SRCLST); |
520 writel( regs.besv2wght, mga_mmio_base + BESV2WGHT); | |
1 | 521 |
522 //update the registers somewhere between 1 and 2 frames from now. | |
523 writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), | |
524 mga_mmio_base + BESGLOBCTL); | |
525 | |
77 | 526 #if 0 |
61 | 527 printk(KERN_DEBUG "mga_vid: wrote BES registers\n"); |
528 printk(KERN_DEBUG "mga_vid: BESCTL = 0x%08x\n", | |
1 | 529 readl(mga_mmio_base + BESCTL)); |
61 | 530 printk(KERN_DEBUG "mga_vid: BESGLOBCTL = 0x%08x\n", |
1 | 531 readl(mga_mmio_base + BESGLOBCTL)); |
61 | 532 printk(KERN_DEBUG "mga_vid: BESSTATUS= 0x%08x\n", |
1 | 533 readl(mga_mmio_base + BESSTATUS)); |
77 | 534 #endif |
2344 | 535 #ifdef CRTC2 |
536 // printk("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL)); | |
537 // printk("c2misc:0x%08x\n",readl(mga_mmio_base + C2MISC)); | |
538 // printk("c2ctl:0x%08x c2datactl:0x%08x\n",cregs.c2ctl,cregs.c2datactl); | |
539 | |
540 // writel(cregs.c2ctl, mga_mmio_base + C2CTL); | |
541 | |
542 writel(((readl(mga_mmio_base + C2CTL) & ~0x03e00000) + (cregs.c2ctl & 0x03e00000)), mga_mmio_base + C2CTL); | |
543 writel(((readl(mga_mmio_base + C2DATACTL) & ~0x000000ff) + (cregs.c2datactl & 0x000000ff)), mga_mmio_base + C2DATACTL); | |
544 // ctrc2 | |
545 // disable CRTC2 acording to specs | |
546 // writel(cregs.c2ctl & 0xfffffff0, mga_mmio_base + C2CTL); | |
547 // je to treba ??? | |
548 // writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0xa2, mga_mmio_base + XMISCCTRL); // MAFC - mfcsel & vdoutsel | |
549 // writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0x92, mga_mmio_base + XMISCCTRL); | |
550 // writeb((readb(mga_mmio_base + XMISCCTRL) & ~0xe9) + 0xa2, mga_mmio_base + XMISCCTRL); | |
551 // writel(cregs.c2datactl, mga_mmio_base + C2DATACTL); | |
552 // writel(cregs.c2hparam, mga_mmio_base + C2HPARAM); | |
553 // writel(cregs.c2hsync, mga_mmio_base + C2HSYNC); | |
554 // writel(cregs.c2vparam, mga_mmio_base + C2VPARAM); | |
555 // writel(cregs.c2vsync, mga_mmio_base + C2VSYNC); | |
556 writel(cregs.c2misc, mga_mmio_base + C2MISC); | |
557 | |
558 printk("c2offset = %d\n",cregs.c2offset); | |
559 | |
560 writel(cregs.c2offset, mga_mmio_base + C2OFFSET); | |
561 writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0); | |
562 // writel(cregs.c2startadd1, mga_mmio_base + C2STARTADD1); | |
563 writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0); | |
564 // writel(cregs.c2pl2startadd1, mga_mmio_base + C2PL2STARTADD1); | |
565 writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0); | |
566 // writel(cregs.c2pl3startadd1, mga_mmio_base + C2PL3STARTADD1); | |
567 writel(cregs.c2spicstartadd0, mga_mmio_base + C2SPICSTARTADD0); | |
568 // writel(cregs.c2spicstartadd1, mga_mmio_base + C2SPICSTARTADD1); | |
569 // writel(cregs.c2subpiclut, mga_mmio_base + C2SUBPICLUT); | |
570 // writel(cregs.c2preload, mga_mmio_base + C2PRELOAD); | |
571 // finaly enable everything | |
572 // writel(cregs.c2ctl, mga_mmio_base + C2CTL); | |
573 // printk("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL)); | |
574 // printk("c2misc:0x%08x\n", readl(mga_mmio_base + C2MISC)); | |
575 #endif | |
1 | 576 } |
577 | |
578 static int mga_vid_set_config(mga_vid_config_t *config) | |
579 { | |
580 int x, y, sw, sh, dw, dh; | |
581 int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights; | |
57 | 582 int frame_size=config->frame_size; |
2344 | 583 #ifdef CRTC2 |
584 #define right_margin 0 | |
585 #define left_margin 18 | |
586 #define hsync_len 46 | |
587 #define lower_margin 10 | |
588 #define vsync_len 4 | |
589 #define upper_margin 39 | |
590 | |
591 unsigned int hdispend = (config->src_width + 31) & ~31; | |
592 unsigned int hsyncstart = hdispend + (right_margin & ~7); | |
593 unsigned int hsyncend = hsyncstart + (hsync_len & ~7); | |
594 unsigned int htotal = hsyncend + (left_margin & ~7); | |
595 unsigned int vdispend = config->src_height; | |
596 unsigned int vsyncstart = vdispend + lower_margin; | |
597 unsigned int vsyncend = vsyncstart + vsync_len; | |
598 unsigned int vtotal = vsyncend + upper_margin; | |
599 #endif | |
1 | 600 x = config->x_org; |
601 y = config->y_org; | |
602 sw = config->src_width; | |
603 sh = config->src_height; | |
604 dw = config->dest_width; | |
605 dh = config->dest_height; | |
606 | |
61 | 607 printk(KERN_DEBUG "mga_vid: Setting up a %dx%d+%d+%d video window (src %dx%d) format %X\n", |
1 | 608 dw, dh, x, y, sw, sh, config->format); |
609 | |
610 //FIXME check that window is valid and inside desktop | |
611 | |
612 //FIXME figure out a better way to allocate memory on card | |
613 //allocate 2 megs | |
614 //mga_src_base = mga_mem_base + (MGA_VIDMEM_SIZE-2) * 0x100000; | |
57 | 615 //mga_src_base = (MGA_VIDMEM_SIZE-3) * 0x100000; |
1 | 616 |
617 | |
618 //Setup the BES registers for a three plane 4:2:0 video source | |
619 | |
466 | 620 regs.besglobctl = 0; |
621 | |
1 | 622 switch(config->format){ |
623 case MGA_VID_FORMAT_YV12: | |
470 | 624 case MGA_VID_FORMAT_I420: |
625 case MGA_VID_FORMAT_IYUV: | |
1 | 626 regs.besctl = 1 // BES enabled |
627 + (0<<6) // even start polarity | |
628 + (1<<10) // x filtering enabled | |
629 + (1<<11) // y filtering enabled | |
630 + (1<<16) // chroma upsampling | |
631 + (1<<17) // 4:2:0 mode | |
632 + (1<<18); // dither enabled | |
466 | 633 #if 0 |
1 | 634 if(is_g400) |
635 { | |
636 //zoom disabled, zoom filter disabled, 420 3 plane format, proc amp | |
637 //disabled, rgb mode disabled | |
638 regs.besglobctl = (1<<5); | |
639 } | |
640 else | |
641 { | |
642 //zoom disabled, zoom filter disabled, Cb samples in 0246, Cr | |
643 //in 1357, BES register update on besvcnt | |
466 | 644 regs.besglobctl = 0; |
1 | 645 } |
466 | 646 #endif |
1 | 647 break; |
648 | |
649 case MGA_VID_FORMAT_YUY2: | |
650 regs.besctl = 1 // BES enabled | |
651 + (0<<6) // even start polarity | |
652 + (1<<10) // x filtering enabled | |
653 + (1<<11) // y filtering enabled | |
654 + (1<<16) // chroma upsampling | |
655 + (0<<17) // 4:2:2 mode | |
656 + (1<<18); // dither enabled | |
657 | |
658 regs.besglobctl = 0; // YUY2 format selected | |
659 break; | |
466 | 660 |
661 case MGA_VID_FORMAT_UYVY: | |
662 regs.besctl = 1 // BES enabled | |
663 + (0<<6) // even start polarity | |
664 + (1<<10) // x filtering enabled | |
665 + (1<<11) // y filtering enabled | |
666 + (1<<16) // chroma upsampling | |
667 + (0<<17) // 4:2:2 mode | |
668 + (1<<18); // dither enabled | |
669 | |
670 regs.besglobctl = 1<<6; // UYVY format selected | |
671 break; | |
672 | |
1 | 673 default: |
61 | 674 printk(KERN_ERR "mga_vid: Unsupported pixel format: 0x%X\n",config->format); |
1 | 675 return -1; |
676 } | |
677 | |
678 | |
679 //Disable contrast and brightness control | |
466 | 680 regs.besglobctl |= (1<<5) + (1<<7); |
1 | 681 regs.beslumactl = (0x7f << 16) + (0x80<<0); |
682 regs.beslumactl = 0x80<<0; | |
683 | |
684 //Setup destination window boundaries | |
685 besleft = x > 0 ? x : 0; | |
686 bestop = y > 0 ? y : 0; | |
687 regs.beshcoord = (besleft<<16) + (x + dw-1); | |
688 regs.besvcoord = (bestop<<16) + (y + dh-1); | |
689 | |
690 //Setup source dimensions | |
691 regs.beshsrclst = (sw - 1) << 16; | |
692 regs.bespitch = (sw + 31) & ~31 ; | |
693 | |
694 //Setup horizontal scaling | |
695 ifactor = ((sw-1)<<14)/(dw-1); | |
696 ofsleft = besleft - x; | |
697 | |
698 regs.beshiscal = ifactor<<2; | |
699 regs.beshsrcst = (ofsleft*ifactor)<<2; | |
700 regs.beshsrcend = regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2); | |
701 | |
702 //Setup vertical scaling | |
703 ifactor = ((sh-1)<<14)/(dh-1); | |
704 ofstop = bestop - y; | |
705 | |
706 regs.besviscal = ifactor<<2; | |
707 | |
708 baseadrofs = ((ofstop*regs.besviscal)>>16)*regs.bespitch; | |
57 | 709 //frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2; |
1 | 710 regs.besa1org = (uint32_t) mga_src_base + baseadrofs; |
48 | 711 regs.besa2org = (uint32_t) mga_src_base + baseadrofs + 1*frame_size; |
712 regs.besb1org = (uint32_t) mga_src_base + baseadrofs + 2*frame_size; | |
713 regs.besb2org = (uint32_t) mga_src_base + baseadrofs + 3*frame_size; | |
1 | 714 |
470 | 715 if(config->format==MGA_VID_FORMAT_YV12 |
716 ||config->format==MGA_VID_FORMAT_IYUV | |
717 ||config->format==MGA_VID_FORMAT_I420 | |
718 ){ | |
57 | 719 // planar YUV frames: |
1 | 720 if (is_g400) |
721 baseadrofs = (((ofstop*regs.besviscal)/4)>>16)*regs.bespitch; | |
722 else | |
723 baseadrofs = (((ofstop*regs.besviscal)/2)>>16)*regs.bespitch; | |
724 | |
470 | 725 if(config->format==MGA_VID_FORMAT_YV12){ |
1 | 726 regs.besa1corg = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; |
48 | 727 regs.besa2corg = (uint32_t) mga_src_base + baseadrofs + 1*frame_size + regs.bespitch * sh; |
728 regs.besb1corg = (uint32_t) mga_src_base + baseadrofs + 2*frame_size + regs.bespitch * sh; | |
729 regs.besb2corg = (uint32_t) mga_src_base + baseadrofs + 3*frame_size + regs.bespitch * sh; | |
1 | 730 regs.besa1c3org = regs.besa1corg + ((regs.bespitch * sh) / 4); |
48 | 731 regs.besa2c3org = regs.besa2corg + ((regs.bespitch * sh) / 4); |
1 | 732 regs.besb1c3org = regs.besb1corg + ((regs.bespitch * sh) / 4); |
48 | 733 regs.besb2c3org = regs.besb2corg + ((regs.bespitch * sh) / 4); |
470 | 734 } else { |
735 regs.besa1c3org = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; | |
736 regs.besa2c3org = (uint32_t) mga_src_base + baseadrofs + 1*frame_size + regs.bespitch * sh; | |
737 regs.besb1c3org = (uint32_t) mga_src_base + baseadrofs + 2*frame_size + regs.bespitch * sh; | |
738 regs.besb2c3org = (uint32_t) mga_src_base + baseadrofs + 3*frame_size + regs.bespitch * sh; | |
739 regs.besa1corg = regs.besa1c3org + ((regs.bespitch * sh) / 4); | |
740 regs.besa2corg = regs.besa2c3org + ((regs.bespitch * sh) / 4); | |
741 regs.besb1corg = regs.besb1c3org + ((regs.bespitch * sh) / 4); | |
742 regs.besb2corg = regs.besb2c3org + ((regs.bespitch * sh) / 4); | |
743 } | |
744 | |
57 | 745 } |
1 | 746 |
747 weight = ofstop * (regs.besviscal >> 2); | |
748 weights = weight < 0 ? 1 : 0; | |
48 | 749 regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2); |
750 regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF); | |
1 | 751 |
2344 | 752 #ifdef CRTC2 |
753 // pridat hlavni registry - tj. casovani ... | |
754 | |
755 | |
756 switch(config->format){ | |
757 case MGA_VID_FORMAT_YV12: | |
758 case MGA_VID_FORMAT_I420: | |
759 case MGA_VID_FORMAT_IYUV: | |
760 cregs.c2ctl = 1 // CRTC2 enabled | |
761 + (1<<1) // external clock | |
762 + (0<<2) // external clock | |
763 + (1<<3) // pixel clock enable - not needed ??? | |
764 + (0<<4) // high prioryty req | |
765 + (1<<5) // high prioryty req | |
766 + (0<<6) // high prioryty req | |
767 + (1<<8) // high prioryty req max | |
768 + (0<<9) // high prioryty req max | |
769 + (0<<10) // high prioryty req max | |
770 + (0<<20) // CRTC1 to DAC | |
771 + (1<<21) // 420 mode | |
772 + (1<<22) // 420 mode | |
773 + (1<<23) // 420 mode | |
774 + (0<<24) // single chroma line for 420 mode - need to be corrected | |
775 + (0<<25) /*/ interlace mode - need to be corrected*/ | |
776 + (0<<26) // field legth polariry | |
777 + (0<<27) // field identification polariry | |
778 + (1<<28) // VIDRST detection mode | |
779 + (0<<29) // VIDRST detection mode | |
780 + (1<<30) // Horizontal counter preload | |
781 + (1<<31) // Vertical counter preload | |
782 ; | |
783 cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode | |
784 + (1<<1) // Y filter enable | |
785 + (1<<2) // CbCr filter enable | |
786 + (0<<3) // subpicture enable (disabled) | |
787 + (0<<4) // NTSC enable (disabled - PAL) | |
788 + (0<<5) // C2 static subpicture enable (disabled) | |
789 + (0<<6) // C2 subpicture offset division (disabled) | |
790 + (0<<7) // 422 subformat selection ! | |
791 /* + (0<<8) // 15 bpp high alpha | |
792 + (0<<9) // 15 bpp high alpha | |
793 + (0<<10) // 15 bpp high alpha | |
794 + (0<<11) // 15 bpp high alpha | |
795 + (0<<12) // 15 bpp high alpha | |
796 + (0<<13) // 15 bpp high alpha | |
797 + (0<<14) // 15 bpp high alpha | |
798 + (0<<15) // 15 bpp high alpha | |
799 + (0<<16) // 15 bpp low alpha | |
800 + (0<<17) // 15 bpp low alpha | |
801 + (0<<18) // 15 bpp low alpha | |
802 + (0<<19) // 15 bpp low alpha | |
803 + (0<<20) // 15 bpp low alpha | |
804 + (0<<21) // 15 bpp low alpha | |
805 + (0<<22) // 15 bpp low alpha | |
806 + (0<<23) // 15 bpp low alpha | |
807 + (0<<24) // static subpicture key | |
808 + (0<<25) // static subpicture key | |
809 + (0<<26) // static subpicture key | |
810 + (0<<27) // static subpicture key | |
811 + (0<<28) // static subpicture key | |
812 */ ; | |
813 break; | |
814 | |
815 case MGA_VID_FORMAT_YUY2: | |
816 cregs.c2ctl = 1 // CRTC2 enabled | |
817 + (1<<1) // external clock | |
818 + (0<<2) // external clock | |
819 + (1<<3) // pixel clock enable - not needed ??? | |
820 + (0<<4) // high prioryty req - acc to spec | |
821 + (1<<5) // high prioryty req | |
822 + (0<<6) // high prioryty req | |
823 // 7 reserved | |
824 + (1<<8) // high prioryty req max | |
825 + (0<<9) // high prioryty req max | |
826 + (0<<10) // high prioryty req max | |
827 // 11-19 reserved | |
828 + (0<<20) // CRTC1 to DAC | |
829 + (1<<21) // 422 mode | |
830 + (0<<22) // 422 mode | |
831 + (1<<23) // 422 mode | |
832 + (0<<24) // single chroma line for 420 mode - need to be corrected | |
833 + (0<<25) /*/ interlace mode - need to be corrected*/ | |
834 + (0<<26) // field legth polariry | |
835 + (0<<27) // field identification polariry | |
836 + (1<<28) // VIDRST detection mode | |
837 + (0<<29) // VIDRST detection mode | |
838 + (1<<30) // Horizontal counter preload | |
839 + (1<<31) // Vertical counter preload | |
840 ; | |
841 cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode | |
842 + (1<<1) // Y filter enable | |
843 + (1<<2) // CbCr filter enable | |
844 + (0<<3) // subpicture enable (disabled) | |
845 + (0<<4) // NTSC enable (disabled - PAL) | |
846 + (0<<5) // C2 static subpicture enable (disabled) | |
847 + (0<<6) // C2 subpicture offset division (disabled) | |
848 + (0<<7) // 422 subformat selection ! | |
849 /* + (0<<8) // 15 bpp high alpha | |
850 + (0<<9) // 15 bpp high alpha | |
851 + (0<<10) // 15 bpp high alpha | |
852 + (0<<11) // 15 bpp high alpha | |
853 + (0<<12) // 15 bpp high alpha | |
854 + (0<<13) // 15 bpp high alpha | |
855 + (0<<14) // 15 bpp high alpha | |
856 + (0<<15) // 15 bpp high alpha | |
857 + (0<<16) // 15 bpp low alpha | |
858 + (0<<17) // 15 bpp low alpha | |
859 + (0<<18) // 15 bpp low alpha | |
860 + (0<<19) // 15 bpp low alpha | |
861 + (0<<20) // 15 bpp low alpha | |
862 + (0<<21) // 15 bpp low alpha | |
863 + (0<<22) // 15 bpp low alpha | |
864 + (0<<23) // 15 bpp low alpha | |
865 + (0<<24) // static subpicture key | |
866 + (0<<25) // static subpicture key | |
867 + (0<<26) // static subpicture key | |
868 + (0<<27) // static subpicture key | |
869 + (0<<28) // static subpicture key | |
870 */ ; | |
871 break; | |
872 | |
873 case MGA_VID_FORMAT_UYVY: | |
874 cregs.c2ctl = 1 // CRTC2 enabled | |
875 + (1<<1) // external clock | |
876 + (0<<2) // external clock | |
877 + (1<<3) // pixel clock enable - not needed ??? | |
878 + (0<<4) // high prioryty req | |
879 + (1<<5) // high prioryty req | |
880 + (0<<6) // high prioryty req | |
881 + (1<<8) // high prioryty req max | |
882 + (0<<9) // high prioryty req max | |
883 + (0<<10) // high prioryty req max | |
884 + (0<<20) // CRTC1 to DAC | |
885 + (1<<21) // 422 mode | |
886 + (0<<22) // 422 mode | |
887 + (1<<23) // 422 mode | |
888 + (1<<24) // single chroma line for 420 mode - need to be corrected | |
889 + (1<<25) /*/ interlace mode - need to be corrected*/ | |
890 + (0<<26) // field legth polariry | |
891 + (0<<27) // field identification polariry | |
892 + (1<<28) // VIDRST detection mode | |
893 + (0<<29) // VIDRST detection mode | |
894 + (1<<30) // Horizontal counter preload | |
895 + (1<<31) // Vertical counter preload | |
896 ; | |
897 cregs.c2datactl = 0 // enable dither - propably not needed, we are already in YUV mode | |
898 + (1<<1) // Y filter enable | |
899 + (1<<2) // CbCr filter enable | |
900 + (0<<3) // subpicture enable (disabled) | |
901 + (0<<4) // NTSC enable (disabled - PAL) | |
902 + (0<<5) // C2 static subpicture enable (disabled) | |
903 + (0<<6) // C2 subpicture offset division (disabled) | |
904 + (1<<7) // 422 subformat selection ! | |
905 /* + (0<<8) // 15 bpp high alpha | |
906 + (0<<9) // 15 bpp high alpha | |
907 + (0<<10) // 15 bpp high alpha | |
908 + (0<<11) // 15 bpp high alpha | |
909 + (0<<12) // 15 bpp high alpha | |
910 + (0<<13) // 15 bpp high alpha | |
911 + (0<<14) // 15 bpp high alpha | |
912 + (0<<15) // 15 bpp high alpha | |
913 + (0<<16) // 15 bpp low alpha | |
914 + (0<<17) // 15 bpp low alpha | |
915 + (0<<18) // 15 bpp low alpha | |
916 + (0<<19) // 15 bpp low alpha | |
917 + (0<<20) // 15 bpp low alpha | |
918 + (0<<21) // 15 bpp low alpha | |
919 + (0<<22) // 15 bpp low alpha | |
920 + (0<<23) // 15 bpp low alpha | |
921 + (0<<24) // static subpicture key | |
922 + (0<<25) // static subpicture key | |
923 + (0<<26) // static subpicture key | |
924 + (0<<27) // static subpicture key | |
925 + (0<<28) // static subpicture key | |
926 */ ; | |
927 break; | |
928 | |
929 default: | |
930 printk(KERN_ERR "mga_vid: Unsupported pixel format: 0x%X\n",config->format); | |
931 return -1; | |
932 } | |
933 | |
934 cregs.c2hparam=((hdispend - 8) << 16) | (htotal - 8); | |
935 cregs.c2hsync=((hsyncend - 8) << 16) | (hsyncstart - 8); | |
936 | |
937 cregs.c2misc=0 // CRTCV2 656 togg f0 | |
938 +(0<<1) // CRTCV2 656 togg f0 | |
939 +(0<<2) // CRTCV2 656 togg f0 | |
940 +(0<<4) // CRTCV2 656 togg f1 | |
941 +(0<<5) // CRTCV2 656 togg f1 | |
942 +(0<<6) // CRTCV2 656 togg f1 | |
943 +(0<<8) // Hsync active high | |
944 +(0<<9) // Vsync active high | |
945 // 16-27 c2vlinecomp - nevim co tam dat | |
946 ; | |
947 cregs.c2offset=(regs.bespitch << 1); | |
948 | |
949 cregs.c2pl2startadd0=regs.besa1corg; | |
950 // cregs.c2pl2startadd1=regs.besa2corg; | |
951 cregs.c2pl3startadd0=regs.besa1c3org; | |
952 // cregs.c2pl3startadd1=regs.besa2c3org; | |
953 | |
954 cregs.c2preload=(vsyncstart << 16) | (hsyncstart); // from | |
955 | |
956 cregs.c2spicstartadd0=0; // not used | |
957 // cregs.c2spicstartadd1=0; // not used | |
958 | |
959 cregs.c2startadd0=regs.besa1org; | |
960 // cregs.c2startadd1=regs.besa2org; | |
961 | |
962 cregs.c2subpiclut=0; //not used | |
963 | |
964 cregs.c2vparam=((vdispend - 1) << 16) | (vtotal - 1); | |
965 cregs.c2vsync=((vsyncend - 1) << 16) | (vsyncstart - 1); | |
966 | |
967 | |
968 #endif | |
969 | |
2086 | 970 mga_vid_write_regs(0); |
1 | 971 return 0; |
972 } | |
973 | |
68 | 974 #ifdef MGA_ALLOW_IRQ |
975 | |
48 | 976 static void enable_irq(){ |
977 long int cc; | |
978 | |
979 cc = readl(mga_mmio_base + IEN); | |
63 | 980 // printk(KERN_ALERT "*** !!! IRQREG = %d\n", (int)(cc&0xff)); |
48 | 981 |
982 writeb( 0x11, mga_mmio_base + CRTCX); | |
983 | |
984 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ | |
985 writeb(0x00, mga_mmio_base + CRTCD ); /* enable on */ | |
986 writeb(0x10, mga_mmio_base + CRTCD ); /* clear = 1 */ | |
987 | |
988 writel( regs.besglobctl , mga_mmio_base + BESGLOBCTL); | |
989 | |
990 } | |
991 | |
992 static void disable_irq(){ | |
993 | |
994 writeb( 0x11, mga_mmio_base + CRTCX); | |
995 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ | |
996 | |
997 } | |
998 | |
999 void mga_handle_irq(int irq, void *dev_id, struct pt_regs *pregs) { | |
1000 // static int frame=0; | |
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1001 // static int counter=0; |
48 | 1002 long int cc; |
1003 // if ( ! mga_enabled_flag ) return; | |
1004 | |
68 | 1005 // printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT)); |
1006 | |
48 | 1007 //printk("mga_interrupt #%d\n", irq); |
1008 | |
1009 if ( irq != -1 ) { | |
1010 | |
1011 cc = readl(mga_mmio_base + STATUS); | |
1012 if ( ! (cc & 0x10) ) return; /* vsyncpen */ | |
1013 // debug_irqcnt++; | |
1014 } | |
1015 | |
1016 // if ( debug_irqignore ) { | |
1017 // debug_irqignore = 0; | |
1018 | |
1019 | |
1020 /* | |
1021 if ( mga_conf_deinterlace ) { | |
1022 if ( mga_first_field ) { | |
1023 // printk("mga_interrupt first field\n"); | |
1024 if ( syncfb_interrupt() ) | |
1025 mga_first_field = 0; | |
1026 } else { | |
1027 // printk("mga_interrupt second field\n"); | |
1028 mga_select_buffer( mga_current_field | 2 ); | |
1029 mga_first_field = 1; | |
1030 } | |
1031 } else { | |
1032 syncfb_interrupt(); | |
1033 } | |
1034 */ | |
1035 | |
1036 // frame=(frame+1)&1; | |
1037 regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25); | |
1038 writel( regs.besctl, mga_mmio_base + BESCTL ); | |
2344 | 1039 |
1040 #ifdef CRTC2 | |
1041 // sem pridat vyber obrazku !!!! | |
1042 crtc2_frame_sel(mga_next_frame); | |
1043 #endif | |
48 | 1044 |
1045 #if 0 | |
1046 ++counter; | |
1047 if(!(counter&63)){ | |
1048 printk("mga irq counter = %d\n",counter); | |
1049 } | |
1050 #endif | |
1051 | |
1052 // } else { | |
1053 // debug_irqignore = 1; | |
1054 // } | |
1055 | |
1056 if ( irq != -1 ) { | |
1057 writeb( 0x11, mga_mmio_base + CRTCX); | |
1058 writeb( 0, mga_mmio_base + CRTCD ); | |
1059 writeb( 0x10, mga_mmio_base + CRTCD ); | |
1060 } | |
1061 | |
1062 // writel( regs.besglobctl, mga_mmio_base + BESGLOBCTL); | |
1063 | |
1064 | |
1065 return; | |
1066 | |
1067 } | |
1068 | |
68 | 1069 #endif |
1 | 1070 |
1071 static int mga_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) | |
1072 { | |
1073 int frame; | |
1074 | |
1075 switch(cmd) | |
1076 { | |
1077 case MGA_VID_CONFIG: | |
1078 //FIXME remove | |
68 | 1079 // printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT)); |
61 | 1080 printk(KERN_DEBUG "mga_mmio_base = %p\n",mga_mmio_base); |
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1081 printk(KERN_DEBUG "mga_mem_base = %08x\n",mga_mem_base); |
1 | 1082 //FIXME remove |
1083 | |
61 | 1084 printk(KERN_DEBUG "mga_vid: Received configuration\n"); |
1 | 1085 |
1086 if(copy_from_user(&mga_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t))) | |
1087 { | |
61 | 1088 printk(KERN_ERR "mga_vid: failed copy from userspace\n"); |
1 | 1089 return(-EFAULT); |
1090 } | |
57 | 1091 if(mga_config.version != MGA_VID_VERSION){ |
61 | 1092 printk(KERN_ERR "mga_vid: incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,mga_config.version); |
57 | 1093 return(-EFAULT); |
1094 } | |
1095 | |
1096 if(mga_config.frame_size==0 || mga_config.frame_size>1024*768*2){ | |
61 | 1097 printk(KERN_ERR "mga_vid: illegal frame_size: %d\n",mga_config.frame_size); |
57 | 1098 return(-EFAULT); |
1099 } | |
1100 | |
1101 if(mga_config.num_frames<1 || mga_config.num_frames>4){ | |
61 | 1102 printk(KERN_ERR "mga_vid: illegal num_frames: %d\n",mga_config.num_frames); |
57 | 1103 return(-EFAULT); |
1104 } | |
1105 | |
1106 mga_src_base = (mga_ram_size*0x100000-mga_config.num_frames*mga_config.frame_size); | |
1107 if(mga_src_base<0){ | |
61 | 1108 printk(KERN_ERR "mga_vid: not enough memory for frames!\n"); |
57 | 1109 return(-EFAULT); |
1110 } | |
1111 mga_src_base &= (~0xFFFF); // 64k boundary | |
61 | 1112 printk(KERN_DEBUG "mga YUV buffer base: 0x%X\n", mga_src_base); |
57 | 1113 |
1 | 1114 if (is_g400) |
1115 mga_config.card_type = MGA_G400; | |
1116 else | |
1117 mga_config.card_type = MGA_G200; | |
1118 | |
1119 mga_config.ram_size = mga_ram_size; | |
1120 | |
1121 if (copy_to_user((mga_vid_config_t *) arg, &mga_config, sizeof(mga_vid_config_t))) | |
1122 { | |
61 | 1123 printk(KERN_ERR "mga_vid: failed copy to userspace\n"); |
1 | 1124 return(-EFAULT); |
1125 } | |
1126 return mga_vid_set_config(&mga_config); | |
1127 break; | |
1128 | |
1129 case MGA_VID_ON: | |
61 | 1130 printk(KERN_DEBUG "mga_vid: Video ON\n"); |
1 | 1131 vid_src_ready = 1; |
1132 if(vid_overlay_on) | |
1133 { | |
1134 regs.besctl |= 1; | |
2086 | 1135 mga_vid_write_regs(0); |
1 | 1136 } |
68 | 1137 #ifdef MGA_ALLOW_IRQ |
48 | 1138 if ( mga_irq != -1 ) enable_irq(); |
68 | 1139 #endif |
48 | 1140 mga_next_frame=0; |
1 | 1141 break; |
1142 | |
1143 case MGA_VID_OFF: | |
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1144 printk(KERN_DEBUG "mga_vid: Video OFF (ioctl)\n"); |
1 | 1145 vid_src_ready = 0; |
68 | 1146 #ifdef MGA_ALLOW_IRQ |
48 | 1147 if ( mga_irq != -1 ) disable_irq(); |
68 | 1148 #endif |
1 | 1149 regs.besctl &= ~1; |
466 | 1150 regs.besglobctl &= ~(1<<6); // UYVY format selected |
2086 | 1151 mga_vid_write_regs(0); |
1 | 1152 break; |
1153 | |
1154 case MGA_VID_FSEL: | |
1155 if(copy_from_user(&frame,(int *) arg,sizeof(int))) | |
1156 { | |
61 | 1157 printk(KERN_ERR "mga_vid: FSEL failed copy from userspace\n"); |
1 | 1158 return(-EFAULT); |
1159 } | |
1160 | |
1161 mga_vid_frame_sel(frame); | |
1162 break; | |
1163 | |
1164 default: | |
61 | 1165 printk(KERN_ERR "mga_vid: Invalid ioctl\n"); |
1 | 1166 return (-EINVAL); |
1167 } | |
1168 | |
1169 return 0; | |
1170 } | |
1171 | |
1172 | |
1173 static int mga_vid_find_card(void) | |
1174 { | |
1175 struct pci_dev *dev = NULL; | |
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1176 unsigned int card_option; |
1 | 1177 |
1989 | 1178 if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G550, NULL))) |
1179 { | |
1180 is_g400 = 1; | |
1181 printk(KERN_INFO "mga_vid: Found MGA G550\n"); | |
1182 } | |
1183 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400, NULL))) | |
1 | 1184 { |
1185 is_g400 = 1; | |
77 | 1186 printk(KERN_INFO "mga_vid: Found MGA G400/G450\n"); |
1 | 1187 } |
1188 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, NULL))) | |
1189 { | |
1190 is_g400 = 0; | |
63 | 1191 printk(KERN_INFO "mga_vid: Found MGA G200 AGP\n"); |
1 | 1192 } |
1193 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_PCI, NULL))) | |
1194 { | |
1195 is_g400 = 0; | |
63 | 1196 printk(KERN_INFO "mga_vid: Found MGA G200 PCI\n"); |
1 | 1197 } |
1198 else | |
1199 { | |
61 | 1200 printk(KERN_ERR "mga_vid: No supported cards found\n"); |
1 | 1201 return FALSE; |
1202 } | |
1203 | |
1204 pci_dev = dev; | |
48 | 1205 |
1206 mga_irq = pci_dev->irq; | |
1 | 1207 |
1208 #if LINUX_VERSION_CODE >= 0x020300 | |
1209 mga_mmio_base = ioremap_nocache(dev->resource[1].start,0x4000); | |
1210 mga_mem_base = dev->resource[0].start; | |
1211 #else | |
1212 mga_mmio_base = ioremap_nocache(dev->base_address[1] & PCI_BASE_ADDRESS_MEM_MASK,0x4000); | |
1213 mga_mem_base = dev->base_address[0] & PCI_BASE_ADDRESS_MEM_MASK; | |
1214 #endif | |
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1215 printk(KERN_INFO "mga_vid: MMIO at 0x%p IRQ: %d framebuffer: 0x%08X\n", mga_mmio_base, mga_irq, mga_mem_base); |
1 | 1216 |
1217 pci_read_config_dword(dev, 0x40, &card_option); | |
77 | 1218 printk(KERN_INFO "mga_vid: OPTION word: 0x%08X mem: 0x%02X %s\n", card_option, |
1219 (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM"); | |
1 | 1220 |
57 | 1221 // temp = (card_option >> 10) & 0x17; |
1222 | |
95 | 1223 if (mga_ram_size) { |
1224 printk(KERN_INFO "mga_vid: RAMSIZE forced to %d MB\n", mga_ram_size); | |
91 | 1225 } else { |
90 | 1226 |
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1227 #ifdef MGA_MEMORY_SIZE |
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1228 mga_ram_size = MGA_MEMORY_SIZE; |
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1229 printk(KERN_INFO "mga_vid: hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); |
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1230 |
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1231 #else |
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1232 |
95 | 1233 if (is_g400){ |
75 | 1234 switch((card_option>>10)&0x17){ |
1235 // SDRAM: | |
1236 case 0x00: | |
1237 case 0x04: mga_ram_size = 16; break; | |
105 | 1238 case 0x03: mga_ram_size = 32; break; |
75 | 1239 // SGRAM: |
1240 case 0x10: | |
1241 case 0x14: mga_ram_size = 32; break; | |
1242 case 0x11: | |
1243 case 0x12: mga_ram_size = 16; break; | |
1244 default: | |
1245 mga_ram_size = 16; | |
1246 printk(KERN_INFO "mga_vid: Couldn't detect RAMSIZE, assuming 16MB!"); | |
1247 } | |
95 | 1248 }else{ |
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1249 switch((card_option>>10)&0x17){ |
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1250 // case 0x10: |
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1251 // case 0x13: mga_ram_size = 8; break; |
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1252 default: mga_ram_size = 8; |
64 | 1253 } |
95 | 1254 } |
64 | 1255 #if 0 |
95 | 1256 // printk("List resources -----------\n"); |
1257 for(temp=0;temp<DEVICE_COUNT_RESOURCE;temp++){ | |
1258 struct resource *res=&pci_dev->resource[temp]; | |
1259 if(res->flags){ | |
1260 int size=(1+res->end-res->start)>>20; | |
1261 printk(KERN_DEBUG "res %d: start: 0x%X end: 0x%X (%d MB) flags=0x%X\n",temp,res->start,res->end,size,res->flags); | |
1262 if(res->flags&(IORESOURCE_MEM|IORESOURCE_PREFETCH)){ | |
1263 if(size>mga_ram_size && size<=64) mga_ram_size=size; | |
1264 } | |
1265 } | |
57 | 1266 } |
64 | 1267 #endif |
95 | 1268 printk(KERN_INFO "mga_vid: detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); |
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1269 #endif |
95 | 1270 } |
57 | 1271 |
48 | 1272 |
68 | 1273 #ifdef MGA_ALLOW_IRQ |
48 | 1274 if ( mga_irq != -1 ) { |
1275 int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq); | |
1276 if ( tmp ) { | |
61 | 1277 printk(KERN_INFO "syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp); |
48 | 1278 mga_irq=-1; |
1279 } else { | |
61 | 1280 printk(KERN_DEBUG "syncfb (mga): registered irq %d\n", mga_irq); |
48 | 1281 } |
1282 } else { | |
61 | 1283 printk(KERN_INFO "syncfb (mga): No valid irq was found\n"); |
48 | 1284 mga_irq=-1; |
1285 } | |
68 | 1286 #else |
1287 printk(KERN_INFO "syncfb (mga): IRQ disabled in mga_vid.c\n"); | |
1288 mga_irq=-1; | |
1289 #endif | |
48 | 1290 |
1 | 1291 return TRUE; |
1292 } | |
1293 | |
1294 | |
1295 static ssize_t mga_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) | |
1296 { | |
1297 return -EINVAL; | |
1298 } | |
1299 | |
1300 static ssize_t mga_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) | |
1301 { | |
1302 return -EINVAL; | |
1303 } | |
1304 | |
1305 static int mga_vid_mmap(struct file *file, struct vm_area_struct *vma) | |
1306 { | |
1307 | |
61 | 1308 printk(KERN_DEBUG "mga_vid: mapping video memory into userspace\n"); |
57 | 1309 if(remap_page_range(vma->vm_start, mga_mem_base + mga_src_base, |
1 | 1310 vma->vm_end - vma->vm_start, vma->vm_page_prot)) |
1311 { | |
63 | 1312 printk(KERN_ERR "mga_vid: error mapping video memory\n"); |
1 | 1313 return(-EAGAIN); |
1314 } | |
1315 | |
1316 return(0); | |
1317 } | |
1318 | |
1319 static int mga_vid_release(struct inode *inode, struct file *file) | |
1320 { | |
1321 //Close the window just in case | |
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1322 printk(KERN_DEBUG "mga_vid: Video OFF (release)\n"); |
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1323 |
1 | 1324 vid_src_ready = 0; |
1325 regs.besctl &= ~1; | |
466 | 1326 regs.besglobctl &= ~(1<<6); // UYVY format selected |
2086 | 1327 // mga_config.colkey_on=0; //!!! |
1328 mga_vid_write_regs(1); | |
1 | 1329 mga_vid_in_use = 0; |
1330 | |
93 | 1331 MOD_DEC_USE_COUNT; |
1 | 1332 return 0; |
1333 } | |
1334 | |
1335 static long long mga_vid_lseek(struct file *file, long long offset, int origin) | |
1336 { | |
1337 return -ESPIPE; | |
1338 } | |
1339 | |
1340 static int mga_vid_open(struct inode *inode, struct file *file) | |
1341 { | |
1342 int minor = MINOR(inode->i_rdev); | |
1343 | |
1344 if(minor != 0) | |
1345 return(-ENXIO); | |
1346 | |
1347 if(mga_vid_in_use == 1) | |
1348 return(-EBUSY); | |
1349 | |
1350 mga_vid_in_use = 1; | |
93 | 1351 MOD_INC_USE_COUNT; |
1 | 1352 return(0); |
1353 } | |
1354 | |
1355 #if LINUX_VERSION_CODE >= 0x020400 | |
1356 static struct file_operations mga_vid_fops = | |
1357 { | |
1358 llseek: mga_vid_lseek, | |
1359 read: mga_vid_read, | |
1360 write: mga_vid_write, | |
1361 ioctl: mga_vid_ioctl, | |
1362 mmap: mga_vid_mmap, | |
1363 open: mga_vid_open, | |
1364 release: mga_vid_release | |
1365 }; | |
1366 #else | |
1367 static struct file_operations mga_vid_fops = | |
1368 { | |
1369 mga_vid_lseek, | |
1370 mga_vid_read, | |
1371 mga_vid_write, | |
1372 NULL, | |
1373 NULL, | |
1374 mga_vid_ioctl, | |
1375 mga_vid_mmap, | |
1376 mga_vid_open, | |
1377 NULL, | |
1378 mga_vid_release | |
1379 }; | |
1380 #endif | |
1381 | |
1382 | |
1383 /* | |
1384 * Main Initialization Function | |
1385 */ | |
1386 | |
1387 static int mga_vid_initialize(void) | |
1388 { | |
1389 mga_vid_in_use = 0; | |
1390 | |
77 | 1391 // printk(KERN_INFO "Matrox MGA G200/G400 YUV Video interface v0.01 (c) Aaron Holtzman \n"); |
1392 printk(KERN_INFO "Matrox MGA G200/G400/G450 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n"); | |
90 | 1393 |
95 | 1394 if (mga_ram_size) { |
1395 if (mga_ram_size<4 || mga_ram_size>64) { | |
1396 printk(KERN_ERR "mga_vid: invalid RAMSIZE: %d MB\n", mga_ram_size); | |
90 | 1397 return -EINVAL; |
1398 } | |
1399 } | |
1400 | |
1 | 1401 if(register_chrdev(MGA_VID_MAJOR, "mga_vid", &mga_vid_fops)) |
1402 { | |
61 | 1403 printk(KERN_ERR "mga_vid: unable to get major: %d\n", MGA_VID_MAJOR); |
1 | 1404 return -EIO; |
1405 } | |
1406 | |
1407 if (!mga_vid_find_card()) | |
1408 { | |
61 | 1409 printk(KERN_ERR "mga_vid: no supported devices found\n"); |
1 | 1410 unregister_chrdev(MGA_VID_MAJOR, "mga_vid"); |
1411 return -EINVAL; | |
1412 } | |
1413 | |
1414 return(0); | |
1415 } | |
1416 | |
1417 int init_module(void) | |
1418 { | |
1419 return mga_vid_initialize(); | |
1420 } | |
1421 | |
1422 void cleanup_module(void) | |
1423 { | |
48 | 1424 |
68 | 1425 #ifdef MGA_ALLOW_IRQ |
48 | 1426 if ( mga_irq != -1) |
1427 free_irq(mga_irq, &mga_irq); | |
68 | 1428 #endif |
48 | 1429 |
1 | 1430 if(mga_mmio_base) |
1431 iounmap(mga_mmio_base); | |
1432 | |
1433 //FIXME turn off BES | |
63 | 1434 printk(KERN_INFO "mga_vid: Cleaning up module\n"); |
1 | 1435 unregister_chrdev(MGA_VID_MAJOR, "mga_vid"); |
1436 } | |
1437 |