1
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1 // YUY2 support (see config.format) added by A'rpi/ESP-team
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57
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2 // double buffering added by A'rpi/ESP-team
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3
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4 // Set this value, if autodetection fails! (video ram size in megabytes)
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5 //#define MGA_MEMORY_SIZE 32
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1
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6
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68
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7 //#define MGA_ALLOW_IRQ
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8
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9 #define MGA_VSYNC_POS 2
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10
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1
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11 /*
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12 *
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13 * mga_vid.c
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14 *
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15 * Copyright (C) 1999 Aaron Holtzman
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16 *
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17 * Module skeleton based on gutted agpgart module by Jeff Hartmann
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18 * <slicer@ionet.net>
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19 *
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20 * Matrox MGA G200/G400 YUV Video Interface module Version 0.1.0
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21 *
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22 * BES == Back End Scaler
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23 *
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24 * This software has been released under the terms of the GNU Public
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25 * license. See http://www.gnu.org/copyleft/gpl.html for details.
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26 */
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27
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28 //It's entirely possible this major conflicts with something else
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29 /* mknod /dev/mga_vid c 178 0 */
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30
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31 #include <linux/config.h>
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32 #include <linux/version.h>
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33 #include <linux/module.h>
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34 #include <linux/types.h>
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35 #include <linux/kernel.h>
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36 #include <linux/sched.h>
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37 #include <linux/mm.h>
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38 #include <linux/string.h>
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39 #include <linux/errno.h>
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40 #include <linux/malloc.h>
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41 #include <linux/pci.h>
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63
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42 #include <linux/ioport.h>
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1
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43 #include <linux/init.h>
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44
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45 #include "mga_vid.h"
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46
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47 #ifdef CONFIG_MTRR
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48 #include <asm/mtrr.h>
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49 #endif
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50
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51 #include <asm/uaccess.h>
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52 #include <asm/system.h>
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53 #include <asm/io.h>
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54
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55 #define TRUE 1
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56 #define FALSE 0
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57
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58 #define MGA_VID_MAJOR 178
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59
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57
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60 //#define MGA_VIDMEM_SIZE mga_ram_size
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1
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61
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62 #ifndef PCI_DEVICE_ID_MATROX_G200_PCI
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63 #define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520
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64 #endif
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65
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66 #ifndef PCI_DEVICE_ID_MATROX_G200_AGP
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67 #define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521
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68 #endif
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69
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70 #ifndef PCI_DEVICE_ID_MATROX_G400
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71 #define PCI_DEVICE_ID_MATROX_G400 0x0525
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72 #endif
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73
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74 MODULE_AUTHOR("Aaron Holtzman <aholtzma@engr.uvic.ca>");
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75
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76
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77 typedef struct bes_registers_s
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78 {
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79 //BES Control
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80 uint32_t besctl;
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81 //BES Global control
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82 uint32_t besglobctl;
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83 //Luma control (brightness and contrast)
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84 uint32_t beslumactl;
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85 //Line pitch
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86 uint32_t bespitch;
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87
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88 //Buffer A-1 Chroma 3 plane org
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89 uint32_t besa1c3org;
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90 //Buffer A-1 Chroma org
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91 uint32_t besa1corg;
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92 //Buffer A-1 Luma org
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93 uint32_t besa1org;
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94
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95 //Buffer A-2 Chroma 3 plane org
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96 uint32_t besa2c3org;
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97 //Buffer A-2 Chroma org
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98 uint32_t besa2corg;
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99 //Buffer A-2 Luma org
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100 uint32_t besa2org;
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101
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102 //Buffer B-1 Chroma 3 plane org
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103 uint32_t besb1c3org;
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104 //Buffer B-1 Chroma org
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105 uint32_t besb1corg;
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106 //Buffer B-1 Luma org
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107 uint32_t besb1org;
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108
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109 //Buffer B-2 Chroma 3 plane org
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110 uint32_t besb2c3org;
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111 //Buffer B-2 Chroma org
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112 uint32_t besb2corg;
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113 //Buffer B-2 Luma org
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114 uint32_t besb2org;
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115
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116 //BES Horizontal coord
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117 uint32_t beshcoord;
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118 //BES Horizontal inverse scaling [5.14]
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119 uint32_t beshiscal;
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120 //BES Horizontal source start [10.14] (for scaling)
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121 uint32_t beshsrcst;
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122 //BES Horizontal source ending [10.14] (for scaling)
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123 uint32_t beshsrcend;
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124 //BES Horizontal source last
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125 uint32_t beshsrclst;
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126
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127
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128 //BES Vertical coord
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129 uint32_t besvcoord;
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130 //BES Vertical inverse scaling [5.14]
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131 uint32_t besviscal;
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132 //BES Field 1 vertical source last position
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133 uint32_t besv1srclst;
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134 //BES Field 1 weight start
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135 uint32_t besv1wght;
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136 //BES Field 2 vertical source last position
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137 uint32_t besv2srclst;
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138 //BES Field 2 weight start
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139 uint32_t besv2wght;
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140
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141 } bes_registers_t;
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142
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143 static bes_registers_t regs;
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144 static uint32_t mga_vid_in_use = 0;
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145 static uint32_t is_g400 = 0;
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146 static uint32_t vid_src_ready = 0;
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147 static uint32_t vid_overlay_on = 0;
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148
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149 static uint8_t *mga_mmio_base = 0;
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150 static uint32_t mga_mem_base = 0;
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151
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57
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152 static int mga_src_base = 0; // YUV buffer position in video memory
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153
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154 static uint32_t mga_ram_size = 0; // how much megabytes videoram we have
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1
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155
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156 static struct pci_dev *pci_dev;
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157
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158 static mga_vid_config_t mga_config;
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159
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48
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160 static int mga_irq = -1;
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1
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161
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162 //All register offsets are converted to word aligned offsets (32 bit)
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163 //because we want all our register accesses to be 32 bits
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164 #define VCOUNT 0x1e20
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165
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166 #define PALWTADD 0x3c00 // Index register for X_DATAREG port
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167 #define X_DATAREG 0x3c0a
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168
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169 #define XMULCTRL 0x19
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170 #define BPP_8 0x00
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171 #define BPP_15 0x01
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172 #define BPP_16 0x02
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173 #define BPP_24 0x03
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174 #define BPP_32_DIR 0x04
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175 #define BPP_32_PAL 0x07
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176
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177 #define XCOLMSK 0x40
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178 #define X_COLKEY 0x42
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179 #define XKEYOPMODE 0x51
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180 #define XCOLMSK0RED 0x52
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181 #define XCOLMSK0GREEN 0x53
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182 #define XCOLMSK0BLUE 0x54
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183 #define XCOLKEY0RED 0x55
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184 #define XCOLKEY0GREEN 0x56
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185 #define XCOLKEY0BLUE 0x57
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186
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187 // Backend Scaler registers
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188 #define BESCTL 0x3d20
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189 #define BESGLOBCTL 0x3dc0
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190 #define BESLUMACTL 0x3d40
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191 #define BESPITCH 0x3d24
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48
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192
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1
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193 #define BESA1C3ORG 0x3d60
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194 #define BESA1CORG 0x3d10
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195 #define BESA1ORG 0x3d00
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48
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196
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1
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197 #define BESA2C3ORG 0x3d64
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198 #define BESA2CORG 0x3d14
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199 #define BESA2ORG 0x3d04
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48
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200
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1
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201 #define BESB1C3ORG 0x3d68
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202 #define BESB1CORG 0x3d18
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203 #define BESB1ORG 0x3d08
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48
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204
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1
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205 #define BESB2C3ORG 0x3d6C
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206 #define BESB2CORG 0x3d1C
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207 #define BESB2ORG 0x3d0C
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48
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208
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1
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209 #define BESHCOORD 0x3d28
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210 #define BESHISCAL 0x3d30
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211 #define BESHSRCEND 0x3d3C
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212 #define BESHSRCLST 0x3d50
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213 #define BESHSRCST 0x3d38
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214 #define BESV1WGHT 0x3d48
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215 #define BESV2WGHT 0x3d4c
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216 #define BESV1SRCLST 0x3d54
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217 #define BESV2SRCLST 0x3d58
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218 #define BESVISCAL 0x3d34
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219 #define BESVCOORD 0x3d2c
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220 #define BESSTATUS 0x3dc4
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221
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48
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222 #define CRTCX 0x1fd4
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223 #define CRTCD 0x1fd5
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224 #define IEN 0x1e1c
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225 #define ICLEAR 0x1e18
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226 #define STATUS 0x1e14
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227
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228 static int mga_next_frame=0;
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1
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229
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230 static void mga_vid_frame_sel(int frame)
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231 {
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48
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232 if ( mga_irq != -1 ) {
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233 mga_next_frame=frame;
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234 } else {
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235
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1
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236 //we don't need the vcount protection as we're only hitting
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237 //one register (and it doesn't seem to be double buffered)
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238 regs.besctl = (regs.besctl & ~0x07000000) + (frame << 25);
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239 writel( regs.besctl, mga_mmio_base + BESCTL );
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68
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240
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241 // writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16),
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242 writel( regs.besglobctl + (MGA_VSYNC_POS<<16),
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243 mga_mmio_base + BESGLOBCTL);
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244
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48
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245 }
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1
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246 }
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247
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248
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249 static void mga_vid_write_regs(void)
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250 {
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251 //Make sure internal registers don't get updated until we're done
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252 writel( (readl(mga_mmio_base + VCOUNT)-1)<<16,
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253 mga_mmio_base + BESGLOBCTL);
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254
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255 // color or coordinate keying
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256 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
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257 writeb( mga_config.colkey_on, mga_mmio_base + X_DATAREG);
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258 if ( mga_config.colkey_on )
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259 {
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260 uint32_t r=0, g=0, b=0;
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261
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262 writeb( XMULCTRL, mga_mmio_base + PALWTADD);
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263 switch (readb (mga_mmio_base + X_DATAREG))
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264 {
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265 case BPP_8:
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266 /* Need to look up the color index, just using
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267 color 0 for now. */
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268 break;
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269
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270 case BPP_15:
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271 r = mga_config.colkey_red >> 3;
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272 g = mga_config.colkey_green >> 3;
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273 b = mga_config.colkey_blue >> 3;
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274 break;
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275
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276 case BPP_16:
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277 r = mga_config.colkey_red >> 3;
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278 g = mga_config.colkey_green >> 2;
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279 b = mga_config.colkey_blue >> 3;
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280 break;
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281
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282 case BPP_24:
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283 case BPP_32_DIR:
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284 case BPP_32_PAL:
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285 r = mga_config.colkey_red;
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286 g = mga_config.colkey_green;
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287 b = mga_config.colkey_blue;
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288 break;
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289 }
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290
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291 // Disable color keying on alpha channel
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292 writeb( XCOLMSK, mga_mmio_base + PALWTADD);
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293 writeb( 0x00, mga_mmio_base + X_DATAREG);
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294 writeb( X_COLKEY, mga_mmio_base + PALWTADD);
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295 writeb( 0x00, mga_mmio_base + X_DATAREG);
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296
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297 // Set up color key registers
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298 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD);
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299 writeb( r, mga_mmio_base + X_DATAREG);
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300 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD);
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301 writeb( g, mga_mmio_base + X_DATAREG);
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302 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD);
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303 writeb( b, mga_mmio_base + X_DATAREG);
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304
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305 // Set up color key mask registers
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306 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD);
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307 writeb( 0xff, mga_mmio_base + X_DATAREG);
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308 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD);
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309 writeb( 0xff, mga_mmio_base + X_DATAREG);
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310 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD);
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311 writeb( 0xff, mga_mmio_base + X_DATAREG);
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312 }
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313
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314 // Backend Scaler
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315 writel( regs.besctl, mga_mmio_base + BESCTL);
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316 if(is_g400)
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317 writel( regs.beslumactl, mga_mmio_base + BESLUMACTL);
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318 writel( regs.bespitch, mga_mmio_base + BESPITCH);
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319
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320 writel( regs.besa1org, mga_mmio_base + BESA1ORG);
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321 writel( regs.besa1corg, mga_mmio_base + BESA1CORG);
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48
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322 writel( regs.besa2org, mga_mmio_base + BESA2ORG);
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323 writel( regs.besa2corg, mga_mmio_base + BESA2CORG);
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1
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324 writel( regs.besb1org, mga_mmio_base + BESB1ORG);
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325 writel( regs.besb1corg, mga_mmio_base + BESB1CORG);
|
48
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326 writel( regs.besb2org, mga_mmio_base + BESB2ORG);
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327 writel( regs.besb2corg, mga_mmio_base + BESB2CORG);
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1
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328 if(is_g400)
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329 {
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330 writel( regs.besa1c3org, mga_mmio_base + BESA1C3ORG);
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48
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331 writel( regs.besa2c3org, mga_mmio_base + BESA2C3ORG);
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1
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332 writel( regs.besb1c3org, mga_mmio_base + BESB1C3ORG);
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48
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333 writel( regs.besb2c3org, mga_mmio_base + BESB2C3ORG);
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1
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334 }
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335
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336 writel( regs.beshcoord, mga_mmio_base + BESHCOORD);
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337 writel( regs.beshiscal, mga_mmio_base + BESHISCAL);
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338 writel( regs.beshsrcst, mga_mmio_base + BESHSRCST);
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339 writel( regs.beshsrcend, mga_mmio_base + BESHSRCEND);
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340 writel( regs.beshsrclst, mga_mmio_base + BESHSRCLST);
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341
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342 writel( regs.besvcoord, mga_mmio_base + BESVCOORD);
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343 writel( regs.besviscal, mga_mmio_base + BESVISCAL);
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48
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344
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1
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345 writel( regs.besv1srclst, mga_mmio_base + BESV1SRCLST);
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346 writel( regs.besv1wght, mga_mmio_base + BESV1WGHT);
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48
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347 writel( regs.besv2srclst, mga_mmio_base + BESV2SRCLST);
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348 writel( regs.besv2wght, mga_mmio_base + BESV2WGHT);
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1
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349
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350 //update the registers somewhere between 1 and 2 frames from now.
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351 writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16),
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352 mga_mmio_base + BESGLOBCTL);
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353
|
77
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354 #if 0
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61
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355 printk(KERN_DEBUG "mga_vid: wrote BES registers\n");
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356 printk(KERN_DEBUG "mga_vid: BESCTL = 0x%08x\n",
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1
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357 readl(mga_mmio_base + BESCTL));
|
61
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358 printk(KERN_DEBUG "mga_vid: BESGLOBCTL = 0x%08x\n",
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1
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359 readl(mga_mmio_base + BESGLOBCTL));
|
61
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360 printk(KERN_DEBUG "mga_vid: BESSTATUS= 0x%08x\n",
|
1
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361 readl(mga_mmio_base + BESSTATUS));
|
77
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362 #endif
|
1
|
363 }
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364
|
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365 static int mga_vid_set_config(mga_vid_config_t *config)
|
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366 {
|
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367 int x, y, sw, sh, dw, dh;
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368 int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights;
|
57
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369 int frame_size=config->frame_size;
|
1
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370 x = config->x_org;
|
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371 y = config->y_org;
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372 sw = config->src_width;
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373 sh = config->src_height;
|
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374 dw = config->dest_width;
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375 dh = config->dest_height;
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376
|
61
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377 printk(KERN_DEBUG "mga_vid: Setting up a %dx%d+%d+%d video window (src %dx%d) format %X\n",
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1
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378 dw, dh, x, y, sw, sh, config->format);
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379
|
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380 //FIXME check that window is valid and inside desktop
|
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381
|
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382 //FIXME figure out a better way to allocate memory on card
|
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383 //allocate 2 megs
|
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384 //mga_src_base = mga_mem_base + (MGA_VIDMEM_SIZE-2) * 0x100000;
|
57
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385 //mga_src_base = (MGA_VIDMEM_SIZE-3) * 0x100000;
|
1
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386
|
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387
|
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388 //Setup the BES registers for a three plane 4:2:0 video source
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389
|
|
390 switch(config->format){
|
|
391 case MGA_VID_FORMAT_YV12:
|
|
392 regs.besctl = 1 // BES enabled
|
|
393 + (0<<6) // even start polarity
|
|
394 + (1<<10) // x filtering enabled
|
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395 + (1<<11) // y filtering enabled
|
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396 + (1<<16) // chroma upsampling
|
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397 + (1<<17) // 4:2:0 mode
|
|
398 + (1<<18); // dither enabled
|
|
399
|
|
400 if(is_g400)
|
|
401 {
|
|
402 //zoom disabled, zoom filter disabled, 420 3 plane format, proc amp
|
|
403 //disabled, rgb mode disabled
|
|
404 regs.besglobctl = (1<<5);
|
|
405 }
|
|
406 else
|
|
407 {
|
|
408 //zoom disabled, zoom filter disabled, Cb samples in 0246, Cr
|
|
409 //in 1357, BES register update on besvcnt
|
|
410 regs.besglobctl = 0;
|
|
411 }
|
|
412 break;
|
|
413
|
|
414 case MGA_VID_FORMAT_YUY2:
|
|
415 regs.besctl = 1 // BES enabled
|
|
416 + (0<<6) // even start polarity
|
|
417 + (1<<10) // x filtering enabled
|
|
418 + (1<<11) // y filtering enabled
|
|
419 + (1<<16) // chroma upsampling
|
|
420 + (0<<17) // 4:2:2 mode
|
|
421 + (1<<18); // dither enabled
|
|
422
|
|
423 regs.besglobctl = 0; // YUY2 format selected
|
|
424 break;
|
|
425 default:
|
61
|
426 printk(KERN_ERR "mga_vid: Unsupported pixel format: 0x%X\n",config->format);
|
1
|
427 return -1;
|
|
428 }
|
|
429
|
|
430
|
|
431 //Disable contrast and brightness control
|
|
432 regs.besglobctl = (1<<5) + (1<<7);
|
|
433 regs.beslumactl = (0x7f << 16) + (0x80<<0);
|
|
434 regs.beslumactl = 0x80<<0;
|
|
435
|
|
436 //Setup destination window boundaries
|
|
437 besleft = x > 0 ? x : 0;
|
|
438 bestop = y > 0 ? y : 0;
|
|
439 regs.beshcoord = (besleft<<16) + (x + dw-1);
|
|
440 regs.besvcoord = (bestop<<16) + (y + dh-1);
|
|
441
|
|
442 //Setup source dimensions
|
|
443 regs.beshsrclst = (sw - 1) << 16;
|
|
444 regs.bespitch = (sw + 31) & ~31 ;
|
|
445
|
|
446 //Setup horizontal scaling
|
|
447 ifactor = ((sw-1)<<14)/(dw-1);
|
|
448 ofsleft = besleft - x;
|
|
449
|
|
450 regs.beshiscal = ifactor<<2;
|
|
451 regs.beshsrcst = (ofsleft*ifactor)<<2;
|
|
452 regs.beshsrcend = regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2);
|
|
453
|
|
454 //Setup vertical scaling
|
|
455 ifactor = ((sh-1)<<14)/(dh-1);
|
|
456 ofstop = bestop - y;
|
|
457
|
|
458 regs.besviscal = ifactor<<2;
|
|
459
|
|
460 baseadrofs = ((ofstop*regs.besviscal)>>16)*regs.bespitch;
|
57
|
461 //frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2;
|
1
|
462 regs.besa1org = (uint32_t) mga_src_base + baseadrofs;
|
48
|
463 regs.besa2org = (uint32_t) mga_src_base + baseadrofs + 1*frame_size;
|
|
464 regs.besb1org = (uint32_t) mga_src_base + baseadrofs + 2*frame_size;
|
|
465 regs.besb2org = (uint32_t) mga_src_base + baseadrofs + 3*frame_size;
|
1
|
466
|
57
|
467 if(config->format==MGA_VID_FORMAT_YV12){
|
|
468 // planar YUV frames:
|
1
|
469 if (is_g400)
|
|
470 baseadrofs = (((ofstop*regs.besviscal)/4)>>16)*regs.bespitch;
|
|
471 else
|
|
472 baseadrofs = (((ofstop*regs.besviscal)/2)>>16)*regs.bespitch;
|
|
473
|
|
474 regs.besa1corg = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ;
|
48
|
475 regs.besa2corg = (uint32_t) mga_src_base + baseadrofs + 1*frame_size + regs.bespitch * sh;
|
|
476 regs.besb1corg = (uint32_t) mga_src_base + baseadrofs + 2*frame_size + regs.bespitch * sh;
|
|
477 regs.besb2corg = (uint32_t) mga_src_base + baseadrofs + 3*frame_size + regs.bespitch * sh;
|
1
|
478 regs.besa1c3org = regs.besa1corg + ((regs.bespitch * sh) / 4);
|
48
|
479 regs.besa2c3org = regs.besa2corg + ((regs.bespitch * sh) / 4);
|
1
|
480 regs.besb1c3org = regs.besb1corg + ((regs.bespitch * sh) / 4);
|
48
|
481 regs.besb2c3org = regs.besb2corg + ((regs.bespitch * sh) / 4);
|
57
|
482 }
|
1
|
483
|
|
484 weight = ofstop * (regs.besviscal >> 2);
|
|
485 weights = weight < 0 ? 1 : 0;
|
48
|
486 regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2);
|
|
487 regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF);
|
1
|
488
|
|
489 mga_vid_write_regs();
|
|
490 return 0;
|
|
491 }
|
|
492
|
68
|
493 #ifdef MGA_ALLOW_IRQ
|
|
494
|
48
|
495 static void enable_irq(){
|
|
496 long int cc;
|
|
497
|
|
498 cc = readl(mga_mmio_base + IEN);
|
63
|
499 // printk(KERN_ALERT "*** !!! IRQREG = %d\n", (int)(cc&0xff));
|
48
|
500
|
|
501 writeb( 0x11, mga_mmio_base + CRTCX);
|
|
502
|
|
503 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */
|
|
504 writeb(0x00, mga_mmio_base + CRTCD ); /* enable on */
|
|
505 writeb(0x10, mga_mmio_base + CRTCD ); /* clear = 1 */
|
|
506
|
|
507 writel( regs.besglobctl , mga_mmio_base + BESGLOBCTL);
|
|
508
|
|
509 }
|
|
510
|
|
511 static void disable_irq(){
|
|
512
|
|
513 writeb( 0x11, mga_mmio_base + CRTCX);
|
|
514 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */
|
|
515
|
|
516 }
|
|
517
|
|
518 void mga_handle_irq(int irq, void *dev_id, struct pt_regs *pregs) {
|
|
519 // static int frame=0;
|
|
520 static int counter=0;
|
|
521 long int cc;
|
|
522 // if ( ! mga_enabled_flag ) return;
|
|
523
|
68
|
524 // printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT));
|
|
525
|
48
|
526 //printk("mga_interrupt #%d\n", irq);
|
|
527
|
|
528 if ( irq != -1 ) {
|
|
529
|
|
530 cc = readl(mga_mmio_base + STATUS);
|
|
531 if ( ! (cc & 0x10) ) return; /* vsyncpen */
|
|
532 // debug_irqcnt++;
|
|
533 }
|
|
534
|
|
535 // if ( debug_irqignore ) {
|
|
536 // debug_irqignore = 0;
|
|
537
|
|
538
|
|
539 /*
|
|
540 if ( mga_conf_deinterlace ) {
|
|
541 if ( mga_first_field ) {
|
|
542 // printk("mga_interrupt first field\n");
|
|
543 if ( syncfb_interrupt() )
|
|
544 mga_first_field = 0;
|
|
545 } else {
|
|
546 // printk("mga_interrupt second field\n");
|
|
547 mga_select_buffer( mga_current_field | 2 );
|
|
548 mga_first_field = 1;
|
|
549 }
|
|
550 } else {
|
|
551 syncfb_interrupt();
|
|
552 }
|
|
553 */
|
|
554
|
|
555 // frame=(frame+1)&1;
|
|
556 regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25);
|
|
557 writel( regs.besctl, mga_mmio_base + BESCTL );
|
|
558
|
|
559 #if 0
|
|
560 ++counter;
|
|
561 if(!(counter&63)){
|
|
562 printk("mga irq counter = %d\n",counter);
|
|
563 }
|
|
564 #endif
|
|
565
|
|
566 // } else {
|
|
567 // debug_irqignore = 1;
|
|
568 // }
|
|
569
|
|
570 if ( irq != -1 ) {
|
|
571 writeb( 0x11, mga_mmio_base + CRTCX);
|
|
572 writeb( 0, mga_mmio_base + CRTCD );
|
|
573 writeb( 0x10, mga_mmio_base + CRTCD );
|
|
574 }
|
|
575
|
|
576 // writel( regs.besglobctl, mga_mmio_base + BESGLOBCTL);
|
|
577
|
|
578
|
|
579 return;
|
|
580
|
|
581 }
|
|
582
|
68
|
583 #endif
|
1
|
584
|
|
585 static int mga_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
|
|
586 {
|
|
587 int frame;
|
|
588
|
|
589 switch(cmd)
|
|
590 {
|
|
591 case MGA_VID_CONFIG:
|
|
592 //FIXME remove
|
68
|
593 // printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT));
|
61
|
594 printk(KERN_DEBUG "mga_mmio_base = %p\n",mga_mmio_base);
|
|
595 printk(KERN_DEBUG "mga_mem_base = %08lx\n",mga_mem_base);
|
1
|
596 //FIXME remove
|
|
597
|
61
|
598 printk(KERN_DEBUG "mga_vid: Received configuration\n");
|
1
|
599
|
|
600 if(copy_from_user(&mga_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t)))
|
|
601 {
|
61
|
602 printk(KERN_ERR "mga_vid: failed copy from userspace\n");
|
1
|
603 return(-EFAULT);
|
|
604 }
|
57
|
605 if(mga_config.version != MGA_VID_VERSION){
|
61
|
606 printk(KERN_ERR "mga_vid: incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,mga_config.version);
|
57
|
607 return(-EFAULT);
|
|
608 }
|
|
609
|
|
610 if(mga_config.frame_size==0 || mga_config.frame_size>1024*768*2){
|
61
|
611 printk(KERN_ERR "mga_vid: illegal frame_size: %d\n",mga_config.frame_size);
|
57
|
612 return(-EFAULT);
|
|
613 }
|
|
614
|
|
615 if(mga_config.num_frames<1 || mga_config.num_frames>4){
|
61
|
616 printk(KERN_ERR "mga_vid: illegal num_frames: %d\n",mga_config.num_frames);
|
57
|
617 return(-EFAULT);
|
|
618 }
|
|
619
|
|
620 mga_src_base = (mga_ram_size*0x100000-mga_config.num_frames*mga_config.frame_size);
|
|
621 if(mga_src_base<0){
|
61
|
622 printk(KERN_ERR "mga_vid: not enough memory for frames!\n");
|
57
|
623 return(-EFAULT);
|
|
624 }
|
|
625 mga_src_base &= (~0xFFFF); // 64k boundary
|
61
|
626 printk(KERN_DEBUG "mga YUV buffer base: 0x%X\n", mga_src_base);
|
57
|
627
|
1
|
628 if (is_g400)
|
|
629 mga_config.card_type = MGA_G400;
|
|
630 else
|
|
631 mga_config.card_type = MGA_G200;
|
|
632
|
|
633 mga_config.ram_size = mga_ram_size;
|
|
634
|
|
635 if (copy_to_user((mga_vid_config_t *) arg, &mga_config, sizeof(mga_vid_config_t)))
|
|
636 {
|
61
|
637 printk(KERN_ERR "mga_vid: failed copy to userspace\n");
|
1
|
638 return(-EFAULT);
|
|
639 }
|
|
640 return mga_vid_set_config(&mga_config);
|
|
641 break;
|
|
642
|
|
643 case MGA_VID_ON:
|
61
|
644 printk(KERN_DEBUG "mga_vid: Video ON\n");
|
1
|
645 vid_src_ready = 1;
|
|
646 if(vid_overlay_on)
|
|
647 {
|
|
648 regs.besctl |= 1;
|
|
649 mga_vid_write_regs();
|
|
650 }
|
68
|
651 #ifdef MGA_ALLOW_IRQ
|
48
|
652 if ( mga_irq != -1 ) enable_irq();
|
68
|
653 #endif
|
48
|
654 mga_next_frame=0;
|
1
|
655 break;
|
|
656
|
|
657 case MGA_VID_OFF:
|
61
|
658 printk(KERN_DEBUG "mga_vid: Video OFF\n");
|
1
|
659 vid_src_ready = 0;
|
68
|
660 #ifdef MGA_ALLOW_IRQ
|
48
|
661 if ( mga_irq != -1 ) disable_irq();
|
68
|
662 #endif
|
1
|
663 regs.besctl &= ~1;
|
|
664 mga_vid_write_regs();
|
|
665 break;
|
|
666
|
|
667 case MGA_VID_FSEL:
|
|
668 if(copy_from_user(&frame,(int *) arg,sizeof(int)))
|
|
669 {
|
61
|
670 printk(KERN_ERR "mga_vid: FSEL failed copy from userspace\n");
|
1
|
671 return(-EFAULT);
|
|
672 }
|
|
673
|
|
674 mga_vid_frame_sel(frame);
|
|
675 break;
|
|
676
|
|
677 default:
|
61
|
678 printk(KERN_ERR "mga_vid: Invalid ioctl\n");
|
1
|
679 return (-EINVAL);
|
|
680 }
|
|
681
|
|
682 return 0;
|
|
683 }
|
|
684
|
|
685
|
|
686 static int mga_vid_find_card(void)
|
|
687 {
|
|
688 struct pci_dev *dev = NULL;
|
|
689 unsigned int card_option, temp;
|
|
690
|
|
691 if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400, NULL)))
|
|
692 {
|
|
693 is_g400 = 1;
|
77
|
694 printk(KERN_INFO "mga_vid: Found MGA G400/G450\n");
|
1
|
695 }
|
|
696 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, NULL)))
|
|
697 {
|
|
698 is_g400 = 0;
|
63
|
699 printk(KERN_INFO "mga_vid: Found MGA G200 AGP\n");
|
1
|
700 }
|
|
701 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_PCI, NULL)))
|
|
702 {
|
|
703 is_g400 = 0;
|
63
|
704 printk(KERN_INFO "mga_vid: Found MGA G200 PCI\n");
|
1
|
705 }
|
|
706 else
|
|
707 {
|
61
|
708 printk(KERN_ERR "mga_vid: No supported cards found\n");
|
1
|
709 return FALSE;
|
|
710 }
|
|
711
|
|
712 pci_dev = dev;
|
48
|
713
|
|
714 mga_irq = pci_dev->irq;
|
1
|
715
|
|
716 #if LINUX_VERSION_CODE >= 0x020300
|
|
717 mga_mmio_base = ioremap_nocache(dev->resource[1].start,0x4000);
|
|
718 mga_mem_base = dev->resource[0].start;
|
|
719 #else
|
|
720 mga_mmio_base = ioremap_nocache(dev->base_address[1] & PCI_BASE_ADDRESS_MEM_MASK,0x4000);
|
|
721 mga_mem_base = dev->base_address[0] & PCI_BASE_ADDRESS_MEM_MASK;
|
|
722 #endif
|
63
|
723 printk(KERN_INFO "mga_vid: MMIO at 0x%p IRQ: %d framebuffer: 0x%08lX\n", mga_mmio_base, mga_irq, mga_mem_base);
|
1
|
724
|
|
725 pci_read_config_dword(dev, 0x40, &card_option);
|
77
|
726 printk(KERN_INFO "mga_vid: OPTION word: 0x%08X mem: 0x%02X %s\n", card_option,
|
|
727 (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM");
|
1
|
728
|
57
|
729 // temp = (card_option >> 10) & 0x17;
|
|
730
|
|
731 #ifdef MGA_MEMORY_SIZE
|
|
732 mga_ram_size = MGA_MEMORY_SIZE;
|
63
|
733 printk(KERN_INFO "mga_vid: hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size);
|
1
|
734
|
57
|
735 #else
|
|
736 if (is_g400){
|
75
|
737 switch((card_option>>10)&0x17){
|
|
738 // SDRAM:
|
|
739 case 0x00:
|
|
740 case 0x04: mga_ram_size = 16; break;
|
|
741 case 0x03:
|
|
742 case 0x05: mga_ram_size = 64; break;
|
|
743 // SGRAM:
|
|
744 case 0x10:
|
|
745 case 0x14: mga_ram_size = 32; break;
|
|
746 case 0x11:
|
|
747 case 0x12: mga_ram_size = 16; break;
|
|
748 default:
|
|
749 mga_ram_size = 16;
|
|
750 printk(KERN_INFO "mga_vid: Couldn't detect RAMSIZE, assuming 16MB!");
|
|
751 }
|
|
752 #if 0
|
64
|
753 switch((card_option>>10)&7){
|
75
|
754 case 0:
|
|
755 case 4: mga_ram_size = ((card_option>>14)&1)? 32:16; break;
|
64
|
756 case 1:
|
|
757 case 2: mga_ram_size = 16; break; // SGRAM
|
|
758 case 3:
|
|
759 case 5: mga_ram_size = 64; break; // SDRAM
|
75
|
760 // case 4: mga_ram_size = 32; break; // SGRAM
|
64
|
761 default: mga_ram_size = 16;
|
|
762 }
|
75
|
763 #endif
|
57
|
764 }else{
|
64
|
765 switch((card_option>>11)&3){
|
|
766 case 0: mga_ram_size = 8; break;
|
|
767 default: mga_ram_size = 16;
|
|
768 }
|
1
|
769 }
|
64
|
770 #if 0
|
57
|
771 // printk("List resources -----------\n");
|
|
772 for(temp=0;temp<DEVICE_COUNT_RESOURCE;temp++){
|
|
773 struct resource *res=&pci_dev->resource[temp];
|
|
774 if(res->flags){
|
|
775 int size=(1+res->end-res->start)>>20;
|
61
|
776 printk(KERN_DEBUG "res %d: start: 0x%X end: 0x%X (%d MB) flags=0x%X\n",temp,res->start,res->end,size,res->flags);
|
57
|
777 if(res->flags&(IORESOURCE_MEM|IORESOURCE_PREFETCH)){
|
|
778 if(size>mga_ram_size && size<=64) mga_ram_size=size;
|
|
779 }
|
|
780 }
|
1
|
781 }
|
64
|
782 #endif
|
57
|
783
|
63
|
784 printk(KERN_INFO "mga_vid: detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size);
|
57
|
785 #endif
|
48
|
786
|
68
|
787 #ifdef MGA_ALLOW_IRQ
|
48
|
788 if ( mga_irq != -1 ) {
|
|
789 int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq);
|
|
790 if ( tmp ) {
|
61
|
791 printk(KERN_INFO "syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp);
|
48
|
792 mga_irq=-1;
|
|
793 } else {
|
61
|
794 printk(KERN_DEBUG "syncfb (mga): registered irq %d\n", mga_irq);
|
48
|
795 }
|
|
796 } else {
|
61
|
797 printk(KERN_INFO "syncfb (mga): No valid irq was found\n");
|
48
|
798 mga_irq=-1;
|
|
799 }
|
68
|
800 #else
|
|
801 printk(KERN_INFO "syncfb (mga): IRQ disabled in mga_vid.c\n");
|
|
802 mga_irq=-1;
|
|
803 #endif
|
48
|
804
|
1
|
805 return TRUE;
|
|
806 }
|
|
807
|
|
808
|
|
809 static ssize_t mga_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos)
|
|
810 {
|
|
811 return -EINVAL;
|
|
812 }
|
|
813
|
|
814 static ssize_t mga_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
|
|
815 {
|
|
816 return -EINVAL;
|
|
817 }
|
|
818
|
|
819 static int mga_vid_mmap(struct file *file, struct vm_area_struct *vma)
|
|
820 {
|
|
821
|
61
|
822 printk(KERN_DEBUG "mga_vid: mapping video memory into userspace\n");
|
57
|
823 if(remap_page_range(vma->vm_start, mga_mem_base + mga_src_base,
|
1
|
824 vma->vm_end - vma->vm_start, vma->vm_page_prot))
|
|
825 {
|
63
|
826 printk(KERN_ERR "mga_vid: error mapping video memory\n");
|
1
|
827 return(-EAGAIN);
|
|
828 }
|
|
829
|
|
830 return(0);
|
|
831 }
|
|
832
|
|
833 static int mga_vid_release(struct inode *inode, struct file *file)
|
|
834 {
|
|
835 //Close the window just in case
|
|
836 vid_src_ready = 0;
|
|
837 regs.besctl &= ~1;
|
|
838 mga_vid_write_regs();
|
|
839 mga_vid_in_use = 0;
|
|
840
|
|
841 //FIXME put back in!
|
|
842 //MOD_DEC_USE_COUNT;
|
|
843 return 0;
|
|
844 }
|
|
845
|
|
846 static long long mga_vid_lseek(struct file *file, long long offset, int origin)
|
|
847 {
|
|
848 return -ESPIPE;
|
|
849 }
|
|
850
|
|
851 static int mga_vid_open(struct inode *inode, struct file *file)
|
|
852 {
|
|
853 int minor = MINOR(inode->i_rdev);
|
|
854
|
|
855 if(minor != 0)
|
|
856 return(-ENXIO);
|
|
857
|
|
858 if(mga_vid_in_use == 1)
|
|
859 return(-EBUSY);
|
|
860
|
|
861 mga_vid_in_use = 1;
|
|
862 //FIXME turn me back on!
|
|
863 //MOD_INC_USE_COUNT;
|
|
864 return(0);
|
|
865 }
|
|
866
|
|
867 #if LINUX_VERSION_CODE >= 0x020400
|
|
868 static struct file_operations mga_vid_fops =
|
|
869 {
|
|
870 llseek: mga_vid_lseek,
|
|
871 read: mga_vid_read,
|
|
872 write: mga_vid_write,
|
|
873 ioctl: mga_vid_ioctl,
|
|
874 mmap: mga_vid_mmap,
|
|
875 open: mga_vid_open,
|
|
876 release: mga_vid_release
|
|
877 };
|
|
878 #else
|
|
879 static struct file_operations mga_vid_fops =
|
|
880 {
|
|
881 mga_vid_lseek,
|
|
882 mga_vid_read,
|
|
883 mga_vid_write,
|
|
884 NULL,
|
|
885 NULL,
|
|
886 mga_vid_ioctl,
|
|
887 mga_vid_mmap,
|
|
888 mga_vid_open,
|
|
889 NULL,
|
|
890 mga_vid_release
|
|
891 };
|
|
892 #endif
|
|
893
|
|
894
|
|
895 /*
|
|
896 * Main Initialization Function
|
|
897 */
|
|
898
|
|
899
|
|
900 static int mga_vid_initialize(void)
|
|
901 {
|
|
902 mga_vid_in_use = 0;
|
|
903
|
77
|
904 // printk(KERN_INFO "Matrox MGA G200/G400 YUV Video interface v0.01 (c) Aaron Holtzman \n");
|
|
905 printk(KERN_INFO "Matrox MGA G200/G400/G450 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n");
|
1
|
906 if(register_chrdev(MGA_VID_MAJOR, "mga_vid", &mga_vid_fops))
|
|
907 {
|
61
|
908 printk(KERN_ERR "mga_vid: unable to get major: %d\n", MGA_VID_MAJOR);
|
1
|
909 return -EIO;
|
|
910 }
|
|
911
|
|
912 if (!mga_vid_find_card())
|
|
913 {
|
61
|
914 printk(KERN_ERR "mga_vid: no supported devices found\n");
|
1
|
915 unregister_chrdev(MGA_VID_MAJOR, "mga_vid");
|
|
916 return -EINVAL;
|
|
917 }
|
|
918
|
|
919 return(0);
|
|
920 }
|
|
921
|
|
922 int init_module(void)
|
|
923 {
|
|
924 return mga_vid_initialize();
|
|
925 }
|
|
926
|
|
927 void cleanup_module(void)
|
|
928 {
|
48
|
929
|
68
|
930 #ifdef MGA_ALLOW_IRQ
|
48
|
931 if ( mga_irq != -1)
|
|
932 free_irq(mga_irq, &mga_irq);
|
68
|
933 #endif
|
48
|
934
|
1
|
935 if(mga_mmio_base)
|
|
936 iounmap(mga_mmio_base);
|
|
937
|
|
938 //FIXME turn off BES
|
63
|
939 printk(KERN_INFO "mga_vid: Cleaning up module\n");
|
1
|
940 unregister_chrdev(MGA_VID_MAJOR, "mga_vid");
|
|
941 }
|
|
942
|