Mercurial > mplayer.hg
annotate TOOLS/cpuinfo.c @ 18697:2413ca858602
r18697: scaler -> scale typo fix
author | kraymer |
---|---|
date | Tue, 13 Jun 2006 23:28:56 +0000 |
parents | 2d996eb065d4 |
children | 0e2d54a7cb61 |
rev | line source |
---|---|
12960 | 1 /* small utility to extract CPU information |
17041 | 2 Used by configure to set CPU optimization levels on some operating |
3 systems where /proc/cpuinfo is non-existent or unreliable. */ | |
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4 |
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5 #include <stdio.h> |
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6 #include <sys/time.h> |
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7 #include <stdlib.h> |
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8 #include <string.h> |
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9 #include <unistd.h> |
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10 |
9764 | 11 #ifdef __MINGW32__ |
12 #include <sys/timeb.h> | |
17041 | 13 void gettimeofday(struct timeval* t,void* timezone) { |
14 struct timeb timebuffer; | |
15 ftime( &timebuffer ); | |
16 t->tv_sec=timebuffer.time; | |
17 t->tv_usec=1000*timebuffer.millitm; | |
9764 | 18 } |
19 #define MISSING_USLEEP | |
20 #define sleep(t) _sleep(1000*t); | |
21 #endif | |
22 | |
13612 | 23 #ifdef __BEOS__ |
24 #define usleep(t) snooze(t) | |
25 #endif | |
26 | |
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27 #ifdef M_UNIX |
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28 typedef long long int64_t; |
17041 | 29 #define MISSING_USLEEP |
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30 #else |
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31 #include <inttypes.h> |
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32 #endif |
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33 |
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34 |
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35 typedef struct cpuid_regs { |
17041 | 36 unsigned int eax; |
37 unsigned int ebx; | |
38 unsigned int ecx; | |
39 unsigned int edx; | |
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40 } cpuid_regs_t; |
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41 |
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42 static cpuid_regs_t |
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43 cpuid(int func) { |
17041 | 44 cpuid_regs_t regs; |
45 #define CPUID ".byte 0x0f, 0xa2; " | |
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46 #ifdef __x86_64__ |
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47 asm("mov %%rbx, %%rsi\n\t" |
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48 #else |
18517 | 49 asm("mov %%ebx, %%esi\n\t" |
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50 #endif |
18517 | 51 CPUID"\n\t" |
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52 #ifdef __x86_64__ |
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53 "xchg %%rsi, %%rbx\n\t" |
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54 #else |
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55 "xchg %%esi, %%ebx\n\t" |
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56 #endif |
18517 | 57 : "=a" (regs.eax), "=S" (regs.ebx), "=c" (regs.ecx), "=d" (regs.edx) |
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58 : "0" (func)); |
17041 | 59 return regs; |
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60 } |
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61 |
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62 |
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63 static int64_t |
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64 rdtsc(void) |
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65 { |
17041 | 66 unsigned int i, j; |
67 #define RDTSC ".byte 0x0f, 0x31; " | |
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68 asm volatile (RDTSC : "=a"(i), "=d"(j) : ); |
17041 | 69 return ((int64_t)j<<32) + (int64_t)i; |
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70 } |
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71 |
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72 static const char* |
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73 brandname(int i) |
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74 { |
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75 const static char* brandmap[] = { |
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76 NULL, |
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77 "Intel(R) Celeron(R) processor", |
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78 "Intel(R) Pentium(R) III processor", |
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79 "Intel(R) Pentium(R) III Xeon(tm) processor", |
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80 "Intel(R) Pentium(R) III processor", |
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81 NULL, |
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82 "Mobile Intel(R) Pentium(R) III processor-M", |
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83 "Mobile Intel(R) Celeron(R) processor" |
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84 }; |
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85 |
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86 if (i >= sizeof(brandmap)) |
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87 return NULL; |
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88 else |
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89 return brandmap[i]; |
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90 } |
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91 |
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92 static void |
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93 store32(char *d, unsigned int v) |
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94 { |
17041 | 95 d[0] = v & 0xff; |
96 d[1] = (v >> 8) & 0xff; | |
97 d[2] = (v >> 16) & 0xff; | |
98 d[3] = (v >> 24) & 0xff; | |
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99 } |
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100 |
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101 |
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102 int |
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103 main(int argc, char **argv) |
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104 { |
17041 | 105 cpuid_regs_t regs, regs_ext; |
106 char idstr[13]; | |
107 unsigned max_cpuid; | |
108 unsigned max_ext_cpuid; | |
109 unsigned int amd_flags; | |
110 unsigned int amd_flags2; | |
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111 const char *model_name = NULL; |
17041 | 112 int i; |
113 char processor_name[49]; | |
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114 |
17041 | 115 regs = cpuid(0); |
116 max_cpuid = regs.eax; | |
117 /* printf("%d CPUID function codes\n", max_cpuid+1); */ | |
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118 |
17041 | 119 store32(idstr+0, regs.ebx); |
120 store32(idstr+4, regs.edx); | |
121 store32(idstr+8, regs.ecx); | |
122 idstr[12] = 0; | |
123 printf("vendor_id\t: %s\n", idstr); | |
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124 |
17041 | 125 regs_ext = cpuid((1<<31) + 0); |
126 max_ext_cpuid = regs_ext.eax; | |
127 if (max_ext_cpuid >= (1<<31) + 1) { | |
128 regs_ext = cpuid((1<<31) + 1); | |
129 amd_flags = regs_ext.edx; | |
130 amd_flags2 = regs_ext.ecx; | |
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131 |
17041 | 132 if (max_ext_cpuid >= (1<<31) + 4) { |
133 for (i = 2; i <= 4; i++) { | |
134 regs_ext = cpuid((1<<31) + i); | |
135 store32(processor_name + (i-2)*16, regs_ext.eax); | |
136 store32(processor_name + (i-2)*16 + 4, regs_ext.ebx); | |
137 store32(processor_name + (i-2)*16 + 8, regs_ext.ecx); | |
138 store32(processor_name + (i-2)*16 + 12, regs_ext.edx); | |
139 } | |
140 processor_name[48] = 0; | |
141 model_name = processor_name; | |
142 } | |
143 } else { | |
144 amd_flags = 0; | |
145 amd_flags2 = 0; | |
146 } | |
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147 |
17041 | 148 if (max_cpuid >= 1) { |
149 static struct { | |
150 int bit; | |
151 char *desc;; | |
152 char *description; | |
153 } cap[] = { | |
154 { 0, "fpu", "Floating-point unit on-chip" }, | |
155 { 1, "vme", "Virtual Mode Enhancements" }, | |
156 { 2, "de", "Debugging Extension" }, | |
157 { 3, "pse", "Page Size Extension" }, | |
158 { 4, "tsc", "Time Stamp Counter" }, | |
159 { 5, "msr", "Pentium Processor MSR" }, | |
160 { 6, "pae", "Physical Address Extension" }, | |
161 { 7, "mce", "Machine Check Exception" }, | |
162 { 8, "cx8", "CMPXCHG8B Instruction Supported" }, | |
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163 { 9, "apic", "On-chip APIC Hardware Enabled" }, |
17041 | 164 { 11, "sep", "SYSENTER and SYSEXIT" }, |
165 { 12, "mtrr", "Memory Type Range Registers" }, | |
166 { 13, "pge", "PTE Global Bit" }, | |
167 { 14, "mca", "Machine Check Architecture" }, | |
168 { 15, "cmov", "Conditional Move/Compare Instruction" }, | |
169 { 16, "pat", "Page Attribute Table" }, | |
170 { 17, "pse36", "Page Size Extension 36-bit" }, | |
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171 { 18, "pn", "Processor Serial Number" }, |
17041 | 172 { 19, "cflsh", "CFLUSH instruction" }, |
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173 { 21, "dts", "Debug Store" }, |
17041 | 174 { 22, "acpi", "Thermal Monitor and Clock Ctrl" }, |
175 { 23, "mmx", "MMX Technology" }, | |
176 { 24, "fxsr", "FXSAVE/FXRSTOR" }, | |
177 { 25, "sse", "SSE Extensions" }, | |
178 { 26, "sse2", "SSE2 Extensions" }, | |
179 { 27, "ss", "Self Snoop" }, | |
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180 { 28, "ht", "Multi-threading" }, |
17041 | 181 { 29, "tm", "Therm. Monitor" }, |
182 { 30, "ia64", "IA-64 Processor" }, | |
183 { 31, "pbe", "Pend. Brk. EN." }, | |
184 { -1 } | |
185 }; | |
186 static struct { | |
187 int bit; | |
188 char *desc; | |
189 char *description; | |
190 } cap2[] = { | |
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191 { 0, "pni", "SSE3 Extensions" }, |
17041 | 192 { 3, "monitor", "MONITOR/MWAIT" }, |
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193 { 4, "ds_cpl", "CPL Qualified Debug Store" }, |
17041 | 194 { 5, "vmx", "Virtual Machine Extensions" }, |
195 { 7, "est", "Enhanced Intel SpeedStep Technology" }, | |
196 { 8, "tm2", "Thermal Monitor 2" }, | |
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197 { 10, "cid", "L1 Context ID" }, |
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198 { 13, "cx16", "CMPXCHG16B Available" }, |
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199 { 14, "xtpr", "xTPR Disable" }, |
17041 | 200 { -1 } |
201 }; | |
202 static struct { | |
203 int bit; | |
204 char *desc;; | |
205 char *description; | |
206 } cap_amd[] = { | |
207 { 11, "syscall", "SYSCALL and SYSRET" }, | |
208 { 19, "mp", "MP Capable" }, | |
209 { 20, "nx", "No-Execute Page Protection" }, | |
210 { 22, "mmxext","MMX Technology (AMD Extensions)" }, | |
211 { 25, "fxsr_opt", "Fast FXSAVE/FXRSTOR" }, | |
212 { 27, "rdtscp", "RDTSCP Instruction" }, | |
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213 { 29, "lm", "Long Mode Capable" }, |
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214 { 30, "3dnowext","3DNow! Extensions" }, |
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215 { 31, "3dnow", "3DNow!" }, |
17041 | 216 { -1 } |
217 }; | |
218 static struct { | |
219 int bit; | |
220 char *desc; | |
221 char *description; | |
222 } cap_amd2[] = { | |
223 { 0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode" }, | |
224 { 1, "cmp_legacy", "Chip Multi-Core" }, | |
225 { 2, "svm", "Secure Virtual Machine" }, | |
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226 { 4, "cr8legacy", "CR8 Available in Legacy Mode" }, |
17041 | 227 { -1 } |
228 }; | |
229 unsigned int family, model, stepping; | |
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230 |
17041 | 231 regs = cpuid(1); |
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232 family = (regs.eax >> 8) & 0xf; |
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233 model = (regs.eax >> 4) & 0xf; |
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234 stepping = regs.eax & 0xf; |
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235 |
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236 if (family == 0xf) |
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237 { |
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238 family += (regs.eax >> 20) & 0xff; |
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239 model += ((regs.eax >> 16) & 0xf) << 4; |
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240 } |
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241 |
17041 | 242 printf("cpu family\t: %d\n" |
243 "model\t\t: %d\n" | |
244 "stepping\t: %d\n" , | |
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245 family, |
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246 model, |
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247 stepping); |
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248 |
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249 if (strstr(idstr, "Intel") && !model_name) { |
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250 if (family == 6 && model == 0xb && stepping == 1) |
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251 model_name = "Intel (R) Celeron (R) processor"; |
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252 else |
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253 model_name = brandname(regs.ebx & 0xf); |
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254 } |
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255 |
17041 | 256 printf("flags\t\t:"); |
257 for (i = 0; cap[i].bit >= 0; i++) { | |
258 if (regs.edx & (1 << cap[i].bit)) { | |
259 printf(" %s", cap[i].desc); | |
260 } | |
261 } | |
262 for (i = 0; cap2[i].bit >= 0; i++) { | |
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263 if (regs.ecx & (1 << cap2[i].bit)) { |
17041 | 264 printf(" %s", cap2[i].desc); |
265 } | |
266 } | |
267 /* k6_mtrr is supported by some AMD K6-2/K6-III CPUs but | |
268 it is not indicated by a CPUID feature bit, so we | |
269 have to check the family, model and stepping instead. */ | |
270 if (strstr(idstr, "AMD") && | |
271 family == 5 && | |
272 (model >= 9 || model == 8 && stepping >= 8)) | |
273 printf(" %s", "k6_mtrr"); | |
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274 /* similar for cyrix_arr. */ |
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275 if (strstr(idstr, "Cyrix") && |
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276 (family == 5 && model < 4 || family == 6)) |
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277 printf(" %s", "cyrix_arr"); |
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278 /* as well as centaur_mcr. */ |
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279 if (strstr(idstr, "Centaur") && |
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280 family == 5) |
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281 printf(" %s", "centaur_mcr"); |
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282 |
17041 | 283 for (i = 0; cap_amd[i].bit >= 0; i++) { |
284 if (amd_flags & (1 << cap_amd[i].bit)) { | |
285 printf(" %s", cap_amd[i].desc); | |
286 } | |
287 } | |
288 for (i = 0; cap_amd2[i].bit >= 0; i++) { | |
289 if (amd_flags2 & (1 << cap_amd2[i].bit)) { | |
290 printf(" %s", cap_amd2[i].desc); | |
291 } | |
292 } | |
293 printf("\n"); | |
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294 |
17041 | 295 if (regs.edx & (1 << 4)) { |
296 int64_t tsc_start, tsc_end; | |
297 struct timeval tv_start, tv_end; | |
298 int usec_delay; | |
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299 |
17041 | 300 tsc_start = rdtsc(); |
301 gettimeofday(&tv_start, NULL); | |
302 #ifdef MISSING_USLEEP | |
303 sleep(1); | |
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304 #else |
17041 | 305 usleep(100000); |
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306 #endif |
17041 | 307 tsc_end = rdtsc(); |
308 gettimeofday(&tv_end, NULL); | |
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309 |
17041 | 310 usec_delay = 1000000 * (tv_end.tv_sec - tv_start.tv_sec) |
311 + (tv_end.tv_usec - tv_start.tv_usec); | |
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312 |
17041 | 313 printf("cpu MHz\t\t: %.3f\n", |
314 (double)(tsc_end-tsc_start) / usec_delay); | |
315 } | |
316 } | |
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317 |
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318 printf("model name\t: "); |
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319 if (model_name) |
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320 printf("%s\n", model_name); |
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321 else |
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322 printf("Unknown %s CPU\n", idstr); |
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323 } |