Mercurial > mplayer.hg
annotate TOOLS/cpuinfo.c @ 18517:31c96e2b64b4
fix build on macintel, patch by Zuxy Meng
author | gpoirier |
---|---|
date | Mon, 15 May 2006 15:10:23 +0000 |
parents | 744aa553e4a1 |
children | cbcea803efa1 |
rev | line source |
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12960 | 1 /* small utility to extract CPU information |
17041 | 2 Used by configure to set CPU optimization levels on some operating |
3 systems where /proc/cpuinfo is non-existent or unreliable. */ | |
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4 |
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5 #include <stdio.h> |
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6 #include <sys/time.h> |
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7 #include <stdlib.h> |
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8 #include <string.h> |
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9 #include <unistd.h> |
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10 |
9764 | 11 #ifdef __MINGW32__ |
12 #include <sys/timeb.h> | |
17041 | 13 void gettimeofday(struct timeval* t,void* timezone) { |
14 struct timeb timebuffer; | |
15 ftime( &timebuffer ); | |
16 t->tv_sec=timebuffer.time; | |
17 t->tv_usec=1000*timebuffer.millitm; | |
9764 | 18 } |
19 #define MISSING_USLEEP | |
20 #define sleep(t) _sleep(1000*t); | |
21 #endif | |
22 | |
13612 | 23 #ifdef __BEOS__ |
24 #define usleep(t) snooze(t) | |
25 #endif | |
26 | |
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27 #ifdef M_UNIX |
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28 typedef long long int64_t; |
17041 | 29 #define MISSING_USLEEP |
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30 #else |
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31 #include <inttypes.h> |
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32 #endif |
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33 |
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34 |
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35 typedef struct cpuid_regs { |
17041 | 36 unsigned int eax; |
37 unsigned int ebx; | |
38 unsigned int ecx; | |
39 unsigned int edx; | |
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40 } cpuid_regs_t; |
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41 |
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42 static cpuid_regs_t |
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43 cpuid(int func) { |
17041 | 44 cpuid_regs_t regs; |
45 #define CPUID ".byte 0x0f, 0xa2; " | |
18517 | 46 asm("mov %%ebx, %%esi\n\t" |
47 CPUID"\n\t" | |
48 "xchg %%esi, %%ebx" | |
49 : "=a" (regs.eax), "=S" (regs.ebx), "=c" (regs.ecx), "=d" (regs.edx) | |
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50 : "0" (func)); |
17041 | 51 return regs; |
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52 } |
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53 |
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54 |
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55 static int64_t |
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56 rdtsc(void) |
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57 { |
17041 | 58 unsigned int i, j; |
59 #define RDTSC ".byte 0x0f, 0x31; " | |
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60 asm volatile (RDTSC : "=a"(i), "=d"(j) : ); |
17041 | 61 return ((int64_t)j<<32) + (int64_t)i; |
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62 } |
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63 |
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64 static const char* |
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65 brandname(int i) |
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66 { |
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67 const static char* brandmap[] = { |
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68 NULL, |
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69 "Intel(R) Celeron(R) processor", |
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70 "Intel(R) Pentium(R) III processor", |
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71 "Intel(R) Pentium(R) III Xeon(tm) processor", |
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72 "Intel(R) Pentium(R) III processor", |
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73 NULL, |
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74 "Mobile Intel(R) Pentium(R) III processor-M", |
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75 "Mobile Intel(R) Celeron(R) processor" |
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76 }; |
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77 |
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78 if (i >= sizeof(brandmap)) |
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79 return NULL; |
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80 else |
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81 return brandmap[i]; |
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82 } |
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83 |
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84 static void |
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85 store32(char *d, unsigned int v) |
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86 { |
17041 | 87 d[0] = v & 0xff; |
88 d[1] = (v >> 8) & 0xff; | |
89 d[2] = (v >> 16) & 0xff; | |
90 d[3] = (v >> 24) & 0xff; | |
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91 } |
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92 |
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93 |
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94 int |
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95 main(int argc, char **argv) |
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96 { |
17041 | 97 cpuid_regs_t regs, regs_ext; |
98 char idstr[13]; | |
99 unsigned max_cpuid; | |
100 unsigned max_ext_cpuid; | |
101 unsigned int amd_flags; | |
102 unsigned int amd_flags2; | |
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103 const char *model_name = NULL; |
17041 | 104 int i; |
105 char processor_name[49]; | |
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106 |
17041 | 107 regs = cpuid(0); |
108 max_cpuid = regs.eax; | |
109 /* printf("%d CPUID function codes\n", max_cpuid+1); */ | |
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110 |
17041 | 111 store32(idstr+0, regs.ebx); |
112 store32(idstr+4, regs.edx); | |
113 store32(idstr+8, regs.ecx); | |
114 idstr[12] = 0; | |
115 printf("vendor_id\t: %s\n", idstr); | |
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116 |
17041 | 117 regs_ext = cpuid((1<<31) + 0); |
118 max_ext_cpuid = regs_ext.eax; | |
119 if (max_ext_cpuid >= (1<<31) + 1) { | |
120 regs_ext = cpuid((1<<31) + 1); | |
121 amd_flags = regs_ext.edx; | |
122 amd_flags2 = regs_ext.ecx; | |
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123 |
17041 | 124 if (max_ext_cpuid >= (1<<31) + 4) { |
125 for (i = 2; i <= 4; i++) { | |
126 regs_ext = cpuid((1<<31) + i); | |
127 store32(processor_name + (i-2)*16, regs_ext.eax); | |
128 store32(processor_name + (i-2)*16 + 4, regs_ext.ebx); | |
129 store32(processor_name + (i-2)*16 + 8, regs_ext.ecx); | |
130 store32(processor_name + (i-2)*16 + 12, regs_ext.edx); | |
131 } | |
132 processor_name[48] = 0; | |
133 model_name = processor_name; | |
134 } | |
135 } else { | |
136 amd_flags = 0; | |
137 amd_flags2 = 0; | |
138 } | |
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139 |
17041 | 140 if (max_cpuid >= 1) { |
141 static struct { | |
142 int bit; | |
143 char *desc;; | |
144 char *description; | |
145 } cap[] = { | |
146 { 0, "fpu", "Floating-point unit on-chip" }, | |
147 { 1, "vme", "Virtual Mode Enhancements" }, | |
148 { 2, "de", "Debugging Extension" }, | |
149 { 3, "pse", "Page Size Extension" }, | |
150 { 4, "tsc", "Time Stamp Counter" }, | |
151 { 5, "msr", "Pentium Processor MSR" }, | |
152 { 6, "pae", "Physical Address Extension" }, | |
153 { 7, "mce", "Machine Check Exception" }, | |
154 { 8, "cx8", "CMPXCHG8B Instruction Supported" }, | |
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155 { 9, "apic", "On-chip APIC Hardware Enabled" }, |
17041 | 156 { 11, "sep", "SYSENTER and SYSEXIT" }, |
157 { 12, "mtrr", "Memory Type Range Registers" }, | |
158 { 13, "pge", "PTE Global Bit" }, | |
159 { 14, "mca", "Machine Check Architecture" }, | |
160 { 15, "cmov", "Conditional Move/Compare Instruction" }, | |
161 { 16, "pat", "Page Attribute Table" }, | |
162 { 17, "pse36", "Page Size Extension 36-bit" }, | |
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163 { 18, "pn", "Processor Serial Number" }, |
17041 | 164 { 19, "cflsh", "CFLUSH instruction" }, |
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165 { 21, "dts", "Debug Store" }, |
17041 | 166 { 22, "acpi", "Thermal Monitor and Clock Ctrl" }, |
167 { 23, "mmx", "MMX Technology" }, | |
168 { 24, "fxsr", "FXSAVE/FXRSTOR" }, | |
169 { 25, "sse", "SSE Extensions" }, | |
170 { 26, "sse2", "SSE2 Extensions" }, | |
171 { 27, "ss", "Self Snoop" }, | |
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172 { 28, "ht", "Multi-threading" }, |
17041 | 173 { 29, "tm", "Therm. Monitor" }, |
174 { 30, "ia64", "IA-64 Processor" }, | |
175 { 31, "pbe", "Pend. Brk. EN." }, | |
176 { -1 } | |
177 }; | |
178 static struct { | |
179 int bit; | |
180 char *desc; | |
181 char *description; | |
182 } cap2[] = { | |
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183 { 0, "pni", "SSE3 Extensions" }, |
17041 | 184 { 3, "monitor", "MONITOR/MWAIT" }, |
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185 { 4, "ds_cpl", "CPL Qualified Debug Store" }, |
17041 | 186 { 5, "vmx", "Virtual Machine Extensions" }, |
187 { 7, "est", "Enhanced Intel SpeedStep Technology" }, | |
188 { 8, "tm2", "Thermal Monitor 2" }, | |
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189 { 10, "cid", "L1 Context ID" }, |
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190 { 13, "cx16", "CMPXCHG16B Available" }, |
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191 { 14, "xtpr", "xTPR Disable" }, |
17041 | 192 { -1 } |
193 }; | |
194 static struct { | |
195 int bit; | |
196 char *desc;; | |
197 char *description; | |
198 } cap_amd[] = { | |
199 { 11, "syscall", "SYSCALL and SYSRET" }, | |
200 { 19, "mp", "MP Capable" }, | |
201 { 20, "nx", "No-Execute Page Protection" }, | |
202 { 22, "mmxext","MMX Technology (AMD Extensions)" }, | |
203 { 25, "fxsr_opt", "Fast FXSAVE/FXRSTOR" }, | |
204 { 27, "rdtscp", "RDTSCP Instruction" }, | |
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205 { 29, "lm", "Long Mode Capable" }, |
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206 { 30, "3dnowext","3DNow! Extensions" }, |
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207 { 31, "3dnow", "3DNow!" }, |
17041 | 208 { -1 } |
209 }; | |
210 static struct { | |
211 int bit; | |
212 char *desc; | |
213 char *description; | |
214 } cap_amd2[] = { | |
215 { 0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode" }, | |
216 { 1, "cmp_legacy", "Chip Multi-Core" }, | |
217 { 2, "svm", "Secure Virtual Machine" }, | |
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218 { 4, "cr8legacy", "CR8 Available in Legacy Mode" }, |
17041 | 219 { -1 } |
220 }; | |
221 unsigned int family, model, stepping; | |
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222 |
17041 | 223 regs = cpuid(1); |
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224 family = (regs.eax >> 8) & 0xf; |
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225 model = (regs.eax >> 4) & 0xf; |
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226 stepping = regs.eax & 0xf; |
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227 |
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228 if (family == 0xf) |
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229 { |
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230 family += (regs.eax >> 20) & 0xff; |
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231 model += ((regs.eax >> 16) & 0xf) << 4; |
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232 } |
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233 |
17041 | 234 printf("cpu family\t: %d\n" |
235 "model\t\t: %d\n" | |
236 "stepping\t: %d\n" , | |
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237 family, |
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238 model, |
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239 stepping); |
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240 |
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241 if (strstr(idstr, "Intel") && !model_name) { |
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242 if (family == 6 && model == 0xb && stepping == 1) |
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243 model_name = "Intel (R) Celeron (R) processor"; |
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244 else |
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245 model_name = brandname(regs.ebx & 0xf); |
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246 } |
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247 |
17041 | 248 printf("flags\t\t:"); |
249 for (i = 0; cap[i].bit >= 0; i++) { | |
250 if (regs.edx & (1 << cap[i].bit)) { | |
251 printf(" %s", cap[i].desc); | |
252 } | |
253 } | |
254 for (i = 0; cap2[i].bit >= 0; i++) { | |
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255 if (regs.ecx & (1 << cap2[i].bit)) { |
17041 | 256 printf(" %s", cap2[i].desc); |
257 } | |
258 } | |
259 /* k6_mtrr is supported by some AMD K6-2/K6-III CPUs but | |
260 it is not indicated by a CPUID feature bit, so we | |
261 have to check the family, model and stepping instead. */ | |
262 if (strstr(idstr, "AMD") && | |
263 family == 5 && | |
264 (model >= 9 || model == 8 && stepping >= 8)) | |
265 printf(" %s", "k6_mtrr"); | |
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266 /* similar for cyrix_arr. */ |
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267 if (strstr(idstr, "Cyrix") && |
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268 (family == 5 && model < 4 || family == 6)) |
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269 printf(" %s", "cyrix_arr"); |
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270 |
17041 | 271 for (i = 0; cap_amd[i].bit >= 0; i++) { |
272 if (amd_flags & (1 << cap_amd[i].bit)) { | |
273 printf(" %s", cap_amd[i].desc); | |
274 } | |
275 } | |
276 for (i = 0; cap_amd2[i].bit >= 0; i++) { | |
277 if (amd_flags2 & (1 << cap_amd2[i].bit)) { | |
278 printf(" %s", cap_amd2[i].desc); | |
279 } | |
280 } | |
281 printf("\n"); | |
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282 |
17041 | 283 if (regs.edx & (1 << 4)) { |
284 int64_t tsc_start, tsc_end; | |
285 struct timeval tv_start, tv_end; | |
286 int usec_delay; | |
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287 |
17041 | 288 tsc_start = rdtsc(); |
289 gettimeofday(&tv_start, NULL); | |
290 #ifdef MISSING_USLEEP | |
291 sleep(1); | |
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292 #else |
17041 | 293 usleep(100000); |
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294 #endif |
17041 | 295 tsc_end = rdtsc(); |
296 gettimeofday(&tv_end, NULL); | |
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297 |
17041 | 298 usec_delay = 1000000 * (tv_end.tv_sec - tv_start.tv_sec) |
299 + (tv_end.tv_usec - tv_start.tv_usec); | |
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300 |
17041 | 301 printf("cpu MHz\t\t: %.3f\n", |
302 (double)(tsc_end-tsc_start) / usec_delay); | |
303 } | |
304 } | |
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305 |
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306 printf("model name\t: "); |
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307 if (model_name) |
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308 printf("%s\n", model_name); |
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309 else |
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310 printf("Unknown %s CPU\n", idstr); |
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311 } |