10954
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1 /*
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2 nvidia_vid - VIDIX based video driver for NVIDIA chips
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3 Copyrights 2003 Sascha Sommer. This file is based on sources from
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4 RIVATV (rivatv.sf.net)
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5 Licence: GPL
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6 WARNING: THIS DRIVER IS IN BETTA STAGE
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7
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8 multi buffer support, TNT2 fixes and experimental yv12 support by Dmitry Baryshkov
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9 */
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10
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11
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12 #include <errno.h>
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13 #include <stdio.h>
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14 #include <stdlib.h>
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15 #include <string.h>
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16 #include <inttypes.h>
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17 #include <unistd.h>
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18
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19
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20 #include "../vidix.h"
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21 #include "../fourcc.h"
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22 #include "../../libdha/libdha.h"
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23 #include "../../libdha/pci_ids.h"
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24 #include "../../libdha/pci_names.h"
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25 #include "../../config.h"
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26 #include "../../bswap.h"
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27
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28
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29 pciinfo_t pci_info;
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30
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31
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32 #define MAX_FRAMES 3
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33 #define NV04_BES_SIZE 1024*2000*4
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34
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35
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36 static vidix_capability_t nvidia_cap = {
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37 "NVIDIA RIVA OVERLAY DRIVER",
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38 "Sascha Sommer <saschasommer@freenet.de>",
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39 TYPE_OUTPUT,
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40 { 0, 0, 0, 0 },
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41 2048,
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42 2048,
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43 4,
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44 4,
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45 -1,
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46 FLAG_UPSCALER|FLAG_DOWNSCALER,
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47 VENDOR_NVIDIA2,
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48 -1,
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49 { 0, 0, 0, 0 }
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50 };
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51
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52
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53 unsigned int vixGetVersion(void){
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54 return(VIDIX_VERSION);
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55 }
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56
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57
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58 #define NV_ARCH_03 0x03
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59 #define NV_ARCH_04 0x04
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60 #define NV_ARCH_10 0x10
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61 #define NV_ARCH_20 0x20
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62 #define NV_ARCH_30 0x30
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63
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64 struct nvidia_cards {
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65 unsigned short chip_id;
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66 unsigned short arch;
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67 };
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68
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69
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70 static struct nvidia_cards nvidia_card_ids[] = {
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71 /*tested && working*/
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72 {DEVICE_NVIDIA2_RIVA128, NV_ARCH_03},
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73 {DEVICE_NVIDIA_RIVA_TNT2_MODEL,NV_ARCH_04},
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74 {DEVICE_NVIDIA2_VTNT2,NV_ARCH_04},
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75 {DEVICE_NVIDIA_NV11_GEFORCE2_MX,NV_ARCH_10},
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76 /*untested*/
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77 {DEVICE_NVIDIA2_RIVA128ZX,NV_ARCH_03},
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78 {DEVICE_NVIDIA2_TNT,NV_ARCH_04},
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79 {DEVICE_NVIDIA2_TNT2,NV_ARCH_04},
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80 {DEVICE_NVIDIA2_UTNT2 ,NV_ARCH_04},
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81 {DEVICE_NVIDIA2_ITNT2,NV_ARCH_04},
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82 {DEVICE_NVIDIA_NV5_RIVA_TNT2,NV_ARCH_04},
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83 };
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84
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85
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86 static int find_chip(unsigned chip_id){
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87 unsigned i;
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88 for(i = 0;i < sizeof(nvidia_card_ids)/sizeof(struct nvidia_cards);i++)
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89 {
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90 if(chip_id == nvidia_card_ids[i].chip_id)return i;
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91 }
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92 return -1;
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93 }
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94
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95 int vixProbe(int verbose, int force){
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96 pciinfo_t lst[MAX_PCI_DEVICES];
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97 unsigned i,num_pci;
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98 int err;
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99
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100 if (force)
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101 printf("[nvidia_vid]: warning: forcing not supported yet!\n");
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102 err = pci_scan(lst,&num_pci);
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103 if(err){
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104 printf("[nvidia_vid] Error occured during pci scan: %s\n",strerror(err));
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105 return err;
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106 }
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107 else {
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108 err = ENXIO;
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109 for(i=0; i < num_pci; i++){
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110 if(lst[i].vendor == VENDOR_NVIDIA2 || lst[i].vendor == VENDOR_NVIDIA){
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111 int idx;
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112 const char *dname;
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113 idx = find_chip(lst[i].device);
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114 if(idx == -1)
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115 continue;
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116 dname = pci_device_name(lst[i].vendor, lst[i].device);
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117 dname = dname ? dname : "Unknown chip";
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118 printf("[nvidia_vid] Found chip: %s\n", dname);
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119 if ((lst[i].command & PCI_COMMAND_IO) == 0){
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120 printf("[nvidia_vid] Device is disabled, ignoring\n");
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121 continue;
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122 }
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123 nvidia_cap.device_id = lst[i].device;
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124 err = 0;
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125 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));
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126 break;
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127 }
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128 }
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129 }
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130 if(err && verbose) printf("[nvidia_vid] Can't find chip\n");
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131 return err;
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132 }
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133
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134
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135
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136
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137 /*
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138 * PCI-Memory IO access macros.
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139 */
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140 #define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val))
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141 #define VID_RD08(p,i) (((uint8_t *)(p))[(i)])
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142
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143 #define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val))
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144 #define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4])
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145
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146 #ifndef USE_RMW_CYCLES
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147 /*
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148 * Can be used to inhibit READ-MODIFY-WRITE cycles. On by default.
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149 */
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150
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151 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory")
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152
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153 #undef VID_WR08
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154 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); })
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155 #undef VID_RD08
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156 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; })
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157
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158 #undef VID_WR32
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159 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); })
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160 #undef VID_RD32
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161 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; })
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162 #endif /* USE_RMW_CYCLES */
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163
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164 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val))
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165 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val))
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166 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val))
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167
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168
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169
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170
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171
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172
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173 struct rivatv_chip {
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174 volatile uint32_t *PMC; /* general control */
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175 volatile uint32_t *PME; /* multimedia port */
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176 volatile uint32_t *PFB; /* framebuffer control */
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177 volatile uint32_t *PVIDEO; /* overlay control */
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178 volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */
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179 volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */
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180 volatile uint32_t *PRAMIN; /* instance memory */
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181 volatile uint32_t *PRAMHT; /* hash table */
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182 volatile uint32_t *PRAMFC; /* fifo context table */
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183 volatile uint32_t *PRAMRO; /* fifo runout table */
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184 volatile uint32_t *PFIFO; /* fifo control region */
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185 volatile uint32_t *FIFO; /* fifo channels (USER) */
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186 volatile uint32_t *PGRAPH; /* graphics engine */
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187
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188 unsigned long fbsize; /* framebuffer size */
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189 int arch; /* compatible NV_ARCH_XX define */
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190 int realarch; /* real architecture */
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191 void (* lock) (struct rivatv_chip *, int);
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192 };
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193 typedef struct rivatv_chip rivatv_chip;
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194
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195
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196 struct rivatv_info {
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197 unsigned int colorkey; /* saved xv colorkey*/
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198 unsigned int vidixcolorkey; /*currently used colorkey*/
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199 unsigned int depth;
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200 unsigned int format;
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201 unsigned int pitch;
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202 unsigned int width,height;
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203 unsigned int d_width,d_height; /*scaled width && height*/
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204 unsigned int wx,wy; /*window x && y*/
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205 unsigned int screen_x; /*screen width*/
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206 unsigned long buffer_size; /* size of the image buffer */
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207 struct rivatv_chip chip; /* NV architecture structure */
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208 void* video_base; /* virtual address of control region */
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209 void* control_base; /* virtual address of fb region */
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210 unsigned long picture_base; /* direct pointer to video picture */
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211 unsigned long picture_offset; /* offset of video picture in frame buffer */
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212 // struct rivatv_dma dma; /* DMA structure */
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213 unsigned int next_frame;
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214 unsigned int num_frames; /* number of buffers */
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215 };
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216 typedef struct rivatv_info rivatv_info;
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217
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218 //framebuffer size funcs
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219 static unsigned long rivatv_fbsize_nv03 (struct rivatv_chip *chip){
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220 if (VID_RD32 (chip->PFB, 0) & 0x00000020) {
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221 if (((VID_RD32 (chip->PMC, 0) & 0xF0) == 0x20)
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222 && ((VID_RD32 (chip->PMC, 0) & 0x0F) >= 0x02)) {
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223 /* SDRAM 128 ZX. */
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224 return ((1 << (VID_RD32 (chip->PFB, 0) & 0x03)) * 1024 * 1024);
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225 }
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226 else {
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227 return 1024 * 1024 * 8;
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228 }
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229 }
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230 else {
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231 /* SGRAM 128. */
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232 switch (chip->PFB[0x00000000] & 0x00000003) {
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233 case 0:
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234 return 1024 * 1024 * 8;
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235 break;
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236 case 2:
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237 return 1024 * 1024 * 4;
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238 break;
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239 default:
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240 return 1024 * 1024 * 2;
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241 break;
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242 }
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243 }
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244 }
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245 static unsigned long rivatv_fbsize_nv04 (struct rivatv_chip *chip){
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246 if (VID_RD32 (chip->PFB, 0) & 0x00000100) {
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247 return ((VID_RD32 (chip->PFB, 0) >> 12) & 0x0F) * 1024 * 1024 * 2
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248 + 1024 * 1024 * 2;
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249 } else {
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250 switch (VID_RD32 (chip->PFB, 0) & 0x00000003) {
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251 case 0:
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252 return 1024 * 1024 * 32;
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253 break;
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254 case 1:
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255 return 1024 * 1024 * 4;
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256 break;
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257 case 2:
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258 return 1024 * 1024 * 8;
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259 break;
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260 case 3:
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261 default:
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262 return 1024 * 1024 * 16;
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263 break;
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264 }
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265 }
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266 }
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267
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268 static unsigned long rivatv_fbsize_nv10 (struct rivatv_chip *chip){
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269 return ((VID_RD32 (chip->PFB, 0x20C) >> 20) & 0x000000FF) * 1024 * 1024;
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270 }
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271
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272 //lock funcs
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273 static void rivatv_lock_nv03 (struct rivatv_chip *chip, int LockUnlock){
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274 VID_WR08 (chip->PVIO, 0x3C4, 0x06);
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275 VID_WR08 (chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57);
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276 }
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277
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278 static void rivatv_lock_nv04 (struct rivatv_chip *chip, int LockUnlock){
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279 VID_WR08 (chip->PCIO, 0x3C4, 0x06);
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280 VID_WR08 (chip->PCIO, 0x3C5, LockUnlock ? 0x99 : 0x57);
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281 VID_WR08 (chip->PCIO, 0x3D4, 0x1F);
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282 VID_WR08 (chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57);
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283 }
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284
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285
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286
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287
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288 /* Enable PFB (Framebuffer), PVIDEO (Overlay unit) and PME (Mediaport) if neccessary. */
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289 static void rivatv_enable_PMEDIA (struct rivatv_info *info){
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290 uint32_t reg;
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291
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292 /* switch off interrupts once for a while */
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293 // VID_WR32 (info->chip.PME, 0x200140, 0x00);
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294 // VID_WR32 (info->chip.PMC, 0x000140, 0x00);
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295
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296 reg = VID_RD32 (info->chip.PMC, 0x000200);
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297
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298 /* NV3 (0x10100010): NV03_PMC_ENABLE_PMEDIA, NV03_PMC_ENABLE_PFB, NV03_PMC_ENABLE_PVIDEO */
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299
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300 if ((reg & 0x10100010) != 0x10100010) {
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301 printf("PVIDEO and PFB disabled, enabling...\n");
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302 VID_OR32 (info->chip.PMC, 0x000200, 0x10100010);
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303 }
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304
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305 /* save the current colorkey */
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306 switch (info->chip.arch ) {
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307 case NV_ARCH_10:
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308 case NV_ARCH_20:
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309 case NV_ARCH_30:
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310 /* NV_PVIDEO_COLOR_KEY */
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311 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0xB00);
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312 break;
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313 case NV_ARCH_03:
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314 case NV_ARCH_04:
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315 /* NV_PVIDEO_KEY */
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316 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0x240);
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317 break;
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318 }
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319
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320
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321 /* re-enable interrupts again */
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322 // VID_WR32 (info->chip.PMC, 0x000140, 0x01);
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323 // VID_WR32 (info->chip.PME, 0x200140, 0x01);
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324 }
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325
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326 /* Stop overlay video. */
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327 void rivatv_overlay_stop (struct rivatv_info *info) {
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328 switch (info->chip.arch ) {
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329 case NV_ARCH_10:
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330 case NV_ARCH_20:
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331 case NV_ARCH_30:
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332 /* NV_PVIDEO_COLOR_KEY */
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333 /* Xv-Extension-Hack: Restore previously saved value. */
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334 VID_WR32 (info->chip.PVIDEO, 0xB00, info->colorkey);
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335 /* NV_PVIDEO_STOP */
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336 VID_OR32 (info->chip.PVIDEO, 0x704, 0x11);
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337 /* NV_PVIDEO_BUFFER */
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338 VID_AND32 (info->chip.PVIDEO, 0x700, ~0x11);
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339 /* NV_PVIDEO_INTR_EN_BUFFER */
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340 VID_AND32 (info->chip.PVIDEO, 0x140, ~0x11);
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341 break;
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342 case NV_ARCH_03:
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343 case NV_ARCH_04:
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344 /* NV_PVIDEO_KEY */
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345 VID_WR32 (info->chip.PVIDEO, 0x240, info->colorkey);
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346 /* NV_PVIDEO_OVERLAY_VIDEO_OFF */
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347 VID_AND32 (info->chip.PVIDEO, 0x244, ~0x01);
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348 /* NV_PVIDEO_INTR_EN_0_NOTIFY */
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349 VID_AND32 (info->chip.PVIDEO, 0x140, ~0x01);
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350 /* NV_PVIDEO_OE_STATE */
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351 VID_WR32 (info->chip.PVIDEO, 0x224, 0);
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352 /* NV_PVIDEO_SU_STATE */
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353 VID_WR32 (info->chip.PVIDEO, 0x228, 0);
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354 /* NV_PVIDEO_RM_STATE */
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355 VID_WR32 (info->chip.PVIDEO, 0x22C, 0);
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356 break;
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357 }
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358 }
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359
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360 /* Get pan offset of the physical screen. */
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361 static uint32_t rivatv_overlay_pan (struct rivatv_info *info){
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362 uint32_t pan;
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363 info->chip.lock (&info->chip, 0);
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364 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0D);
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365 pan = VID_RD08 (info->chip.PCIO, 0x3D5);
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366 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0C);
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367 pan |= VID_RD08 (info->chip.PCIO, 0x3D5) << 8;
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368 VID_WR08 (info->chip.PCIO, 0x3D4, 0x19);
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369 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x1F) << 16;
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370 VID_WR08 (info->chip.PCIO, 0x3D4, 0x2D);
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371 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x60) << 16;
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372 return pan << 2;
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373 }
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374
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375 /* Compute and set colorkey depending on the colour depth. */
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376 static void rivatv_overlay_colorkey (rivatv_info* info, unsigned int chromakey){
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377 uint32_t r, g, b, key = 0;
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378 r = (chromakey & 0x00FF0000) >> 16;
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379 g = (chromakey & 0x0000FF00) >> 8;
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380 b = chromakey & 0x000000FF;
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381 switch (info->depth) {
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382 case 15:
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383 key = ((r >> 3) << 10) | ((g >> 3) << 5) | ((b >> 3));
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384 break;
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385 case 16:
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386 key = ((r >> 3) << 11) | ((g >> 2) << 5) | ((b >> 3));
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387 break;
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388 case 24:
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389 key = chromakey & 0x00FFFFFF;
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390 break;
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391 case 32:
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392 key = chromakey;
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393 break;
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394 default:
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395 /* THINKME: Possible to pass a colour index for 8 bpp ? */
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396 printf ("invalid color depth: %d bpp\n", info->depth);
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397 break;
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398 }
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399 switch (info->chip.arch) {
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400 case NV_ARCH_10:
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401 case NV_ARCH_20:
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402 case NV_ARCH_30:
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403 VID_WR32 (info->chip.PVIDEO, 0xB00, key);
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404 break;
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405 case NV_ARCH_03:
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406 case NV_ARCH_04:
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407 VID_WR32 (info->chip.PVIDEO, 0x240, key);
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408 break;
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409 }
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410 }
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411
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412
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413 /* Start overlay video. */
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414 void rivatv_overlay_start (struct rivatv_info *info,int bufno){
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415 uint32_t base, size, offset, xscale, yscale, pan,bpp, pitch0=0;
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416 int x, y;
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417 int lwidth=info->d_width, lheight=info->d_height;
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418 int bps;
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419
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420 /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/
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421 info->chip.lock (&info->chip, 0);
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422 switch (info->chip.arch) {
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423 case NV_ARCH_03:
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424 pitch0 = info->chip.PGRAPH[0x00000650/4];
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425 break;
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426 case NV_ARCH_04:
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427 case NV_ARCH_10:
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428 case NV_ARCH_20:
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429 case NV_ARCH_30:
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430 pitch0 = info->chip.PGRAPH[0x00000670/4];
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431 break;
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432 }
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433 VID_WR08(info->chip.PCIO, 0x03D4, 0x28);
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434 bpp = VID_RD08(info->chip.PCIO,0x03D5);
|
|
435 if(bpp==3)bpp = 4; //fixme do nvidia cards support 24bpp?
|
|
436 if((bpp == 2) && (info->chip.PVIDEO[0x00000600/4] & 0x00001000) == 0x0)info->depth=15; //0x00101100 for BGR16
|
|
437 else info->depth = bpp*8;
|
|
438 if(!bpp)printf("[nvidia_vid] error invalid bpp\n");
|
|
439 else
|
|
440 {
|
|
441 // printf("[nvidia_vid] video mode: %ux%u@%u\n",screen_x = pitch0/bpp,(pitch0/bpp*3)/4,info->depth);
|
|
442 info->screen_x = pitch0/bpp;
|
|
443 }
|
|
444
|
|
445 bps = info->screen_x * ((info->depth+1)/8);
|
|
446 /* get pan offset of the physical screen */
|
|
447 pan = rivatv_overlay_pan (info);
|
|
448 size = info->buffer_size;
|
|
449 /* adjust window position depending on the pan offset */
|
|
450 x = info->wx - (pan % bps) * 8 / info->depth;
|
|
451 y = info->wy - (pan / bps);
|
|
452
|
|
453 base = info->picture_offset;
|
|
454 offset = bufno*size;
|
|
455
|
|
456 /* adjust negative output window variables */
|
|
457 if (x < 0) {
|
|
458 lwidth = info->d_width + x;
|
|
459 offset += (-x * info->width / info->d_width) << 1;
|
|
460 // offset += (-window->x * port->vld_width / window->width) << 1;
|
|
461 x = 0;
|
|
462 }
|
|
463 if (y < 0) {
|
|
464 lheight = info->d_height + y;
|
|
465 offset += (-y * info->height / info->d_height * info->width) << 1;
|
|
466 // offset += (-window->y * port->vld_height / window->height * port->org_width) << 1;
|
|
467 y = 0;
|
|
468 }
|
|
469
|
|
470 switch (info->chip.arch) {
|
|
471 case NV_ARCH_10:
|
|
472 case NV_ARCH_20:
|
|
473 case NV_ARCH_30:
|
|
474
|
|
475 /* NV_PVIDEO_BASE */
|
|
476 VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base);
|
|
477 //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base);
|
|
478 /* NV_PVIDEO_LIMIT */
|
|
479 VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + size - 1);
|
|
480 //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1);
|
|
481
|
|
482 /* extra code for NV20 && NV30 architectures */
|
|
483 if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30) {
|
|
484 VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base);
|
|
485 //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base);
|
|
486 VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + size - 1);
|
|
487 //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1);
|
|
488 }
|
|
489
|
|
490 /* NV_PVIDEO_LUMINANCE */
|
|
491 VID_WR32 (info->chip.PVIDEO, 0x910 + 0, 0x00001000);
|
|
492 //VID_WR32 (info->chip.PVIDEO, 0x910 + 4, 0x00001000);
|
|
493 /* NV_PVIDEO_CHROMINANCE */
|
|
494 VID_WR32 (info->chip.PVIDEO, 0x918 + 0, 0x00001000);
|
|
495 //VID_WR32 (info->chip.PVIDEO, 0x918 + 4, 0x00001000);
|
|
496
|
|
497 /* NV_PVIDEO_OFFSET */
|
|
498 VID_WR32 (info->chip.PVIDEO, 0x920 + 0, offset + 0);
|
|
499 //VID_WR32 (info->chip.PVIDEO, 0x920 + 4, offset + pitch);
|
|
500 /* NV_PVIDEO_SIZE_IN */
|
|
501 VID_WR32 (info->chip.PVIDEO, 0x928 + 0, ((info->height) << 16) | info->width);
|
|
502 //VID_WR32 (info->chip.PVIDEO, 0x928 + 4, ((port->org_height/2) << 16) | port->org_width);
|
|
503 /* NV_PVIDEO_POINT_IN */
|
|
504 VID_WR32 (info->chip.PVIDEO, 0x930 + 0, 0x00000000);
|
|
505 //VID_WR32 (info->chip.PVIDEO, 0x930 + 4, 0x00000000);
|
|
506 /* NV_PVIDEO_DS_DX_RATIO */
|
|
507 VID_WR32 (info->chip.PVIDEO, 0x938 + 0, (info->width << 20) / info->d_width);
|
|
508 //VID_WR32 (info->chip.PVIDEO, 0x938 + 4, (port->org_width << 20) / window->width);
|
|
509 /* NV_PVIDEO_DT_DY_RATIO */
|
|
510 VID_WR32 (info->chip.PVIDEO, 0x940 + 0, ((info->height) << 20) / info->d_height);
|
|
511 //VID_WR32 (info->chip.PVIDEO, 0x940 + 4, ((port->org_height/2) << 20) / window->height);
|
|
512
|
|
513 /* NV_PVIDEO_POINT_OUT */
|
|
514 VID_WR32 (info->chip.PVIDEO, 0x948 + 0, ((y + 0) << 16) | x);
|
|
515 //VID_WR32 (info->chip.PVIDEO, 0x948 + 4, ((y + 0) << 16) | x);
|
|
516 /* NV_PVIDEO_SIZE_OUT */
|
|
517 VID_WR32 (info->chip.PVIDEO, 0x950 + 0, (lheight << 16) | lwidth);
|
|
518 //VID_WR32 (info->chip.PVIDEO, 0x950 + 4, (height << 16) | width);
|
|
519
|
|
520 /* NV_PVIDEO_FORMAT */
|
|
521 VID_WR32 (info->chip.PVIDEO, 0x958 + 0, (info->pitch << 0) | 0x00100000|(((info->format==IMGFMT_YV12)?1:0))<<16);
|
|
522 //VID_WR32 (info->chip.PVIDEO, 0x958 + 4, (pitch << 1) | 0x00100000);
|
|
523
|
|
524 /* NV_PVIDEO_INTR_EN_BUFFER */
|
|
525 VID_OR32 (info->chip.PVIDEO, 0x140, 0x01/*0x11*/);
|
|
526 /* NV_PVIDEO_STOP */
|
|
527 VID_AND32 (info->chip.PVIDEO, 0x704, 0xFFFFFFEE);
|
|
528 /* NV_PVIDEO_BUFFER */
|
|
529 VID_OR32 (info->chip.PVIDEO, 0x700, 0x01/*0x11*/);
|
|
530 break;
|
|
531
|
|
532 case NV_ARCH_03:
|
|
533 case NV_ARCH_04:
|
|
534
|
|
535
|
|
536 /* NV_PVIDEO_OE_STATE */
|
|
537 VID_WR32 (info->chip.PVIDEO, 0x224, 0);
|
|
538 /* NV_PVIDEO_SU_STATE */
|
|
539 VID_WR32 (info->chip.PVIDEO, 0x228, 0);
|
|
540 /* NV_PVIDEO_RM_STATE */
|
|
541 VID_WR32 (info->chip.PVIDEO, 0x22C, 0);
|
|
542
|
|
543 /* NV_PVIDEO_BUFF0_START_ADDRESS */
|
|
544 VID_WR32 (info->chip.PVIDEO, 0x20C + 0, base + offset + 0);
|
|
545 VID_WR32 (info->chip.PVIDEO, 0x20C + 4, base + offset + 0);
|
|
546 /* NV_PVIDEO_BUFF0_PITCH_LENGTH */
|
|
547 VID_WR32 (info->chip.PVIDEO, 0x214 + 0, info->pitch);
|
|
548 VID_WR32 (info->chip.PVIDEO, 0x214 + 4, info->pitch);
|
|
549
|
|
550 /* NV_PVIDEO_WINDOW_START */
|
|
551 VID_WR32 (info->chip.PVIDEO, 0x230, (y << 16) | x);
|
|
552 /* NV_PVIDEO_WINDOW_SIZE */
|
|
553 VID_WR32 (info->chip.PVIDEO, 0x234, (lheight << 16) | lwidth);
|
|
554 /* NV_PVIDEO_STEP_SIZE */
|
|
555 yscale = ((info->height - 1) << 11) / (info->d_height - 1);
|
|
556 xscale = ((info->width - 1) << 11) / (info->d_width - 1);
|
|
557 VID_WR32 (info->chip.PVIDEO, 0x200, (yscale << 16) | xscale);
|
|
558
|
|
559 /* NV_PVIDEO_RED_CSC_OFFSET */
|
|
560 VID_WR32 (info->chip.PVIDEO, 0x280, 0x69);
|
|
561 /* NV_PVIDEO_GREEN_CSC_OFFSET */
|
|
562 VID_WR32 (info->chip.PVIDEO, 0x284, 0x3e);
|
|
563 /* NV_PVIDEO_BLUE_CSC_OFFSET */
|
|
564 VID_WR32 (info->chip.PVIDEO, 0x288, 0x89);
|
|
565 /* NV_PVIDEO_CSC_ADJUST */
|
|
566 VID_WR32 (info->chip.PVIDEO, 0x28C, 0x00000); /* No colour correction! */
|
|
567
|
|
568 /* NV_PVIDEO_CONTROL_Y (BLUR_ON, LINE_HALF) */
|
|
569 VID_WR32 (info->chip.PVIDEO, 0x204, 0x001);
|
|
570 /* NV_PVIDEO_CONTROL_X (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */
|
|
571 VID_WR32 (info->chip.PVIDEO, 0x208, 0x111); /*rivatv 0x110 */
|
|
572
|
|
573 /* NV_PVIDEO_FIFO_BURST_LENGTH */
|
|
574 VID_WR32 (info->chip.PVIDEO, 0x23C, 0x03);
|
|
575 /* NV_PVIDEO_FIFO_THRES_SIZE */
|
|
576 VID_WR32 (info->chip.PVIDEO, 0x238, 0x38); /*windows uses 0x40*/
|
|
577
|
|
578 /* NV_PVIDEO_BUFF0_OFFSET */
|
|
579 VID_WR32 (info->chip.PVIDEO, 0x21C + 0, 0);
|
|
580 VID_WR32 (info->chip.PVIDEO, 0x21C + 4, 0);
|
|
581
|
|
582
|
|
583
|
|
584
|
|
585 /* NV_PVIDEO_INTR_EN_0_NOTIFY_ENABLED */
|
|
586 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01);
|
|
587 /* NV_PVIDEO_OVERLAY (KEY_ON, VIDEO_ON, FORMAT_CCIR) */
|
|
588
|
|
589 VID_WR32 (info->chip.PVIDEO, 0x244, (info->format==IMGFMT_YUY2)?0x111:0x011);
|
|
590 /* NV_PVIDEO_SU_STATE */
|
|
591 VID_XOR32 (info->chip.PVIDEO, 0x228, 1 << 16);
|
|
592 break;
|
|
593 }
|
|
594 /*set colorkey*/
|
|
595 rivatv_overlay_colorkey(info,info->vidixcolorkey);
|
|
596
|
|
597 }
|
|
598
|
|
599
|
|
600 static rivatv_info* info;
|
|
601
|
|
602
|
|
603
|
|
604
|
|
605 int vixInit(void){
|
|
606 int mtrr;
|
|
607 info = (rivatv_info*)calloc(1,sizeof(rivatv_info));
|
|
608 info->control_base = map_phys_mem(pci_info.base0, 0x00C00000 + 0x00008000);
|
|
609 info->chip.arch = nvidia_card_ids[find_chip(pci_info.device)].arch;
|
|
610 printf("[nvidia_vid] arch %x register base %x\n",info->chip.arch,(unsigned int)info->control_base);
|
|
611 info->chip.PFIFO = (uint32_t *) (info->control_base + 0x00002000);
|
|
612 info->chip.FIFO = (uint32_t *) (info->control_base + 0x00800000);
|
|
613 info->chip.PMC = (uint32_t *) (info->control_base + 0x00000000);
|
|
614 info->chip.PFB = (uint32_t *) (info->control_base + 0x00100000);
|
|
615 info->chip.PME = (uint32_t *) (info->control_base + 0x00000000);
|
|
616 info->chip.PCIO = (uint8_t *) (info->control_base + 0x00601000);
|
|
617 info->chip.PVIO = (uint8_t *) (info->control_base + 0x000C0000);
|
|
618 info->chip.PGRAPH = (uint32_t *) (info->control_base + 0x00400000);
|
|
619 /* setup chip specific functions */
|
|
620 switch (info->chip.arch) {
|
|
621 case NV_ARCH_03:
|
|
622 info->chip.lock = rivatv_lock_nv03;
|
|
623 info->chip.fbsize = rivatv_fbsize_nv03 (&info->chip);
|
|
624 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000);
|
|
625 break;
|
|
626 case NV_ARCH_04:
|
|
627 info->chip.lock = rivatv_lock_nv04;
|
|
628 info->chip.fbsize = rivatv_fbsize_nv04 (&info->chip);
|
|
629 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000);
|
|
630 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000);
|
|
631 break;
|
|
632 case NV_ARCH_10:
|
|
633 case NV_ARCH_20:
|
|
634 case NV_ARCH_30:
|
|
635 info->chip.lock = rivatv_lock_nv04;
|
|
636 info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip);
|
|
637 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000);
|
|
638 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000);
|
|
639 break;
|
|
640 }
|
|
641 switch (info->chip.arch) {
|
|
642 case NV_ARCH_03:
|
|
643 {
|
|
644 /* This maps framebuffer @6MB, thus 2MB are left for video. */
|
|
645 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize);
|
|
646 /* This may trash your screen for resolutions greater than 1024x768, sorry. */
|
|
647 info->picture_offset = 2*1024*768*4 ;
|
|
648 info->picture_base = (uint32_t) info->video_base + info->picture_offset;
|
|
649 info->chip.PRAMIN = (uint32_t *) (info->video_base + 0x00C00000);
|
|
650 break;
|
|
651 }
|
|
652 case NV_ARCH_04:
|
|
653 case NV_ARCH_10:
|
|
654 case NV_ARCH_20:
|
|
655 case NV_ARCH_30:
|
|
656 {
|
|
657 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize);
|
|
658 info->picture_offset = info->chip.fbsize - NV04_BES_SIZE;
|
|
659 // info->picture_base = (unsigned long)map_phys_mem(pci_info.base1+info->picture_offset,NV04_BES_SIZE);
|
|
660 info->picture_base = (uint32_t) info->video_base + info->picture_offset;
|
|
661 break;
|
|
662 }
|
|
663 }
|
|
664
|
|
665 printf("[nvidia_vid] detected memory size %u MB\n",(uint32_t)(info->chip.fbsize /1024/1024));
|
|
666
|
|
667 if ((mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB))!= 0)
|
|
668 printf("[nvidia_vid]: unable to setup MTRR: %s\n", strerror(mtrr));
|
|
669 else
|
|
670 printf("[nvidia_vid]: MTRR set up\n");
|
|
671
|
|
672 /*get some info about the screen dimension and depth*/
|
|
673 {
|
|
674 uint32_t bpp=0,pitch0=0;
|
|
675 info->chip.lock (&info->chip, 0);
|
|
676 switch (info->chip.arch) {
|
|
677 case NV_ARCH_03:
|
|
678 pitch0 = info->chip.PGRAPH[0x00000650/4];
|
|
679 break;
|
|
680 case NV_ARCH_04:
|
|
681 case NV_ARCH_10:
|
|
682 case NV_ARCH_20:
|
|
683 case NV_ARCH_30:
|
|
684 pitch0 = info->chip.PGRAPH[0x00000670/4];
|
|
685 break;
|
|
686 }
|
|
687 VID_WR08(info->chip.PCIO, 0x03D4, 0x28);
|
|
688 bpp = VID_RD08(info->chip.PCIO,0x03D5);
|
|
689 if(bpp==3)bpp = 4; //fixme do nvidia cards support 24bpp?
|
|
690 if((bpp == 2) && (info->chip.PVIDEO[0x00000600/4] & 0x00001000) == 0x0)info->depth=15; //0x00101100 for BGR16
|
|
691 else info->depth = bpp*8;
|
|
692 if(!bpp)printf("[nvidia_vid] error invalid bpp\n");
|
|
693 else printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x = pitch0/bpp,(pitch0/bpp*3)/4,info->depth);
|
|
694 }
|
|
695
|
|
696 rivatv_enable_PMEDIA(info);
|
|
697 info->next_frame = 0;
|
|
698 return 0;
|
|
699 }
|
|
700
|
|
701 void vixDestroy(void){
|
|
702 unmap_phys_mem(info->control_base ,0x00C00000 + 0x00008000);
|
|
703 unmap_phys_mem(info->video_base, info->chip.fbsize);
|
|
704 free(info);
|
|
705 }
|
|
706
|
|
707 int vixGetCapability(vidix_capability_t *to){
|
|
708 memcpy(to, &nvidia_cap, sizeof(vidix_capability_t));
|
|
709 return 0;
|
|
710 }
|
|
711
|
|
712 inline static int is_supported_fourcc(uint32_t fourcc)
|
|
713 {
|
|
714 if (fourcc == IMGFMT_UYVY ||
|
|
715 (fourcc == IMGFMT_YUY2 && info->chip.arch <= NV_ARCH_04) ||
|
|
716 (fourcc == IMGFMT_YV12 && info->chip.arch >= NV_ARCH_10))
|
|
717 return 1;
|
|
718 else
|
|
719 return 0;
|
|
720 }
|
|
721
|
|
722 int vixQueryFourcc(vidix_fourcc_t *to){
|
|
723 if(is_supported_fourcc(to->fourcc)){
|
|
724 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP |
|
|
725 VID_DEPTH_4BPP | VID_DEPTH_8BPP |
|
|
726 VID_DEPTH_12BPP| VID_DEPTH_15BPP|
|
|
727 VID_DEPTH_16BPP| VID_DEPTH_24BPP|
|
|
728 VID_DEPTH_32BPP;
|
|
729 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
|
|
730 return 0;
|
|
731 }
|
|
732 else to->depth = to->flags = 0;
|
|
733 return ENOSYS;
|
|
734 }
|
|
735
|
|
736 int vixConfigPlayback(vidix_playback_t *vinfo){
|
|
737 uint32_t i;
|
|
738 printf("called %s\n", __FUNCTION__);
|
|
739 if (! is_supported_fourcc(vinfo->fourcc))
|
|
740 return ENOSYS;
|
|
741
|
|
742 info->width = vinfo->src.w;
|
|
743 info->height = vinfo->src.h;
|
|
744
|
|
745 info->d_width = vinfo->dest.w;
|
|
746 info->d_height = vinfo->dest.h;
|
|
747 info->wx = vinfo->dest.x;
|
|
748 info->wy = vinfo->dest.y;
|
|
749 info->format = vinfo->fourcc;
|
|
750
|
|
751 printf("[nvidia_vid] setting up a %dx%d-%dx%d video window (src %dx%d), format 0x%X\n",
|
|
752 info->d_width, info->d_height, info->wx, info->wy, info->width, info->height, vinfo->fourcc);
|
|
753
|
|
754
|
|
755 vinfo->dga_addr=(void*)(info->picture_base);
|
|
756
|
|
757 switch (vinfo->fourcc)
|
|
758 {
|
|
759 case IMGFMT_YUY2:
|
|
760 case IMGFMT_UYVY:
|
|
761
|
|
762 vinfo->dest.pitch.y = 2;
|
|
763 vinfo->dest.pitch.u = 0;
|
|
764 vinfo->dest.pitch.v = 0;
|
|
765
|
|
766 vinfo->offset.y = 0;
|
|
767 vinfo->offset.v = 0;
|
|
768 vinfo->offset.u = 0;
|
|
769
|
|
770 info->pitch = info->width << 1;
|
|
771 vinfo->frame_size = info->pitch * info->height;
|
|
772 break;
|
|
773 case IMGFMT_YV12:
|
|
774 vinfo->dest.pitch.y = 1;
|
|
775 vinfo->dest.pitch.u = 1;
|
|
776 vinfo->dest.pitch.v = 1;
|
|
777
|
|
778 vinfo->offset.y = 0;
|
|
779 vinfo->offset.v = (info->width) * info->height;
|
|
780 vinfo->offset.u = vinfo->offset.v * 5 / 4;
|
|
781
|
|
782 info->pitch = info->width + (info->width >> 1);
|
|
783 vinfo->frame_size = info->pitch * info->height;
|
|
784 break;
|
|
785 }
|
|
786 info->buffer_size = vinfo->frame_size;
|
|
787 info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size;
|
|
788 if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES;
|
|
789 // vinfo->num_frames = 1;
|
|
790 // printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames);
|
|
791 for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i;
|
|
792 return 0;
|
|
793 }
|
|
794
|
|
795 int vixPlaybackOn(void){
|
|
796 rivatv_overlay_start(info,info->next_frame);
|
|
797 return 0;
|
|
798 }
|
|
799
|
|
800 int vixPlaybackOff(void){
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801 rivatv_overlay_stop(info);
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802 return 0;
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803 }
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804
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805 int vixSetGrKeys( const vidix_grkey_t * grkey){
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806 info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue);
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807 printf("[nvidia_vid] set colorkey 0x%x\n",info->vidixcolorkey);
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808 rivatv_overlay_colorkey(info,info->vidixcolorkey);
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809 return 0;
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810 }
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811
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812 int vixPlaybackFrameSelect(unsigned int frame){
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813 // printf("selecting buffer %d\n", frame);
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814 rivatv_overlay_start(info, frame);
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815 if (info->num_frames >= 1)
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816 info->next_frame = (frame+1)%info->num_frames;
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817 return 0;
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818 }
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