Mercurial > mplayer.hg
annotate drivers/mga_vid.c @ 95:2c2d82db06ef
mga_force_memsize->mga_ram_size
author | arpi_esp |
---|---|
date | Mon, 12 Mar 2001 01:57:14 +0000 |
parents | fbd99740af99 |
children | 7fe6855f19cd |
rev | line source |
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1 | 1 // YUY2 support (see config.format) added by A'rpi/ESP-team |
57 | 2 // double buffering added by A'rpi/ESP-team |
3 | |
4 // Set this value, if autodetection fails! (video ram size in megabytes) | |
91 | 5 // #define MGA_MEMORY_SIZE 16 |
1 | 6 |
68 | 7 //#define MGA_ALLOW_IRQ |
8 | |
9 #define MGA_VSYNC_POS 2 | |
10 | |
1 | 11 /* |
12 * | |
13 * mga_vid.c | |
14 * | |
15 * Copyright (C) 1999 Aaron Holtzman | |
16 * | |
17 * Module skeleton based on gutted agpgart module by Jeff Hartmann | |
18 * <slicer@ionet.net> | |
19 * | |
20 * Matrox MGA G200/G400 YUV Video Interface module Version 0.1.0 | |
21 * | |
22 * BES == Back End Scaler | |
23 * | |
24 * This software has been released under the terms of the GNU Public | |
25 * license. See http://www.gnu.org/copyleft/gpl.html for details. | |
26 */ | |
27 | |
28 //It's entirely possible this major conflicts with something else | |
29 /* mknod /dev/mga_vid c 178 0 */ | |
30 | |
31 #include <linux/config.h> | |
32 #include <linux/version.h> | |
33 #include <linux/module.h> | |
34 #include <linux/types.h> | |
35 #include <linux/kernel.h> | |
36 #include <linux/sched.h> | |
37 #include <linux/mm.h> | |
38 #include <linux/string.h> | |
39 #include <linux/errno.h> | |
40 #include <linux/malloc.h> | |
41 #include <linux/pci.h> | |
63 | 42 #include <linux/ioport.h> |
1 | 43 #include <linux/init.h> |
44 | |
45 #include "mga_vid.h" | |
46 | |
47 #ifdef CONFIG_MTRR | |
48 #include <asm/mtrr.h> | |
49 #endif | |
50 | |
51 #include <asm/uaccess.h> | |
52 #include <asm/system.h> | |
53 #include <asm/io.h> | |
54 | |
55 #define TRUE 1 | |
56 #define FALSE 0 | |
57 | |
58 #define MGA_VID_MAJOR 178 | |
59 | |
57 | 60 //#define MGA_VIDMEM_SIZE mga_ram_size |
1 | 61 |
62 #ifndef PCI_DEVICE_ID_MATROX_G200_PCI | |
63 #define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520 | |
64 #endif | |
65 | |
66 #ifndef PCI_DEVICE_ID_MATROX_G200_AGP | |
67 #define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521 | |
68 #endif | |
69 | |
70 #ifndef PCI_DEVICE_ID_MATROX_G400 | |
71 #define PCI_DEVICE_ID_MATROX_G400 0x0525 | |
72 #endif | |
73 | |
74 MODULE_AUTHOR("Aaron Holtzman <aholtzma@engr.uvic.ca>"); | |
75 | |
76 | |
77 typedef struct bes_registers_s | |
78 { | |
79 //BES Control | |
80 uint32_t besctl; | |
81 //BES Global control | |
82 uint32_t besglobctl; | |
83 //Luma control (brightness and contrast) | |
84 uint32_t beslumactl; | |
85 //Line pitch | |
86 uint32_t bespitch; | |
87 | |
88 //Buffer A-1 Chroma 3 plane org | |
89 uint32_t besa1c3org; | |
90 //Buffer A-1 Chroma org | |
91 uint32_t besa1corg; | |
92 //Buffer A-1 Luma org | |
93 uint32_t besa1org; | |
94 | |
95 //Buffer A-2 Chroma 3 plane org | |
96 uint32_t besa2c3org; | |
97 //Buffer A-2 Chroma org | |
98 uint32_t besa2corg; | |
99 //Buffer A-2 Luma org | |
100 uint32_t besa2org; | |
101 | |
102 //Buffer B-1 Chroma 3 plane org | |
103 uint32_t besb1c3org; | |
104 //Buffer B-1 Chroma org | |
105 uint32_t besb1corg; | |
106 //Buffer B-1 Luma org | |
107 uint32_t besb1org; | |
108 | |
109 //Buffer B-2 Chroma 3 plane org | |
110 uint32_t besb2c3org; | |
111 //Buffer B-2 Chroma org | |
112 uint32_t besb2corg; | |
113 //Buffer B-2 Luma org | |
114 uint32_t besb2org; | |
115 | |
116 //BES Horizontal coord | |
117 uint32_t beshcoord; | |
118 //BES Horizontal inverse scaling [5.14] | |
119 uint32_t beshiscal; | |
120 //BES Horizontal source start [10.14] (for scaling) | |
121 uint32_t beshsrcst; | |
122 //BES Horizontal source ending [10.14] (for scaling) | |
123 uint32_t beshsrcend; | |
124 //BES Horizontal source last | |
125 uint32_t beshsrclst; | |
126 | |
127 | |
128 //BES Vertical coord | |
129 uint32_t besvcoord; | |
130 //BES Vertical inverse scaling [5.14] | |
131 uint32_t besviscal; | |
132 //BES Field 1 vertical source last position | |
133 uint32_t besv1srclst; | |
134 //BES Field 1 weight start | |
135 uint32_t besv1wght; | |
136 //BES Field 2 vertical source last position | |
137 uint32_t besv2srclst; | |
138 //BES Field 2 weight start | |
139 uint32_t besv2wght; | |
140 | |
141 } bes_registers_t; | |
142 | |
143 static bes_registers_t regs; | |
144 static uint32_t mga_vid_in_use = 0; | |
145 static uint32_t is_g400 = 0; | |
146 static uint32_t vid_src_ready = 0; | |
147 static uint32_t vid_overlay_on = 0; | |
148 | |
149 static uint8_t *mga_mmio_base = 0; | |
150 static uint32_t mga_mem_base = 0; | |
151 | |
57 | 152 static int mga_src_base = 0; // YUV buffer position in video memory |
153 | |
154 static uint32_t mga_ram_size = 0; // how much megabytes videoram we have | |
1 | 155 |
95 | 156 //static int mga_force_memsize = 0; |
90 | 157 |
95 | 158 MODULE_PARM(mga_ram_size, "i"); |
90 | 159 |
160 | |
1 | 161 static struct pci_dev *pci_dev; |
162 | |
163 static mga_vid_config_t mga_config; | |
164 | |
48 | 165 static int mga_irq = -1; |
1 | 166 |
167 //All register offsets are converted to word aligned offsets (32 bit) | |
168 //because we want all our register accesses to be 32 bits | |
169 #define VCOUNT 0x1e20 | |
170 | |
171 #define PALWTADD 0x3c00 // Index register for X_DATAREG port | |
172 #define X_DATAREG 0x3c0a | |
173 | |
174 #define XMULCTRL 0x19 | |
175 #define BPP_8 0x00 | |
176 #define BPP_15 0x01 | |
177 #define BPP_16 0x02 | |
178 #define BPP_24 0x03 | |
179 #define BPP_32_DIR 0x04 | |
180 #define BPP_32_PAL 0x07 | |
181 | |
182 #define XCOLMSK 0x40 | |
183 #define X_COLKEY 0x42 | |
184 #define XKEYOPMODE 0x51 | |
185 #define XCOLMSK0RED 0x52 | |
186 #define XCOLMSK0GREEN 0x53 | |
187 #define XCOLMSK0BLUE 0x54 | |
188 #define XCOLKEY0RED 0x55 | |
189 #define XCOLKEY0GREEN 0x56 | |
190 #define XCOLKEY0BLUE 0x57 | |
191 | |
192 // Backend Scaler registers | |
193 #define BESCTL 0x3d20 | |
194 #define BESGLOBCTL 0x3dc0 | |
195 #define BESLUMACTL 0x3d40 | |
196 #define BESPITCH 0x3d24 | |
48 | 197 |
1 | 198 #define BESA1C3ORG 0x3d60 |
199 #define BESA1CORG 0x3d10 | |
200 #define BESA1ORG 0x3d00 | |
48 | 201 |
1 | 202 #define BESA2C3ORG 0x3d64 |
203 #define BESA2CORG 0x3d14 | |
204 #define BESA2ORG 0x3d04 | |
48 | 205 |
1 | 206 #define BESB1C3ORG 0x3d68 |
207 #define BESB1CORG 0x3d18 | |
208 #define BESB1ORG 0x3d08 | |
48 | 209 |
1 | 210 #define BESB2C3ORG 0x3d6C |
211 #define BESB2CORG 0x3d1C | |
212 #define BESB2ORG 0x3d0C | |
48 | 213 |
1 | 214 #define BESHCOORD 0x3d28 |
215 #define BESHISCAL 0x3d30 | |
216 #define BESHSRCEND 0x3d3C | |
217 #define BESHSRCLST 0x3d50 | |
218 #define BESHSRCST 0x3d38 | |
219 #define BESV1WGHT 0x3d48 | |
220 #define BESV2WGHT 0x3d4c | |
221 #define BESV1SRCLST 0x3d54 | |
222 #define BESV2SRCLST 0x3d58 | |
223 #define BESVISCAL 0x3d34 | |
224 #define BESVCOORD 0x3d2c | |
225 #define BESSTATUS 0x3dc4 | |
226 | |
48 | 227 #define CRTCX 0x1fd4 |
228 #define CRTCD 0x1fd5 | |
229 #define IEN 0x1e1c | |
230 #define ICLEAR 0x1e18 | |
231 #define STATUS 0x1e14 | |
232 | |
233 static int mga_next_frame=0; | |
1 | 234 |
235 static void mga_vid_frame_sel(int frame) | |
236 { | |
48 | 237 if ( mga_irq != -1 ) { |
238 mga_next_frame=frame; | |
239 } else { | |
240 | |
1 | 241 //we don't need the vcount protection as we're only hitting |
242 //one register (and it doesn't seem to be double buffered) | |
243 regs.besctl = (regs.besctl & ~0x07000000) + (frame << 25); | |
244 writel( regs.besctl, mga_mmio_base + BESCTL ); | |
68 | 245 |
246 // writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), | |
247 writel( regs.besglobctl + (MGA_VSYNC_POS<<16), | |
248 mga_mmio_base + BESGLOBCTL); | |
249 | |
48 | 250 } |
1 | 251 } |
252 | |
253 | |
254 static void mga_vid_write_regs(void) | |
255 { | |
256 //Make sure internal registers don't get updated until we're done | |
257 writel( (readl(mga_mmio_base + VCOUNT)-1)<<16, | |
258 mga_mmio_base + BESGLOBCTL); | |
259 | |
260 // color or coordinate keying | |
261 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); | |
262 writeb( mga_config.colkey_on, mga_mmio_base + X_DATAREG); | |
263 if ( mga_config.colkey_on ) | |
264 { | |
265 uint32_t r=0, g=0, b=0; | |
266 | |
267 writeb( XMULCTRL, mga_mmio_base + PALWTADD); | |
268 switch (readb (mga_mmio_base + X_DATAREG)) | |
269 { | |
270 case BPP_8: | |
271 /* Need to look up the color index, just using | |
272 color 0 for now. */ | |
273 break; | |
274 | |
275 case BPP_15: | |
276 r = mga_config.colkey_red >> 3; | |
277 g = mga_config.colkey_green >> 3; | |
278 b = mga_config.colkey_blue >> 3; | |
279 break; | |
280 | |
281 case BPP_16: | |
282 r = mga_config.colkey_red >> 3; | |
283 g = mga_config.colkey_green >> 2; | |
284 b = mga_config.colkey_blue >> 3; | |
285 break; | |
286 | |
287 case BPP_24: | |
288 case BPP_32_DIR: | |
289 case BPP_32_PAL: | |
290 r = mga_config.colkey_red; | |
291 g = mga_config.colkey_green; | |
292 b = mga_config.colkey_blue; | |
293 break; | |
294 } | |
295 | |
296 // Disable color keying on alpha channel | |
297 writeb( XCOLMSK, mga_mmio_base + PALWTADD); | |
298 writeb( 0x00, mga_mmio_base + X_DATAREG); | |
299 writeb( X_COLKEY, mga_mmio_base + PALWTADD); | |
300 writeb( 0x00, mga_mmio_base + X_DATAREG); | |
301 | |
302 // Set up color key registers | |
303 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); | |
304 writeb( r, mga_mmio_base + X_DATAREG); | |
305 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); | |
306 writeb( g, mga_mmio_base + X_DATAREG); | |
307 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); | |
308 writeb( b, mga_mmio_base + X_DATAREG); | |
309 | |
310 // Set up color key mask registers | |
311 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); | |
312 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
313 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); | |
314 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
315 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); | |
316 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
317 } | |
318 | |
319 // Backend Scaler | |
320 writel( regs.besctl, mga_mmio_base + BESCTL); | |
321 if(is_g400) | |
322 writel( regs.beslumactl, mga_mmio_base + BESLUMACTL); | |
323 writel( regs.bespitch, mga_mmio_base + BESPITCH); | |
324 | |
325 writel( regs.besa1org, mga_mmio_base + BESA1ORG); | |
326 writel( regs.besa1corg, mga_mmio_base + BESA1CORG); | |
48 | 327 writel( regs.besa2org, mga_mmio_base + BESA2ORG); |
328 writel( regs.besa2corg, mga_mmio_base + BESA2CORG); | |
1 | 329 writel( regs.besb1org, mga_mmio_base + BESB1ORG); |
330 writel( regs.besb1corg, mga_mmio_base + BESB1CORG); | |
48 | 331 writel( regs.besb2org, mga_mmio_base + BESB2ORG); |
332 writel( regs.besb2corg, mga_mmio_base + BESB2CORG); | |
1 | 333 if(is_g400) |
334 { | |
335 writel( regs.besa1c3org, mga_mmio_base + BESA1C3ORG); | |
48 | 336 writel( regs.besa2c3org, mga_mmio_base + BESA2C3ORG); |
1 | 337 writel( regs.besb1c3org, mga_mmio_base + BESB1C3ORG); |
48 | 338 writel( regs.besb2c3org, mga_mmio_base + BESB2C3ORG); |
1 | 339 } |
340 | |
341 writel( regs.beshcoord, mga_mmio_base + BESHCOORD); | |
342 writel( regs.beshiscal, mga_mmio_base + BESHISCAL); | |
343 writel( regs.beshsrcst, mga_mmio_base + BESHSRCST); | |
344 writel( regs.beshsrcend, mga_mmio_base + BESHSRCEND); | |
345 writel( regs.beshsrclst, mga_mmio_base + BESHSRCLST); | |
346 | |
347 writel( regs.besvcoord, mga_mmio_base + BESVCOORD); | |
348 writel( regs.besviscal, mga_mmio_base + BESVISCAL); | |
48 | 349 |
1 | 350 writel( regs.besv1srclst, mga_mmio_base + BESV1SRCLST); |
351 writel( regs.besv1wght, mga_mmio_base + BESV1WGHT); | |
48 | 352 writel( regs.besv2srclst, mga_mmio_base + BESV2SRCLST); |
353 writel( regs.besv2wght, mga_mmio_base + BESV2WGHT); | |
1 | 354 |
355 //update the registers somewhere between 1 and 2 frames from now. | |
356 writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), | |
357 mga_mmio_base + BESGLOBCTL); | |
358 | |
77 | 359 #if 0 |
61 | 360 printk(KERN_DEBUG "mga_vid: wrote BES registers\n"); |
361 printk(KERN_DEBUG "mga_vid: BESCTL = 0x%08x\n", | |
1 | 362 readl(mga_mmio_base + BESCTL)); |
61 | 363 printk(KERN_DEBUG "mga_vid: BESGLOBCTL = 0x%08x\n", |
1 | 364 readl(mga_mmio_base + BESGLOBCTL)); |
61 | 365 printk(KERN_DEBUG "mga_vid: BESSTATUS= 0x%08x\n", |
1 | 366 readl(mga_mmio_base + BESSTATUS)); |
77 | 367 #endif |
1 | 368 } |
369 | |
370 static int mga_vid_set_config(mga_vid_config_t *config) | |
371 { | |
372 int x, y, sw, sh, dw, dh; | |
373 int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights; | |
57 | 374 int frame_size=config->frame_size; |
1 | 375 x = config->x_org; |
376 y = config->y_org; | |
377 sw = config->src_width; | |
378 sh = config->src_height; | |
379 dw = config->dest_width; | |
380 dh = config->dest_height; | |
381 | |
61 | 382 printk(KERN_DEBUG "mga_vid: Setting up a %dx%d+%d+%d video window (src %dx%d) format %X\n", |
1 | 383 dw, dh, x, y, sw, sh, config->format); |
384 | |
385 //FIXME check that window is valid and inside desktop | |
386 | |
387 //FIXME figure out a better way to allocate memory on card | |
388 //allocate 2 megs | |
389 //mga_src_base = mga_mem_base + (MGA_VIDMEM_SIZE-2) * 0x100000; | |
57 | 390 //mga_src_base = (MGA_VIDMEM_SIZE-3) * 0x100000; |
1 | 391 |
392 | |
393 //Setup the BES registers for a three plane 4:2:0 video source | |
394 | |
395 switch(config->format){ | |
396 case MGA_VID_FORMAT_YV12: | |
397 regs.besctl = 1 // BES enabled | |
398 + (0<<6) // even start polarity | |
399 + (1<<10) // x filtering enabled | |
400 + (1<<11) // y filtering enabled | |
401 + (1<<16) // chroma upsampling | |
402 + (1<<17) // 4:2:0 mode | |
403 + (1<<18); // dither enabled | |
404 | |
405 if(is_g400) | |
406 { | |
407 //zoom disabled, zoom filter disabled, 420 3 plane format, proc amp | |
408 //disabled, rgb mode disabled | |
409 regs.besglobctl = (1<<5); | |
410 } | |
411 else | |
412 { | |
413 //zoom disabled, zoom filter disabled, Cb samples in 0246, Cr | |
414 //in 1357, BES register update on besvcnt | |
415 regs.besglobctl = 0; | |
416 } | |
417 break; | |
418 | |
419 case MGA_VID_FORMAT_YUY2: | |
420 regs.besctl = 1 // BES enabled | |
421 + (0<<6) // even start polarity | |
422 + (1<<10) // x filtering enabled | |
423 + (1<<11) // y filtering enabled | |
424 + (1<<16) // chroma upsampling | |
425 + (0<<17) // 4:2:2 mode | |
426 + (1<<18); // dither enabled | |
427 | |
428 regs.besglobctl = 0; // YUY2 format selected | |
429 break; | |
430 default: | |
61 | 431 printk(KERN_ERR "mga_vid: Unsupported pixel format: 0x%X\n",config->format); |
1 | 432 return -1; |
433 } | |
434 | |
435 | |
436 //Disable contrast and brightness control | |
437 regs.besglobctl = (1<<5) + (1<<7); | |
438 regs.beslumactl = (0x7f << 16) + (0x80<<0); | |
439 regs.beslumactl = 0x80<<0; | |
440 | |
441 //Setup destination window boundaries | |
442 besleft = x > 0 ? x : 0; | |
443 bestop = y > 0 ? y : 0; | |
444 regs.beshcoord = (besleft<<16) + (x + dw-1); | |
445 regs.besvcoord = (bestop<<16) + (y + dh-1); | |
446 | |
447 //Setup source dimensions | |
448 regs.beshsrclst = (sw - 1) << 16; | |
449 regs.bespitch = (sw + 31) & ~31 ; | |
450 | |
451 //Setup horizontal scaling | |
452 ifactor = ((sw-1)<<14)/(dw-1); | |
453 ofsleft = besleft - x; | |
454 | |
455 regs.beshiscal = ifactor<<2; | |
456 regs.beshsrcst = (ofsleft*ifactor)<<2; | |
457 regs.beshsrcend = regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2); | |
458 | |
459 //Setup vertical scaling | |
460 ifactor = ((sh-1)<<14)/(dh-1); | |
461 ofstop = bestop - y; | |
462 | |
463 regs.besviscal = ifactor<<2; | |
464 | |
465 baseadrofs = ((ofstop*regs.besviscal)>>16)*regs.bespitch; | |
57 | 466 //frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2; |
1 | 467 regs.besa1org = (uint32_t) mga_src_base + baseadrofs; |
48 | 468 regs.besa2org = (uint32_t) mga_src_base + baseadrofs + 1*frame_size; |
469 regs.besb1org = (uint32_t) mga_src_base + baseadrofs + 2*frame_size; | |
470 regs.besb2org = (uint32_t) mga_src_base + baseadrofs + 3*frame_size; | |
1 | 471 |
57 | 472 if(config->format==MGA_VID_FORMAT_YV12){ |
473 // planar YUV frames: | |
1 | 474 if (is_g400) |
475 baseadrofs = (((ofstop*regs.besviscal)/4)>>16)*regs.bespitch; | |
476 else | |
477 baseadrofs = (((ofstop*regs.besviscal)/2)>>16)*regs.bespitch; | |
478 | |
479 regs.besa1corg = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; | |
48 | 480 regs.besa2corg = (uint32_t) mga_src_base + baseadrofs + 1*frame_size + regs.bespitch * sh; |
481 regs.besb1corg = (uint32_t) mga_src_base + baseadrofs + 2*frame_size + regs.bespitch * sh; | |
482 regs.besb2corg = (uint32_t) mga_src_base + baseadrofs + 3*frame_size + regs.bespitch * sh; | |
1 | 483 regs.besa1c3org = regs.besa1corg + ((regs.bespitch * sh) / 4); |
48 | 484 regs.besa2c3org = regs.besa2corg + ((regs.bespitch * sh) / 4); |
1 | 485 regs.besb1c3org = regs.besb1corg + ((regs.bespitch * sh) / 4); |
48 | 486 regs.besb2c3org = regs.besb2corg + ((regs.bespitch * sh) / 4); |
57 | 487 } |
1 | 488 |
489 weight = ofstop * (regs.besviscal >> 2); | |
490 weights = weight < 0 ? 1 : 0; | |
48 | 491 regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2); |
492 regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF); | |
1 | 493 |
494 mga_vid_write_regs(); | |
495 return 0; | |
496 } | |
497 | |
68 | 498 #ifdef MGA_ALLOW_IRQ |
499 | |
48 | 500 static void enable_irq(){ |
501 long int cc; | |
502 | |
503 cc = readl(mga_mmio_base + IEN); | |
63 | 504 // printk(KERN_ALERT "*** !!! IRQREG = %d\n", (int)(cc&0xff)); |
48 | 505 |
506 writeb( 0x11, mga_mmio_base + CRTCX); | |
507 | |
508 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ | |
509 writeb(0x00, mga_mmio_base + CRTCD ); /* enable on */ | |
510 writeb(0x10, mga_mmio_base + CRTCD ); /* clear = 1 */ | |
511 | |
512 writel( regs.besglobctl , mga_mmio_base + BESGLOBCTL); | |
513 | |
514 } | |
515 | |
516 static void disable_irq(){ | |
517 | |
518 writeb( 0x11, mga_mmio_base + CRTCX); | |
519 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ | |
520 | |
521 } | |
522 | |
523 void mga_handle_irq(int irq, void *dev_id, struct pt_regs *pregs) { | |
524 // static int frame=0; | |
525 static int counter=0; | |
526 long int cc; | |
527 // if ( ! mga_enabled_flag ) return; | |
528 | |
68 | 529 // printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT)); |
530 | |
48 | 531 //printk("mga_interrupt #%d\n", irq); |
532 | |
533 if ( irq != -1 ) { | |
534 | |
535 cc = readl(mga_mmio_base + STATUS); | |
536 if ( ! (cc & 0x10) ) return; /* vsyncpen */ | |
537 // debug_irqcnt++; | |
538 } | |
539 | |
540 // if ( debug_irqignore ) { | |
541 // debug_irqignore = 0; | |
542 | |
543 | |
544 /* | |
545 if ( mga_conf_deinterlace ) { | |
546 if ( mga_first_field ) { | |
547 // printk("mga_interrupt first field\n"); | |
548 if ( syncfb_interrupt() ) | |
549 mga_first_field = 0; | |
550 } else { | |
551 // printk("mga_interrupt second field\n"); | |
552 mga_select_buffer( mga_current_field | 2 ); | |
553 mga_first_field = 1; | |
554 } | |
555 } else { | |
556 syncfb_interrupt(); | |
557 } | |
558 */ | |
559 | |
560 // frame=(frame+1)&1; | |
561 regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25); | |
562 writel( regs.besctl, mga_mmio_base + BESCTL ); | |
563 | |
564 #if 0 | |
565 ++counter; | |
566 if(!(counter&63)){ | |
567 printk("mga irq counter = %d\n",counter); | |
568 } | |
569 #endif | |
570 | |
571 // } else { | |
572 // debug_irqignore = 1; | |
573 // } | |
574 | |
575 if ( irq != -1 ) { | |
576 writeb( 0x11, mga_mmio_base + CRTCX); | |
577 writeb( 0, mga_mmio_base + CRTCD ); | |
578 writeb( 0x10, mga_mmio_base + CRTCD ); | |
579 } | |
580 | |
581 // writel( regs.besglobctl, mga_mmio_base + BESGLOBCTL); | |
582 | |
583 | |
584 return; | |
585 | |
586 } | |
587 | |
68 | 588 #endif |
1 | 589 |
590 static int mga_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) | |
591 { | |
592 int frame; | |
593 | |
594 switch(cmd) | |
595 { | |
596 case MGA_VID_CONFIG: | |
597 //FIXME remove | |
68 | 598 // printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT)); |
61 | 599 printk(KERN_DEBUG "mga_mmio_base = %p\n",mga_mmio_base); |
600 printk(KERN_DEBUG "mga_mem_base = %08lx\n",mga_mem_base); | |
1 | 601 //FIXME remove |
602 | |
61 | 603 printk(KERN_DEBUG "mga_vid: Received configuration\n"); |
1 | 604 |
605 if(copy_from_user(&mga_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t))) | |
606 { | |
61 | 607 printk(KERN_ERR "mga_vid: failed copy from userspace\n"); |
1 | 608 return(-EFAULT); |
609 } | |
57 | 610 if(mga_config.version != MGA_VID_VERSION){ |
61 | 611 printk(KERN_ERR "mga_vid: incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,mga_config.version); |
57 | 612 return(-EFAULT); |
613 } | |
614 | |
615 if(mga_config.frame_size==0 || mga_config.frame_size>1024*768*2){ | |
61 | 616 printk(KERN_ERR "mga_vid: illegal frame_size: %d\n",mga_config.frame_size); |
57 | 617 return(-EFAULT); |
618 } | |
619 | |
620 if(mga_config.num_frames<1 || mga_config.num_frames>4){ | |
61 | 621 printk(KERN_ERR "mga_vid: illegal num_frames: %d\n",mga_config.num_frames); |
57 | 622 return(-EFAULT); |
623 } | |
624 | |
625 mga_src_base = (mga_ram_size*0x100000-mga_config.num_frames*mga_config.frame_size); | |
626 if(mga_src_base<0){ | |
61 | 627 printk(KERN_ERR "mga_vid: not enough memory for frames!\n"); |
57 | 628 return(-EFAULT); |
629 } | |
630 mga_src_base &= (~0xFFFF); // 64k boundary | |
61 | 631 printk(KERN_DEBUG "mga YUV buffer base: 0x%X\n", mga_src_base); |
57 | 632 |
1 | 633 if (is_g400) |
634 mga_config.card_type = MGA_G400; | |
635 else | |
636 mga_config.card_type = MGA_G200; | |
637 | |
638 mga_config.ram_size = mga_ram_size; | |
639 | |
640 if (copy_to_user((mga_vid_config_t *) arg, &mga_config, sizeof(mga_vid_config_t))) | |
641 { | |
61 | 642 printk(KERN_ERR "mga_vid: failed copy to userspace\n"); |
1 | 643 return(-EFAULT); |
644 } | |
645 return mga_vid_set_config(&mga_config); | |
646 break; | |
647 | |
648 case MGA_VID_ON: | |
61 | 649 printk(KERN_DEBUG "mga_vid: Video ON\n"); |
1 | 650 vid_src_ready = 1; |
651 if(vid_overlay_on) | |
652 { | |
653 regs.besctl |= 1; | |
654 mga_vid_write_regs(); | |
655 } | |
68 | 656 #ifdef MGA_ALLOW_IRQ |
48 | 657 if ( mga_irq != -1 ) enable_irq(); |
68 | 658 #endif |
48 | 659 mga_next_frame=0; |
1 | 660 break; |
661 | |
662 case MGA_VID_OFF: | |
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663 printk(KERN_DEBUG "mga_vid: Video OFF (ioctl)\n"); |
1 | 664 vid_src_ready = 0; |
68 | 665 #ifdef MGA_ALLOW_IRQ |
48 | 666 if ( mga_irq != -1 ) disable_irq(); |
68 | 667 #endif |
1 | 668 regs.besctl &= ~1; |
669 mga_vid_write_regs(); | |
670 break; | |
671 | |
672 case MGA_VID_FSEL: | |
673 if(copy_from_user(&frame,(int *) arg,sizeof(int))) | |
674 { | |
61 | 675 printk(KERN_ERR "mga_vid: FSEL failed copy from userspace\n"); |
1 | 676 return(-EFAULT); |
677 } | |
678 | |
679 mga_vid_frame_sel(frame); | |
680 break; | |
681 | |
682 default: | |
61 | 683 printk(KERN_ERR "mga_vid: Invalid ioctl\n"); |
1 | 684 return (-EINVAL); |
685 } | |
686 | |
687 return 0; | |
688 } | |
689 | |
690 | |
691 static int mga_vid_find_card(void) | |
692 { | |
693 struct pci_dev *dev = NULL; | |
694 unsigned int card_option, temp; | |
695 | |
696 if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400, NULL))) | |
697 { | |
698 is_g400 = 1; | |
77 | 699 printk(KERN_INFO "mga_vid: Found MGA G400/G450\n"); |
1 | 700 } |
701 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, NULL))) | |
702 { | |
703 is_g400 = 0; | |
63 | 704 printk(KERN_INFO "mga_vid: Found MGA G200 AGP\n"); |
1 | 705 } |
706 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_PCI, NULL))) | |
707 { | |
708 is_g400 = 0; | |
63 | 709 printk(KERN_INFO "mga_vid: Found MGA G200 PCI\n"); |
1 | 710 } |
711 else | |
712 { | |
61 | 713 printk(KERN_ERR "mga_vid: No supported cards found\n"); |
1 | 714 return FALSE; |
715 } | |
716 | |
717 pci_dev = dev; | |
48 | 718 |
719 mga_irq = pci_dev->irq; | |
1 | 720 |
721 #if LINUX_VERSION_CODE >= 0x020300 | |
722 mga_mmio_base = ioremap_nocache(dev->resource[1].start,0x4000); | |
723 mga_mem_base = dev->resource[0].start; | |
724 #else | |
725 mga_mmio_base = ioremap_nocache(dev->base_address[1] & PCI_BASE_ADDRESS_MEM_MASK,0x4000); | |
726 mga_mem_base = dev->base_address[0] & PCI_BASE_ADDRESS_MEM_MASK; | |
727 #endif | |
63 | 728 printk(KERN_INFO "mga_vid: MMIO at 0x%p IRQ: %d framebuffer: 0x%08lX\n", mga_mmio_base, mga_irq, mga_mem_base); |
1 | 729 |
730 pci_read_config_dword(dev, 0x40, &card_option); | |
77 | 731 printk(KERN_INFO "mga_vid: OPTION word: 0x%08X mem: 0x%02X %s\n", card_option, |
732 (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM"); | |
1 | 733 |
57 | 734 // temp = (card_option >> 10) & 0x17; |
735 | |
736 #ifdef MGA_MEMORY_SIZE | |
737 mga_ram_size = MGA_MEMORY_SIZE; | |
63 | 738 printk(KERN_INFO "mga_vid: hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); |
1 | 739 |
57 | 740 #else |
95 | 741 if (mga_ram_size) { |
742 printk(KERN_INFO "mga_vid: RAMSIZE forced to %d MB\n", mga_ram_size); | |
91 | 743 } else { |
90 | 744 |
95 | 745 if (is_g400){ |
75 | 746 switch((card_option>>10)&0x17){ |
747 // SDRAM: | |
748 case 0x00: | |
749 case 0x04: mga_ram_size = 16; break; | |
750 case 0x03: | |
751 case 0x05: mga_ram_size = 64; break; | |
752 // SGRAM: | |
753 case 0x10: | |
754 case 0x14: mga_ram_size = 32; break; | |
755 case 0x11: | |
756 case 0x12: mga_ram_size = 16; break; | |
757 default: | |
758 mga_ram_size = 16; | |
759 printk(KERN_INFO "mga_vid: Couldn't detect RAMSIZE, assuming 16MB!"); | |
760 } | |
95 | 761 }else{ |
64 | 762 switch((card_option>>11)&3){ |
763 case 0: mga_ram_size = 8; break; | |
764 default: mga_ram_size = 16; | |
765 } | |
95 | 766 } |
64 | 767 #if 0 |
95 | 768 // printk("List resources -----------\n"); |
769 for(temp=0;temp<DEVICE_COUNT_RESOURCE;temp++){ | |
770 struct resource *res=&pci_dev->resource[temp]; | |
771 if(res->flags){ | |
772 int size=(1+res->end-res->start)>>20; | |
773 printk(KERN_DEBUG "res %d: start: 0x%X end: 0x%X (%d MB) flags=0x%X\n",temp,res->start,res->end,size,res->flags); | |
774 if(res->flags&(IORESOURCE_MEM|IORESOURCE_PREFETCH)){ | |
775 if(size>mga_ram_size && size<=64) mga_ram_size=size; | |
776 } | |
777 } | |
57 | 778 } |
64 | 779 #endif |
95 | 780 printk(KERN_INFO "mga_vid: detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); |
781 } | |
57 | 782 |
783 #endif | |
48 | 784 |
68 | 785 #ifdef MGA_ALLOW_IRQ |
48 | 786 if ( mga_irq != -1 ) { |
787 int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq); | |
788 if ( tmp ) { | |
61 | 789 printk(KERN_INFO "syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp); |
48 | 790 mga_irq=-1; |
791 } else { | |
61 | 792 printk(KERN_DEBUG "syncfb (mga): registered irq %d\n", mga_irq); |
48 | 793 } |
794 } else { | |
61 | 795 printk(KERN_INFO "syncfb (mga): No valid irq was found\n"); |
48 | 796 mga_irq=-1; |
797 } | |
68 | 798 #else |
799 printk(KERN_INFO "syncfb (mga): IRQ disabled in mga_vid.c\n"); | |
800 mga_irq=-1; | |
801 #endif | |
48 | 802 |
1 | 803 return TRUE; |
804 } | |
805 | |
806 | |
807 static ssize_t mga_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) | |
808 { | |
809 return -EINVAL; | |
810 } | |
811 | |
812 static ssize_t mga_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) | |
813 { | |
814 return -EINVAL; | |
815 } | |
816 | |
817 static int mga_vid_mmap(struct file *file, struct vm_area_struct *vma) | |
818 { | |
819 | |
61 | 820 printk(KERN_DEBUG "mga_vid: mapping video memory into userspace\n"); |
57 | 821 if(remap_page_range(vma->vm_start, mga_mem_base + mga_src_base, |
1 | 822 vma->vm_end - vma->vm_start, vma->vm_page_prot)) |
823 { | |
63 | 824 printk(KERN_ERR "mga_vid: error mapping video memory\n"); |
1 | 825 return(-EAGAIN); |
826 } | |
827 | |
828 return(0); | |
829 } | |
830 | |
831 static int mga_vid_release(struct inode *inode, struct file *file) | |
832 { | |
833 //Close the window just in case | |
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834 printk(KERN_DEBUG "mga_vid: Video OFF (release)\n"); |
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835 |
1 | 836 vid_src_ready = 0; |
837 regs.besctl &= ~1; | |
838 mga_vid_write_regs(); | |
839 mga_vid_in_use = 0; | |
840 | |
93 | 841 MOD_DEC_USE_COUNT; |
1 | 842 return 0; |
843 } | |
844 | |
845 static long long mga_vid_lseek(struct file *file, long long offset, int origin) | |
846 { | |
847 return -ESPIPE; | |
848 } | |
849 | |
850 static int mga_vid_open(struct inode *inode, struct file *file) | |
851 { | |
852 int minor = MINOR(inode->i_rdev); | |
853 | |
854 if(minor != 0) | |
855 return(-ENXIO); | |
856 | |
857 if(mga_vid_in_use == 1) | |
858 return(-EBUSY); | |
859 | |
860 mga_vid_in_use = 1; | |
93 | 861 MOD_INC_USE_COUNT; |
1 | 862 return(0); |
863 } | |
864 | |
865 #if LINUX_VERSION_CODE >= 0x020400 | |
866 static struct file_operations mga_vid_fops = | |
867 { | |
868 llseek: mga_vid_lseek, | |
869 read: mga_vid_read, | |
870 write: mga_vid_write, | |
871 ioctl: mga_vid_ioctl, | |
872 mmap: mga_vid_mmap, | |
873 open: mga_vid_open, | |
874 release: mga_vid_release | |
875 }; | |
876 #else | |
877 static struct file_operations mga_vid_fops = | |
878 { | |
879 mga_vid_lseek, | |
880 mga_vid_read, | |
881 mga_vid_write, | |
882 NULL, | |
883 NULL, | |
884 mga_vid_ioctl, | |
885 mga_vid_mmap, | |
886 mga_vid_open, | |
887 NULL, | |
888 mga_vid_release | |
889 }; | |
890 #endif | |
891 | |
892 | |
893 /* | |
894 * Main Initialization Function | |
895 */ | |
896 | |
897 static int mga_vid_initialize(void) | |
898 { | |
899 mga_vid_in_use = 0; | |
900 | |
77 | 901 // printk(KERN_INFO "Matrox MGA G200/G400 YUV Video interface v0.01 (c) Aaron Holtzman \n"); |
902 printk(KERN_INFO "Matrox MGA G200/G400/G450 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n"); | |
90 | 903 |
95 | 904 if (mga_ram_size) { |
905 if (mga_ram_size<4 || mga_ram_size>64) { | |
906 printk(KERN_ERR "mga_vid: invalid RAMSIZE: %d MB\n", mga_ram_size); | |
90 | 907 return -EINVAL; |
908 } | |
909 } | |
910 | |
1 | 911 if(register_chrdev(MGA_VID_MAJOR, "mga_vid", &mga_vid_fops)) |
912 { | |
61 | 913 printk(KERN_ERR "mga_vid: unable to get major: %d\n", MGA_VID_MAJOR); |
1 | 914 return -EIO; |
915 } | |
916 | |
917 if (!mga_vid_find_card()) | |
918 { | |
61 | 919 printk(KERN_ERR "mga_vid: no supported devices found\n"); |
1 | 920 unregister_chrdev(MGA_VID_MAJOR, "mga_vid"); |
921 return -EINVAL; | |
922 } | |
923 | |
924 return(0); | |
925 } | |
926 | |
927 int init_module(void) | |
928 { | |
929 return mga_vid_initialize(); | |
930 } | |
931 | |
932 void cleanup_module(void) | |
933 { | |
48 | 934 |
68 | 935 #ifdef MGA_ALLOW_IRQ |
48 | 936 if ( mga_irq != -1) |
937 free_irq(mga_irq, &mga_irq); | |
68 | 938 #endif |
48 | 939 |
1 | 940 if(mga_mmio_base) |
941 iounmap(mga_mmio_base); | |
942 | |
943 //FIXME turn off BES | |
63 | 944 printk(KERN_INFO "mga_vid: Cleaning up module\n"); |
1 | 945 unregister_chrdev(MGA_VID_MAJOR, "mga_vid"); |
946 } | |
947 |