Mercurial > mplayer.hg
annotate vidix/sis_regs.h @ 32404:2f42741403a8
ignore debhelper generated debug logfiles
author | siretart |
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date | Thu, 14 Oct 2010 08:43:19 +0000 |
parents | 3abd1629658b |
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rev | line source |
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23074 | 1 /* |
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2 * SiS register definitions and access macros |
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3 * From SiS X11 driver |
23074 | 4 * |
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5 * Copyright (C) 2001-2003 by Thomas Winischhofer, Vienna, Austria |
23074 | 6 * |
7 * This file is part of MPlayer. | |
8 * | |
9 * MPlayer is free software; you can redistribute it and/or modify | |
10 * it under the terms of the GNU General Public License as published by | |
11 * the Free Software Foundation; either version 2 of the License, or | |
12 * (at your option) any later version. | |
13 * | |
14 * MPlayer is distributed in the hope that it will be useful, | |
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 * GNU General Public License for more details. | |
18 * | |
26719 | 19 * You should have received a copy of the GNU General Public License along |
20 * with MPlayer; if not, write to the Free Software Foundation, Inc., | |
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
23074 | 22 */ |
22850 | 23 |
26030 | 24 #ifndef MPLAYER_SIS_REGS_H |
25 #define MPLAYER_SIS_REGS_H | |
22850 | 26 |
27 #define inSISREG(base) INPORT8(base) | |
28 #define outSISREG(base,val) OUTPORT8(base, val) | |
29 #define orSISREG(base,val) do { \ | |
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30 unsigned char tmp = INPORT8(base); \ |
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31 outSISREG(base, tmp | (val)); \ |
22850 | 32 } while (0) |
33 #define andSISREG(base,val) do { \ | |
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34 unsigned char tmp = INPORT8(base); \ |
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35 outSISREG(base, tmp & (val)); \ |
22850 | 36 } while (0) |
37 | |
38 #define inSISIDXREG(base,idx,var) do { \ | |
39 OUTPORT8(base, idx); var=INPORT8((base)+1); \ | |
40 } while (0) | |
41 #define outSISIDXREG(base,idx,val) do { \ | |
42 OUTPORT8(base, idx); OUTPORT8((base)+1, val); \ | |
43 } while (0) | |
44 #define orSISIDXREG(base,idx,val) do { \ | |
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45 unsigned char tmp; \ |
22850 | 46 OUTPORT8(base, idx); \ |
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47 tmp = INPORT8((base)+1)|(val); \ |
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48 outSISIDXREG(base,idx,tmp); \ |
22850 | 49 } while (0) |
50 #define andSISIDXREG(base,idx,and) do { \ | |
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51 unsigned char tmp; \ |
22850 | 52 OUTPORT8(base, idx); \ |
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53 tmp = INPORT8((base)+1)&(and); \ |
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54 outSISIDXREG(base,idx,tmp); \ |
22850 | 55 } while (0) |
56 #define setSISIDXREG(base,idx,and,or) do { \ | |
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57 unsigned char tmp; \ |
22850 | 58 OUTPORT8(base, idx); \ |
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59 tmp = (INPORT8((base)+1)&(and))|(or); \ |
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60 outSISIDXREG(base,idx,tmp); \ |
22850 | 61 } while (0) |
62 | |
63 #define BITMASK(h,l) (((unsigned)(1U << ((h)-(l)+1))-1)<<(l)) | |
64 #define GENMASK(mask) BITMASK(1?mask,0?mask) | |
65 | |
66 #define GETBITS(var,mask) (((var) & GENMASK(mask)) >> (0?mask)) | |
67 #define SETBITS(val,mask) ((val) << (0?mask)) | |
68 #define SETBIT(n) (1<<(n)) | |
69 | |
70 #define GETBITSTR(val,from,to) ((GETBITS(val,from)) << (0?to)) | |
71 #define SETVARBITS(var,val,from,to) (((var)&(~(GENMASK(to)))) | \ | |
72 GETBITSTR(val,from,to)) | |
73 #define GETVAR8(var) ((var)&0xFF) | |
74 #define SETVAR8(var,val) (var) = GETVAR8(val) | |
75 | |
76 /* #define VGA_RELIO_BASE 0x380 */ | |
77 | |
78 #define AROFFSET 0x40 /* VGA_ATTR_INDEX - VGA_RELIO_BASE */ | |
79 #define ARROFFSET 0x41 /* VGA_ATTR_DATA_R - VGA_RELIO_BASE */ | |
80 #define GROFFSET 0x4e /* VGA_GRAPH_INDEX - VGA_RELIO_BASE */ | |
81 #define SROFFSET 0x44 /* VGA_SEQ_INDEX - VGA_RELIO_BASE */ | |
82 #define CROFFSET 0x54 /* VGA_CRTC_INDEX_OFFSET + VGA_IOBASE_COLOR - VGA_RELIO_BASE */ | |
83 #define MISCROFFSET 0x4c /* VGA_MISC_OUT_R - VGA_RELIO_BASE */ | |
84 #define MISCWOFFSET 0x42 /* VGA_MISC_OUT_W - VGA_RELIO_BASE */ | |
85 #define INPUTSTATOFFSET 0x5A | |
86 #define PART1OFFSET 0x04 | |
87 #define PART2OFFSET 0x10 | |
88 #define PART3OFFSET 0x12 | |
89 #define PART4OFFSET 0x14 | |
90 #define PART5OFFSET 0x16 | |
91 #define VIDEOOFFSET 0x02 | |
92 #define COLREGOFFSET 0x48 | |
93 | |
94 #define SIS_IOBASE sis_iobase /* var defined in sis_vid.c */ | |
95 #define SISAR SIS_IOBASE + AROFFSET | |
96 #define SISARR SIS_IOBASE + ARROFFSET | |
97 #define SISGR SIS_IOBASE + GROFFSET | |
98 #define SISSR SIS_IOBASE + SROFFSET | |
99 #define SISCR SIS_IOBASE + CROFFSET | |
100 #define SISMISCR SIS_IOBASE + MISCROFFSET | |
101 #define SISMISCW SIS_IOBASE + MISCWOFFSET | |
102 #define SISINPSTAT SIS_IOBASE + INPUTSTATOFFSET | |
103 #define SISPART1 SIS_IOBASE + PART1OFFSET | |
104 #define SISPART2 SIS_IOBASE + PART2OFFSET | |
105 #define SISPART3 SIS_IOBASE + PART3OFFSET | |
106 #define SISPART4 SIS_IOBASE + PART4OFFSET | |
107 #define SISPART5 SIS_IOBASE + PART5OFFSET | |
108 #define SISVID SIS_IOBASE + VIDEOOFFSET | |
109 #define SISCOLIDX SIS_IOBASE + COLREGOFFSET | |
110 #define SISCOLDATA SIS_IOBASE + COLREGOFFSET + 1 | |
111 #define SISCOL2IDX SISPART5 | |
112 #define SISCOL2DATA SISPART5 + 1 | |
113 | |
114 | |
115 #define vc_index_offset 0x00 /* Video capture - unused */ | |
116 #define vc_data_offset 0x01 | |
117 #define vi_index_offset VIDEOOFFSET | |
118 #define vi_data_offset (VIDEOOFFSET + 1) | |
119 #define crt2_index_offset PART1OFFSET | |
120 #define crt2_port_offset (PART1OFFSET + 1) | |
121 #define sr_index_offset SROFFSET | |
122 #define sr_data_offset (SROFFSET + 1) | |
123 #define cr_index_offset CROFFSET | |
124 #define cr_data_offset (CROFFSET + 1) | |
125 #define input_stat INPUTSTATOFFSET | |
126 | |
127 /* For old chipsets (5597/5598, 6326, 530/620) ------------ */ | |
128 /* SR (3C4) */ | |
129 #define BankReg 0x06 | |
130 #define ClockReg 0x07 | |
131 #define CPUThreshold 0x08 | |
132 #define CRTThreshold 0x09 | |
133 #define CRTCOff 0x0A | |
134 #define DualBanks 0x0B | |
135 #define MMIOEnable 0x0B | |
136 #define RAMSize 0x0C | |
137 #define Mode64 0x0C | |
138 #define ExtConfStatus1 0x0E | |
139 #define ClockBase 0x13 | |
140 #define LinearAdd0 0x20 | |
141 #define LinearAdd1 0x21 | |
142 #define GraphEng 0x27 | |
143 #define MemClock0 0x28 | |
144 #define MemClock1 0x29 | |
145 #define XR2A 0x2A | |
146 #define XR2B 0x2B | |
147 #define TurboQueueBase 0x2C | |
148 #define FBSize 0x2F | |
149 #define ExtMiscCont5 0x34 | |
150 #define ExtMiscCont9 0x3C | |
151 | |
152 /* 3x4 */ | |
153 #define Offset 0x13 | |
154 | |
155 /* SiS Registers for 300, 540, 630, 730, 315, 550, 650, 740 */ | |
156 | |
157 /* VGA standard register */ | |
158 #define Index_SR_Graphic_Mode 0x06 | |
159 #define Index_SR_RAMDAC_Ctrl 0x07 | |
160 #define Index_SR_Threshold_Ctrl1 0x08 | |
161 #define Index_SR_Threshold_Ctrl2 0x09 | |
162 #define Index_SR_Misc_Ctrl 0x0F | |
163 #define Index_SR_DDC 0x11 | |
164 #define Index_SR_Feature_Connector_Ctrl 0x12 | |
165 #define Index_SR_DRAM_Sizing 0x14 | |
166 #define Index_SR_DRAM_State_Machine_Ctrl 0x15 | |
167 #define Index_SR_AGP_PCI_State_Machine 0x21 | |
168 #define Index_SR_Internal_MCLK0 0x28 | |
169 #define Index_SR_Internal_MCLK1 0x29 | |
170 #define Index_SR_Internal_DCLK1 0x2B | |
171 #define Index_SR_Internal_DCLK2 0x2C | |
172 #define Index_SR_Internal_DCLK3 0x2D | |
173 #define Index_SR_Ext_Clock_Sel 0x32 | |
174 #define Index_SR_Int_Status 0x34 | |
175 #define Index_SR_Int_Enable 0x35 | |
176 #define Index_SR_Int_Reset 0x36 | |
177 #define Index_SR_Power_On_Trap 0x38 | |
178 #define Index_SR_Power_On_Trap2 0x39 | |
179 #define Index_SR_Power_On_Trap3 0x3A | |
180 | |
181 /* video registers (300/630/730/315/550/650/740 only) */ | |
182 #define Index_VI_Passwd 0x00 | |
183 | |
184 /* Video overlay horizontal start/end, unit=screen pixels */ | |
185 #define Index_VI_Win_Hor_Disp_Start_Low 0x01 | |
186 #define Index_VI_Win_Hor_Disp_End_Low 0x02 | |
187 #define Index_VI_Win_Hor_Over 0x03 /* Overflow */ | |
188 | |
189 /* Video overlay vertical start/end, unit=screen pixels */ | |
190 #define Index_VI_Win_Ver_Disp_Start_Low 0x04 | |
191 #define Index_VI_Win_Ver_Disp_End_Low 0x05 | |
192 #define Index_VI_Win_Ver_Over 0x06 /* Overflow */ | |
193 | |
194 /* Y Plane (4:2:0) or YUV (4:2:2) buffer start address, unit=word */ | |
195 #define Index_VI_Disp_Y_Buf_Start_Low 0x07 | |
196 #define Index_VI_Disp_Y_Buf_Start_Middle 0x08 | |
197 #define Index_VI_Disp_Y_Buf_Start_High 0x09 | |
198 | |
199 /* U Plane (4:2:0) buffer start address, unit=word */ | |
200 #define Index_VI_U_Buf_Start_Low 0x0A | |
201 #define Index_VI_U_Buf_Start_Middle 0x0B | |
202 #define Index_VI_U_Buf_Start_High 0x0C | |
203 | |
204 /* V Plane (4:2:0) buffer start address, unit=word */ | |
205 #define Index_VI_V_Buf_Start_Low 0x0D | |
206 #define Index_VI_V_Buf_Start_Middle 0x0E | |
207 #define Index_VI_V_Buf_Start_High 0x0F | |
208 | |
209 /* Pitch for Y, UV Planes, unit=word */ | |
210 #define Index_VI_Disp_Y_Buf_Pitch_Low 0x10 | |
211 #define Index_VI_Disp_UV_Buf_Pitch_Low 0x11 | |
212 #define Index_VI_Disp_Y_UV_Buf_Pitch_Middle 0x12 | |
213 | |
214 /* What is this ? */ | |
215 #define Index_VI_Disp_Y_Buf_Preset_Low 0x13 | |
216 #define Index_VI_Disp_Y_Buf_Preset_Middle 0x14 | |
217 | |
218 #define Index_VI_UV_Buf_Preset_Low 0x15 | |
219 #define Index_VI_UV_Buf_Preset_Middle 0x16 | |
220 #define Index_VI_Disp_Y_UV_Buf_Preset_High 0x17 | |
221 | |
222 /* Scaling control registers */ | |
223 #define Index_VI_Hor_Post_Up_Scale_Low 0x18 | |
224 #define Index_VI_Hor_Post_Up_Scale_High 0x19 | |
225 #define Index_VI_Ver_Up_Scale_Low 0x1A | |
226 #define Index_VI_Ver_Up_Scale_High 0x1B | |
227 #define Index_VI_Scale_Control 0x1C | |
228 | |
229 /* Playback line buffer control */ | |
230 #define Index_VI_Play_Threshold_Low 0x1D | |
231 #define Index_VI_Play_Threshold_High 0x1E | |
232 #define Index_VI_Line_Buffer_Size 0x1F | |
233 | |
234 /* Destination color key */ | |
235 #define Index_VI_Overlay_ColorKey_Red_Min 0x20 | |
236 #define Index_VI_Overlay_ColorKey_Green_Min 0x21 | |
237 #define Index_VI_Overlay_ColorKey_Blue_Min 0x22 | |
238 #define Index_VI_Overlay_ColorKey_Red_Max 0x23 | |
239 #define Index_VI_Overlay_ColorKey_Green_Max 0x24 | |
240 #define Index_VI_Overlay_ColorKey_Blue_Max 0x25 | |
241 | |
242 /* Source color key, YUV color space */ | |
243 #define Index_VI_Overlay_ChromaKey_Red_Y_Min 0x26 | |
244 #define Index_VI_Overlay_ChromaKey_Green_U_Min 0x27 | |
245 #define Index_VI_Overlay_ChromaKey_Blue_V_Min 0x28 | |
246 #define Index_VI_Overlay_ChromaKey_Red_Y_Max 0x29 | |
247 #define Index_VI_Overlay_ChromaKey_Green_U_Max 0x2A | |
248 #define Index_VI_Overlay_ChromaKey_Blue_V_Max 0x2B | |
249 | |
250 /* Contrast enhancement and brightness control */ | |
251 #define Index_VI_Contrast_Factor 0x2C /* obviously unused/undefined */ | |
252 #define Index_VI_Brightness 0x2D | |
253 #define Index_VI_Contrast_Enh_Ctrl 0x2E | |
254 | |
255 #define Index_VI_Key_Overlay_OP 0x2F | |
256 | |
257 #define Index_VI_Control_Misc0 0x30 | |
258 #define Index_VI_Control_Misc1 0x31 | |
259 #define Index_VI_Control_Misc2 0x32 | |
260 | |
261 /* TW: Subpicture registers */ | |
262 #define Index_VI_SubPict_Buf_Start_Low 0x33 | |
263 #define Index_VI_SubPict_Buf_Start_Middle 0x34 | |
264 #define Index_VI_SubPict_Buf_Start_High 0x35 | |
265 | |
266 /* TW: What is this ? */ | |
267 #define Index_VI_SubPict_Buf_Preset_Low 0x36 | |
268 #define Index_VI_SubPict_Buf_Preset_Middle 0x37 | |
269 | |
270 /* TW: Subpicture pitch, unit=16 bytes */ | |
271 #define Index_VI_SubPict_Buf_Pitch 0x38 | |
272 | |
273 /* TW: Subpicture scaling control */ | |
274 #define Index_VI_SubPict_Hor_Scale_Low 0x39 | |
275 #define Index_VI_SubPict_Hor_Scale_High 0x3A | |
276 #define Index_VI_SubPict_Vert_Scale_Low 0x3B | |
277 #define Index_VI_SubPict_Vert_Scale_High 0x3C | |
278 | |
279 #define Index_VI_SubPict_Scale_Control 0x3D | |
280 /* (0x40 = enable/disable subpicture) */ | |
281 | |
282 /* TW: Subpicture line buffer control */ | |
283 #define Index_VI_SubPict_Threshold 0x3E | |
284 | |
285 /* TW: What is this? */ | |
286 #define Index_VI_FIFO_Max 0x3F | |
287 | |
288 /* TW: Subpicture palette; 16 colors, total 32 bytes address space */ | |
289 #define Index_VI_SubPict_Pal_Base_Low 0x40 | |
290 #define Index_VI_SubPict_Pal_Base_High 0x41 | |
291 | |
292 /* I wish I knew how to use these ... */ | |
293 #define Index_MPEG_Read_Ctrl0 0x60 /* MPEG auto flip */ | |
294 #define Index_MPEG_Read_Ctrl1 0x61 /* MPEG auto flip */ | |
295 #define Index_MPEG_Read_Ctrl2 0x62 /* MPEG auto flip */ | |
296 #define Index_MPEG_Read_Ctrl3 0x63 /* MPEG auto flip */ | |
297 | |
298 /* TW: MPEG AutoFlip scale */ | |
299 #define Index_MPEG_Ver_Up_Scale_Low 0x64 | |
300 #define Index_MPEG_Ver_Up_Scale_High 0x65 | |
301 | |
302 #define Index_MPEG_Y_Buf_Preset_Low 0x66 | |
303 #define Index_MPEG_Y_Buf_Preset_Middle 0x67 | |
304 #define Index_MPEG_UV_Buf_Preset_Low 0x68 | |
305 #define Index_MPEG_UV_Buf_Preset_Middle 0x69 | |
306 #define Index_MPEG_Y_UV_Buf_Preset_High 0x6A | |
307 | |
308 /* TW: The following registers only exist on the 310/325 series */ | |
309 | |
310 /* TW: Bit 16:24 of Y_U_V buf start address (?) */ | |
311 #define Index_VI_Y_Buf_Start_Over 0x6B | |
312 #define Index_VI_U_Buf_Start_Over 0x6C | |
313 #define Index_VI_V_Buf_Start_Over 0x6D | |
314 | |
315 #define Index_VI_Disp_Y_Buf_Pitch_High 0x6E | |
316 #define Index_VI_Disp_UV_Buf_Pitch_High 0x6F | |
317 | |
318 /* Hue and saturation */ | |
319 #define Index_VI_Hue 0x70 | |
320 #define Index_VI_Saturation 0x71 | |
321 | |
322 #define Index_VI_SubPict_Start_Over 0x72 | |
323 #define Index_VI_SubPict_Buf_Pitch_High 0x73 | |
324 | |
325 #define Index_VI_Control_Misc3 0x74 | |
326 | |
327 | |
328 /* TW: Bits (and helpers) for Index_VI_Control_Misc0 */ | |
329 #define VI_Misc0_Enable_Overlay 0x02 | |
330 #define VI_Misc0_420_Plane_Enable 0x04 /* Select Plane or Packed mode */ | |
331 #define VI_Misc0_422_Enable 0x20 /* Select 422 or 411 mode */ | |
332 #define VI_Misc0_Fmt_YVU420P 0x0C /* YUV420 Planar (I420, YV12) */ | |
333 #define VI_Misc0_Fmt_YUYV 0x28 /* YUYV Packed (YUY2) */ | |
334 #define VI_Misc0_Fmt_UYVY 0x08 /* (UYVY) */ | |
335 | |
336 /* TW: Bits for Index_VI_Control_Misc1 */ | |
337 /* #define VI_Misc1_? 0x01 */ | |
338 #define VI_Misc1_BOB_Enable 0x02 | |
339 #define VI_Misc1_Line_Merge 0x04 | |
340 #define VI_Misc1_Field_Mode 0x08 | |
341 /* #define VI_Misc1_? 0x10 */ | |
342 #define VI_Misc1_Non_Interleave 0x20 /* 300 series only? */ | |
343 #define VI_Misc1_Buf_Addr_Lock 0x20 /* 310 series only? */ | |
344 /* #define VI_Misc1_? 0x40 */ | |
345 /* #define VI_Misc1_? 0x80 */ | |
346 | |
347 /* TW: Bits for Index_VI_Control_Misc2 */ | |
348 #define VI_Misc2_Select_Video2 0x01 | |
349 #define VI_Misc2_Video2_On_Top 0x02 | |
350 /* #define VI_Misc2_? 0x04 */ | |
351 #define VI_Misc2_Vertical_Interpol 0x08 | |
352 #define VI_Misc2_Dual_Line_Merge 0x10 | |
353 #define VI_Misc2_All_Line_Merge 0x20 /* 310 series only? */ | |
354 #define VI_Misc2_Auto_Flip_Enable 0x40 /* 300 series only? */ | |
355 #define VI_Misc2_Video_Reg_Write_Enable 0x80 /* 310 series only? */ | |
356 | |
357 /* TW: Bits for Index_VI_Control_Misc3 */ | |
358 #define VI_Misc3_Submit_Video_1 0x01 /* AKA "address ready" */ | |
359 #define VI_Misc3_Submit_Video_2 0x02 /* AKA "address ready" */ | |
360 #define VI_Misc3_Submit_SubPict 0x04 /* AKA "address ready" */ | |
361 | |
362 /* TW: Values for Index_VI_Key_Overlay_OP (0x2F) */ | |
363 #define VI_ROP_Never 0x00 | |
364 #define VI_ROP_DestKey 0x03 | |
365 #define VI_ROP_Always 0x0F | |
366 | |
367 /* | |
368 * CRT_2 function control register --------------------------------- | |
369 */ | |
370 #define Index_CRT2_FC_CONTROL 0x00 | |
371 #define Index_CRT2_FC_SCREEN_HIGH 0x04 | |
372 #define Index_CRT2_FC_SCREEN_MID 0x05 | |
373 #define Index_CRT2_FC_SCREEN_LOW 0x06 | |
374 #define Index_CRT2_FC_ENABLE_WRITE 0x24 | |
375 #define Index_CRT2_FC_VR 0x25 | |
376 #define Index_CRT2_FC_VCount 0x27 | |
377 #define Index_CRT2_FC_VCount1 0x28 | |
378 | |
379 #define Index_310_CRT2_FC_VR 0x30 /* d[1] = vertical retrace */ | |
380 #define Index_310_CRT2_FC_RT 0x33 /* d[7] = retrace in progress */ | |
381 | |
382 /* video attributes - these should probably be configurable on the fly | |
383 * so users with different desktop sizes can keep | |
384 * captured data off the desktop | |
385 */ | |
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386 #define VINWID 704 |
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387 #define VINHGT VINHGT_NTSC |
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388 #define VINHGT_NTSC 240 |
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389 #define VINHGT_PAL 290 |
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390 #define VIN_WINDOW (704 * 291 * 2) |
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391 #define VBI_WINDOW (704 * 64 * 2) |
22850 | 392 |
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393 #define VIN_FIELD_EVEN 1 |
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394 #define VIN_FIELD_ODD 2 |
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changeset
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395 #define VIN_FIELD_BOTH 4 |
22850 | 396 |
397 | |
398 /* i2c registers (TW; not on 300/310/325 series) */ | |
399 #define X_INDEXREG 0x14 | |
400 #define X_PORTREG 0x15 | |
401 #define X_DATA 0x0f | |
402 #define I2C_SCL 0x00 | |
403 #define I2C_SDA 0x01 | |
404 #define I2C_DELAY 10 | |
405 | |
406 /* mmio registers for video */ | |
407 #define REG_PRIM_CRT_COUNTER 0x8514 | |
408 | |
409 /* TW: MPEG MMIO registers (630 and later) ----------------------------*/ | |
410 | |
411 /* Not public (yet?) */ | |
412 | |
26030 | 413 #endif /* MPLAYER_SIS_REGS_H */ |