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1911
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1 #ifndef _RADEON_H
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2 #define _RADEON_H
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3
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4
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5 /* radeon PCI ids */
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6 #define PCI_DEVICE_ID_RADEON_QD 0x5144
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7 #define PCI_DEVICE_ID_RADEON_QE 0x5145
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8 #define PCI_DEVICE_ID_RADEON_QF 0x5146
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9 #define PCI_DEVICE_ID_RADEON_QG 0x5147
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1913
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10 #define PCI_DEVICE_ID_RADEON_QY 0x5159
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11 #define PCI_DEVICE_ID_RADEON_QZ 0x515A
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1915
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12 #define PCI_DEVICE_ID_RADEON_LY 0x4C59
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13 #define PCI_DEVICE_ID_RADEON_LZ 0x4C5A
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14 #define PCI_DEVICE_ID_RADEON_LW 0x4C57
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1911
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15
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16 #define RADEON_REGSIZE 0x4000
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17
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18
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19 #define MM_INDEX 0x0000
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1915
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20 /* MM_INDEX bit constants */
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21 # define MM_APER 0x80000000
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1911
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22 #define MM_DATA 0x0004
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23 #define BUS_CNTL 0x0030
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1915
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24 /* BUS_CNTL bit constants */
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25 # define BUS_DBL_RESYNC 0x00000001
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26 # define BUS_MSTR_RESET 0x00000002
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27 # define BUS_FLUSH_BUF 0x00000004
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28 # define BUS_STOP_REQ_DIS 0x00000008
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29 # define BUS_ROTATION_DIS 0x00000010
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30 # define BUS_MASTER_DIS 0x00000040
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31 # define BUS_ROM_WRT_EN 0x00000080
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32 # define BUS_DIS_ROM 0x00001000
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33 # define BUS_PCI_READ_RETRY_EN 0x00002000
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34 # define BUS_AGP_AD_STEPPING_EN 0x00004000
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35 # define BUS_PCI_WRT_RETRY_EN 0x00008000
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36 # define BUS_MSTR_RD_MULT 0x00100000
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37 # define BUS_MSTR_RD_LINE 0x00200000
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38 # define BUS_SUSPEND 0x00400000
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39 # define LAT_16X 0x00800000
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40 # define BUS_RD_DISCARD_EN 0x01000000
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41 # define BUS_RD_ABORT_EN 0x02000000
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42 # define BUS_MSTR_WS 0x04000000
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43 # define BUS_PARKING_DIS 0x08000000
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44 # define BUS_MSTR_DISCONNECT_EN 0x10000000
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45 # define BUS_WRT_BURST 0x20000000
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46 # define BUS_READ_BURST 0x40000000
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47 # define BUS_RDY_READ_DLY 0x80000000
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1911
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48 #define HI_STAT 0x004C
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49 #define BUS_CNTL1 0x0034
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1915
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50 # define BUS_WAIT_ON_LOCK_EN (1 << 4)
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1911
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51 #define I2C_CNTL_1 0x0094
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52 #define CONFIG_CNTL 0x00E0
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1915
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53 /* CONFIG_CNTL bit constants */
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54 # define CFG_VGA_RAM_EN 0x00000100
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1911
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55 #define CONFIG_MEMSIZE 0x00F8
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56 #define CONFIG_APER_0_BASE 0x0100
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57 #define CONFIG_APER_1_BASE 0x0104
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58 #define CONFIG_APER_SIZE 0x0108
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59 #define CONFIG_REG_1_BASE 0x010C
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60 #define CONFIG_REG_APER_SIZE 0x0110
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61 #define PAD_AGPINPUT_DELAY 0x0164
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62 #define PAD_CTLR_STRENGTH 0x0168
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63 #define PAD_CTLR_UPDATE 0x016C
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64 #define AGP_CNTL 0x0174
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1915
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65 # define AGP_APER_SIZE_256MB (0x00 << 0)
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66 # define AGP_APER_SIZE_128MB (0x20 << 0)
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67 # define AGP_APER_SIZE_64MB (0x30 << 0)
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68 # define AGP_APER_SIZE_32MB (0x38 << 0)
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69 # define AGP_APER_SIZE_16MB (0x3c << 0)
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70 # define AGP_APER_SIZE_8MB (0x3e << 0)
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71 # define AGP_APER_SIZE_4MB (0x3f << 0)
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72 # define AGP_APER_SIZE_MASK (0x3f << 0)
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1911
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73 #define BM_STATUS 0x0160
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74 #define CAP0_TRIG_CNTL 0x0950
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75 #define VIPH_CONTROL 0x0C40
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76 #define VENDOR_ID 0x0F00
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77 #define DEVICE_ID 0x0F02
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78 #define COMMAND 0x0F04
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79 #define STATUS 0x0F06
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80 #define REVISION_ID 0x0F08
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81 #define REGPROG_INF 0x0F09
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82 #define SUB_CLASS 0x0F0A
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83 #define BASE_CODE 0x0F0B
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84 #define CACHE_LINE 0x0F0C
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85 #define LATENCY 0x0F0D
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86 #define HEADER 0x0F0E
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87 #define BIST 0x0F0F
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88 #define REG_MEM_BASE 0x0F10
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89 #define REG_IO_BASE 0x0F14
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90 #define REG_REG_BASE 0x0F18
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91 #define ADAPTER_ID 0x0F2C
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92 #define BIOS_ROM 0x0F30
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93 #define CAPABILITIES_PTR 0x0F34
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94 #define INTERRUPT_LINE 0x0F3C
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95 #define INTERRUPT_PIN 0x0F3D
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96 #define MIN_GRANT 0x0F3E
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97 #define MAX_LATENCY 0x0F3F
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98 #define ADAPTER_ID_W 0x0F4C
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99 #define PMI_CAP_ID 0x0F50
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100 #define PMI_NXT_CAP_PTR 0x0F51
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101 #define PMI_PMC_REG 0x0F52
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102 #define PM_STATUS 0x0F54
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103 #define PMI_DATA 0x0F57
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104 #define AGP_CAP_ID 0x0F58
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105 #define AGP_STATUS 0x0F5C
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1915
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106 # define AGP_1X_MODE 0x01
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107 # define AGP_2X_MODE 0x02
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108 # define AGP_4X_MODE 0x04
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109 # define AGP_MODE_MASK 0x07
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1911
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110 #define AGP_COMMAND 0x0F60
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111 #define AIC_CTRL 0x01D0
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112 #define AIC_STAT 0x01D4
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113 #define AIC_PT_BASE 0x01D8
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114 #define AIC_LO_ADDR 0x01DC
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115 #define AIC_HI_ADDR 0x01E0
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116 #define AIC_TLB_ADDR 0x01E4
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117 #define AIC_TLB_DATA 0x01E8
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118 #define DAC_CNTL 0x0058
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1915
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119 /* DAC_CNTL bit constants */
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120 # define DAC_8BIT_EN 0x00000100
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121 # define DAC_4BPP_PIX_ORDER 0x00000200
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122 # define DAC_CRC_EN 0x00080000
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123 # define DAC_MASK_ALL (0xff << 24)
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124 # define DAC_VGA_ADR_EN (1 << 13)
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125 # define DAC_RANGE_CNTL (3 << 0)
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126 # define DAC_BLANKING (1 << 2)
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127 #define DAC_CNTL2 0x007c
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128 /* DAC_CNTL2 bit constants */
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129 # define DAC2_DAC_CLK_SEL (1 << 0)
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130 # define DAC2_DAC2_CLK_SEL (1 << 1)
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131 # define DAC2_PALETTE_ACC_CTL (1 << 5)
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132 #define TV_DAC_CNTL 0x088c
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133 /* TV_DAC_CNTL bit constants */
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134 # define TV_DAC_STD_MASK 0x0300
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135 # define TV_DAC_RDACPD (1 << 24)
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136 # define TV_DAC_GDACPD (1 << 25)
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137 # define TV_DAC_BDACPD (1 << 26)
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1911
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138 #define CRTC_GEN_CNTL 0x0050
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1915
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139 /* CRTC_GEN_CNTL bit constants */
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140 # define CRTC_DBL_SCAN_EN 0x00000001
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141 # define CRTC_INTERLACE_EN (1 << 1)
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142 # define CRTC_CSYNC_EN (1 << 4)
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143 # define CRTC_CUR_EN 0x00010000
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144 # define CRTC_CUR_MODE_MASK (7 << 17)
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145 # define CRTC_ICON_EN (1 << 20)
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146 # define CRTC_EXT_DISP_EN (1 << 24)
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147 # define CRTC_EN (1 << 25)
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148 # define CRTC_DISP_REQ_EN_B (1 << 26)
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149 #define CRTC2_GEN_CNTL 0x03f8
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150 /* CRTC2_GEN_CNTL bit constants */
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151 # define CRTC2_DBL_SCAN_EN (1 << 0)
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152 # define CRTC2_INTERLACE_EN (1 << 1)
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153 # define CRTC2_SYNC_TRISTAT (1 << 4)
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154 # define CRTC2_HSYNC_TRISTAT (1 << 5)
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155 # define CRTC2_VSYNC_TRISTAT (1 << 6)
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156 # define CRTC2_CRT2_ON (1 << 7)
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157 # define CRTC2_ICON_EN (1 << 15)
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158 # define CRTC2_CUR_EN (1 << 16)
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159 # define CRTC2_CUR_MODE_MASK (7 << 20)
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160 # define CRTC2_DISP_DIS (1 << 23)
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161 # define CRTC2_EN (1 << 25)
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162 # define CRTC2_DISP_REQ_EN_B (1 << 26)
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163 # define CRTC2_HSYNC_DIS (1 << 28)
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164 # define CRTC2_VSYNC_DIS (1 << 29)
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1911
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165 #define MEM_CNTL 0x0140
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1915
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166 /* MEM_CNTL bit constants */
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167 # define MEM_CTLR_STATUS_IDLE 0x00000000
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168 # define MEM_CTLR_STATUS_BUSY 0x00100000
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169 # define MEM_SEQNCR_STATUS_IDLE 0x00000000
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170 # define MEM_SEQNCR_STATUS_BUSY 0x00200000
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171 # define MEM_ARBITER_STATUS_IDLE 0x00000000
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172 # define MEM_ARBITER_STATUS_BUSY 0x00400000
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173 # define MEM_REQ_UNLOCK 0x00000000
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174 # define MEM_REQ_LOCK 0x00800000
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1911
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175 #define EXT_MEM_CNTL 0x0144
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176 #define MC_AGP_LOCATION 0x014C
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177 #define MEM_IO_CNTL_A0 0x0178
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178 #define MEM_INIT_LATENCY_TIMER 0x0154
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179 #define MEM_SDRAM_MODE_REG 0x0158
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180 #define AGP_BASE 0x0170
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181 #define MEM_IO_CNTL_A1 0x017C
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182 #define MEM_IO_CNTL_B0 0x0180
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183 #define MEM_IO_CNTL_B1 0x0184
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184 #define MC_DEBUG 0x0188
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185 #define MC_STATUS 0x0150
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186 #define MEM_IO_OE_CNTL 0x018C
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187 #define MC_FB_LOCATION 0x0148
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188 #define HOST_PATH_CNTL 0x0130
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189 #define MEM_VGA_WP_SEL 0x0038
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190 #define MEM_VGA_RP_SEL 0x003C
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191 #define HDP_DEBUG 0x0138
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192 #define SW_SEMAPHORE 0x013C
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193 #define SURFACE_CNTL 0x0B00
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1915
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194 /* SURFACE_CNTL bit constants */
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195 # define SURF_TRANSLATION_DIS (1 << 8)
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196 # define NONSURF_AP0_SWP_16BPP (1 << 20)
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197 # define NONSURF_AP0_SWP_32BPP (2 << 20)
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198 #define SURFACE0_LOWER_BOUND 0x0B04
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199 #define SURFACE1_LOWER_BOUND 0x0B14
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200 #define SURFACE2_LOWER_BOUND 0x0B24
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201 #define SURFACE3_LOWER_BOUND 0x0B34
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202 #define SURFACE4_LOWER_BOUND 0x0B44
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203 #define SURFACE5_LOWER_BOUND 0x0B54
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204 #define SURFACE6_LOWER_BOUND 0x0B64
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205 #define SURFACE7_LOWER_BOUND 0x0B74
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206 #define SURFACE0_UPPER_BOUND 0x0B08
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207 #define SURFACE1_UPPER_BOUND 0x0B18
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208 #define SURFACE2_UPPER_BOUND 0x0B28
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209 #define SURFACE3_UPPER_BOUND 0x0B38
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210 #define SURFACE4_UPPER_BOUND 0x0B48
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211 #define SURFACE5_UPPER_BOUND 0x0B58
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212 #define SURFACE6_UPPER_BOUND 0x0B68
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213 #define SURFACE7_UPPER_BOUND 0x0B78
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214 #define SURFACE0_INFO 0x0B0C
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215 #define SURFACE1_INFO 0x0B1C
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216 #define SURFACE2_INFO 0x0B2C
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217 #define SURFACE3_INFO 0x0B3C
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218 #define SURFACE4_INFO 0x0B4C
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219 #define SURFACE5_INFO 0x0B5C
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220 #define SURFACE6_INFO 0x0B6C
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221 #define SURFACE7_INFO 0x0B7C
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222 #define SURFACE_ACCESS_FLAGS 0x0BF8
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223 #define SURFACE_ACCESS_CLR 0x0BFC
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224 #define GEN_INT_CNTL 0x0040
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225 #define GEN_INT_STATUS 0x0044
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1915
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226 # define VSYNC_INT_AK (1 << 2)
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227 # define VSYNC_INT (1 << 2)
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1911
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228 #define CRTC_EXT_CNTL 0x0054
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1915
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229 /* CRTC_EXT_CNTL bit constants */
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230 # define CRTC_VGA_XOVERSCAN (1 << 0)
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231 # define VGA_ATI_LINEAR 0x00000008
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232 # define VGA_128KAP_PAGING 0x00000010
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233 # define XCRT_CNT_EN (1 << 6)
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234 # define CRTC_HSYNC_DIS (1 << 8)
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235 # define CRTC_VSYNC_DIS (1 << 9)
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236 # define CRTC_DISPLAY_DIS (1 << 10)
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237 # define CRTC_SYNC_TRISTAT (1 << 11)
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238 # define CRTC_CRT_ON (1 << 15)
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239 #define CRTC_EXT_CNTL_DPMS_BYTE 0x0055
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240 # define CRTC_HSYNC_DIS_BYTE (1 << 0)
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241 # define CRTC_VSYNC_DIS_BYTE (1 << 1)
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242 # define CRTC_DISPLAY_DIS_BYTE (1 << 2)
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1911
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243 #define RB3D_CNTL 0x1C3C
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244 #define WAIT_UNTIL 0x1720
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245 #define ISYNC_CNTL 0x1724
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246 #define RBBM_GUICNTL 0x172C
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247 #define RBBM_STATUS 0x0E40
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248 #define RBBM_STATUS_alt_1 0x1740
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249 #define RBBM_CNTL 0x00EC
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250 #define RBBM_CNTL_alt_1 0x0E44
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251 #define RBBM_SOFT_RESET 0x00F0
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1915
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252 /* RBBM_SOFT_RESET bit constants */
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253 # define SOFT_RESET_CP (1 << 0)
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254 # define SOFT_RESET_HI (1 << 1)
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255 # define SOFT_RESET_SE (1 << 2)
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256 # define SOFT_RESET_RE (1 << 3)
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257 # define SOFT_RESET_PP (1 << 4)
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258 # define SOFT_RESET_E2 (1 << 5)
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259 # define SOFT_RESET_RB (1 << 6)
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260 # define SOFT_RESET_HDP (1 << 7)
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261 #define RBBM_SOFT_RESET_alt_1 0x0E48
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262 #define NQWAIT_UNTIL 0x0E50
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263 #define RBBM_DEBUG 0x0E6C
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264 #define RBBM_CMDFIFO_ADDR 0x0E70
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265 #define RBBM_CMDFIFO_DATAL 0x0E74
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266 #define RBBM_CMDFIFO_DATAH 0x0E78
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267 #define RBBM_CMDFIFO_STAT 0x0E7C
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268 #define CRTC_STATUS 0x005C
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1915
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269 /* CRTC_STATUS bit constants */
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270 # define CRTC_VBLANK 0x00000001
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271 # define CRTC_VBLANK_SAVE (1 << 1)
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1911
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272 #define GPIO_VGA_DDC 0x0060
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273 #define GPIO_DVI_DDC 0x0064
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274 #define GPIO_MONID 0x0068
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275 #define PALETTE_INDEX 0x00B0
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276 #define PALETTE_DATA 0x00B4
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277 #define PALETTE_30_DATA 0x00B8
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278 #define CRTC_H_TOTAL_DISP 0x0200
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1915
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279 # define CRTC_H_TOTAL (0x03ff << 0)
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280 # define CRTC_H_TOTAL_SHIFT 0
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281 # define CRTC_H_DISP (0x01ff << 16)
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282 # define CRTC_H_DISP_SHIFT 16
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283 #define CRTC2_H_TOTAL_DISP 0x0300
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284 # define CRTC2_H_TOTAL (0x03ff << 0)
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285 # define CRTC2_H_TOTAL_SHIFT 0
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286 # define CRTC2_H_DISP (0x01ff << 16)
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287 # define CRTC2_H_DISP_SHIFT 16
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288 #define CRTC_H_SYNC_STRT_WID 0x0204
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289 # define CRTC_H_SYNC_STRT_PIX (0x07 << 0)
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290 # define CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)
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291 # define CRTC_H_SYNC_STRT_CHAR_SHIFT 3
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292 # define CRTC_H_SYNC_WID (0x3f << 16)
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293 # define CRTC_H_SYNC_WID_SHIFT 16
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294 # define CRTC_H_SYNC_POL (1 << 23)
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295 #define CRTC2_H_SYNC_STRT_WID 0x0304
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296 # define CRTC2_H_SYNC_STRT_PIX (0x07 << 0)
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297 # define CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)
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298 # define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
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299 # define CRTC2_H_SYNC_WID (0x3f << 16)
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300 # define CRTC2_H_SYNC_WID_SHIFT 16
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301 # define CRTC2_H_SYNC_POL (1 << 23)
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1911
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302 #define CRTC_V_TOTAL_DISP 0x0208
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1915
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303 # define CRTC_V_TOTAL (0x07ff << 0)
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304 # define CRTC_V_TOTAL_SHIFT 0
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305 # define CRTC_V_DISP (0x07ff << 16)
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306 # define CRTC_V_DISP_SHIFT 16
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307 #define CRTC2_V_TOTAL_DISP 0x0308
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308 # define CRTC2_V_TOTAL (0x07ff << 0)
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309 # define CRTC2_V_TOTAL_SHIFT 0
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310 # define CRTC2_V_DISP (0x07ff << 16)
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311 # define CRTC2_V_DISP_SHIFT 16
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1911
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312 #define CRTC_V_SYNC_STRT_WID 0x020C
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1915
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313 # define CRTC_V_SYNC_STRT (0x7ff << 0)
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314 # define CRTC_V_SYNC_STRT_SHIFT 0
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315 # define CRTC_V_SYNC_WID (0x1f << 16)
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316 # define CRTC_V_SYNC_WID_SHIFT 16
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317 # define CRTC_V_SYNC_POL (1 << 23)
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318 #define CRTC2_V_SYNC_STRT_WID 0x030C
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319 # define CRTC2_V_SYNC_STRT (0x7ff << 0)
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320 # define CRTC2_V_SYNC_STRT_SHIFT 0
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321 # define CRTC2_V_SYNC_WID (0x1f << 16)
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322 # define CRTC2_V_SYNC_WID_SHIFT 16
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323 # define CRTC2_V_SYNC_POL (1 << 23)
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1911
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324 #define CRTC_VLINE_CRNT_VLINE 0x0210
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1915
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325 # define CRTC_CRNT_VLINE_MASK (0x7ff << 16)
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326 #define CRTC2_VLINE_CRNT_VLINE 0x0310
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1911
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327 #define CRTC_CRNT_FRAME 0x0214
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1915
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328 #define CRTC2_CRNT_FRAME 0x0314
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1911
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329 #define CRTC_GUI_TRIG_VLINE 0x0218
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1915
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330 #define CRTC2_GUI_TRIG_VLINE 0x0318
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1911
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331 #define CRTC_DEBUG 0x021C
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1915
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332 #define CRTC2_DEBUG 0x031C
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1911
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333 #define CRTC_OFFSET_RIGHT 0x0220
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334 #define CRTC_OFFSET 0x0224
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1915
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335 #define CRTC2_OFFSET 0x0324
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1911
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336 #define CRTC_OFFSET_CNTL 0x0228
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1915
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337 # define CRTC_TILE_EN (1 << 15)
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338 #define CRTC2_OFFSET_CNTL 0x0328
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339 # define CRTC2_TILE_EN (1 << 15)
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1911
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340 #define CRTC_PITCH 0x022C
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1915
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341 #define CRTC2_PITCH 0x032C
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1911
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342 #define OVR_CLR 0x0230
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343 #define OVR_WID_LEFT_RIGHT 0x0234
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344 #define OVR_WID_TOP_BOTTOM 0x0238
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345 #define DISPLAY_BASE_ADDR 0x023C
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346 #define SNAPSHOT_VH_COUNTS 0x0240
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347 #define SNAPSHOT_F_COUNT 0x0244
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348 #define N_VIF_COUNT 0x0248
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349 #define SNAPSHOT_VIF_COUNT 0x024C
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350 #define FP_CRTC_H_TOTAL_DISP 0x0250
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1915
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351 #define FP_CRTC2_H_TOTAL_DISP 0x0350
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1911
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352 #define FP_CRTC_V_TOTAL_DISP 0x0254
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1915
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353 #define FP_CRTC2_V_TOTAL_DISP 0x0354
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1911
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354 #define CRT_CRTC_H_SYNC_STRT_WID 0x0258
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355 #define CRT_CRTC_V_SYNC_STRT_WID 0x025C
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356 #define CUR_OFFSET 0x0260
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357 #define CUR_HORZ_VERT_POSN 0x0264
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358 #define CUR_HORZ_VERT_OFF 0x0268
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1915
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359 /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
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360 # define CUR_LOCK 0x80000000
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1911
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361 #define CUR_CLR0 0x026C
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362 #define CUR_CLR1 0x0270
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1915
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363 #define CUR2_OFFSET 0x0360
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364 #define CUR2_HORZ_VERT_POSN 0x0364
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365 #define CUR2_HORZ_VERT_OFF 0x0368
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366 # define CUR2_LOCK (1 << 31)
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367 #define CUR2_CLR0 0x036c
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368 #define CUR2_CLR1 0x0370
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1911
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369 #define FP_HORZ_VERT_ACTIVE 0x0278
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370 #define CRTC_MORE_CNTL 0x027C
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371 #define DAC_EXT_CNTL 0x0280
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372 #define FP_GEN_CNTL 0x0284
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1915
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373 /* FP_GEN_CNTL bit constants */
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374 # define FP_FPON (1 << 0)
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375 # define FP_TMDS_EN (1 << 2)
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376 # define FP_EN_TMDS (1 << 7)
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377 # define FP_DETECT_SENSE (1 << 8)
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378 # define FP_SEL_CRTC2 (1 << 13)
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379 # define FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
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380 # define FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
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381 # define FP_CRTC_DONT_SHADOW_HEND (1 << 17)
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382 # define FP_CRTC_USE_SHADOW_VEND (1 << 18)
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383 # define FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
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384 # define FP_DFP_SYNC_SEL (1 << 21)
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385 # define FP_CRTC_LOCK_8DOT (1 << 22)
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386 # define FP_CRT_SYNC_SEL (1 << 23)
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387 # define FP_USE_SHADOW_EN (1 << 24)
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388 # define FP_CRT_SYNC_ALT (1 << 26)
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389 #define FP2_GEN_CNTL 0x0288
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390 /* FP2_GEN_CNTL bit constants */
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391 # define FP2_FPON (1 << 0)
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392 # define FP2_TMDS_EN (1 << 2)
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393 # define FP2_EN_TMDS (1 << 7)
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394 # define FP2_DETECT_SENSE (1 << 8)
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395 # define FP2_SEL_CRTC2 (1 << 13)
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396 # define FP2_FP_POL (1 << 16)
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397 # define FP2_LP_POL (1 << 17)
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398 # define FP2_SCK_POL (1 << 18)
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399 # define FP2_LCD_CNTL_MASK (7 << 19)
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400 # define FP2_PAD_FLOP_EN (1 << 22)
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401 # define FP2_CRC_EN (1 << 23)
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402 # define FP2_CRC_READ_EN (1 << 24)
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1911
|
403 #define FP_HORZ_STRETCH 0x028C
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404 #define FP_VERT_STRETCH 0x0290
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405 #define FP_H_SYNC_STRT_WID 0x02C4
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1915
|
406 #define FP_H2_SYNC_STRT_WID 0x03C4
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1911
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407 #define FP_V_SYNC_STRT_WID 0x02C8
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1915
|
408 #define FP_V2_SYNC_STRT_WID 0x03C8
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409 #define FP_HORZ_STRETCH 0x028C
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410 #define FP_HORZ2_STRETCH 0x038C
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411 #define FP_VERT_STRETCH 0x0290
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412 #define FP_VERT2_STRETCH 0x0390
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1911
|
413 #define AUX_WINDOW_HORZ_CNTL 0x02D8
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414 #define AUX_WINDOW_VERT_CNTL 0x02DC
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415 #define DDA_CONFIG 0x02e0
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416 #define DDA_ON_OFF 0x02e4
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417 #define GRPH_BUFFER_CNTL 0x02F0
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418 #define VGA_BUFFER_CNTL 0x02F4
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419 #define OV0_Y_X_START 0x0400
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420 #define OV0_Y_X_END 0x0404
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421 #define OV0_PIPELINE_CNTL 0x0408
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422 #define OV0_REG_LOAD_CNTL 0x0410
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423 #define OV0_SCALE_CNTL 0x0420
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424 #define OV0_V_INC 0x0424
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425 #define OV0_P1_V_ACCUM_INIT 0x0428
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426 #define OV0_P23_V_ACCUM_INIT 0x042C
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427 #define OV0_P1_BLANK_LINES_AT_TOP 0x0430
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428 #define OV0_P23_BLANK_LINES_AT_TOP 0x0434
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429 #define OV0_BASE_ADDR 0x043C
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430 #define OV0_VID_BUF0_BASE_ADRS 0x0440
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431 #define OV0_VID_BUF1_BASE_ADRS 0x0444
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432 #define OV0_VID_BUF2_BASE_ADRS 0x0448
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433 #define OV0_VID_BUF3_BASE_ADRS 0x044C
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434 #define OV0_VID_BUF4_BASE_ADRS 0x0450
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435 #define OV0_VID_BUF5_BASE_ADRS 0x0454
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436 #define OV0_VID_BUF_PITCH0_VALUE 0x0460
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437 #define OV0_VID_BUF_PITCH1_VALUE 0x0464
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438 #define OV0_AUTO_FLIP_CNTRL 0x0470
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439 #define OV0_DEINTERLACE_PATTERN 0x0474
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440 #define OV0_SUBMIT_HISTORY 0x0478
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441 #define OV0_H_INC 0x0480
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442 #define OV0_STEP_BY 0x0484
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443 #define OV0_P1_H_ACCUM_INIT 0x0488
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444 #define OV0_P23_H_ACCUM_INIT 0x048C
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445 #define OV0_P1_X_START_END 0x0494
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446 #define OV0_P2_X_START_END 0x0498
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447 #define OV0_P3_X_START_END 0x049C
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|
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448 #define OV0_FILTER_CNTL 0x04A0
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449 #define OV0_FOUR_TAP_COEF_0 0x04B0
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|
450 #define OV0_FOUR_TAP_COEF_1 0x04B4
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451 #define OV0_FOUR_TAP_COEF_2 0x04B8
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452 #define OV0_FOUR_TAP_COEF_3 0x04BC
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453 #define OV0_FOUR_TAP_COEF_4 0x04C0
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454 #define OV0_FLAG_CNTRL 0x04DC
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455 #define OV0_SLICE_CNTL 0x04E0
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|
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456 #define OV0_VID_KEY_CLR_LOW 0x04E4
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|
457 #define OV0_VID_KEY_CLR_HIGH 0x04E8
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458 #define OV0_GRPH_KEY_CLR_LOW 0x04EC
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459 #define OV0_GRPH_KEY_CLR_HIGH 0x04F0
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|
|
460 #define OV0_KEY_CNTL 0x04F4
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|
|
461 #define OV0_TEST 0x04F8
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|
|
462 #define SUBPIC_CNTL 0x0540
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|
|
463 #define SUBPIC_DEFCOLCON 0x0544
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|
|
464 #define SUBPIC_Y_X_START 0x054C
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|
|
465 #define SUBPIC_Y_X_END 0x0550
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|
|
466 #define SUBPIC_V_INC 0x0554
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|
|
467 #define SUBPIC_H_INC 0x0558
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|
|
468 #define SUBPIC_BUF0_OFFSET 0x055C
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|
|
469 #define SUBPIC_BUF1_OFFSET 0x0560
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|
|
470 #define SUBPIC_LC0_OFFSET 0x0564
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|
|
471 #define SUBPIC_LC1_OFFSET 0x0568
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|
|
472 #define SUBPIC_PITCH 0x056C
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|
|
473 #define SUBPIC_BTN_HLI_COLCON 0x0570
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|
|
474 #define SUBPIC_BTN_HLI_Y_X_START 0x0574
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|
|
475 #define SUBPIC_BTN_HLI_Y_X_END 0x0578
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|
|
476 #define SUBPIC_PALETTE_INDEX 0x057C
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|
|
477 #define SUBPIC_PALETTE_DATA 0x0580
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|
|
478 #define SUBPIC_H_ACCUM_INIT 0x0584
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|
|
479 #define SUBPIC_V_ACCUM_INIT 0x0588
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|
|
480 #define DISP_MISC_CNTL 0x0D00
|
|
1915
|
481 # define SOFT_RESET_GRPH_PP (1 << 0)
|
|
1911
|
482 #define DAC_MACRO_CNTL 0x0D04
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|
|
483 #define DISP_PWR_MAN 0x0D08
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|
|
484 #define DISP_TEST_DEBUG_CNTL 0x0D10
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|
|
485 #define DISP_HW_DEBUG 0x0D14
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|
|
486 #define DAC_CRC_SIG1 0x0D18
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|
|
487 #define DAC_CRC_SIG2 0x0D1C
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|
|
488 #define OV0_LIN_TRANS_A 0x0D20
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|
|
489 #define OV0_LIN_TRANS_B 0x0D24
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|
|
490 #define OV0_LIN_TRANS_C 0x0D28
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|
|
491 #define OV0_LIN_TRANS_D 0x0D2C
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|
|
492 #define OV0_LIN_TRANS_E 0x0D30
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|
|
493 #define OV0_LIN_TRANS_F 0x0D34
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|
|
494 #define OV0_GAMMA_0_F 0x0D40
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|
|
495 #define OV0_GAMMA_10_1F 0x0D44
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|
|
496 #define OV0_GAMMA_20_3F 0x0D48
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|
|
497 #define OV0_GAMMA_40_7F 0x0D4C
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|
|
498 #define OV0_GAMMA_380_3BF 0x0D50
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|
|
499 #define OV0_GAMMA_3C0_3FF 0x0D54
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|
|
500 #define DISP_MERGE_CNTL 0x0D60
|
|
|
501 #define DISP_OUTPUT_CNTL 0x0D64
|
|
1915
|
502 # define DISP_DAC_SOURCE_MASK 0x03
|
|
|
503 # define DISP_DAC_SOURCE_CRTC2 0x01
|
|
1911
|
504 #define DISP_LIN_TRANS_GRPH_A 0x0D80
|
|
|
505 #define DISP_LIN_TRANS_GRPH_B 0x0D84
|
|
|
506 #define DISP_LIN_TRANS_GRPH_C 0x0D88
|
|
|
507 #define DISP_LIN_TRANS_GRPH_D 0x0D8C
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|
|
508 #define DISP_LIN_TRANS_GRPH_E 0x0D90
|
|
|
509 #define DISP_LIN_TRANS_GRPH_F 0x0D94
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|
|
510 #define DISP_LIN_TRANS_VID_A 0x0D98
|
|
|
511 #define DISP_LIN_TRANS_VID_B 0x0D9C
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|
|
512 #define DISP_LIN_TRANS_VID_C 0x0DA0
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|
|
513 #define DISP_LIN_TRANS_VID_D 0x0DA4
|
|
|
514 #define DISP_LIN_TRANS_VID_E 0x0DA8
|
|
|
515 #define DISP_LIN_TRANS_VID_F 0x0DAC
|
|
|
516 #define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0
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|
|
517 #define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4
|
|
|
518 #define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8
|
|
|
519 #define RMX_HORZ_PHASE 0x0DBC
|
|
|
520 #define DAC_EMBEDDED_SYNC_CNTL 0x0DC0
|
|
|
521 #define DAC_BROAD_PULSE 0x0DC4
|
|
|
522 #define DAC_SKEW_CLKS 0x0DC8
|
|
|
523 #define DAC_INCR 0x0DCC
|
|
|
524 #define DAC_NEG_SYNC_LEVEL 0x0DD0
|
|
|
525 #define DAC_POS_SYNC_LEVEL 0x0DD4
|
|
|
526 #define DAC_BLANK_LEVEL 0x0DD8
|
|
|
527 #define CLOCK_CNTL_INDEX 0x0008
|
|
1915
|
528 /* CLOCK_CNTL_INDEX bit constants */
|
|
|
529 # define PLL_WR_EN 0x00000080
|
|
|
530 # define RADEON_PLL_DIV_SEL (3 << 8)
|
|
|
531 # define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8)
|
|
1911
|
532 #define CLOCK_CNTL_DATA 0x000C
|
|
|
533 #define CP_RB_CNTL 0x0704
|
|
|
534 #define CP_RB_BASE 0x0700
|
|
|
535 #define CP_RB_RPTR_ADDR 0x070C
|
|
|
536 #define CP_RB_RPTR 0x0710
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|
|
537 #define CP_RB_WPTR 0x0714
|
|
|
538 #define CP_RB_WPTR_DELAY 0x0718
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|
|
539 #define CP_IB_BASE 0x0738
|
|
|
540 #define CP_IB_BUFSZ 0x073C
|
|
|
541 #define SCRATCH_REG0 0x15E0
|
|
|
542 #define GUI_SCRATCH_REG0 0x15E0
|
|
|
543 #define SCRATCH_REG1 0x15E4
|
|
|
544 #define GUI_SCRATCH_REG1 0x15E4
|
|
|
545 #define SCRATCH_REG2 0x15E8
|
|
|
546 #define GUI_SCRATCH_REG2 0x15E8
|
|
|
547 #define SCRATCH_REG3 0x15EC
|
|
|
548 #define GUI_SCRATCH_REG3 0x15EC
|
|
|
549 #define SCRATCH_REG4 0x15F0
|
|
|
550 #define GUI_SCRATCH_REG4 0x15F0
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|
|
551 #define SCRATCH_REG5 0x15F4
|
|
|
552 #define GUI_SCRATCH_REG5 0x15F4
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|
|
553 #define SCRATCH_UMSK 0x0770
|
|
|
554 #define SCRATCH_ADDR 0x0774
|
|
|
555 #define DP_BRUSH_FRGD_CLR 0x147C
|
|
|
556 #define DP_BRUSH_BKGD_CLR 0x1478
|
|
|
557 #define DST_LINE_START 0x1600
|
|
|
558 #define DST_LINE_END 0x1604
|
|
|
559 #define SRC_OFFSET 0x15AC
|
|
|
560 #define SRC_PITCH 0x15B0
|
|
|
561 #define SRC_TILE 0x1704
|
|
|
562 #define SRC_PITCH_OFFSET 0x1428
|
|
|
563 #define SRC_X 0x1414
|
|
|
564 #define SRC_Y 0x1418
|
|
|
565 #define SRC_X_Y 0x1590
|
|
|
566 #define SRC_Y_X 0x1434
|
|
|
567 #define DST_Y_X 0x1438
|
|
|
568 #define DST_WIDTH_HEIGHT 0x1598
|
|
|
569 #define DST_HEIGHT_WIDTH 0x143c
|
|
|
570 #define SRC_CLUT_ADDRESS 0x1780
|
|
|
571 #define SRC_CLUT_DATA 0x1784
|
|
|
572 #define SRC_CLUT_DATA_RD 0x1788
|
|
|
573 #define HOST_DATA0 0x17C0
|
|
|
574 #define HOST_DATA1 0x17C4
|
|
|
575 #define HOST_DATA2 0x17C8
|
|
|
576 #define HOST_DATA3 0x17CC
|
|
|
577 #define HOST_DATA4 0x17D0
|
|
|
578 #define HOST_DATA5 0x17D4
|
|
|
579 #define HOST_DATA6 0x17D8
|
|
|
580 #define HOST_DATA7 0x17DC
|
|
|
581 #define HOST_DATA_LAST 0x17E0
|
|
|
582 #define DP_SRC_ENDIAN 0x15D4
|
|
|
583 #define DP_SRC_FRGD_CLR 0x15D8
|
|
|
584 #define DP_SRC_BKGD_CLR 0x15DC
|
|
|
585 #define SC_LEFT 0x1640
|
|
|
586 #define SC_RIGHT 0x1644
|
|
|
587 #define SC_TOP 0x1648
|
|
|
588 #define SC_BOTTOM 0x164C
|
|
|
589 #define SRC_SC_RIGHT 0x1654
|
|
|
590 #define SRC_SC_BOTTOM 0x165C
|
|
|
591 #define DP_CNTL 0x16C0
|
|
1915
|
592 /* DP_CNTL bit constants */
|
|
|
593 # define DST_X_RIGHT_TO_LEFT 0x00000000
|
|
|
594 # define DST_X_LEFT_TO_RIGHT 0x00000001
|
|
|
595 # define DST_Y_BOTTOM_TO_TOP 0x00000000
|
|
|
596 # define DST_Y_TOP_TO_BOTTOM 0x00000002
|
|
|
597 # define DST_X_MAJOR 0x00000000
|
|
|
598 # define DST_Y_MAJOR 0x00000004
|
|
|
599 # define DST_X_TILE 0x00000008
|
|
|
600 # define DST_Y_TILE 0x00000010
|
|
|
601 # define DST_LAST_PEL 0x00000020
|
|
|
602 # define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
|
|
|
603 # define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
|
|
|
604 # define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
|
|
|
605 # define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
|
|
|
606 # define DST_BRES_SIGN 0x00000100
|
|
|
607 # define DST_HOST_BIG_ENDIAN_EN 0x00000200
|
|
|
608 # define DST_POLYLINE_NONLAST 0x00008000
|
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609 # define DST_RASTER_STALL 0x00010000
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610 # define DST_POLY_EDGE 0x00040000
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1911
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611 #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0
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1915
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612 /* DP_CNTL_XDIR_YDIR_YMAJOR bit constants (short version of DP_CNTL) */
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613 # define DST_X_MAJOR_S 0x00000000
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614 # define DST_Y_MAJOR_S 0x00000001
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615 # define DST_Y_BOTTOM_TO_TOP_S 0x00000000
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616 # define DST_Y_TOP_TO_BOTTOM_S 0x00008000
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617 # define DST_X_RIGHT_TO_LEFT_S 0x00000000
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618 # define DST_X_LEFT_TO_RIGHT_S 0x80000000
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1911
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619 #define DP_DATATYPE 0x16C4
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1915
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620 /* DP_DATATYPE bit constants */
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621 # define DST_8BPP 0x00000002
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622 # define DST_15BPP 0x00000003
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623 # define DST_16BPP 0x00000004
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624 # define DST_24BPP 0x00000005
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625 # define DST_32BPP 0x00000006
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626 # define DST_8BPP_RGB332 0x00000007
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627 # define DST_8BPP_Y8 0x00000008
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628 # define DST_8BPP_RGB8 0x00000009
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629 # define DST_16BPP_VYUY422 0x0000000b
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630 # define DST_16BPP_YVYU422 0x0000000c
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631 # define DST_32BPP_AYUV444 0x0000000e
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632 # define DST_16BPP_ARGB4444 0x0000000f
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633 # define BRUSH_SOLIDCOLOR 0x00000d00
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634 # define SRC_MONO 0x00000000
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635 # define SRC_MONO_LBKGD 0x00010000
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636 # define SRC_DSTCOLOR 0x00030000
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637 # define BYTE_ORDER_MSB_TO_LSB 0x00000000
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638 # define BYTE_ORDER_LSB_TO_MSB 0x40000000
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639 # define DP_CONVERSION_TEMP 0x80000000
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640 # define HOST_BIG_ENDIAN_EN (1 << 29)
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1911
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641 #define DP_MIX 0x16C8
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1915
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642 /* DP_MIX bit constants */
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643 # define DP_SRC_RECT 0x00000200
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644 # define DP_SRC_HOST 0x00000300
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645 # define DP_SRC_HOST_BYTEALIGN 0x00000400
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1911
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646 #define DP_WRITE_MSK 0x16CC
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647 #define DP_XOP 0x17F8
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648 #define CLR_CMP_CLR_SRC 0x15C4
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649 #define CLR_CMP_CLR_DST 0x15C8
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650 #define CLR_CMP_CNTL 0x15C0
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1915
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651 /* CLR_CMP_CNTL bit constants */
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652 # define COMPARE_SRC_FALSE 0x00000000
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653 # define COMPARE_SRC_TRUE 0x00000001
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654 # define COMPARE_SRC_NOT_EQUAL 0x00000004
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655 # define COMPARE_SRC_EQUAL 0x00000005
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656 # define COMPARE_SRC_EQUAL_FLIP 0x00000007
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657 # define COMPARE_DST_FALSE 0x00000000
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658 # define COMPARE_DST_TRUE 0x00000100
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659 # define COMPARE_DST_NOT_EQUAL 0x00000400
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660 # define COMPARE_DST_EQUAL 0x00000500
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|
661 # define COMPARE_DESTINATION 0x00000000
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662 # define COMPARE_SOURCE 0x01000000
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663 # define COMPARE_SRC_AND_DST 0x02000000
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|
1911
|
664 #define CLR_CMP_MSK 0x15CC
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|
|
665 #define DSTCACHE_MODE 0x1710
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666 #define DSTCACHE_CTLSTAT 0x1714
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1915
|
667 /* DSTCACHE_CTLSTAT bit constants */
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668 # define RB2D_DC_FLUSH (3 << 0)
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|
669 # define RB2D_DC_FLUSH_ALL 0xf
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670 # define RB2D_DC_BUSY (1 << 31)
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1911
|
671 #define DEFAULT_PITCH_OFFSET 0x16E0
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672 #define DEFAULT_SC_BOTTOM_RIGHT 0x16E8
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1915
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673 /* DEFAULT_SC_BOTTOM_RIGHT bit constants */
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674 # define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
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675 # define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
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|
1911
|
676 #define DP_GUI_MASTER_CNTL 0x146C
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1915
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677 /* DP_GUI_MASTER_CNTL bit constants */
|
|
|
678 # define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
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|
|
679 # define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001
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|
|
680 # define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
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|
|
681 # define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002
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|
|
682 # define GMC_SRC_CLIP_DEFAULT 0x00000000
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|
|
683 # define GMC_SRC_CLIP_LEAVE 0x00000004
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|
|
684 # define GMC_DST_CLIP_DEFAULT 0x00000000
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|
|
685 # define GMC_DST_CLIP_LEAVE 0x00000008
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|
|
686 # define GMC_BRUSH_8x8MONO 0x00000000
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|
|
687 # define GMC_BRUSH_8x8MONO_LBKGD 0x00000010
|
|
|
688 # define GMC_BRUSH_8x1MONO 0x00000020
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|
|
689 # define GMC_BRUSH_8x1MONO_LBKGD 0x00000030
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|
|
690 # define GMC_BRUSH_1x8MONO 0x00000040
|
|
|
691 # define GMC_BRUSH_1x8MONO_LBKGD 0x00000050
|
|
|
692 # define GMC_BRUSH_32x1MONO 0x00000060
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|
|
693 # define GMC_BRUSH_32x1MONO_LBKGD 0x00000070
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|
|
694 # define GMC_BRUSH_32x32MONO 0x00000080
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|
|
695 # define GMC_BRUSH_32x32MONO_LBKGD 0x00000090
|
|
|
696 # define GMC_BRUSH_8x8COLOR 0x000000a0
|
|
|
697 # define GMC_BRUSH_8x1COLOR 0x000000b0
|
|
|
698 # define GMC_BRUSH_1x8COLOR 0x000000c0
|
|
|
699 # define GMC_BRUSH_SOLID_COLOR 0x000000d0
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|
|
700 # define GMC_DST_8BPP 0x00000200
|
|
|
701 # define GMC_DST_15BPP 0x00000300
|
|
|
702 # define GMC_DST_16BPP 0x00000400
|
|
|
703 # define GMC_DST_24BPP 0x00000500
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|
|
704 # define GMC_DST_32BPP 0x00000600
|
|
|
705 # define GMC_DST_8BPP_RGB332 0x00000700
|
|
|
706 # define GMC_DST_8BPP_Y8 0x00000800
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|
|
707 # define GMC_DST_8BPP_RGB8 0x00000900
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|
|
708 # define GMC_DST_16BPP_VYUY422 0x00000b00
|
|
|
709 # define GMC_DST_16BPP_YVYU422 0x00000c00
|
|
|
710 # define GMC_DST_32BPP_AYUV444 0x00000e00
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|
|
711 # define GMC_DST_16BPP_ARGB4444 0x00000f00
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|
|
712 # define GMC_SRC_MONO 0x00000000
|
|
|
713 # define GMC_SRC_MONO_LBKGD 0x00001000
|
|
|
714 # define GMC_SRC_DSTCOLOR 0x00003000
|
|
|
715 # define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
|
|
|
716 # define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000
|
|
|
717 # define GMC_DP_CONVERSION_TEMP_9300 0x00008000
|
|
|
718 # define GMC_DP_CONVERSION_TEMP_6500 0x00000000
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|
|
719 # define GMC_DP_SRC_RECT 0x02000000
|
|
|
720 # define GMC_DP_SRC_HOST 0x03000000
|
|
|
721 # define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000
|
|
|
722 # define GMC_3D_FCN_EN_CLR 0x00000000
|
|
|
723 # define GMC_3D_FCN_EN_SET 0x08000000
|
|
|
724 # define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000
|
|
|
725 # define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
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|
|
726 # define GMC_AUX_CLIP_LEAVE 0x00000000
|
|
|
727 # define GMC_AUX_CLIP_CLEAR 0x20000000
|
|
|
728 # define GMC_WRITE_MASK_LEAVE 0x00000000
|
|
|
729 # define GMC_WRITE_MASK_SET 0x40000000
|
|
|
730 # define GMC_CLR_CMP_CNTL_DIS (1 << 28)
|
|
|
731 # define GMC_SRC_DATATYPE_COLOR (3 << 12)
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|
|
732 # define ROP3_S 0x00cc0000
|
|
|
733 # define ROP3_SRCCOPY 0x00cc0000
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|
|
734 # define ROP3_P 0x00f00000
|
|
|
735 # define ROP3_PATCOPY 0x00f00000
|
|
|
736 # define DP_SRC_SOURCE_MASK (7 << 24)
|
|
|
737 # define GMC_BRUSH_NONE (15 << 4)
|
|
|
738 # define DP_SRC_SOURCE_MEMORY (2 << 24)
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|
|
739 # define GMC_BRUSH_SOLIDCOLOR 0x000000d0
|
|
1911
|
740 #define SC_TOP_LEFT 0x16EC
|
|
|
741 #define SC_BOTTOM_RIGHT 0x16F0
|
|
|
742 #define SRC_SC_BOTTOM_RIGHT 0x16F4
|
|
|
743 #define RB2D_DSTCACHE_CTLSTAT 0x342C
|
|
|
744
|
|
1915
|
745 #define RADEON_BASE_CODE 0x0f0b
|
|
|
746 #define RADEON_BIOS_0_SCRATCH 0x0010
|
|
|
747 #define RADEON_BIOS_1_SCRATCH 0x0014
|
|
|
748 #define RADEON_BIOS_2_SCRATCH 0x0018
|
|
|
749 #define RADEON_BIOS_3_SCRATCH 0x001c
|
|
|
750 #define RADEON_BIOS_4_SCRATCH 0x0020
|
|
|
751 #define RADEON_BIOS_5_SCRATCH 0x0024
|
|
|
752 #define RADEON_BIOS_6_SCRATCH 0x0028
|
|
|
753 #define RADEON_BIOS_7_SCRATCH 0x002c
|
|
|
754
|
|
1911
|
755
|
|
|
756 #define CLK_PIN_CNTL 0x0001
|
|
|
757 #define PPLL_CNTL 0x0002
|
|
|
758 #define PPLL_REF_DIV 0x0003
|
|
|
759 #define PPLL_DIV_0 0x0004
|
|
|
760 #define PPLL_DIV_1 0x0005
|
|
|
761 #define PPLL_DIV_2 0x0006
|
|
|
762 #define PPLL_DIV_3 0x0007
|
|
|
763 #define VCLK_ECP_CNTL 0x0008
|
|
|
764 #define HTOTAL_CNTL 0x0009
|
|
|
765 #define M_SPLL_REF_FB_DIV 0x000a
|
|
|
766 #define AGP_PLL_CNTL 0x000b
|
|
|
767 #define SPLL_CNTL 0x000c
|
|
|
768 #define SCLK_CNTL 0x000d
|
|
|
769 #define MPLL_CNTL 0x000e
|
|
|
770 #define MCLK_CNTL 0x0012
|
|
1915
|
771 /* MCLK_CNTL bit constants */
|
|
|
772 # define FORCEON_MCLKA (1 << 16)
|
|
|
773 # define FORCEON_MCLKB (1 << 17)
|
|
|
774 # define FORCEON_YCLKA (1 << 18)
|
|
|
775 # define FORCEON_YCLKB (1 << 19)
|
|
|
776 # define FORCEON_MC (1 << 20)
|
|
|
777 # define FORCEON_AIC (1 << 21)
|
|
1911
|
778 #define AGP_PLL_CNTL 0x000b
|
|
|
779 #define PLL_TEST_CNTL 0x0013
|
|
|
780
|
|
|
781 /* masks */
|
|
|
782
|
|
|
783 #define CONFIG_MEMSIZE_MASK 0x1f000000
|
|
|
784 #define MEM_CFG_TYPE 0x40000000
|
|
|
785 #define DST_OFFSET_MASK 0x003fffff
|
|
|
786 #define DST_PITCH_MASK 0x3fc00000
|
|
|
787 #define DEFAULT_TILE_MASK 0xc0000000
|
|
|
788 #define PPLL_DIV_SEL_MASK 0x00000300
|
|
|
789 #define PPLL_RESET 0x00000001
|
|
|
790 #define PPLL_ATOMIC_UPDATE_EN 0x00010000
|
|
|
791 #define PPLL_REF_DIV_MASK 0x000003ff
|
|
|
792 #define PPLL_FB3_DIV_MASK 0x000007ff
|
|
|
793 #define PPLL_POST3_DIV_MASK 0x00070000
|
|
|
794 #define PPLL_ATOMIC_UPDATE_R 0x00008000
|
|
|
795 #define PPLL_ATOMIC_UPDATE_W 0x00008000
|
|
|
796 #define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000
|
|
|
797
|
|
|
798 #define GUI_ACTIVE 0x80000000
|
|
|
799
|
|
1915
|
800 /* GEN_RESET_CNTL bit constants */
|
|
|
801 #define SOFT_RESET_GUI 0x00000001
|
|
|
802 #define SOFT_RESET_VCLK 0x00000100
|
|
|
803 #define SOFT_RESET_PCLK 0x00000200
|
|
|
804 #define SOFT_RESET_ECP 0x00000400
|
|
|
805 #define SOFT_RESET_DISPENG_XCLK 0x00000800
|
|
|
806
|
|
1911
|
807 #endif /* _RADEON_H */
|
|
|
808
|
