Mercurial > mplayer.hg
annotate TOOLS/cpuinfo.c @ 22865:441582f3ed87
simplified function prototypes to avoid casts but keep external API compatibility
author | ben |
---|---|
date | Sun, 01 Apr 2007 12:39:06 +0000 |
parents | 915194317cb7 |
children |
rev | line source |
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12960 | 1 /* small utility to extract CPU information |
17041 | 2 Used by configure to set CPU optimization levels on some operating |
3 systems where /proc/cpuinfo is non-existent or unreliable. */ | |
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4 |
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5 #include <stdio.h> |
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6 #include <sys/time.h> |
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7 #include <stdlib.h> |
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8 #include <string.h> |
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9 #include <unistd.h> |
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10 |
18910 | 11 #if defined(__MINGW32__) && (__MINGW32_MAJOR_VERSION <= 3) && (__MINGW32_MINOR_VERSION < 10) |
9764 | 12 #include <sys/timeb.h> |
17041 | 13 void gettimeofday(struct timeval* t,void* timezone) { |
14 struct timeb timebuffer; | |
15 ftime( &timebuffer ); | |
16 t->tv_sec=timebuffer.time; | |
17 t->tv_usec=1000*timebuffer.millitm; | |
9764 | 18 } |
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19 #endif |
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20 #ifdef __MINGW32__ |
9764 | 21 #define MISSING_USLEEP |
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22 #include <windows.h> |
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23 #define sleep(t) Sleep(1000*t); |
9764 | 24 #endif |
25 | |
13612 | 26 #ifdef __BEOS__ |
27 #define usleep(t) snooze(t) | |
28 #endif | |
29 | |
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30 #ifdef M_UNIX |
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31 typedef long long int64_t; |
17041 | 32 #define MISSING_USLEEP |
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33 #else |
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34 #include <inttypes.h> |
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35 #endif |
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36 |
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37 #define CPUID_FEATURE_DEF(bit, desc, description) \ |
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38 { bit, desc } |
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39 |
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40 typedef struct cpuid_regs { |
17041 | 41 unsigned int eax; |
42 unsigned int ebx; | |
43 unsigned int ecx; | |
44 unsigned int edx; | |
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45 } cpuid_regs_t; |
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46 |
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47 static cpuid_regs_t |
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48 cpuid(int func) { |
17041 | 49 cpuid_regs_t regs; |
50 #define CPUID ".byte 0x0f, 0xa2; " | |
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51 #ifdef __x86_64__ |
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52 asm("mov %%rbx, %%rsi\n\t" |
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53 #else |
18517 | 54 asm("mov %%ebx, %%esi\n\t" |
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55 #endif |
18517 | 56 CPUID"\n\t" |
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57 #ifdef __x86_64__ |
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58 "xchg %%rsi, %%rbx\n\t" |
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59 #else |
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60 "xchg %%esi, %%ebx\n\t" |
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61 #endif |
18517 | 62 : "=a" (regs.eax), "=S" (regs.ebx), "=c" (regs.ecx), "=d" (regs.edx) |
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63 : "0" (func)); |
17041 | 64 return regs; |
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65 } |
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66 |
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67 |
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68 static int64_t |
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69 rdtsc(void) |
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70 { |
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71 uint64_t i; |
17041 | 72 #define RDTSC ".byte 0x0f, 0x31; " |
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73 asm volatile (RDTSC : "=A"(i) : ); |
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74 return i; |
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75 } |
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76 |
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77 static const char* |
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78 brandname(int i) |
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79 { |
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80 const static char* brandmap[] = { |
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81 NULL, |
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82 "Intel(R) Celeron(R) processor", |
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83 "Intel(R) Pentium(R) III processor", |
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84 "Intel(R) Pentium(R) III Xeon(tm) processor", |
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85 "Intel(R) Pentium(R) III processor", |
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86 NULL, |
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87 "Mobile Intel(R) Pentium(R) III processor-M", |
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88 "Mobile Intel(R) Celeron(R) processor" |
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89 }; |
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90 |
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91 if (i >= sizeof(brandmap)) |
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92 return NULL; |
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93 else |
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94 return brandmap[i]; |
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95 } |
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96 |
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97 static void |
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98 store32(char *d, unsigned int v) |
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99 { |
17041 | 100 d[0] = v & 0xff; |
101 d[1] = (v >> 8) & 0xff; | |
102 d[2] = (v >> 16) & 0xff; | |
103 d[3] = (v >> 24) & 0xff; | |
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104 } |
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105 |
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106 |
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107 int |
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108 main(int argc, char **argv) |
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109 { |
17041 | 110 cpuid_regs_t regs, regs_ext; |
111 char idstr[13]; | |
112 unsigned max_cpuid; | |
113 unsigned max_ext_cpuid; | |
114 unsigned int amd_flags; | |
115 unsigned int amd_flags2; | |
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116 const char *model_name = NULL; |
17041 | 117 int i; |
118 char processor_name[49]; | |
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119 |
17041 | 120 regs = cpuid(0); |
121 max_cpuid = regs.eax; | |
122 /* printf("%d CPUID function codes\n", max_cpuid+1); */ | |
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123 |
17041 | 124 store32(idstr+0, regs.ebx); |
125 store32(idstr+4, regs.edx); | |
126 store32(idstr+8, regs.ecx); | |
127 idstr[12] = 0; | |
128 printf("vendor_id\t: %s\n", idstr); | |
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129 |
17041 | 130 regs_ext = cpuid((1<<31) + 0); |
131 max_ext_cpuid = regs_ext.eax; | |
132 if (max_ext_cpuid >= (1<<31) + 1) { | |
133 regs_ext = cpuid((1<<31) + 1); | |
134 amd_flags = regs_ext.edx; | |
135 amd_flags2 = regs_ext.ecx; | |
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136 |
17041 | 137 if (max_ext_cpuid >= (1<<31) + 4) { |
138 for (i = 2; i <= 4; i++) { | |
139 regs_ext = cpuid((1<<31) + i); | |
140 store32(processor_name + (i-2)*16, regs_ext.eax); | |
141 store32(processor_name + (i-2)*16 + 4, regs_ext.ebx); | |
142 store32(processor_name + (i-2)*16 + 8, regs_ext.ecx); | |
143 store32(processor_name + (i-2)*16 + 12, regs_ext.edx); | |
144 } | |
145 processor_name[48] = 0; | |
146 model_name = processor_name; | |
22195 | 147 while (*model_name == ' ') { |
148 model_name++; | |
149 } | |
17041 | 150 } |
151 } else { | |
152 amd_flags = 0; | |
153 amd_flags2 = 0; | |
154 } | |
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155 |
17041 | 156 if (max_cpuid >= 1) { |
157 static struct { | |
158 int bit; | |
20001 | 159 char *desc; |
17041 | 160 } cap[] = { |
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161 CPUID_FEATURE_DEF(0, "fpu", "Floating-point unit on-chip"), |
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162 CPUID_FEATURE_DEF(1, "vme", "Virtual Mode Enhancements"), |
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163 CPUID_FEATURE_DEF(2, "de", "Debugging Extension"), |
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164 CPUID_FEATURE_DEF(3, "pse", "Page Size Extension"), |
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165 CPUID_FEATURE_DEF(4, "tsc", "Time Stamp Counter"), |
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166 CPUID_FEATURE_DEF(5, "msr", "Pentium Processor MSR"), |
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167 CPUID_FEATURE_DEF(6, "pae", "Physical Address Extension"), |
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168 CPUID_FEATURE_DEF(7, "mce", "Machine Check Exception"), |
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169 CPUID_FEATURE_DEF(8, "cx8", "CMPXCHG8B Instruction Supported"), |
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170 CPUID_FEATURE_DEF(9, "apic", "On-chip APIC Hardware Enabled"), |
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171 CPUID_FEATURE_DEF(11, "sep", "SYSENTER and SYSEXIT"), |
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172 CPUID_FEATURE_DEF(12, "mtrr", "Memory Type Range Registers"), |
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173 CPUID_FEATURE_DEF(13, "pge", "PTE Global Bit"), |
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174 CPUID_FEATURE_DEF(14, "mca", "Machine Check Architecture"), |
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175 CPUID_FEATURE_DEF(15, "cmov", "Conditional Move/Compare Instruction"), |
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176 CPUID_FEATURE_DEF(16, "pat", "Page Attribute Table"), |
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177 CPUID_FEATURE_DEF(17, "pse36", "Page Size Extension 36-bit"), |
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178 CPUID_FEATURE_DEF(18, "pn", "Processor Serial Number"), |
22372 | 179 CPUID_FEATURE_DEF(19, "clflush", "CFLUSH instruction"), |
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180 CPUID_FEATURE_DEF(21, "dts", "Debug Store"), |
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181 CPUID_FEATURE_DEF(22, "acpi", "Thermal Monitor and Clock Ctrl"), |
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182 CPUID_FEATURE_DEF(23, "mmx", "MMX Technology"), |
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183 CPUID_FEATURE_DEF(24, "fxsr", "FXSAVE/FXRSTOR"), |
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184 CPUID_FEATURE_DEF(25, "sse", "SSE Extensions"), |
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185 CPUID_FEATURE_DEF(26, "sse2", "SSE2 Extensions"), |
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186 CPUID_FEATURE_DEF(27, "ss", "Self Snoop"), |
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187 CPUID_FEATURE_DEF(28, "ht", "Multi-threading"), |
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188 CPUID_FEATURE_DEF(29, "tm", "Therm. Monitor"), |
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189 CPUID_FEATURE_DEF(30, "ia64", "IA-64 Processor"), |
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190 CPUID_FEATURE_DEF(31, "pbe", "Pend. Brk. EN."), |
17041 | 191 { -1 } |
192 }; | |
193 static struct { | |
194 int bit; | |
195 char *desc; | |
196 } cap2[] = { | |
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197 CPUID_FEATURE_DEF(0, "pni", "SSE3 Extensions"), |
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198 CPUID_FEATURE_DEF(3, "monitor", "MONITOR/MWAIT"), |
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199 CPUID_FEATURE_DEF(4, "ds_cpl", "CPL Qualified Debug Store"), |
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200 CPUID_FEATURE_DEF(5, "vmx", "Virtual Machine Extensions"), |
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201 CPUID_FEATURE_DEF(6, "smx", "Safer Mode Extensions"), |
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202 CPUID_FEATURE_DEF(7, "est", "Enhanced Intel SpeedStep Technology"), |
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203 CPUID_FEATURE_DEF(8, "tm2", "Thermal Monitor 2"), |
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204 CPUID_FEATURE_DEF(9, "ssse3", "Supplemental SSE3"), |
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205 CPUID_FEATURE_DEF(10, "cid", "L1 Context ID"), |
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206 CPUID_FEATURE_DEF(13, "cx16", "CMPXCHG16B Available"), |
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207 CPUID_FEATURE_DEF(14, "xtpr", "xTPR Disable"), |
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208 CPUID_FEATURE_DEF(18, "dca", "Direct Cache Access"), |
17041 | 209 { -1 } |
210 }; | |
211 static struct { | |
212 int bit; | |
20000 | 213 char *desc; |
17041 | 214 } cap_amd[] = { |
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215 CPUID_FEATURE_DEF(11, "syscall", "SYSCALL and SYSRET"), |
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216 CPUID_FEATURE_DEF(19, "mp", "MP Capable"), |
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217 CPUID_FEATURE_DEF(20, "nx", "No-Execute Page Protection"), |
22371 | 218 CPUID_FEATURE_DEF(22, "mmxext", "MMX Technology (AMD Extensions)"), |
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219 CPUID_FEATURE_DEF(25, "fxsr_opt", "Fast FXSAVE/FXRSTOR"), |
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220 CPUID_FEATURE_DEF(27, "rdtscp", "RDTSCP Instruction"), |
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221 CPUID_FEATURE_DEF(29, "lm", "Long Mode Capable"), |
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222 CPUID_FEATURE_DEF(30, "3dnowext", "3DNow! Extensions"), |
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223 CPUID_FEATURE_DEF(31, "3dnow", "3DNow!"), |
17041 | 224 { -1 } |
225 }; | |
226 static struct { | |
227 int bit; | |
228 char *desc; | |
229 } cap_amd2[] = { | |
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230 CPUID_FEATURE_DEF(0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode"), |
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231 CPUID_FEATURE_DEF(1, "cmp_legacy", "Chip Multi-Core"), |
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232 CPUID_FEATURE_DEF(2, "svm", "Secure Virtual Machine"), |
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233 CPUID_FEATURE_DEF(4, "cr8legacy", "CR8 Available in Legacy Mode"), |
17041 | 234 { -1 } |
235 }; | |
236 unsigned int family, model, stepping; | |
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237 |
17041 | 238 regs = cpuid(1); |
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239 family = (regs.eax >> 8) & 0xf; |
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240 model = (regs.eax >> 4) & 0xf; |
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241 stepping = regs.eax & 0xf; |
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242 |
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243 if (family == 0xf) |
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244 { |
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245 family += (regs.eax >> 20) & 0xff; |
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246 model += ((regs.eax >> 16) & 0xf) << 4; |
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247 } |
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248 |
17041 | 249 printf("cpu family\t: %d\n" |
250 "model\t\t: %d\n" | |
251 "stepping\t: %d\n" , | |
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252 family, |
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253 model, |
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254 stepping); |
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255 |
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256 if (strstr(idstr, "Intel") && !model_name) { |
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257 if (family == 6 && model == 0xb && stepping == 1) |
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258 model_name = "Intel (R) Celeron (R) processor"; |
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259 else |
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260 model_name = brandname(regs.ebx & 0xf); |
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261 } |
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262 |
17041 | 263 printf("flags\t\t:"); |
264 for (i = 0; cap[i].bit >= 0; i++) { | |
265 if (regs.edx & (1 << cap[i].bit)) { | |
266 printf(" %s", cap[i].desc); | |
267 } | |
268 } | |
269 for (i = 0; cap2[i].bit >= 0; i++) { | |
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270 if (regs.ecx & (1 << cap2[i].bit)) { |
17041 | 271 printf(" %s", cap2[i].desc); |
272 } | |
273 } | |
274 /* k6_mtrr is supported by some AMD K6-2/K6-III CPUs but | |
275 it is not indicated by a CPUID feature bit, so we | |
276 have to check the family, model and stepping instead. */ | |
277 if (strstr(idstr, "AMD") && | |
278 family == 5 && | |
279 (model >= 9 || model == 8 && stepping >= 8)) | |
280 printf(" %s", "k6_mtrr"); | |
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281 /* similar for cyrix_arr. */ |
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282 if (strstr(idstr, "Cyrix") && |
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283 (family == 5 && model < 4 || family == 6)) |
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284 printf(" %s", "cyrix_arr"); |
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285 /* as well as centaur_mcr. */ |
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286 if (strstr(idstr, "Centaur") && |
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287 family == 5) |
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288 printf(" %s", "centaur_mcr"); |
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289 |
17041 | 290 for (i = 0; cap_amd[i].bit >= 0; i++) { |
291 if (amd_flags & (1 << cap_amd[i].bit)) { | |
292 printf(" %s", cap_amd[i].desc); | |
293 } | |
294 } | |
295 for (i = 0; cap_amd2[i].bit >= 0; i++) { | |
296 if (amd_flags2 & (1 << cap_amd2[i].bit)) { | |
297 printf(" %s", cap_amd2[i].desc); | |
298 } | |
299 } | |
300 printf("\n"); | |
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301 |
17041 | 302 if (regs.edx & (1 << 4)) { |
303 int64_t tsc_start, tsc_end; | |
304 struct timeval tv_start, tv_end; | |
305 int usec_delay; | |
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306 |
17041 | 307 tsc_start = rdtsc(); |
308 gettimeofday(&tv_start, NULL); | |
309 #ifdef MISSING_USLEEP | |
310 sleep(1); | |
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311 #else |
17041 | 312 usleep(100000); |
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313 #endif |
17041 | 314 tsc_end = rdtsc(); |
315 gettimeofday(&tv_end, NULL); | |
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316 |
17041 | 317 usec_delay = 1000000 * (tv_end.tv_sec - tv_start.tv_sec) |
318 + (tv_end.tv_usec - tv_start.tv_usec); | |
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319 |
17041 | 320 printf("cpu MHz\t\t: %.3f\n", |
321 (double)(tsc_end-tsc_start) / usec_delay); | |
322 } | |
323 } | |
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324 |
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325 printf("model name\t: "); |
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326 if (model_name) |
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327 printf("%s\n", model_name); |
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328 else |
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329 printf("Unknown %s CPU\n", idstr); |
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330 } |