Mercurial > mplayer.hg
annotate TOOLS/cpuinfo.c @ 21125:4aff19cc00bb
Also support absolute url redirection, e.g. http://www.youtube.com/v/buKaqRG2SFA
(video does not play anyway though).
author | reimar |
---|---|
date | Tue, 21 Nov 2006 16:26:38 +0000 |
parents | 2d5790e4ee8f |
children | ababf115f90d |
rev | line source |
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12960 | 1 /* small utility to extract CPU information |
17041 | 2 Used by configure to set CPU optimization levels on some operating |
3 systems where /proc/cpuinfo is non-existent or unreliable. */ | |
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4 |
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5 #include <stdio.h> |
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6 #include <sys/time.h> |
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7 #include <stdlib.h> |
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8 #include <string.h> |
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9 #include <unistd.h> |
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10 |
18910 | 11 #if defined(__MINGW32__) && (__MINGW32_MAJOR_VERSION <= 3) && (__MINGW32_MINOR_VERSION < 10) |
9764 | 12 #include <sys/timeb.h> |
17041 | 13 void gettimeofday(struct timeval* t,void* timezone) { |
14 struct timeb timebuffer; | |
15 ftime( &timebuffer ); | |
16 t->tv_sec=timebuffer.time; | |
17 t->tv_usec=1000*timebuffer.millitm; | |
9764 | 18 } |
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19 #endif |
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20 #ifdef __MINGW32__ |
9764 | 21 #define MISSING_USLEEP |
22 #define sleep(t) _sleep(1000*t); | |
23 #endif | |
24 | |
13612 | 25 #ifdef __BEOS__ |
26 #define usleep(t) snooze(t) | |
27 #endif | |
28 | |
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29 #ifdef M_UNIX |
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30 typedef long long int64_t; |
17041 | 31 #define MISSING_USLEEP |
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32 #else |
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33 #include <inttypes.h> |
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34 #endif |
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35 |
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36 #define CPUID_FEATURE_DEF(bit, desc, description) \ |
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37 { bit, desc } |
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38 |
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39 typedef struct cpuid_regs { |
17041 | 40 unsigned int eax; |
41 unsigned int ebx; | |
42 unsigned int ecx; | |
43 unsigned int edx; | |
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44 } cpuid_regs_t; |
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45 |
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46 static cpuid_regs_t |
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47 cpuid(int func) { |
17041 | 48 cpuid_regs_t regs; |
49 #define CPUID ".byte 0x0f, 0xa2; " | |
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50 #ifdef __x86_64__ |
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51 asm("mov %%rbx, %%rsi\n\t" |
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52 #else |
18517 | 53 asm("mov %%ebx, %%esi\n\t" |
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54 #endif |
18517 | 55 CPUID"\n\t" |
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56 #ifdef __x86_64__ |
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57 "xchg %%rsi, %%rbx\n\t" |
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58 #else |
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59 "xchg %%esi, %%ebx\n\t" |
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60 #endif |
18517 | 61 : "=a" (regs.eax), "=S" (regs.ebx), "=c" (regs.ecx), "=d" (regs.edx) |
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62 : "0" (func)); |
17041 | 63 return regs; |
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64 } |
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65 |
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66 |
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67 static int64_t |
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68 rdtsc(void) |
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69 { |
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70 uint64_t i; |
17041 | 71 #define RDTSC ".byte 0x0f, 0x31; " |
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72 asm volatile (RDTSC : "=A"(i) : ); |
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73 return i; |
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74 } |
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75 |
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76 static const char* |
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77 brandname(int i) |
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78 { |
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79 const static char* brandmap[] = { |
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80 NULL, |
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81 "Intel(R) Celeron(R) processor", |
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82 "Intel(R) Pentium(R) III processor", |
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83 "Intel(R) Pentium(R) III Xeon(tm) processor", |
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84 "Intel(R) Pentium(R) III processor", |
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85 NULL, |
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86 "Mobile Intel(R) Pentium(R) III processor-M", |
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87 "Mobile Intel(R) Celeron(R) processor" |
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88 }; |
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89 |
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90 if (i >= sizeof(brandmap)) |
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91 return NULL; |
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92 else |
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93 return brandmap[i]; |
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94 } |
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95 |
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96 static void |
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97 store32(char *d, unsigned int v) |
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98 { |
17041 | 99 d[0] = v & 0xff; |
100 d[1] = (v >> 8) & 0xff; | |
101 d[2] = (v >> 16) & 0xff; | |
102 d[3] = (v >> 24) & 0xff; | |
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103 } |
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104 |
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105 |
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106 int |
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107 main(int argc, char **argv) |
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108 { |
17041 | 109 cpuid_regs_t regs, regs_ext; |
110 char idstr[13]; | |
111 unsigned max_cpuid; | |
112 unsigned max_ext_cpuid; | |
113 unsigned int amd_flags; | |
114 unsigned int amd_flags2; | |
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115 const char *model_name = NULL; |
17041 | 116 int i; |
117 char processor_name[49]; | |
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118 |
17041 | 119 regs = cpuid(0); |
120 max_cpuid = regs.eax; | |
121 /* printf("%d CPUID function codes\n", max_cpuid+1); */ | |
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122 |
17041 | 123 store32(idstr+0, regs.ebx); |
124 store32(idstr+4, regs.edx); | |
125 store32(idstr+8, regs.ecx); | |
126 idstr[12] = 0; | |
127 printf("vendor_id\t: %s\n", idstr); | |
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128 |
17041 | 129 regs_ext = cpuid((1<<31) + 0); |
130 max_ext_cpuid = regs_ext.eax; | |
131 if (max_ext_cpuid >= (1<<31) + 1) { | |
132 regs_ext = cpuid((1<<31) + 1); | |
133 amd_flags = regs_ext.edx; | |
134 amd_flags2 = regs_ext.ecx; | |
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135 |
17041 | 136 if (max_ext_cpuid >= (1<<31) + 4) { |
137 for (i = 2; i <= 4; i++) { | |
138 regs_ext = cpuid((1<<31) + i); | |
139 store32(processor_name + (i-2)*16, regs_ext.eax); | |
140 store32(processor_name + (i-2)*16 + 4, regs_ext.ebx); | |
141 store32(processor_name + (i-2)*16 + 8, regs_ext.ecx); | |
142 store32(processor_name + (i-2)*16 + 12, regs_ext.edx); | |
143 } | |
144 processor_name[48] = 0; | |
145 model_name = processor_name; | |
146 } | |
147 } else { | |
148 amd_flags = 0; | |
149 amd_flags2 = 0; | |
150 } | |
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151 |
17041 | 152 if (max_cpuid >= 1) { |
153 static struct { | |
154 int bit; | |
20001 | 155 char *desc; |
17041 | 156 } cap[] = { |
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157 CPUID_FEATURE_DEF(0, "fpu", "Floating-point unit on-chip"), |
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158 CPUID_FEATURE_DEF(1, "vme", "Virtual Mode Enhancements"), |
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159 CPUID_FEATURE_DEF(2, "de", "Debugging Extension"), |
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160 CPUID_FEATURE_DEF(3, "pse", "Page Size Extension"), |
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161 CPUID_FEATURE_DEF(4, "tsc", "Time Stamp Counter"), |
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162 CPUID_FEATURE_DEF(5, "msr", "Pentium Processor MSR"), |
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163 CPUID_FEATURE_DEF(6, "pae", "Physical Address Extension"), |
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164 CPUID_FEATURE_DEF(7, "mce", "Machine Check Exception"), |
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165 CPUID_FEATURE_DEF(8, "cx8", "CMPXCHG8B Instruction Supported"), |
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166 CPUID_FEATURE_DEF(9, "apic", "On-chip APIC Hardware Enabled"), |
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167 CPUID_FEATURE_DEF(11, "sep", "SYSENTER and SYSEXIT"), |
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168 CPUID_FEATURE_DEF(12, "mtrr", "Memory Type Range Registers"), |
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169 CPUID_FEATURE_DEF(13, "pge", "PTE Global Bit"), |
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170 CPUID_FEATURE_DEF(14, "mca", "Machine Check Architecture"), |
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171 CPUID_FEATURE_DEF(15, "cmov", "Conditional Move/Compare Instruction"), |
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172 CPUID_FEATURE_DEF(16, "pat", "Page Attribute Table"), |
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173 CPUID_FEATURE_DEF(17, "pse36", "Page Size Extension 36-bit"), |
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174 CPUID_FEATURE_DEF(18, "pn", "Processor Serial Number"), |
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175 CPUID_FEATURE_DEF(19, "cflsh", "CFLUSH instruction"), |
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176 CPUID_FEATURE_DEF(21, "dts", "Debug Store"), |
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177 CPUID_FEATURE_DEF(22, "acpi", "Thermal Monitor and Clock Ctrl"), |
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178 CPUID_FEATURE_DEF(23, "mmx", "MMX Technology"), |
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179 CPUID_FEATURE_DEF(24, "fxsr", "FXSAVE/FXRSTOR"), |
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180 CPUID_FEATURE_DEF(25, "sse", "SSE Extensions"), |
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181 CPUID_FEATURE_DEF(26, "sse2", "SSE2 Extensions"), |
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182 CPUID_FEATURE_DEF(27, "ss", "Self Snoop"), |
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183 CPUID_FEATURE_DEF(28, "ht", "Multi-threading"), |
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184 CPUID_FEATURE_DEF(29, "tm", "Therm. Monitor"), |
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185 CPUID_FEATURE_DEF(30, "ia64", "IA-64 Processor"), |
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186 CPUID_FEATURE_DEF(31, "pbe", "Pend. Brk. EN."), |
17041 | 187 { -1 } |
188 }; | |
189 static struct { | |
190 int bit; | |
191 char *desc; | |
192 } cap2[] = { | |
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193 CPUID_FEATURE_DEF(0, "pni", "SSE3 Extensions"), |
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194 CPUID_FEATURE_DEF(3, "monitor", "MONITOR/MWAIT"), |
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195 CPUID_FEATURE_DEF(4, "ds_cpl", "CPL Qualified Debug Store"), |
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196 CPUID_FEATURE_DEF(5, "vmx", "Virtual Machine Extensions"), |
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197 CPUID_FEATURE_DEF(6, "smx", "Safer Mode Extensions"), |
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198 CPUID_FEATURE_DEF(7, "est", "Enhanced Intel SpeedStep Technology"), |
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199 CPUID_FEATURE_DEF(8, "tm2", "Thermal Monitor 2"), |
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200 CPUID_FEATURE_DEF(9, "ssse3", "Supplemental SSE3"), |
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201 CPUID_FEATURE_DEF(10, "cid", "L1 Context ID"), |
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202 CPUID_FEATURE_DEF(13, "cx16", "CMPXCHG16B Available"), |
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203 CPUID_FEATURE_DEF(14, "xtpr", "xTPR Disable"), |
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204 CPUID_FEATURE_DEF(18, "dca", "Direct Cache Access"), |
17041 | 205 { -1 } |
206 }; | |
207 static struct { | |
208 int bit; | |
20000 | 209 char *desc; |
17041 | 210 } cap_amd[] = { |
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211 CPUID_FEATURE_DEF(11, "syscall", "SYSCALL and SYSRET"), |
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212 CPUID_FEATURE_DEF(19, "mp", "MP Capable"), |
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213 CPUID_FEATURE_DEF(20, "nx", "No-Execute Page Protection"), |
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214 CPUID_FEATURE_DEF(22, "mmxext","MMX Technology (AMD Extensions)"), |
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215 CPUID_FEATURE_DEF(25, "fxsr_opt", "Fast FXSAVE/FXRSTOR"), |
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216 CPUID_FEATURE_DEF(27, "rdtscp", "RDTSCP Instruction"), |
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217 CPUID_FEATURE_DEF(29, "lm", "Long Mode Capable"), |
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218 CPUID_FEATURE_DEF(30, "3dnowext", "3DNow! Extensions"), |
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219 CPUID_FEATURE_DEF(31, "3dnow", "3DNow!"), |
17041 | 220 { -1 } |
221 }; | |
222 static struct { | |
223 int bit; | |
224 char *desc; | |
225 } cap_amd2[] = { | |
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226 CPUID_FEATURE_DEF(0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode"), |
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227 CPUID_FEATURE_DEF(1, "cmp_legacy", "Chip Multi-Core"), |
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228 CPUID_FEATURE_DEF(2, "svm", "Secure Virtual Machine"), |
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229 CPUID_FEATURE_DEF(4, "cr8legacy", "CR8 Available in Legacy Mode"), |
17041 | 230 { -1 } |
231 }; | |
232 unsigned int family, model, stepping; | |
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233 |
17041 | 234 regs = cpuid(1); |
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235 family = (regs.eax >> 8) & 0xf; |
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236 model = (regs.eax >> 4) & 0xf; |
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237 stepping = regs.eax & 0xf; |
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238 |
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239 if (family == 0xf) |
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240 { |
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241 family += (regs.eax >> 20) & 0xff; |
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242 model += ((regs.eax >> 16) & 0xf) << 4; |
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243 } |
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244 |
17041 | 245 printf("cpu family\t: %d\n" |
246 "model\t\t: %d\n" | |
247 "stepping\t: %d\n" , | |
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248 family, |
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249 model, |
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250 stepping); |
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251 |
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252 if (strstr(idstr, "Intel") && !model_name) { |
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253 if (family == 6 && model == 0xb && stepping == 1) |
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254 model_name = "Intel (R) Celeron (R) processor"; |
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255 else |
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256 model_name = brandname(regs.ebx & 0xf); |
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257 } |
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258 |
17041 | 259 printf("flags\t\t:"); |
260 for (i = 0; cap[i].bit >= 0; i++) { | |
261 if (regs.edx & (1 << cap[i].bit)) { | |
262 printf(" %s", cap[i].desc); | |
263 } | |
264 } | |
265 for (i = 0; cap2[i].bit >= 0; i++) { | |
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266 if (regs.ecx & (1 << cap2[i].bit)) { |
17041 | 267 printf(" %s", cap2[i].desc); |
268 } | |
269 } | |
270 /* k6_mtrr is supported by some AMD K6-2/K6-III CPUs but | |
271 it is not indicated by a CPUID feature bit, so we | |
272 have to check the family, model and stepping instead. */ | |
273 if (strstr(idstr, "AMD") && | |
274 family == 5 && | |
275 (model >= 9 || model == 8 && stepping >= 8)) | |
276 printf(" %s", "k6_mtrr"); | |
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277 /* similar for cyrix_arr. */ |
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278 if (strstr(idstr, "Cyrix") && |
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279 (family == 5 && model < 4 || family == 6)) |
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280 printf(" %s", "cyrix_arr"); |
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281 /* as well as centaur_mcr. */ |
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282 if (strstr(idstr, "Centaur") && |
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283 family == 5) |
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284 printf(" %s", "centaur_mcr"); |
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285 |
17041 | 286 for (i = 0; cap_amd[i].bit >= 0; i++) { |
287 if (amd_flags & (1 << cap_amd[i].bit)) { | |
288 printf(" %s", cap_amd[i].desc); | |
289 } | |
290 } | |
291 for (i = 0; cap_amd2[i].bit >= 0; i++) { | |
292 if (amd_flags2 & (1 << cap_amd2[i].bit)) { | |
293 printf(" %s", cap_amd2[i].desc); | |
294 } | |
295 } | |
296 printf("\n"); | |
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297 |
17041 | 298 if (regs.edx & (1 << 4)) { |
299 int64_t tsc_start, tsc_end; | |
300 struct timeval tv_start, tv_end; | |
301 int usec_delay; | |
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302 |
17041 | 303 tsc_start = rdtsc(); |
304 gettimeofday(&tv_start, NULL); | |
305 #ifdef MISSING_USLEEP | |
306 sleep(1); | |
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307 #else |
17041 | 308 usleep(100000); |
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309 #endif |
17041 | 310 tsc_end = rdtsc(); |
311 gettimeofday(&tv_end, NULL); | |
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312 |
17041 | 313 usec_delay = 1000000 * (tv_end.tv_sec - tv_start.tv_sec) |
314 + (tv_end.tv_usec - tv_start.tv_usec); | |
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315 |
17041 | 316 printf("cpu MHz\t\t: %.3f\n", |
317 (double)(tsc_end-tsc_start) / usec_delay); | |
318 } | |
319 } | |
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320 |
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321 printf("model name\t: "); |
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322 if (model_name) |
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323 printf("%s\n", model_name); |
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324 else |
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325 printf("Unknown %s CPU\n", idstr); |
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326 } |