Mercurial > mplayer.hg
annotate vidix/savage_vid.c @ 22858:6c57087c5a2d
checking for dynamic drivers version number is now pointless
author | ben |
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date | Sun, 01 Apr 2007 11:13:04 +0000 |
parents | 77def5093daf |
children | 3657ff134131 |
rev | line source |
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22850 | 1 /* |
2 Driver for S3 Savage Series | |
3 | |
4 Copyright (C) 2004 by Reza Jelveh | |
5 | |
6 Based on the X11 driver and nvidia vid | |
7 | |
8 Thanks to Alex Deucher for Support | |
9 | |
10 This program is free software; you can redistribute it and/or modify | |
11 it under the terms of the GNU General Public License as published by | |
12 the Free Software Foundation; either version 2 of the License, or | |
13 (at your option) any later version. | |
14 | |
15 This program is distributed in the hope that it will be useful, | |
16 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 GNU General Public License for more details. | |
19 | |
20 You should have received a copy of the GNU General Public License | |
21 along with this program; if not, write to the Free Software | |
22 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
23 | |
24 Changes: | |
25 2004-11-09 | |
26 Initial version | |
27 | |
28 To Do: | |
29 | |
30 */ | |
31 | |
32 | |
33 #include <errno.h> | |
34 #include <stdio.h> | |
35 #include <stdlib.h> | |
36 #include <string.h> | |
37 #include <inttypes.h> | |
38 #include <unistd.h> | |
39 #include <math.h> | |
40 | |
41 #include "vidix.h" | |
22857
77def5093daf
switch to new internal vidix API, no more dlopen/dlsym, libvidix is now a fully static library with all drivers built-in
ben
parents:
22850
diff
changeset
|
42 #include "vidixlib.h" |
22850 | 43 #include "fourcc.h" |
44 #include "../libdha/libdha.h" | |
45 #include "../libdha/pci_ids.h" | |
46 #include "../libdha/pci_names.h" | |
47 #include "../config.h" | |
48 | |
49 #include "savage_regs.h" | |
50 | |
51 | |
52 #define VF_STREAMS_ON 0x0001 | |
53 #define BASE_PAD 0xf | |
54 #define FRAMEBUFFER_SIZE 1024*2000*4 | |
55 /************************************** | |
56 S3 streams processor | |
57 **************************************/ | |
58 | |
59 #define EXT_MISC_CTRL2 0x67 | |
60 | |
61 /* New streams */ | |
62 | |
63 /* CR67[2] = 1 : enable stream 1 */ | |
64 #define ENABLE_STREAM1 0x04 | |
65 /* CR67[1] = 1 : enable stream 2 */ | |
66 #define ENABLE_STREAM2 0x02 | |
67 /* mask to clear CR67[2,1] */ | |
68 #define NO_STREAMS 0xF9 | |
69 /* CR67[3] = 1 : Mem-mapped regs */ | |
70 #define USE_MM_FOR_PRI_STREAM 0x08 | |
71 | |
72 #define HDM_SHIFT 16 | |
73 #define HDSCALE_4 (2 << HDM_SHIFT) | |
74 #define HDSCALE_8 (3 << HDM_SHIFT) | |
75 #define HDSCALE_16 (4 << HDM_SHIFT) | |
76 #define HDSCALE_32 (5 << HDM_SHIFT) | |
77 #define HDSCALE_64 (6 << HDM_SHIFT) | |
78 | |
79 /* Old Streams */ | |
80 | |
81 #define ENABLE_STREAMS_OLD 0x0c | |
82 #define NO_STREAMS_OLD 0xf3 | |
83 /* CR69[0] = 1 : Mem-mapped regs */ | |
84 #define USE_MM_FOR_PRI_STREAM_OLD 0x01 | |
85 | |
86 void SavageStreamsOn(void); | |
87 | |
88 /* | |
89 * There are two different streams engines used in the Savage line. | |
90 * The old engine is in the 3D, 4, Pro, and Twister. | |
91 * The new engine is in the 2000, MX, IX, and Super. | |
92 */ | |
93 | |
94 | |
95 /* streams registers for old engine */ | |
96 #define PSTREAM_CONTROL_REG 0x8180 | |
97 #define COL_CHROMA_KEY_CONTROL_REG 0x8184 | |
98 #define SSTREAM_CONTROL_REG 0x8190 | |
99 #define CHROMA_KEY_UPPER_BOUND_REG 0x8194 | |
100 #define SSTREAM_STRETCH_REG 0x8198 | |
101 #define COLOR_ADJUSTMENT_REG 0x819C | |
102 #define BLEND_CONTROL_REG 0x81A0 | |
103 #define PSTREAM_FBADDR0_REG 0x81C0 | |
104 #define PSTREAM_FBADDR1_REG 0x81C4 | |
105 #define PSTREAM_STRIDE_REG 0x81C8 | |
106 #define DOUBLE_BUFFER_REG 0x81CC | |
107 #define SSTREAM_FBADDR0_REG 0x81D0 | |
108 #define SSTREAM_FBADDR1_REG 0x81D4 | |
109 #define SSTREAM_STRIDE_REG 0x81D8 | |
110 #define SSTREAM_VSCALE_REG 0x81E0 | |
111 #define SSTREAM_VINITIAL_REG 0x81E4 | |
112 #define SSTREAM_LINES_REG 0x81E8 | |
113 #define STREAMS_FIFO_REG 0x81EC | |
114 #define PSTREAM_WINDOW_START_REG 0x81F0 | |
115 #define PSTREAM_WINDOW_SIZE_REG 0x81F4 | |
116 #define SSTREAM_WINDOW_START_REG 0x81F8 | |
117 #define SSTREAM_WINDOW_SIZE_REG 0x81FC | |
118 #define FIFO_CONTROL 0x8200 | |
119 #define PSTREAM_FBSIZE_REG 0x8300 | |
120 #define SSTREAM_FBSIZE_REG 0x8304 | |
121 #define SSTREAM_FBADDR2_REG 0x8308 | |
122 | |
123 #define OS_XY(x,y) (((x+1)<<16)|(y+1)) | |
124 #define OS_WH(x,y) (((x-1)<<16)|(y)) | |
125 | |
126 #define PCI_COMMAND_MEM 0x2 | |
127 #define MAX_FRAMES 3 | |
128 /** | |
129 * @brief Information on PCI device. | |
130 */ | |
131 pciinfo_t pci_info; | |
132 | |
133 /** | |
134 * @brief Unichrome driver colorkey settings. | |
135 */ | |
136 static vidix_grkey_t savage_grkey; | |
137 | |
138 static int frames[VID_PLAY_MAXFRAMES]; | |
139 uint8_t *vio; | |
140 uint8_t mclk_save[3]; | |
141 | |
142 #define outb(reg,val) OUTPORT8(reg,val) | |
143 #define inb(reg) INPORT8(reg) | |
144 #define outw(reg,val) OUTPORT16(reg,val) | |
145 #define inw(reg) INPORT16(reg) | |
146 #define outl(reg,val) OUTPORT32(reg,val) | |
147 #define inl(reg) INPORT32(reg) | |
148 | |
149 | |
150 /* | |
151 * PCI-Memory IO access macros. | |
152 */ | |
153 #define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val)) | |
154 #define VID_RD08(p,i) (((uint8_t *)(p))[(i)]) | |
155 | |
156 #define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val)) | |
157 #define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4]) | |
158 | |
159 #ifndef USE_RMW_CYCLES | |
160 /* | |
161 * Can be used to inhibit READ-MODIFY-WRITE cycles. On by default. | |
162 */ | |
163 | |
164 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") | |
165 | |
166 #undef VID_WR08 | |
167 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) | |
168 #undef VID_RD08 | |
169 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) | |
170 | |
171 #undef VID_WR16 | |
172 #define VID_WR16(p,i,val) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]=(val); }) | |
173 #undef VID_RD16 | |
174 #define VID_RD16(p,i) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]; }) | |
175 | |
176 #undef VID_WR32 | |
177 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); }) | |
178 #undef VID_RD32 | |
179 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) | |
180 #endif /* USE_RMW_CYCLES */ | |
181 | |
182 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) | |
183 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) | |
184 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) | |
185 | |
186 | |
187 /* from x driver */ | |
188 | |
189 #define VGAIN8(addr) VID_RD08(info->control_base+0x8000, addr) | |
190 #define VGAIN16(addr) VID_RD16(info->control_base+0x8000, addr) | |
191 #define VGAIN(addr) VID_RD32(info->control_base+0x8000, addr) | |
192 | |
193 #define VGAOUT8(addr,val) VID_WR08(info->control_base+0x8000, addr, val) | |
194 #define VGAOUT16(addr,val) VID_WR16(info->control_base+0x8000, addr, val) | |
195 #define VGAOUT(addr,val) VID_WR32(info->control_base+0x8000, addr, val) | |
196 | |
197 #define INREG(addr) VID_RD32(info->control_base, addr) | |
198 #define OUTREG(addr,val) VID_WR32(info->control_base, addr, val) | |
199 #define INREG8(addr) VID_RD08(info->control_base, addr) | |
200 #define OUTREG8(addr,val) VID_WR08(info->control_base, addr, val) | |
201 #define INREG16(addr) VID_RD16(info->control_base, addr) | |
202 #define OUTREG16(addr,val) VID_WR16(info->control_base, addr, val) | |
203 | |
204 #define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1)) | |
205 | |
206 | |
207 void debugout(unsigned int addr, unsigned int val); | |
208 | |
209 | |
210 struct savage_chip { | |
211 volatile uint32_t *PMC; /* general control */ | |
212 volatile uint32_t *PME; /* multimedia port */ | |
213 volatile uint32_t *PFB; /* framebuffer control */ | |
214 volatile uint32_t *PVIDEO; /* overlay control */ | |
215 volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ | |
216 volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ | |
217 volatile uint32_t *PRAMIN; /* instance memory */ | |
218 volatile uint32_t *PRAMHT; /* hash table */ | |
219 volatile uint32_t *PRAMFC; /* fifo context table */ | |
220 volatile uint32_t *PRAMRO; /* fifo runout table */ | |
221 volatile uint32_t *PFIFO; /* fifo control region */ | |
222 volatile uint32_t *FIFO; /* fifo channels (USER) */ | |
223 volatile uint32_t *PGRAPH; /* graphics engine */ | |
224 | |
225 int arch; /* compatible NV_ARCH_XX define */ | |
226 unsigned long fbsize; /* framebuffer size */ | |
227 void (* lock) (struct savage_chip *, int); | |
228 }; | |
229 typedef struct savage_chip savage_chip; | |
230 | |
231 | |
232 struct savage_info { | |
233 unsigned int use_colorkey; | |
234 unsigned int colorkey; /* saved xv colorkey*/ | |
235 unsigned int vidixcolorkey; /*currently used colorkey*/ | |
236 unsigned int depth; | |
237 unsigned int bpp; | |
238 unsigned int videoFlags; | |
239 unsigned int format; | |
240 unsigned int pitch; | |
241 unsigned int blendBase; | |
242 unsigned int lastKnownPitch; | |
243 unsigned int displayWidth, displayHeight; | |
244 unsigned int brightness,hue,saturation,contrast; | |
245 unsigned int src_w,src_h; | |
246 unsigned int drw_w,drw_h; /*scaled width && height*/ | |
247 unsigned int wx,wy; /*window x && y*/ | |
248 unsigned int screen_x; /*screen width*/ | |
249 unsigned int screen_y; /*screen height*/ | |
250 unsigned long buffer_size; /* size of the image buffer */ | |
251 struct savage_chip chip; /* NV architecture structure */ | |
252 void* video_base; /* virtual address of control region */ | |
253 void* control_base; /* virtual address of fb region */ | |
254 unsigned long picture_base; /* direct pointer to video picture */ | |
255 unsigned long picture_offset; /* offset of video picture in frame buffer */ | |
256 // struct savage_dma dma; /* DMA structure */ | |
257 unsigned int cur_frame; | |
258 unsigned int num_frames; /* number of buffers */ | |
259 int bps; /* bytes per line */ | |
260 void (*SavageWaitIdle) (); | |
261 void (*SavageWaitFifo) (int space); | |
262 }; | |
263 typedef struct savage_info savage_info; | |
264 | |
265 | |
266 static savage_info* info; | |
267 | |
268 | |
269 /** | |
270 * @brief Unichrome driver vidix capabilities. | |
271 */ | |
272 static vidix_capability_t savage_cap = { | |
273 "Savage/ProSavage/Twister vidix", | |
274 "Reza Jelveh <reza.jelveh@tuhh.de>", | |
275 TYPE_OUTPUT, | |
276 {0, 0, 0, 0}, | |
277 4096, | |
278 4096, | |
279 4, | |
280 4, | |
281 -1, | |
282 FLAG_UPSCALER | FLAG_DOWNSCALER, | |
283 VENDOR_S3_INC, | |
284 -1, | |
285 {0, 0, 0, 0} | |
286 }; | |
287 | |
288 struct savage_cards { | |
289 unsigned short chip_id; | |
290 unsigned short arch; | |
291 }; | |
292 | |
293 | |
294 static | |
295 unsigned int GetBlendForFourCC( int id ) | |
296 { | |
297 switch( id ) { | |
298 case IMGFMT_YUY2: | |
299 case IMGFMT_YV12: | |
300 case IMGFMT_I420: | |
301 return 1; | |
302 case IMGFMT_Y211: | |
303 return 4; | |
304 case IMGFMT_RGB15: | |
305 return 3; | |
306 case IMGFMT_RGB16: | |
307 return 5; | |
308 default: | |
309 return 0; | |
310 } | |
311 } | |
312 | |
313 /** | |
314 * @brief list of card IDs compliant with the Unichrome driver . | |
315 */ | |
316 static struct savage_cards savage_card_ids[] = { | |
317 /*[ProSavage PN133] AGP4X VGA Controller (Twister)*/ | |
318 { PCI_CHIP_S3TWISTER_P, S3_PROSAVAGE }, | |
319 /*[ProSavage KN133] AGP4X VGA Controller (TwisterK)*/ | |
320 { PCI_CHIP_S3TWISTER_K, S3_PROSAVAGE }, | |
321 /*ProSavage DDR*/ | |
322 { PCI_CHIP_PROSAVAGE_DDR , S3_PROSAVAGE }, | |
323 /*[ProSavageDDR P4M266 K] */ | |
324 { PCI_CHIP_PROSAVAGE_DDRK , S3_PROSAVAGE }, | |
325 }; | |
326 | |
327 static void SavageSetColorOld(void) | |
328 { | |
329 | |
330 | |
331 if( | |
332 (info->format == IMGFMT_RGB15) || | |
333 (info->format == IMGFMT_RGB16) | |
334 ) | |
335 { | |
336 OUTREG( COLOR_ADJUSTMENT_REG, 0 ); | |
337 } | |
338 else | |
339 { | |
340 /* Change 0..255 into 0..15 */ | |
341 long sat = info->saturation * 16 / 256; | |
342 double hue = info->hue * 0.017453292; | |
343 unsigned long hs1 = ((long)(sat * cos(hue))) & 0x1f; | |
344 unsigned long hs2 = ((long)(sat * sin(hue))) & 0x1f; | |
345 | |
346 OUTREG( COLOR_ADJUSTMENT_REG, | |
347 0x80008000 | | |
348 (info->brightness + 128) | | |
349 ((info->contrast & 0xf8) << (12-7)) | | |
350 (hs1 << 16) | | |
351 (hs2 << 24) | |
352 ); | |
353 debugout( COLOR_ADJUSTMENT_REG, | |
354 0x80008000 | | |
355 (info->brightness + 128) | | |
356 ((info->contrast & 0xf8) << (12-7)) | | |
357 (hs1 << 16) | | |
358 (hs2 << 24) | |
359 ); | |
360 | |
361 } | |
362 } | |
363 | |
364 static void SavageSetColorKeyOld(void) | |
365 { | |
366 int red, green, blue; | |
367 | |
368 /* Here, we reset the colorkey and all the controls. */ | |
369 | |
370 red = (info->vidixcolorkey & 0x00FF0000) >> 16; | |
371 green = (info->vidixcolorkey & 0x0000FF00) >> 8; | |
372 blue = info->vidixcolorkey & 0x000000FF; | |
373 | |
374 if( !info->vidixcolorkey ) { | |
375 printf("SavageSetColorKey disabling colorkey\n"); | |
376 OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 ); | |
377 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 ); | |
378 OUTREG( BLEND_CONTROL_REG, 0 ); | |
379 } | |
380 else { | |
381 switch (info->depth) { | |
382 // FIXME: isnt fixed yet | |
383 case 8: | |
384 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
385 0x37000000 | (info->vidixcolorkey & 0xFF) ); | |
386 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
387 0x00000000 | (info->vidixcolorkey & 0xFF) ); | |
388 break; | |
389 case 15: | |
390 /* 15 bpp 555 */ | |
391 red&=0x1f; | |
392 green&=0x1f; | |
393 blue&=0x1f; | |
394 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
395 0x05000000 | (red<<19) | (green<<11) | (blue<<3) ); | |
396 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
397 0x00000000 | (red<<19) | (green<<11) | (blue<<3) ); | |
398 break; | |
399 case 16: | |
400 /* 16 bpp 565 */ | |
401 red&=0x1f; | |
402 green&=0x3f; | |
403 blue&=0x1f; | |
404 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
405 0x16000000 | (red<<19) | (green<<10) | (blue<<3) ); | |
406 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
407 0x00020002 | (red<<19) | (green<<10) | (blue<<3) ); | |
408 break; | |
409 case 24: | |
410 /* 24 bpp 888 */ | |
411 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
412 0x17000000 | (red<<16) | (green<<8) | (blue) ); | |
413 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
414 0x00000000 | (red<<16) | (green<<8) | (blue) ); | |
415 break; | |
416 } | |
417 | |
418 /* We use destination colorkey */ | |
419 OUTREG( BLEND_CONTROL_REG, 0x05000000 ); | |
420 } | |
421 } | |
422 | |
423 | |
424 static void | |
425 SavageDisplayVideoOld(void) | |
426 { | |
427 int vgaCRIndex, vgaCRReg, vgaIOBase; | |
428 unsigned int ssControl; | |
429 int cr92; | |
430 | |
431 | |
432 vgaIOBase = 0x3d0; | |
433 vgaCRIndex = vgaIOBase + 4; | |
434 vgaCRReg = vgaIOBase + 5; | |
435 | |
436 // if( psav->videoFourCC != id ) | |
437 // SavageStreamsOff(pScrn); | |
438 | |
439 if( !info->videoFlags & VF_STREAMS_ON ) | |
440 { | |
441 SavageStreamsOn(); | |
442 // SavageResetVideo(); | |
443 SavageSetColorOld(); | |
444 SavageSetColorKeyOld(); | |
445 } | |
446 | |
447 | |
448 | |
449 | |
450 /* Set surface format. */ | |
451 | |
452 OUTREG(SSTREAM_CONTROL_REG,GetBlendForFourCC(info->format) << 24 | info->src_w); | |
453 | |
454 debugout(SSTREAM_CONTROL_REG,GetBlendForFourCC(info->format) << 24 | info->src_w); | |
455 | |
456 /* Calculate horizontal scale factor. */ | |
457 | |
458 //FIXME: enable scaling | |
459 OUTREG(SSTREAM_STRETCH_REG, (info->src_w << 15) / info->drw_w ); | |
460 // debugout(SSTREAM_STRETCH_REG, 1 << 15); | |
461 | |
462 OUTREG(SSTREAM_LINES_REG, info->src_h ); | |
463 debugout(SSTREAM_LINES_REG, info->src_h ); | |
464 | |
465 | |
466 OUTREG(SSTREAM_VINITIAL_REG, 0 ); | |
467 debugout(SSTREAM_VINITIAL_REG, 0 ); | |
468 /* Calculate vertical scale factor. */ | |
469 | |
470 // OUTREG(SSTREAM_VSCALE_REG, 1 << 15); | |
471 OUTREG(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) ); | |
472 debugout(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) ); | |
473 // OUTREG(SSTREAM_VSCALE_REG, (info->src_h << 15) / info->drw_h ); | |
474 | |
475 /* Set surface location and stride. */ | |
476 | |
477 OUTREG(SSTREAM_FBADDR0_REG, info->picture_offset ); | |
478 debugout(SSTREAM_FBADDR0_REG, info->picture_offset ); | |
479 | |
480 OUTREG(SSTREAM_FBADDR1_REG, 0 ); | |
481 debugout(SSTREAM_FBADDR1_REG, 0 ); | |
482 | |
483 OUTREG(SSTREAM_STRIDE_REG, info->pitch ); | |
484 debugout(SSTREAM_STRIDE_REG, info->pitch ); | |
485 | |
486 OUTREG(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) ); | |
487 debugout(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) ); | |
488 OUTREG(SSTREAM_WINDOW_SIZE_REG, OS_WH(info->drw_w, info->drw_h) ); | |
489 debugout(SSTREAM_WINDOW_SIZE_REG, OS_WH(info->drw_w, info->drw_h) ); | |
490 | |
491 | |
492 | |
493 ssControl = 0; | |
494 | |
495 if( info->src_w > (info->drw_w << 1) ) | |
496 { | |
497 /* BUGBUG shouldn't this be >=? */ | |
498 if( info->src_w <= (info->drw_w << 2) ) | |
499 ssControl |= HDSCALE_4; | |
500 else if( info->src_w > (info->drw_w << 3) ) | |
501 ssControl |= HDSCALE_8; | |
502 else if( info->src_w > (info->drw_w << 4) ) | |
503 ssControl |= HDSCALE_16; | |
504 else if( info->src_w > (info->drw_w << 5) ) | |
505 ssControl |= HDSCALE_32; | |
506 else if( info->src_w > (info->drw_w << 6) ) | |
507 ssControl |= HDSCALE_64; | |
508 } | |
509 | |
510 ssControl |= info->src_w; | |
511 ssControl |= (1 << 24); | |
512 | |
513 //FIXME: enable scaling | |
514 OUTREG(SSTREAM_CONTROL_REG, ssControl); | |
515 debugout(SSTREAM_CONTROL_REG, ssControl); | |
516 | |
517 // FIXME: this should actually be enabled | |
518 | |
519 info->pitch = (info->pitch + 7) / 8; | |
520 VGAOUT8(vgaCRIndex, 0x92); | |
521 cr92 = VGAIN8(vgaCRReg); | |
522 VGAOUT8(vgaCRReg, (cr92 & 0x40) | (info->pitch >> 8) | 0x80); | |
523 VGAOUT8(vgaCRIndex, 0x93); | |
524 VGAOUT8(vgaCRReg, info->pitch); | |
525 OUTREG(STREAMS_FIFO_REG, 2 | 25 << 5 | 32 << 11); | |
526 | |
527 | |
528 | |
529 | |
530 } | |
531 | |
532 static void SavageInitStreamsOld(void) | |
533 { | |
534 /*unsigned long jDelta;*/ | |
535 unsigned long format = 0; | |
536 | |
537 /* | |
538 * For the OLD streams engine, several of these registers | |
539 * cannot be touched unless streams are on. Seems backwards to me; | |
540 * I'd want to set 'em up, then cut 'em loose. | |
541 */ | |
542 | |
543 | |
544 /*jDelta = pScrn->displayWidth * (pScrn->bitsPerPixel + 7) / 8;*/ | |
545 switch( info->depth ) { | |
546 case 8: format = 0 << 24; break; | |
547 case 15: format = 3 << 24; break; | |
548 case 16: format = 5 << 24; break; | |
549 case 24: format = 7 << 24; break; | |
550 } | |
551 #warning enable this again | |
552 OUTREG(PSTREAM_FBSIZE_REG, | |
553 info->screen_y * info->screen_x * (info->bpp >> 3)); | |
554 | |
555 OUTREG( PSTREAM_WINDOW_START_REG, OS_XY(0,0) ); | |
556 OUTREG( PSTREAM_WINDOW_SIZE_REG, OS_WH(info->screen_x, info->screen_y) ); | |
557 OUTREG( PSTREAM_FBADDR1_REG, 0 ); | |
558 /*OUTREG( PSTREAM_STRIDE_REG, jDelta );*/ | |
559 OUTREG( PSTREAM_CONTROL_REG, format ); | |
560 OUTREG( PSTREAM_FBADDR0_REG, 0 ); | |
561 | |
562 /*OUTREG( PSTREAM_FBSIZE_REG, jDelta * pScrn->virtualY >> 3 );*/ | |
563 | |
564 OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 ); | |
565 OUTREG( SSTREAM_CONTROL_REG, 0 ); | |
566 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 ); | |
567 OUTREG( SSTREAM_STRETCH_REG, 0 ); | |
568 OUTREG( COLOR_ADJUSTMENT_REG, 0 ); | |
569 OUTREG( BLEND_CONTROL_REG, 1 << 24 ); | |
570 OUTREG( DOUBLE_BUFFER_REG, 0 ); | |
571 OUTREG( SSTREAM_FBADDR0_REG, 0 ); | |
572 OUTREG( SSTREAM_FBADDR1_REG, 0 ); | |
573 OUTREG( SSTREAM_FBADDR2_REG, 0 ); | |
574 OUTREG( SSTREAM_FBSIZE_REG, 0 ); | |
575 OUTREG( SSTREAM_STRIDE_REG, 0 ); | |
576 OUTREG( SSTREAM_VSCALE_REG, 0 ); | |
577 OUTREG( SSTREAM_LINES_REG, 0 ); | |
578 OUTREG( SSTREAM_VINITIAL_REG, 0 ); | |
579 #warning is this needed? | |
580 OUTREG( SSTREAM_WINDOW_START_REG, OS_XY(0xfffe, 0xfffe) ); | |
581 OUTREG( SSTREAM_WINDOW_SIZE_REG, OS_WH(10,2) ); | |
582 | |
583 } | |
584 | |
585 void | |
586 SavageStreamsOn(void) | |
587 { | |
588 unsigned char jStreamsControl; | |
589 unsigned short vgaCRIndex = 0x3d0 + 4; | |
590 unsigned short vgaCRReg = 0x3d0 + 5; | |
591 | |
592 // xf86ErrorFVerb(STREAMS_TRACE, "SavageStreamsOn\n" ); | |
593 | |
594 /* Sequence stolen from streams.c in M7 NT driver */ | |
595 | |
596 | |
597 enable_app_io (); | |
598 | |
599 /* Unlock extended registers. */ | |
600 | |
601 /* FIXME: it looks like mmaped io is broken with vgaout16 */ | |
602 VGAOUT16(vgaCRIndex, 0x4838 ); | |
603 VGAOUT16(vgaCRIndex, 0xa039); | |
604 VGAOUT16(0x3c4, 0x0608); | |
605 | |
606 | |
607 | |
608 VGAOUT8( vgaCRIndex, EXT_MISC_CTRL2 ); | |
609 | |
610 if( S3_SAVAGE_MOBILE_SERIES(info->chip.arch) ) | |
611 { | |
612 // SavageInitStreamsNew( pScrn ); | |
613 | |
614 jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAM1; | |
615 | |
616 /* Wait for VBLANK. */ | |
617 VerticalRetraceWait(); | |
618 /* Fire up streams! */ | |
619 VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
620 /* These values specify brightness, contrast, saturation and hue. */ | |
621 OUTREG( SEC_STREAM_COLOR_CONVERT1, 0x0000C892 ); | |
622 OUTREG( SEC_STREAM_COLOR_CONVERT2, 0x00039F9A ); | |
623 OUTREG( SEC_STREAM_COLOR_CONVERT3, 0x01F1547E ); | |
624 } | |
625 else if (info->chip.arch == S3_SAVAGE2000) | |
626 { | |
627 // SavageInitStreams2000( pScrn ); | |
628 | |
629 jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAM1; | |
630 | |
631 /* Wait for VBLANK. */ | |
632 VerticalRetraceWait(); | |
633 /* Fire up streams! */ | |
634 VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
635 /* These values specify brightness, contrast, saturation and hue. */ | |
636 OUTREG( SEC_STREAM_COLOR_CONVERT0_2000, 0x0000C892 ); | |
637 OUTREG( SEC_STREAM_COLOR_CONVERT1_2000, 0x00033400 ); | |
638 OUTREG( SEC_STREAM_COLOR_CONVERT2_2000, 0x000001CF ); | |
639 OUTREG( SEC_STREAM_COLOR_CONVERT3_2000, 0x01F1547E ); | |
640 } | |
641 else | |
642 { | |
643 jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAMS_OLD; | |
644 | |
645 /* Wait for VBLANK. */ | |
646 | |
647 VerticalRetraceWait(); | |
648 | |
649 /* Fire up streams! */ | |
650 | |
651 VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
652 | |
653 SavageInitStreamsOld( ); | |
654 } | |
655 | |
656 /* Wait for VBLANK. */ | |
657 | |
658 VerticalRetraceWait(); | |
659 | |
660 /* Turn on secondary stream TV flicker filter, once we support TV. */ | |
661 | |
662 /* SR70 |= 0x10 */ | |
663 | |
664 info->videoFlags |= VF_STREAMS_ON; | |
665 | |
666 } | |
667 | |
668 | |
669 | |
670 | |
671 static void savage_getscreenproperties(struct savage_info *info){ | |
672 unsigned char bpp=0; | |
673 uint32_t width=0; | |
674 | |
675 uint32_t vgaIOBase, vgaCRIndex, vgaCRReg; | |
676 | |
677 vgaIOBase = 0x3d0; | |
678 vgaCRIndex = vgaIOBase + 4; | |
679 vgaCRReg = vgaIOBase + 5; | |
680 | |
681 | |
682 /* a little reversed from x driver source code */ | |
683 VGAOUT8(vgaCRIndex, 0x67); | |
684 bpp = VGAIN8(vgaCRReg); | |
685 | |
686 | |
687 switch (bpp&0xf0) { | |
688 case 0x00: | |
689 case 0x10: | |
690 info->depth=8; | |
691 info->bpp=8; | |
692 break; | |
693 case 0x20: | |
694 case 0x30: | |
695 info->depth=15; | |
696 info->bpp=16; | |
697 break; | |
698 case 0x40: | |
699 case 0x50: | |
700 info->depth=16; | |
701 info->bpp=16; | |
702 break; | |
703 case 0x70: | |
704 case 0xd0: | |
705 info->depth=24; | |
706 info->bpp=32; | |
707 break; | |
708 | |
709 | |
710 } | |
711 | |
712 | |
713 VGAOUT8(vgaCRIndex, 0x1); | |
714 info->screen_x = (1 + VGAIN8(vgaCRReg)) <<3; | |
715 /*get screen height*/ | |
716 /* get first 8 bits in VT_DISPLAY_END*/ | |
717 VGAOUT8(0x03D4, 0x12); | |
718 info->screen_y = VGAIN8(0x03D5); | |
719 VGAOUT8(0x03D4,0x07); | |
720 /* get 9th bit in CRTC_OVERFLOW*/ | |
721 info->screen_y |= (VGAIN8(0x03D5) &0x02)<<7; | |
722 /* and the 10th in CRTC_OVERFLOW*/ | |
723 info->screen_y |=(VGAIN8(0x03D5) &0x40)<<3; | |
724 ++info->screen_y; | |
725 | |
726 printf("screen_x = %d, screen_y = %d, bpp = %d\n",info->screen_x,info->screen_y,info->bpp); | |
727 } | |
728 | |
729 | |
730 static void SavageStreamsOff(void) | |
731 { | |
732 unsigned char jStreamsControl; | |
733 unsigned short vgaCRIndex = 0x3d0 + 4; | |
734 unsigned short vgaCRReg = 0x3d0 + 5; | |
735 | |
736 | |
737 /* Unlock extended registers. */ | |
738 | |
739 VGAOUT16(vgaCRIndex, 0x4838); | |
740 VGAOUT16(vgaCRIndex, 0xa039); | |
741 VGAOUT16(0x3c4, 0x0608); | |
742 | |
743 VGAOUT8( vgaCRIndex, EXT_MISC_CTRL2 ); | |
744 if( S3_SAVAGE_MOBILE_SERIES(info->chip.arch) || | |
745 (info->chip.arch == S3_SUPERSAVAGE) || | |
746 (info->chip.arch == S3_SAVAGE2000) ) | |
747 jStreamsControl = VGAIN8( vgaCRReg ) & NO_STREAMS; | |
748 else | |
749 jStreamsControl = VGAIN8( vgaCRReg ) & NO_STREAMS_OLD; | |
750 | |
751 /* Wait for VBLANK. */ | |
752 | |
753 VerticalRetraceWait(); | |
754 | |
755 /* Kill streams. */ | |
756 | |
757 VGAOUT16(vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
758 | |
759 VGAOUT16(vgaCRIndex, 0x0093 ); | |
760 VGAOUT8( vgaCRIndex, 0x92 ); | |
761 VGAOUT8( vgaCRReg, VGAIN8(vgaCRReg) & 0x40 ); | |
762 | |
763 info->videoFlags &= ~VF_STREAMS_ON; | |
764 } | |
765 | |
766 /** | |
767 * @brief Find chip index in Unichrome compliant devices list. | |
768 * | |
769 * @param chip_id PCI device ID. | |
770 * | |
771 * @returns index position in savage_card_ids if successful. | |
772 * -1 if chip_id is not a compliant chipset ID. | |
773 */ | |
774 | |
775 static int find_chip(unsigned chip_id){ | |
776 unsigned i; | |
777 for(i = 0;i < sizeof(savage_card_ids)/sizeof(struct savage_cards);i++) | |
778 { | |
779 if(chip_id == savage_card_ids[i].chip_id)return i; | |
780 } | |
781 return -1; | |
782 } | |
783 | |
784 /** | |
785 * @brief Probe hardware to find some useable chipset. | |
786 * | |
787 * @param verbose specifies verbose level. | |
788 * @param force specifies force mode : driver should ignore | |
789 * device_id (danger but useful for new devices) | |
790 * | |
791 * @returns 0 if it can handle something in PC. | |
792 * a negative error code otherwise. | |
793 */ | |
794 | |
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795 static int savage_probe(int verbose, int force){ |
22850 | 796 pciinfo_t lst[MAX_PCI_DEVICES]; |
797 unsigned i,num_pci; | |
798 int err; | |
799 | |
800 if (force) | |
801 printf("[savage_vid]: warning: forcing not supported yet!\n"); | |
802 err = pci_scan(lst,&num_pci); | |
803 if(err){ | |
804 printf("[savage_vid] Error occurred during pci scan: %s\n",strerror(err)); | |
805 return err; | |
806 } | |
807 else { | |
808 err = ENXIO; | |
809 for(i=0; i < num_pci; i++){ | |
810 if(lst[i].vendor == VENDOR_S3_INC) { | |
811 int idx; | |
812 const char *dname; | |
813 idx = find_chip(lst[i].device); | |
814 if(idx == -1) | |
815 continue; | |
816 dname = pci_device_name(lst[i].vendor, lst[i].device); | |
817 dname = dname ? dname : "Unknown chip"; | |
818 printf("[savage_vid] Found chip: %s\n", dname); | |
819 // FIXME: whats wrong here? | |
820 if ((lst[i].command & PCI_COMMAND_IO ) == 0){ | |
821 printf("[savage_vid] Device is disabled, ignoring\n"); | |
822 continue; | |
823 } | |
824 savage_cap.device_id = lst[i].device; | |
825 err = 0; | |
826 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); | |
827 break; | |
828 } | |
829 } | |
830 } | |
831 if(err && verbose) printf("[savage_vid] Can't find chip\n"); | |
832 return err; | |
833 } | |
834 | |
835 /** | |
836 * @brief Initializes driver. | |
837 * | |
838 * @returns 0 if ok. | |
839 * a negative error code otherwise. | |
840 */ | |
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841 static int |
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842 savage_init (void) |
22850 | 843 { |
844 int mtrr; | |
845 unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp; | |
846 | |
847 static unsigned char RamSavage3D[] = { 8, 4, 4, 2 }; | |
848 static unsigned char RamSavage4[] = { 2, 4, 8, 12, 16, 32, 64, 32 }; | |
849 static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 }; | |
850 static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 16, 2 }; | |
851 | |
852 int videoRam, videoRambytes; | |
853 | |
854 uint32_t vgaIOBase, vgaCRIndex, vgaCRReg ; | |
855 | |
856 unsigned char val; | |
857 | |
858 vgaIOBase = 0x3d0; | |
859 vgaCRIndex = vgaIOBase + 4; | |
860 vgaCRReg = vgaIOBase + 5; | |
861 | |
862 fprintf(stderr, "vixInit enter \n"); | |
863 // //getc(stdin); | |
864 | |
865 info = calloc(1,sizeof(savage_info)); | |
866 | |
867 | |
868 /* need this if we want direct outb and inb access? */ | |
869 enable_app_io (); | |
870 | |
871 /* 12mb + 32kb ? */ | |
872 /* allocate some space for control registers */ | |
873 info->chip.arch = savage_card_ids[find_chip(pci_info.device)].arch; | |
874 | |
875 if (info->chip.arch == S3_SAVAGE3D) { | |
876 info->control_base = map_phys_mem(pci_info.base0+SAVAGE_NEWMMIO_REGBASE_S3, SAVAGE_NEWMMIO_REGSIZE); | |
877 } | |
878 else { | |
879 info->control_base = map_phys_mem(pci_info.base0+SAVAGE_NEWMMIO_REGBASE_S4, SAVAGE_NEWMMIO_REGSIZE); | |
880 } | |
881 | |
882 // info->chip.PCIO = (uint8_t *) (info->control_base + SAVAGE_NEWMMIO_VGABASE); | |
883 | |
884 // FIXME: enable mmio? | |
885 val = VGAIN8 (0x3c3); | |
886 VGAOUT8 (0x3c3, val | 0x01); | |
887 val = VGAIN8 (0x3cc); | |
888 VGAOUT8 (0x3c2, val | 0x01); | |
889 | |
890 if (info->chip.arch >= S3_SAVAGE4) | |
891 { | |
892 VGAOUT8 (0x3d4, 0x40); | |
893 val = VGAIN8 (0x3d5); | |
894 VGAOUT8 (0x3d5, val | 1); | |
895 } | |
896 | |
897 | |
898 | |
899 /* unprotect CRTC[0-7] */ | |
900 VGAOUT8(vgaCRIndex, 0x11); | |
901 tmp = VGAIN8(vgaCRReg); | |
902 // printf("$########## tmp = %d\n",tmp); | |
903 VGAOUT8(vgaCRReg, tmp & 0x7f); | |
904 | |
905 | |
906 /* unlock extended regs */ | |
907 VGAOUT16(vgaCRIndex, 0x4838); | |
908 VGAOUT16(vgaCRIndex, 0xa039); | |
909 VGAOUT16(0x3c4, 0x0608); | |
910 | |
911 VGAOUT8(vgaCRIndex, 0x40); | |
912 tmp = VGAIN8(vgaCRReg); | |
913 VGAOUT8(vgaCRReg, tmp & ~0x01); | |
914 | |
915 /* unlock sys regs */ | |
916 VGAOUT8(vgaCRIndex, 0x38); | |
917 VGAOUT8(vgaCRReg, 0x48); | |
918 | |
919 /* Unlock system registers. */ | |
920 VGAOUT16(vgaCRIndex, 0x4838); | |
921 | |
922 /* Next go on to detect amount of installed ram */ | |
923 | |
924 VGAOUT8(vgaCRIndex, 0x36); /* for register CR36 (CONFG_REG1), */ | |
925 config1 = VGAIN8(vgaCRReg); /* get amount of vram installed */ | |
926 | |
927 | |
928 switch( info->chip.arch ) { | |
929 case S3_SAVAGE3D: | |
930 videoRam = RamSavage3D[ (config1 & 0xC0) >> 6 ] * 1024; | |
931 break; | |
932 | |
933 case S3_SAVAGE4: | |
934 /* | |
935 * The Savage4 has one ugly special case to consider. On | |
936 * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB | |
937 * when it really means 8MB. Why do it the same when you | |
938 * can do it different... | |
939 */ | |
940 VGAOUT8(0x3d4, 0x68); /* memory control 1 */ | |
941 if( (VGAIN8(0x3d5) & 0xC0) == (0x01 << 6) ) | |
942 RamSavage4[1] = 8; | |
943 | |
944 /*FALLTHROUGH*/ | |
945 | |
946 case S3_SAVAGE2000: | |
947 videoRam = RamSavage4[ (config1 & 0xE0) >> 5 ] * 1024; | |
948 break; | |
949 | |
950 case S3_SAVAGE_MX: | |
951 videoRam = RamSavageMX[ (config1 & 0x0E) >> 1 ] * 1024; | |
952 break; | |
953 | |
954 case S3_PROSAVAGE: | |
955 videoRam = RamSavageNB[ (config1 & 0xE0) >> 5 ] * 1024; | |
956 break; | |
957 | |
958 default: | |
959 /* How did we get here? */ | |
960 videoRam = 0; | |
961 break; | |
962 } | |
963 | |
964 | |
965 printf("###### videoRam = %d\n",videoRam); | |
966 info->chip.fbsize = videoRam * 1024; | |
967 | |
968 | |
969 /* reset graphics engine to avoid memory corruption */ | |
970 /* VGAOUT8 (0x3d4, 0x66); | |
971 cr66 = VGAIN8 (0x3d5); | |
972 VGAOUT8 (0x3d5, cr66 | 0x02); | |
973 udelay (10000); | |
974 | |
975 VGAOUT8 (0x3d4, 0x66); | |
976 VGAOUT8 (0x3d5, cr66 & ~0x02); /* clear reset flag */ | |
977 /* udelay (10000); */ | |
978 | |
979 /* This maps framebuffer @6MB, thus 2MB are left for video. */ | |
980 if (info->chip.arch == S3_SAVAGE3D) { | |
981 info->video_base = map_phys_mem(pci_info.base0, info->chip.fbsize); | |
982 info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1); | |
983 } | |
984 else { | |
985 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
986 info->picture_offset = info->chip.fbsize - FRAMEBUFFER_SIZE; | |
987 // info->picture_offset = 1024*1024* 4 * 2; | |
988 } | |
989 if ( info->video_base < 0 ){ | |
990 printf("errno = %s\n", strerror(errno)); | |
991 return -1; | |
992 } | |
993 | |
994 | |
995 info->picture_base = (uint32_t) info->video_base + info->picture_offset; | |
996 | |
997 if ( info->chip.arch == S3_SAVAGE3D ){ | |
998 mtrr = mtrr_set_type(pci_info.base0, info->chip.fbsize, MTRR_TYPE_WRCOMB); | |
999 } | |
1000 else{ | |
1001 mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB); | |
1002 } | |
1003 | |
1004 if (mtrr!= 0) | |
1005 printf("[savage_vid] unable to setup MTRR: %s\n", strerror(mtrr)); | |
1006 else | |
1007 printf("[savage_vid] MTRR set up\n"); | |
1008 | |
1009 /* This may trash your screen for resolutions greater than 1024x768, sorry. */ | |
1010 | |
1011 | |
1012 savage_getscreenproperties(info); | |
1013 // return -1; | |
1014 info->videoFlags = 0; | |
1015 | |
1016 SavageStreamsOn(); | |
1017 //getc(stdin); | |
1018 //FIXME ADD | |
1019 return 0; | |
1020 } | |
1021 | |
1022 /** | |
1023 * @brief Destroys driver. | |
1024 */ | |
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1025 static void |
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1026 savage_destroy (void) |
22850 | 1027 { |
1028 unmap_phys_mem(info->video_base, info->chip.fbsize); | |
1029 unmap_phys_mem(info->control_base, SAVAGE_NEWMMIO_REGSIZE); | |
1030 //FIXME ADD | |
1031 } | |
1032 | |
1033 /** | |
1034 * @brief Get chipset's hardware capabilities. | |
1035 * | |
1036 * @param to Pointer to the vidix_capability_t structure to be filled. | |
1037 * | |
1038 * @returns 0. | |
1039 */ | |
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1040 static int |
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1041 savage_get_caps (vidix_capability_t * to) |
22850 | 1042 { |
1043 memcpy (to, &savage_cap, sizeof (vidix_capability_t)); | |
1044 return 0; | |
1045 } | |
1046 | |
1047 /** | |
1048 * @brief Report if the video FourCC is supported by hardware. | |
1049 * | |
1050 * @param fourcc input image format. | |
1051 * | |
1052 * @returns 1 if the fourcc is supported. | |
1053 * 0 otherwise. | |
1054 */ | |
1055 static int | |
1056 is_supported_fourcc (uint32_t fourcc) | |
1057 { | |
1058 switch (fourcc) | |
1059 { | |
1060 //FIXME: YV12 isnt working properly yet | |
1061 // case IMGFMT_YV12: | |
1062 // case IMGFMT_I420: | |
1063 case IMGFMT_UYVY: | |
1064 case IMGFMT_YVYU: | |
1065 case IMGFMT_YUY2: | |
1066 case IMGFMT_RGB15: | |
1067 case IMGFMT_RGB16: | |
1068 // case IMGFMT_BGR32: | |
1069 return 1; | |
1070 default: | |
1071 return 0; | |
1072 } | |
1073 } | |
1074 | |
1075 /** | |
1076 * @brief Try to configure video memory for given fourcc. | |
1077 * | |
1078 * @param to Pointer to the vidix_fourcc_t structure to be filled. | |
1079 * | |
1080 * @returns 0 if ok. | |
1081 * errno otherwise. | |
1082 */ | |
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1083 static int |
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1084 savage_query_fourcc (vidix_fourcc_t * to) |
22850 | 1085 { |
1086 if (is_supported_fourcc (to->fourcc)) | |
1087 { | |
1088 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
1089 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
1090 VID_DEPTH_12BPP | VID_DEPTH_15BPP | | |
1091 VID_DEPTH_16BPP | VID_DEPTH_24BPP | VID_DEPTH_32BPP; | |
1092 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; | |
1093 return 0; | |
1094 } | |
1095 else | |
1096 to->depth = to->flags = 0; | |
1097 | |
1098 return ENOSYS; | |
1099 } | |
1100 | |
1101 /** | |
1102 * @brief Get the GrKeys | |
1103 * | |
1104 * @param grkey Pointer to the vidix_grkey_t structure to be filled by driver. | |
1105 * | |
1106 * @return 0. | |
1107 */ | |
1108 /*int | |
1109 vixGetGrKeys (vidix_grkey_t * grkey) | |
1110 { | |
1111 | |
1112 // if(info->d_width && info->d_height)savage_overlay_start(info,0); | |
1113 | |
1114 return (0); | |
1115 } | |
1116 * */ | |
1117 | |
1118 /** | |
1119 * @brief Set the GrKeys | |
1120 * | |
1121 * @param grkey Colorkey to be set. | |
1122 * | |
1123 * @return 0. | |
1124 */ | |
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1125 static int |
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1126 savage_set_gkeys (const vidix_grkey_t * grkey) |
22850 | 1127 { |
1128 if (grkey->ckey.op == CKEY_FALSE) | |
1129 { | |
1130 info->use_colorkey = 0; | |
1131 info->vidixcolorkey=0; | |
1132 printf("[savage_vid] colorkeying disabled\n"); | |
1133 } | |
1134 else { | |
1135 info->use_colorkey = 1; | |
1136 info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); | |
1137 | |
1138 printf("[savage_vid] set colorkey 0x%x\n",info->vidixcolorkey); | |
1139 } | |
1140 //FIXME: freezes if streams arent enabled | |
1141 SavageSetColorKeyOld(); | |
1142 return (0); | |
1143 } | |
1144 | |
1145 /** | |
1146 * @brief Unichrome driver equalizer capabilities. | |
1147 */ | |
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1148 static vidix_video_eq_t equal = { |
22850 | 1149 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | VEQ_CAP_HUE, |
1150 300, 100, 0, 0, 0, 0, 0, 0 | |
1151 }; | |
1152 | |
1153 | |
1154 /** | |
1155 * @brief Get the equalizer capabilities. | |
1156 * | |
1157 * @param eq Pointer to the vidix_video_eq_t structure to be filled by driver. | |
1158 * | |
1159 * @return 0. | |
1160 */ | |
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1161 static int |
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1162 savage_get_eq (vidix_video_eq_t * eq) |
22850 | 1163 { |
1164 memcpy (eq, &equal, sizeof (vidix_video_eq_t)); | |
1165 return 0; | |
1166 } | |
1167 | |
1168 /** | |
1169 * @brief Set the equalizer capabilities for color correction | |
1170 * | |
1171 * @param eq equalizer capabilities to be set. | |
1172 * | |
1173 * @return 0. | |
1174 */ | |
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1175 static int |
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1176 savage_set_eq (const vidix_video_eq_t * eq) |
22850 | 1177 { |
1178 return 0; | |
1179 } | |
1180 | |
1181 /** | |
1182 * @brief Y, U, V offsets. | |
1183 */ | |
1184 static int YOffs, UOffs, VOffs; | |
1185 | |
1186 /** | |
1187 * @brief Configure driver for playback. Driver should prepare BES. | |
1188 * | |
1189 * @param info configuration description for playback. | |
1190 * | |
1191 * @returns 0 in case of success. | |
1192 * -1 otherwise. | |
1193 */ | |
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1194 static int |
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1195 savage_config_playback (vidix_playback_t * vinfo) |
22850 | 1196 { |
1197 int uv_size, swap_uv; | |
1198 unsigned int i; | |
1199 int extfifo_on; | |
1200 int srcPitch,srcPitch2; | |
1201 | |
1202 /* Overlay register settings */ | |
1203 uint32_t win_start, win_end; | |
1204 uint32_t zoom, mini; | |
1205 uint32_t dcount, falign, qwfetch; | |
1206 uint32_t y_start, u_start, v_start; | |
1207 uint32_t v_ctrl, fifo_ctrl; | |
1208 | |
1209 if (!is_supported_fourcc (vinfo->fourcc)) | |
1210 return -1; | |
1211 | |
1212 | |
1213 | |
1214 info->src_w = vinfo->src.w; | |
1215 info->src_h = vinfo->src.h; | |
1216 | |
1217 info->drw_w = vinfo->dest.w; | |
1218 info->drw_h = vinfo->dest.h; | |
1219 | |
1220 info->wx = vinfo->dest.x; | |
1221 info->wy = vinfo->dest.y; | |
1222 info->format = vinfo->fourcc; | |
1223 | |
1224 info->lastKnownPitch = 0; | |
1225 info->brightness = 0; | |
1226 info->contrast = 128; | |
1227 info->saturation = 128; | |
1228 info->hue = 0; | |
1229 | |
1230 | |
1231 vinfo->dga_addr=(void*)(info->picture_base); | |
1232 | |
1233 | |
1234 vinfo->offset.y = 0; | |
1235 vinfo->offset.v = 0; | |
1236 vinfo->offset.u = 0; | |
1237 | |
1238 vinfo->dest.pitch.y = 32; | |
1239 vinfo->dest.pitch.u = 32; | |
1240 vinfo->dest.pitch.v = 32; | |
1241 // vinfo->dest.pitch.u = 0; | |
1242 // vinfo->dest.pitch.v = 0; | |
1243 | |
1244 | |
1245 info->pitch = ((info->src_w << 1) + 15) & ~15; | |
1246 | |
1247 swap_uv = 0; | |
1248 switch (vinfo->fourcc) | |
1249 { | |
1250 case IMGFMT_YUY2: | |
1251 case IMGFMT_UYVY: | |
1252 | |
1253 info->pitch = ((info->src_w << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1); | |
1254 | |
1255 info->pitch = info->src_w << 1; | |
1256 info->pitch = ALIGN_TO (info->src_w << 1, 32); | |
1257 uv_size = 0; | |
1258 break; | |
1259 case IMGFMT_YV12: | |
1260 swap_uv = 1; | |
1261 | |
1262 | |
1263 | |
1264 /* | |
1265 srcPitch = (info->src_w + 3) & ~3; | |
1266 vinfo->offset.u = srcPitch * info->src_h; | |
1267 srcPitch2 = ((info->src_w >> 1) + 3) & ~3; | |
1268 vinfo->offset.v = (srcPitch2 * (info->src_h >> 1)) + vinfo->offset.v; | |
1269 | |
1270 vinfo->dest.pitch.y=srcPitch ; | |
1271 vinfo->dest.pitch.v=srcPitch2 ; | |
1272 vinfo->dest.pitch.u=srcPitch2 ; | |
1273 */ | |
1274 | |
1275 | |
1276 info->pitch = ALIGN_TO (info->src_w, 32); | |
1277 uv_size = (info->pitch >> 1) * (info->src_h >> 1); | |
1278 | |
1279 vinfo->offset.y = 0; | |
1280 vinfo->offset.v = vinfo->offset.y + info->pitch * info->src_h; | |
1281 vinfo->offset.u = vinfo->offset.v + uv_size; | |
1282 vinfo->frame_size = vinfo->offset.u + uv_size; | |
1283 /* YOffs = info->offset.y; | |
1284 UOffs = (swap_uv ? vinfo->offset.v : vinfo->offset.u); | |
1285 VOffs = (swap_uv ? vinfo->offset.u : vinfo->offset.v); | |
1286 */ | |
1287 // vinfo->offset.y = info->src_w; | |
1288 // vinfo->offset.v = vinfo->offset.y + info->src_w /2 * info->src_h; | |
1289 // vinfo->offset.u = vinfo->offset.v + (info->src_w >> 1) * (info->src_h >> 1) ; | |
1290 | |
1291 break; | |
1292 } | |
1293 info->pitch |= ((info->pitch >> 1) << 16); | |
1294 | |
1295 vinfo->frame_size = info->pitch * info->src_h; | |
1296 | |
1297 printf("$#### destination pitch = %u\n", info->pitch&0xffff); | |
1298 | |
1299 | |
1300 | |
1301 | |
1302 info->buffer_size = vinfo->frame_size; | |
1303 info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; | |
1304 if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; | |
1305 // vinfo->num_frames = 1; | |
1306 // printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); | |
1307 for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; | |
1308 | |
1309 return 0; | |
1310 } | |
1311 | |
1312 /** | |
1313 * @brief Set playback on : driver should activate BES on this call. | |
1314 * | |
1315 * @return 0. | |
1316 */ | |
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1317 static int |
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1318 savage_playback_on (void) |
22850 | 1319 { |
1320 // FIXME: enable | |
1321 SavageDisplayVideoOld(); | |
1322 //FIXME ADD | |
1323 return 0; | |
1324 } | |
1325 | |
1326 /** | |
1327 * @brief Set playback off : driver should deactivate BES on this call. | |
1328 * | |
1329 * @return 0. | |
1330 */ | |
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1331 static int |
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1332 savage_playback_off (void) |
22850 | 1333 { |
1334 // otherwise we wont disable streams properly in new xorg | |
1335 // FIXME: shouldnt this be enabled? | |
1336 // SavageStreamsOn(); | |
1337 SavageStreamsOff(); | |
1338 // info->vidixcolorkey=0x0; | |
1339 | |
1340 // OUTREG( SSTREAM_WINDOW_START_REG, OS_XY(0xfffe, 0xfffe) ); | |
1341 // SavageSetColorKeyOld(); | |
1342 //FIXME ADD | |
1343 return 0; | |
1344 } | |
1345 | |
1346 /** | |
1347 * @brief Driver should prepare and activate corresponded frame. | |
1348 * | |
1349 * @param frame the frame index. | |
1350 * | |
1351 * @return 0. | |
1352 * | |
1353 * @note This function is used only for double and triple buffering | |
1354 * and never used for single buffering playback. | |
1355 */ | |
1356 #if 0 | |
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1357 static int |
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1358 savage_frame_select (unsigned int frame) |
22850 | 1359 { |
1360 ////FIXME ADD | |
1361 // savage_overlay_start(info, frame); | |
1362 //if (info->num_frames >= 1) | |
1363 // info->cur_frame = frame//(frame+1)%info->num_frames; | |
1364 // | |
1365 // savage4_waitidle(info); | |
1366 | |
1367 printf("vixPlaybackFrameSelect Leave\n" ); | |
1368 // FIXME: does this work to avoid tearing? | |
1369 // VerticalRetraceWait(); | |
1370 | |
1371 return 0; | |
1372 } | |
1373 | |
1374 #endif | |
1375 | |
1376 | |
1377 | |
1378 void debugout(unsigned int addr, unsigned int val){ | |
1379 return ; | |
1380 switch ( addr ){ | |
1381 case PSTREAM_CONTROL_REG: | |
1382 fprintf(stderr,"PSTREAM_CONTROL_REG"); | |
1383 break; | |
1384 case COL_CHROMA_KEY_CONTROL_REG: | |
1385 fprintf(stderr,"COL_CHROMA_KEY_CONTROL_REG"); | |
1386 break; | |
1387 case SSTREAM_CONTROL_REG: | |
1388 fprintf(stderr,"SSTREAM_CONTROL_REG"); | |
1389 break; | |
1390 case CHROMA_KEY_UPPER_BOUND_REG: | |
1391 fprintf(stderr,"CHROMA_KEY_UPPER_BOUND_REG"); | |
1392 break; | |
1393 case SSTREAM_STRETCH_REG: | |
1394 fprintf(stderr,"SSTREAM_STRETCH_REG"); | |
1395 break; | |
1396 case COLOR_ADJUSTMENT_REG: | |
1397 fprintf(stderr,"COLOR_ADJUSTMENT_REG"); | |
1398 break; | |
1399 case BLEND_CONTROL_REG: | |
1400 fprintf(stderr,"BLEND_CONTROL_REG"); | |
1401 break; | |
1402 case PSTREAM_FBADDR0_REG: | |
1403 fprintf(stderr,"PSTREAM_FBADDR0_REG"); | |
1404 break; | |
1405 case PSTREAM_FBADDR1_REG: | |
1406 fprintf(stderr,"PSTREAM_FBADDR1_REG"); | |
1407 break; | |
1408 case PSTREAM_STRIDE_REG: | |
1409 fprintf(stderr,"PSTREAM_STRIDE_REG"); | |
1410 break; | |
1411 case DOUBLE_BUFFER_REG: | |
1412 fprintf(stderr,"DOUBLE_BUFFER_REG"); | |
1413 break; | |
1414 case SSTREAM_FBADDR0_REG: | |
1415 fprintf(stderr,"SSTREAM_FBADDR0_REG"); | |
1416 break; | |
1417 case SSTREAM_FBADDR1_REG: | |
1418 fprintf(stderr,"SSTREAM_FBADDR1_REG"); | |
1419 break; | |
1420 case SSTREAM_STRIDE_REG: | |
1421 fprintf(stderr,"SSTREAM_STRIDE_REG"); | |
1422 break; | |
1423 case SSTREAM_VSCALE_REG: | |
1424 fprintf(stderr,"SSTREAM_VSCALE_REG"); | |
1425 break; | |
1426 case SSTREAM_VINITIAL_REG: | |
1427 fprintf(stderr,"SSTREAM_VINITIAL_REG"); | |
1428 break; | |
1429 case SSTREAM_LINES_REG: | |
1430 fprintf(stderr,"SSTREAM_LINES_REG"); | |
1431 break; | |
1432 case STREAMS_FIFO_REG: | |
1433 fprintf(stderr,"STREAMS_FIFO_REG"); | |
1434 break; | |
1435 case PSTREAM_WINDOW_START_REG: | |
1436 fprintf(stderr,"PSTREAM_WINDOW_START_REG"); | |
1437 break; | |
1438 case PSTREAM_WINDOW_SIZE_REG: | |
1439 fprintf(stderr,"PSTREAM_WINDOW_SIZE_REG"); | |
1440 break; | |
1441 case SSTREAM_WINDOW_START_REG: | |
1442 fprintf(stderr,"SSTREAM_WINDOW_START_REG"); | |
1443 break; | |
1444 case SSTREAM_WINDOW_SIZE_REG: | |
1445 fprintf(stderr,"SSTREAM_WINDOW_SIZE_REG"); | |
1446 break; | |
1447 case FIFO_CONTROL: | |
1448 fprintf(stderr,"FIFO_CONTROL"); | |
1449 break; | |
1450 case PSTREAM_FBSIZE_REG: | |
1451 fprintf(stderr,"PSTREAM_FBSIZE_REG"); | |
1452 break; | |
1453 case SSTREAM_FBSIZE_REG: | |
1454 fprintf(stderr,"SSTREAM_FBSIZE_REG"); | |
1455 break; | |
1456 case SSTREAM_FBADDR2_REG: | |
1457 fprintf(stderr,"SSTREAM_FBADDR2_REG"); | |
1458 break; | |
1459 | |
1460 } | |
1461 fprintf(stderr,":\t\t 0x%08X = %u\n",val,val); | |
1462 } | |
1463 | |
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1464 VDXDriver savage_drv = { |
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1465 "savage", |
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1466 NULL, |
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1467 .probe = savage_probe, |
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1468 .get_caps = savage_get_caps, |
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1469 .query_fourcc = savage_query_fourcc, |
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1470 .init = savage_init, |
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1471 .destroy = savage_destroy, |
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1472 .config_playback = savage_config_playback, |
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1473 .playback_on = savage_playback_on, |
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1474 .playback_off = savage_playback_off, |
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1475 #if 0 |
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1476 .frame_sel = savage_frame_select, |
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1477 #endif |
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1478 .get_eq = savage_get_eq, |
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1479 .set_eq = savage_set_eq, |
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1480 .set_gkey = savage_set_gkeys, |
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1481 }; |