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1 /*
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2 * drivers/video/radeonfb.c
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3 * framebuffer driver for ATI Radeon chipset video boards
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4 *
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5 * Copyright 2000 Ani Joshi <ajoshi@unixbox.com>
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6 *
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7 *
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8 * ChangeLog:
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9 * 2000-08-03 initial version 0.0.1
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10 * 2000-09-10 more bug fixes, public release 0.0.5
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11 * 2001-02-19 mode bug fixes, 0.0.7
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12 * 2001-07-05 fixed scrolling issues, engine initialization,
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13 * and minor mode tweaking, 0.0.9
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14 *
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1912
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15 * 2001-09-07 Radeon VE support
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1913
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16 * 2001-09-10 Radeon VE QZ support by Nick Kurshev <nickols_k@mail.ru>
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17 * (limitations: on dualhead Radeons (VE, M6, M7)
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18 * driver works only on second head (DVI port).
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19 * TVout is not supported too. M6 & M7 chips
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20 * currently are not supported. Driver has a lot
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21 * of other bugs. Probably they can be solved by
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22 * importing XFree86 code, which has ATI's support).,
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23 * 0.0.11
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24 *
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25 *
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26 * Special thanks to ATI DevRel team for their hardware donations.
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27 *
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28 */
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29
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30
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1913
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31 #define RADEON_VERSION "0.0.11"
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32
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33
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34 #include <linux/config.h>
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35 #include <linux/module.h>
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36 #include <linux/kernel.h>
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37 #include <linux/errno.h>
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38 #include <linux/string.h>
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39 #include <linux/mm.h>
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40 #include <linux/tty.h>
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41 #include <linux/malloc.h>
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42 #include <linux/delay.h>
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43 #include <linux/fb.h>
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44 #include <linux/console.h>
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45 #include <linux/selection.h>
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46 #include <linux/ioport.h>
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47 #include <linux/init.h>
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48 #include <linux/pci.h>
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49
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50 #include <asm/io.h>
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51
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52 #include <video/fbcon.h>
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53 #include <video/fbcon-cfb8.h>
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54 #include <video/fbcon-cfb16.h>
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55 #include <video/fbcon-cfb24.h>
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56 #include <video/fbcon-cfb32.h>
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57
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58 #include "radeon.h"
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59
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60
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61 #define DEBUG 0
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62
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63 #if DEBUG
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64 #define RTRACE printk
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65 #else
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66 #define RTRACE if(0) printk
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67 #endif
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68
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69
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70
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71 enum radeon_chips {
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72 RADEON_QD,
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73 RADEON_QE,
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74 RADEON_QF,
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75 RADEON_QG,
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76 RADEON_QY,
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77 RADEON_QZ
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78 };
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79
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80
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81 static struct pci_device_id radeonfb_pci_table[] __devinitdata = {
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82 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD},
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83 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE},
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84 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF},
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85 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
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86 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
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87 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
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88 { 0, }
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89 };
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90 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
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91
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92
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93 typedef struct {
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94 u16 reg;
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95 u32 val;
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96 } reg_val;
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97
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98
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99 /* these common regs are cleared before mode setting so they do not
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100 * interfere with anything
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101 */
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102 reg_val common_regs[] = {
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103 { OVR_CLR, 0 },
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104 { OVR_WID_LEFT_RIGHT, 0 },
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105 { OVR_WID_TOP_BOTTOM, 0 },
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106 { OV0_SCALE_CNTL, 0 },
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107 { SUBPIC_CNTL, 0 },
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108 { VIPH_CONTROL, 0 },
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109 { I2C_CNTL_1, 0 },
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110 { GEN_INT_CNTL, 0 },
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111 { CAP0_TRIG_CNTL, 0 },
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112 };
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113
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114 #define COMMON_REGS_SIZE = (sizeof(common_regs)/sizeof(common_regs[0]))
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115
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116 typedef struct {
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117 u8 clock_chip_type;
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118 u8 struct_size;
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119 u8 accelerator_entry;
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120 u8 VGA_entry;
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121 u16 VGA_table_offset;
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122 u16 POST_table_offset;
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123 u16 XCLK;
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124 u16 MCLK;
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125 u8 num_PLL_blocks;
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126 u8 size_PLL_blocks;
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127 u16 PCLK_ref_freq;
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128 u16 PCLK_ref_divider;
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129 u32 PCLK_min_freq;
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130 u32 PCLK_max_freq;
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131 u16 MCLK_ref_freq;
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132 u16 MCLK_ref_divider;
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133 u32 MCLK_min_freq;
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134 u32 MCLK_max_freq;
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135 u16 XCLK_ref_freq;
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136 u16 XCLK_ref_divider;
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137 u32 XCLK_min_freq;
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138 u32 XCLK_max_freq;
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139 } __attribute__ ((packed)) PLL_BLOCK;
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140
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141
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142 struct pll_info {
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143 int ppll_max;
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144 int ppll_min;
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145 int xclk;
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146 int ref_div;
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147 int ref_clk;
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148 };
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149
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150
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151 struct ram_info {
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152 int ml;
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153 int mb;
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154 int trcd;
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155 int trp;
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156 int twr;
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157 int cl;
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158 int tr2w;
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159 int loop_latency;
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160 int rloop;
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161 };
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162
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163
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164 struct radeon_regs {
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165 u32 crtc_h_total_disp;
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166 u32 crtc_h_sync_strt_wid;
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167 u32 crtc_v_total_disp;
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168 u32 crtc_v_sync_strt_wid;
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169 u32 crtc_pitch;
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170 u32 flags;
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171 u32 pix_clock;
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172 int xres, yres;
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173 int bpp;
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174 u32 crtc_gen_cntl;
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175 u32 crtc_ext_cntl;
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176 u32 dac_cntl;
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177 u32 dda_config;
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178 u32 dda_on_off;
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179 u32 ppll_div_3;
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180 u32 ppll_ref_div;
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181 };
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182
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183
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184 struct radeonfb_info {
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185 struct fb_info info;
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186
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187 struct radeon_regs state;
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188 struct radeon_regs init_state;
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189
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190 char name[14];
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191 char ram_type[12];
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192
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193 u32 mmio_base_phys;
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194 u32 fb_base_phys;
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195
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196 u32 mmio_base;
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197 u32 fb_base;
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198
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199 struct pci_dev *pdev;
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200
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201 struct display disp;
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202 int currcon;
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203 struct display *currcon_display;
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204
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205 struct { u8 red, green, blue, pad; } palette[256];
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206
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207 int chipset;
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208 int video_ram;
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209 u8 rev;
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210 int pitch, bpp, depth;
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211 int xres, yres, pixclock;
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212
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213 u32 dp_gui_master_cntl;
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214
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215 struct pll_info pll;
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216 int pll_output_freq, post_div, fb_div;
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217
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218 struct ram_info ram;
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219
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220 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
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221 union {
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222 #if defined(FBCON_HAS_CFB16)
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223 u_int16_t cfb16[16];
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224 #endif
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225 #if defined(FBCON_HAS_CFB32)
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226 u_int32_t cfb32[16];
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227 #endif
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228 } con_cmap;
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229 #endif
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230 };
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231
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232
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233 static struct fb_var_screeninfo radeonfb_default_var = {
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234 640, 480, 640, 480, 0, 0, 8, 0,
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235 {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
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236 0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2,
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237 0, FB_VMODE_NONINTERLACED
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238 };
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239
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240
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241 /*
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242 * IO macros
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243 */
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244
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245 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
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246 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
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247 #define INREG(addr) readl((rinfo->mmio_base)+addr)
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248 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
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249
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250 #define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \
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251 OUTREG(CLOCK_CNTL_DATA, val)
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252 #define OUTPLLP(addr,val,mask) \
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253 do { \
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254 unsigned int _tmp = INPLL(addr); \
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255 _tmp &= (mask); \
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256 _tmp |= (val); \
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257 OUTPLL(addr, _tmp); \
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258 } while (0)
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259
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260 #define OUTREGP(addr,val,mask) \
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261 do { \
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262 unsigned int _tmp = INREG(addr); \
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263 _tmp &= (mask); \
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264 _tmp |= (val); \
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265 OUTREG(addr, _tmp); \
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266 } while (0)
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267
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268
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269 static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
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270 {
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271 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f);
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272 return (INREG(CLOCK_CNTL_DATA));
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273 }
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274
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275 #define INPLL(addr) _INPLL(rinfo, addr)
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276
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277
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278 /*
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279 * 2D engine routines
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280 */
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281
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282 static __inline__ void radeon_engine_flush (struct radeonfb_info *rinfo)
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283 {
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284 int i;
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285
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286 /* initiate flush */
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287 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
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288 ~RB2D_DC_FLUSH_ALL);
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289
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290 for (i=0; i < 2000000; i++) {
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291 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
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292 break;
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293 }
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294 }
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295
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296
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297 static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
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298 {
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299 int i;
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300
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301 for (i=0; i<2000000; i++)
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302 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
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303 return;
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304 }
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305
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306
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307 static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo)
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308 {
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309 int i;
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310
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311 /* ensure FIFO is empty before waiting for idle */
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312 _radeon_fifo_wait (rinfo, 64);
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313
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314 for (i=0; i<2000000; i++) {
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315 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
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316 radeon_engine_flush (rinfo);
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317 return;
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318 }
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319 }
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320 }
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321
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322
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323 #define radeon_engine_idle() _radeon_engine_idle(rinfo)
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324 #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
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325
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326
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327
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328 /*
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329 * helper routines
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330 */
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331
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332 static __inline__ u32 radeon_get_dstbpp(u16 depth)
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333 {
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334 switch (depth) {
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335 case 8:
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336 return DST_8BPP;
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337 case 15:
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338 return DST_15BPP;
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339 case 16:
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340 return DST_16BPP;
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341 case 32:
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342 return DST_32BPP;
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343 default:
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344 return 0;
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345 }
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346 }
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347
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348
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349 static void _radeon_engine_reset(struct radeonfb_info *rinfo)
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350 {
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351 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
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352
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353 radeon_engine_flush (rinfo);
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354
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355 clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
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356 mclk_cntl = INPLL(MCLK_CNTL);
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357
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358 OUTPLL(MCLK_CNTL, (mclk_cntl |
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359 FORCEON_MCLKA |
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360 FORCEON_MCLKB |
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361 FORCEON_YCLKA |
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362 FORCEON_YCLKB |
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363 FORCEON_MC |
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364 FORCEON_AIC));
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365 rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
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366
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367 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
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368 SOFT_RESET_CP |
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369 SOFT_RESET_HI |
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370 SOFT_RESET_SE |
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371 SOFT_RESET_RE |
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372 SOFT_RESET_PP |
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373 SOFT_RESET_E2 |
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374 SOFT_RESET_RB |
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375 SOFT_RESET_HDP);
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376 INREG(RBBM_SOFT_RESET);
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377 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
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378 ~(SOFT_RESET_CP |
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379 SOFT_RESET_HI |
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380 SOFT_RESET_SE |
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381 SOFT_RESET_RE |
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382 SOFT_RESET_PP |
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383 SOFT_RESET_E2 |
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384 SOFT_RESET_RB |
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385 SOFT_RESET_HDP));
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386 INREG(RBBM_SOFT_RESET);
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387
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388 OUTPLL(MCLK_CNTL, mclk_cntl);
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389 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
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390 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
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391
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392 return;
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393 }
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394
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395 #define radeon_engine_reset() _radeon_engine_reset(rinfo)
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396
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397
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398 static __inline__ u8 radeon_get_post_div_bitval(int post_div)
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399 {
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400 switch (post_div) {
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401 case 1:
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402 return 0x00;
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403 case 2:
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404 return 0x01;
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405 case 3:
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406 return 0x04;
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407 case 4:
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408 return 0x02;
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409 case 6:
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410 return 0x06;
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411 case 8:
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412 return 0x03;
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413 case 12:
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414 return 0x07;
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415 default:
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416 return 0x02;
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417 }
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418 }
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419
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420
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421
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422 static __inline__ int round_div(int num, int den)
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423 {
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424 return (num + (den / 2)) / den;
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425 }
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426
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427
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428
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429 static __inline__ int min_bits_req(int val)
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430 {
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431 int bits_req = 0;
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432
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433 if (val == 0)
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434 bits_req = 1;
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435
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436 while (val) {
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437 val >>= 1;
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438 bits_req++;
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439 }
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440
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441 return (bits_req);
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442 }
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443
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444
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445 static __inline__ int _max(int val1, int val2)
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446 {
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447 if (val1 >= val2)
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448 return val1;
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449 else
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450 return val2;
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451 }
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452
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453
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454
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455 /*
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456 * globals
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457 */
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458
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459 static char fontname[40] __initdata;
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460 static char *mode_option __initdata;
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461 static char noaccel __initdata = 0;
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462
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463 #ifdef FBCON_HAS_CFB8
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464 static struct display_switch fbcon_radeon8;
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465 #endif
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466
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467
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468 /*
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469 * prototypes
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470 */
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471
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472 static int radeonfb_get_fix (struct fb_fix_screeninfo *fix, int con,
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473 struct fb_info *info);
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474 static int radeonfb_get_var (struct fb_var_screeninfo *var, int con,
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475 struct fb_info *info);
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476 static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
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477 struct fb_info *info);
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478 static int radeonfb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
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479 struct fb_info *info);
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480 static int radeonfb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
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481 struct fb_info *info);
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482 static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con,
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483 struct fb_info *info);
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484 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
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485 unsigned long arg, int con, struct fb_info *info);
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486 static int radeonfb_switch (int con, struct fb_info *info);
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487 static int radeonfb_updatevar (int con, struct fb_info *info);
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488 static void radeonfb_blank (int blank, struct fb_info *info);
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489 static int radeon_get_cmap_len (const struct fb_var_screeninfo *var);
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490 static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green,
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491 unsigned *blue, unsigned *transp,
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492 struct fb_info *info);
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493 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
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494 unsigned blue, unsigned transp, struct fb_info *info);
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495 static void radeon_set_dispsw (struct radeonfb_info *rinfo);
|
|
496 static void radeon_save_state (struct radeonfb_info *rinfo,
|
|
497 struct radeon_regs *save);
|
|
498 static void radeon_engine_init (struct radeonfb_info *rinfo);
|
|
499 static void radeon_load_video_mode (struct radeonfb_info *rinfo,
|
|
500 struct fb_var_screeninfo *mode);
|
|
501 static void radeon_write_mode (struct radeonfb_info *rinfo,
|
|
502 struct radeon_regs *mode);
|
|
503 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo);
|
|
504 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo);
|
|
505 static int radeon_init_disp_var (struct radeonfb_info *rinfo);
|
|
506 static int radeonfb_pci_register (struct pci_dev *pdev,
|
|
507 const struct pci_device_id *ent);
|
|
508 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev);
|
|
509 static char *radeon_find_rom(struct radeonfb_info *rinfo);
|
|
510 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg);
|
|
511
|
|
512
|
|
513 static struct fb_ops radeon_fb_ops = {
|
|
514 fb_get_fix: radeonfb_get_fix,
|
|
515 fb_get_var: radeonfb_get_var,
|
|
516 fb_set_var: radeonfb_set_var,
|
|
517 fb_get_cmap: radeonfb_get_cmap,
|
|
518 fb_set_cmap: radeonfb_set_cmap,
|
|
519 fb_pan_display: radeonfb_pan_display,
|
|
520 fb_ioctl: radeonfb_ioctl,
|
|
521 };
|
|
522
|
|
523
|
|
524 static struct pci_driver radeonfb_driver = {
|
|
525 name: "radeonfb",
|
|
526 id_table: radeonfb_pci_table,
|
|
527 probe: radeonfb_pci_register,
|
|
528 remove: radeonfb_pci_unregister,
|
|
529 };
|
|
530
|
|
531
|
|
532 int __init radeonfb_init (void)
|
|
533 {
|
|
534 return pci_module_init (&radeonfb_driver);
|
|
535 }
|
|
536
|
|
537
|
|
538 void __exit radeonfb_exit (void)
|
|
539 {
|
|
540 pci_unregister_driver (&radeonfb_driver);
|
|
541 }
|
|
542
|
|
543
|
|
544 int __init radeonfb_setup (char *options)
|
|
545 {
|
|
546 char *this_opt;
|
|
547
|
|
548 if (!options || !*options)
|
|
549 return 0;
|
|
550
|
|
551 for (this_opt = strtok (options, ","); this_opt;
|
|
552 this_opt = strtok (NULL, ",")) {
|
|
553 if (!strncmp (this_opt, "font:", 5)) {
|
|
554 char *p;
|
|
555 int i;
|
|
556
|
|
557 p = this_opt + 5;
|
|
558 for (i=0; i<sizeof (fontname) - 1; i++)
|
|
559 if (!*p || *p == ' ' || *p == ',')
|
|
560 break;
|
|
561 memcpy(fontname, this_opt + 5, i);
|
|
562 } else if (!strncmp(this_opt, "noaccel", 7)) {
|
|
563 noaccel = 1;
|
|
564 }
|
|
565 else mode_option = this_opt;
|
|
566 }
|
|
567
|
|
568 return 0;
|
|
569 }
|
|
570
|
|
571 #ifdef MODULE
|
|
572 module_init(radeonfb_init);
|
|
573 module_exit(radeonfb_exit);
|
|
574 #endif
|
|
575
|
|
576
|
|
577 MODULE_AUTHOR("Ani Joshi");
|
|
578 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
|
|
579
|
|
580
|
|
581
|
|
582 static int radeonfb_pci_register (struct pci_dev *pdev,
|
|
583 const struct pci_device_id *ent)
|
|
584 {
|
|
585 struct radeonfb_info *rinfo;
|
|
586 u32 tmp;
|
|
587 int i, j;
|
|
588 char *bios_seg = NULL;
|
|
589
|
|
590 rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL);
|
|
591 if (!rinfo) {
|
|
592 printk ("radeonfb: could not allocate memory\n");
|
|
593 return -ENODEV;
|
|
594 }
|
|
595
|
|
596 memset (rinfo, 0, sizeof (struct radeonfb_info));
|
|
597
|
|
598 /* enable device */
|
|
599 {
|
|
600 int err;
|
|
601
|
|
602 if ((err = pci_enable_device(pdev))) {
|
|
603 printk("radeonfb: cannot enable device\n");
|
|
604 kfree (rinfo);
|
|
605 return -ENODEV;
|
|
606 }
|
|
607 }
|
|
608
|
|
609 /* set base addrs */
|
|
610 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
|
|
611 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
|
|
612
|
|
613 /* request the mem regions */
|
|
614 if (!request_mem_region (rinfo->fb_base_phys,
|
|
615 pci_resource_len(pdev, 0), "radeonfb")) {
|
|
616 printk ("radeonfb: cannot reserve FB region\n");
|
|
617 kfree (rinfo);
|
|
618 return -ENODEV;
|
|
619 }
|
|
620
|
|
621 if (!request_mem_region (rinfo->mmio_base_phys,
|
|
622 pci_resource_len(pdev, 2), "radeonfb")) {
|
|
623 printk ("radeonfb: cannot reserve MMIO region\n");
|
|
624 release_mem_region (rinfo->fb_base_phys,
|
|
625 pci_resource_len(pdev, 0));
|
|
626 kfree (rinfo);
|
|
627 return -ENODEV;
|
|
628 }
|
|
629
|
|
630 /* map the regions */
|
|
631 rinfo->mmio_base = (u32) ioremap (rinfo->mmio_base_phys,
|
|
632 RADEON_REGSIZE);
|
|
633 if (!rinfo->mmio_base) {
|
|
634 printk ("radeonfb: cannot map MMIO\n");
|
|
635 release_mem_region (rinfo->mmio_base_phys,
|
|
636 pci_resource_len(pdev, 2));
|
|
637 release_mem_region (rinfo->fb_base_phys,
|
|
638 pci_resource_len(pdev, 0));
|
|
639 kfree (rinfo);
|
|
640 return -ENODEV;
|
|
641 }
|
|
642
|
|
643 /* chipset */
|
|
644 switch (pdev->device) {
|
|
645 case PCI_DEVICE_ID_RADEON_QD:
|
|
646 strcpy(rinfo->name, "Radeon QD ");
|
|
647 break;
|
|
648 case PCI_DEVICE_ID_RADEON_QE:
|
|
649 strcpy(rinfo->name, "Radeon QE ");
|
|
650 break;
|
|
651 case PCI_DEVICE_ID_RADEON_QF:
|
|
652 strcpy(rinfo->name, "Radeon QF ");
|
|
653 break;
|
|
654 case PCI_DEVICE_ID_RADEON_QG:
|
|
655 strcpy(rinfo->name, "Radeon QG ");
|
|
656 break;
|
1913
|
657 case PCI_DEVICE_ID_RADEON_QY:
|
|
658 strcpy(rinfo->name, "Radeon VE QY");
|
|
659 break;
|
|
660 case PCI_DEVICE_ID_RADEON_QZ:
|
|
661 strcpy(rinfo->name, "Radeon VE QZ");
|
1912
|
662 break;
|
1911
|
663 default:
|
|
664 return -ENODEV;
|
|
665 }
|
|
666
|
|
667 /* framebuffer size */
|
|
668 tmp = INREG(CONFIG_MEMSIZE);
|
|
669
|
|
670 /* mem size is bits [28:0], mask off the rest */
|
|
671 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
|
|
672
|
|
673 /* ram type */
|
|
674 tmp = INREG(MEM_SDRAM_MODE_REG);
|
|
675 switch ((MEM_CFG_TYPE & tmp) >> 30) {
|
|
676 case 0:
|
|
677 /* SDR SGRAM (2:1) */
|
|
678 strcpy(rinfo->ram_type, "SDR SGRAM");
|
|
679 rinfo->ram.ml = 4;
|
|
680 rinfo->ram.mb = 4;
|
|
681 rinfo->ram.trcd = 1;
|
|
682 rinfo->ram.trp = 2;
|
|
683 rinfo->ram.twr = 1;
|
|
684 rinfo->ram.cl = 2;
|
|
685 rinfo->ram.loop_latency = 16;
|
|
686 rinfo->ram.rloop = 16;
|
|
687
|
|
688 break;
|
|
689 case 1:
|
|
690 /* DDR SGRAM */
|
|
691 strcpy(rinfo->ram_type, "DDR SGRAM");
|
|
692 rinfo->ram.ml = 4;
|
|
693 rinfo->ram.mb = 4;
|
|
694 rinfo->ram.trcd = 3;
|
|
695 rinfo->ram.trp = 3;
|
|
696 rinfo->ram.twr = 2;
|
|
697 rinfo->ram.cl = 3;
|
|
698 rinfo->ram.tr2w = 1;
|
|
699 rinfo->ram.loop_latency = 16;
|
|
700 rinfo->ram.rloop = 16;
|
|
701
|
|
702 break;
|
|
703 default:
|
|
704 /* 64-bit SDR SGRAM */
|
|
705 strcpy(rinfo->ram_type, "SDR SGRAM 64");
|
|
706 rinfo->ram.ml = 4;
|
|
707 rinfo->ram.mb = 8;
|
|
708 rinfo->ram.trcd = 3;
|
|
709 rinfo->ram.trp = 3;
|
|
710 rinfo->ram.twr = 1;
|
|
711 rinfo->ram.cl = 3;
|
|
712 rinfo->ram.tr2w = 1;
|
|
713 rinfo->ram.loop_latency = 17;
|
|
714 rinfo->ram.rloop = 17;
|
|
715
|
|
716 break;
|
|
717 }
|
|
718
|
|
719 bios_seg = radeon_find_rom(rinfo);
|
|
720 radeon_get_pllinfo(rinfo, bios_seg);
|
|
721
|
|
722 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d\n",
|
|
723 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
|
|
724
|
|
725 RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
|
|
726
|
|
727 rinfo->fb_base = (u32) ioremap (rinfo->fb_base_phys,
|
|
728 rinfo->video_ram);
|
|
729 if (!rinfo->fb_base) {
|
|
730 printk ("radeonfb: cannot map FB\n");
|
|
731 iounmap ((void*)rinfo->mmio_base);
|
|
732 release_mem_region (rinfo->mmio_base_phys,
|
|
733 pci_resource_len(pdev, 2));
|
|
734 release_mem_region (rinfo->fb_base_phys,
|
|
735 pci_resource_len(pdev, 0));
|
|
736 kfree (rinfo);
|
|
737 return -ENODEV;
|
|
738 }
|
|
739
|
|
740 /* XXX turn off accel for now, blts aren't working right */
|
|
741 noaccel = 1;
|
|
742
|
|
743 /* set all the vital stuff */
|
|
744 radeon_set_fbinfo (rinfo);
|
|
745
|
|
746 /* save current mode regs before we switch into the new one
|
|
747 * so we can restore this upon __exit
|
|
748 */
|
|
749 radeon_save_state (rinfo, &rinfo->init_state);
|
|
750
|
|
751 /* init palette */
|
|
752 for (i=0; i<16; i++) {
|
|
753 j = color_table[i];
|
|
754 rinfo->palette[i].red = default_red[j];
|
|
755 rinfo->palette[i].green = default_grn[j];
|
|
756 rinfo->palette[i].blue = default_blu[j];
|
|
757 }
|
|
758
|
|
759 pdev->driver_data = rinfo;
|
|
760
|
|
761 if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
|
|
762 printk ("radeonfb: could not register framebuffer\n");
|
|
763 iounmap ((void*)rinfo->fb_base);
|
|
764 iounmap ((void*)rinfo->mmio_base);
|
|
765 release_mem_region (rinfo->mmio_base_phys,
|
|
766 pci_resource_len(pdev, 2));
|
|
767 release_mem_region (rinfo->fb_base_phys,
|
|
768 pci_resource_len(pdev, 0));
|
|
769 kfree (rinfo);
|
|
770 return -ENODEV;
|
|
771 }
|
|
772
|
|
773 if (!noaccel) {
|
|
774 /* initialize the engine */
|
|
775 radeon_engine_init (rinfo);
|
|
776 }
|
|
777
|
1912
|
778 printk ("radeonfb: ATI %s %d MB\n", rinfo->name,
|
1911
|
779 (rinfo->video_ram/(1024*1024)));
|
|
780
|
|
781 return 0;
|
|
782 }
|
|
783
|
|
784
|
|
785
|
|
786 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
|
|
787 {
|
|
788 struct radeonfb_info *rinfo = pdev->driver_data;
|
|
789
|
|
790 if (!rinfo)
|
|
791 return;
|
|
792
|
|
793 /* restore original state */
|
|
794 radeon_write_mode (rinfo, &rinfo->init_state);
|
|
795
|
|
796 unregister_framebuffer ((struct fb_info *) rinfo);
|
|
797
|
|
798 iounmap ((void*)rinfo->mmio_base);
|
|
799 iounmap ((void*)rinfo->fb_base);
|
|
800
|
|
801 release_mem_region (rinfo->mmio_base_phys,
|
|
802 pci_resource_len(pdev, 2));
|
|
803 release_mem_region (rinfo->fb_base_phys,
|
|
804 pci_resource_len(pdev, 0));
|
|
805
|
|
806 kfree (rinfo);
|
|
807 }
|
|
808
|
|
809
|
|
810
|
|
811 static char *radeon_find_rom(struct radeonfb_info *rinfo)
|
|
812 {
|
|
813 u32 segstart;
|
|
814 char *rom_base;
|
|
815 char *rom;
|
|
816 int stage;
|
|
817 int i;
|
|
818 char aty_rom_sig[] = "761295520";
|
|
819 char radeon_sig[] = "RG6";
|
|
820
|
|
821 #if defined(__i386__)
|
|
822 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
|
|
823 stage = 1;
|
|
824
|
|
825 rom_base = (char *)ioremap(segstart, 0x1000);
|
|
826
|
|
827 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
|
|
828 stage = 2;
|
|
829
|
|
830
|
|
831 if (stage != 2) {
|
|
832 iounmap(rom_base);
|
|
833 continue;
|
|
834 }
|
|
835
|
|
836 rom = rom_base;
|
|
837
|
|
838 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
|
|
839 if (aty_rom_sig[0] == *rom)
|
|
840 if (strncmp(aty_rom_sig, rom,
|
|
841 strlen(aty_rom_sig)) == 0)
|
|
842 stage = 3;
|
|
843 rom++;
|
|
844 }
|
|
845 if (stage != 3) {
|
|
846 iounmap(rom_base);
|
|
847 continue;
|
|
848 }
|
|
849 rom = rom_base;
|
|
850
|
|
851 for (i = 0; (i < 512) && (stage != 4); i++) {
|
|
852 if (radeon_sig[0] == *rom)
|
|
853 if (strncmp(radeon_sig, rom,
|
|
854 strlen(radeon_sig)) == 0)
|
|
855 stage = 4;
|
|
856 rom++;
|
|
857 }
|
|
858 if (stage != 4) {
|
|
859 iounmap(rom_base);
|
|
860 continue;
|
|
861 }
|
|
862
|
|
863 return rom_base;
|
|
864 }
|
|
865 #endif
|
|
866 return NULL;
|
|
867 }
|
|
868
|
|
869
|
|
870
|
|
871 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg)
|
|
872 {
|
|
873 void *bios_header;
|
|
874 void *header_ptr;
|
|
875 u16 bios_header_offset, pll_info_offset;
|
|
876 PLL_BLOCK pll;
|
|
877
|
|
878 if (bios_seg) {
|
|
879 bios_header = bios_seg + 0x48L;
|
|
880 header_ptr = bios_header;
|
|
881
|
|
882 bios_header_offset = readw(header_ptr);
|
|
883 bios_header = bios_seg + bios_header_offset;
|
|
884 bios_header += 0x30;
|
|
885
|
|
886 header_ptr = bios_header;
|
|
887 pll_info_offset = readw(header_ptr);
|
|
888 header_ptr = bios_seg + pll_info_offset;
|
|
889
|
|
890 memcpy_fromio(&pll, header_ptr, 50);
|
|
891
|
|
892 rinfo->pll.xclk = (u32)pll.XCLK;
|
|
893 rinfo->pll.ref_clk = (u32)pll.PCLK_ref_freq;
|
|
894 rinfo->pll.ref_div = (u32)pll.PCLK_ref_divider;
|
|
895 rinfo->pll.ppll_min = pll.PCLK_min_freq;
|
|
896 rinfo->pll.ppll_max = pll.PCLK_max_freq;
|
|
897 } else {
|
|
898 /* no BIOS or BIOS not found, use defaults */
|
|
899
|
|
900 rinfo->pll.ppll_max = 35000;
|
|
901 rinfo->pll.ppll_min = 12000;
|
|
902 rinfo->pll.xclk = 16600;
|
|
903 rinfo->pll.ref_div = 67;
|
|
904 rinfo->pll.ref_clk = 2700;
|
|
905 }
|
|
906 }
|
|
907
|
|
908 static void radeon_engine_init (struct radeonfb_info *rinfo)
|
|
909 {
|
|
910 u32 temp;
|
|
911
|
|
912 /* disable 3D engine */
|
|
913 OUTREG(RB3D_CNTL, 0);
|
|
914
|
|
915 radeon_engine_reset ();
|
|
916
|
|
917 radeon_fifo_wait (1);
|
|
918 OUTREG(DSTCACHE_MODE, 0);
|
|
919
|
|
920 /* XXX */
|
|
921 rinfo->pitch = ((rinfo->xres * (rinfo->depth / 8) + 0x3f)) >> 6;
|
|
922
|
|
923 radeon_fifo_wait (1);
|
|
924 temp = INREG(DEFAULT_PITCH_OFFSET);
|
|
925 OUTREG(DEFAULT_PITCH_OFFSET, ((temp & 0xc0000000) |
|
|
926 (rinfo->pitch << 0x16)));
|
|
927
|
|
928 radeon_fifo_wait (1);
|
|
929 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
|
|
930
|
|
931 radeon_fifo_wait (1);
|
|
932 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
|
|
933 DEFAULT_SC_BOTTOM_MAX));
|
|
934
|
|
935 temp = radeon_get_dstbpp(rinfo->depth);
|
|
936 rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
|
|
937 radeon_fifo_wait (1);
|
|
938 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
939 GMC_BRUSH_SOLID_COLOR |
|
|
940 GMC_SRC_DATATYPE_COLOR));
|
|
941
|
|
942 radeon_fifo_wait (7);
|
|
943
|
|
944 /* clear line drawing regs */
|
|
945 OUTREG(DST_LINE_START, 0);
|
|
946 OUTREG(DST_LINE_END, 0);
|
|
947
|
|
948 /* set brush color regs */
|
|
949 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
|
|
950 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
|
|
951
|
|
952 /* set source color regs */
|
|
953 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
|
|
954 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
|
|
955
|
|
956 /* default write mask */
|
|
957 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
958
|
|
959 radeon_engine_idle ();
|
|
960 }
|
|
961
|
|
962
|
|
963
|
|
964 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
|
|
965 {
|
|
966 struct fb_info *info;
|
|
967
|
|
968 info = &rinfo->info;
|
|
969
|
|
970 strcpy (info->modename, rinfo->name);
|
|
971 info->node = -1;
|
|
972 info->flags = FBINFO_FLAG_DEFAULT;
|
|
973 info->fbops = &radeon_fb_ops;
|
|
974 info->display_fg = NULL;
|
|
975 strncpy (info->fontname, fontname, sizeof (info->fontname));
|
|
976 info->fontname[sizeof (info->fontname) - 1] = 0;
|
|
977 info->changevar = NULL;
|
|
978 info->switch_con = radeonfb_switch;
|
|
979 info->updatevar = radeonfb_updatevar;
|
|
980 info->blank = radeonfb_blank;
|
|
981
|
|
982 if (radeon_init_disp (rinfo) < 0)
|
|
983 return -1;
|
|
984
|
|
985 return 0;
|
|
986 }
|
|
987
|
|
988
|
|
989
|
|
990 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo)
|
|
991 {
|
|
992 struct fb_info *info;
|
|
993 struct display *disp;
|
|
994
|
|
995 info = &rinfo->info;
|
|
996 disp = &rinfo->disp;
|
|
997
|
|
998 disp->var = radeonfb_default_var;
|
|
999 info->disp = disp;
|
|
1000
|
|
1001 radeon_set_dispsw (rinfo);
|
|
1002
|
|
1003 if (noaccel)
|
|
1004 disp->scrollmode = SCROLL_YREDRAW;
|
|
1005 else
|
|
1006 disp->scrollmode = 0;
|
|
1007
|
|
1008 rinfo->currcon_display = disp;
|
|
1009
|
|
1010 if ((radeon_init_disp_var (rinfo)) < 0)
|
|
1011 return -1;
|
|
1012
|
|
1013 return 0;
|
|
1014 }
|
|
1015
|
|
1016
|
|
1017
|
|
1018 static int radeon_init_disp_var (struct radeonfb_info *rinfo)
|
|
1019 {
|
|
1020 #ifndef MODULE
|
|
1021 if (mode_option)
|
|
1022 fb_find_mode (&rinfo->disp.var, &rinfo->info, mode_option,
|
|
1023 NULL, 0, NULL, 8);
|
|
1024 else
|
|
1025 #endif
|
|
1026 fb_find_mode (&rinfo->disp.var, &rinfo->info, "640x480-8@60",
|
|
1027 NULL, 0, NULL, 0);
|
|
1028
|
|
1029 if (noaccel)
|
|
1030 rinfo->disp.var.accel_flags &= ~FB_ACCELF_TEXT;
|
|
1031 else
|
|
1032 rinfo->disp.var.accel_flags |= FB_ACCELF_TEXT;
|
|
1033
|
|
1034 return 0;
|
|
1035 }
|
|
1036
|
|
1037
|
|
1038
|
|
1039 static void radeon_set_dispsw (struct radeonfb_info *rinfo)
|
|
1040 {
|
|
1041 struct display *disp = &rinfo->disp;
|
|
1042 int accel;
|
|
1043
|
|
1044 accel = disp->var.accel_flags & FB_ACCELF_TEXT;
|
|
1045
|
|
1046 disp->dispsw_data = NULL;
|
|
1047
|
|
1048 disp->screen_base = (char*)rinfo->fb_base;
|
|
1049 disp->type = FB_TYPE_PACKED_PIXELS;
|
|
1050 disp->type_aux = 0;
|
|
1051 disp->ypanstep = 1;
|
|
1052 disp->ywrapstep = 0;
|
|
1053 disp->can_soft_blank = 1;
|
|
1054 disp->inverse = 0;
|
|
1055
|
|
1056 rinfo->depth = disp->var.bits_per_pixel;
|
|
1057 switch (disp->var.bits_per_pixel) {
|
|
1058 #ifdef FBCON_HAS_CFB8
|
|
1059 case 8:
|
|
1060 disp->dispsw = accel ? &fbcon_radeon8 : &fbcon_cfb8;
|
|
1061 disp->visual = FB_VISUAL_PSEUDOCOLOR;
|
|
1062 disp->line_length = disp->var.xres_virtual;
|
|
1063 break;
|
|
1064 #endif
|
|
1065 #ifdef FBCON_HAS_CFB16
|
|
1066 case 16:
|
|
1067 disp->dispsw = &fbcon_cfb16;
|
|
1068 disp->dispsw_data = &rinfo->con_cmap.cfb16;
|
|
1069 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1070 disp->line_length = disp->var.xres_virtual * 2;
|
|
1071 break;
|
|
1072 #endif
|
|
1073 #ifdef FBCON_HAS_CFB32
|
|
1074 case 32:
|
|
1075 disp->dispsw = &fbcon_cfb32;
|
|
1076 disp->dispsw_data = &rinfo->con_cmap.cfb32;
|
|
1077 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1078 disp->line_length = disp->var.xres_virtual * 4;
|
|
1079 break;
|
|
1080 #endif
|
|
1081 default:
|
|
1082 printk ("radeonfb: setting fbcon_dummy renderer\n");
|
|
1083 disp->dispsw = &fbcon_dummy;
|
|
1084 }
|
|
1085
|
|
1086 return;
|
|
1087 }
|
|
1088
|
|
1089
|
|
1090
|
|
1091 /*
|
|
1092 * fb ops
|
|
1093 */
|
|
1094
|
|
1095 static int radeonfb_get_fix (struct fb_fix_screeninfo *fix, int con,
|
|
1096 struct fb_info *info)
|
|
1097 {
|
|
1098 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1099 struct display *disp;
|
|
1100
|
|
1101 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1102
|
|
1103 memset (fix, 0, sizeof (struct fb_fix_screeninfo));
|
|
1104 strcpy (fix->id, rinfo->name);
|
|
1105
|
|
1106 fix->smem_start = rinfo->fb_base_phys;
|
|
1107 fix->smem_len = rinfo->video_ram;
|
|
1108
|
|
1109 fix->type = disp->type;
|
|
1110 fix->type_aux = disp->type_aux;
|
|
1111 fix->visual = disp->visual;
|
|
1112
|
|
1113 fix->xpanstep = 1;
|
|
1114 fix->ypanstep = 1;
|
|
1115 fix->ywrapstep = 0;
|
|
1116
|
|
1117 fix->line_length = disp->line_length;
|
|
1118
|
|
1119 fix->mmio_start = rinfo->mmio_base_phys;
|
|
1120 fix->mmio_len = RADEON_REGSIZE;
|
|
1121 if (noaccel)
|
|
1122 fix->accel = FB_ACCEL_NONE;
|
|
1123 else
|
|
1124 fix->accel = 40; /* XXX */
|
|
1125
|
|
1126 return 0;
|
|
1127 }
|
|
1128
|
|
1129
|
|
1130
|
|
1131 static int radeonfb_get_var (struct fb_var_screeninfo *var, int con,
|
|
1132 struct fb_info *info)
|
|
1133 {
|
|
1134 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1135
|
|
1136 *var = (con < 0) ? rinfo->disp.var : fb_display[con].var;
|
|
1137
|
|
1138 return 0;
|
|
1139 }
|
|
1140
|
|
1141
|
|
1142
|
|
1143 static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
|
|
1144 struct fb_info *info)
|
|
1145 {
|
|
1146 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1147 struct display *disp;
|
|
1148 struct fb_var_screeninfo v;
|
|
1149 int nom, den, i, accel;
|
|
1150 unsigned chgvar = 0;
|
|
1151 static struct {
|
|
1152 int xres, yres;
|
|
1153 } modes[] = {
|
|
1154 {
|
|
1155 1600, 1280}, {
|
|
1156 1280, 1024}, {
|
|
1157 1024, 768}, {
|
|
1158 800, 600}, {
|
|
1159 640, 480}, {
|
|
1160 -1, -1}
|
|
1161 };
|
|
1162
|
|
1163 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1164
|
|
1165 accel = var->accel_flags & FB_ACCELF_TEXT;
|
|
1166
|
|
1167 if (con >= 0) {
|
|
1168 chgvar = ((disp->var.xres != var->xres) ||
|
|
1169 (disp->var.yres != var->yres) ||
|
|
1170 (disp->var.xres_virtual != var->xres_virtual) ||
|
|
1171 (disp->var.yres_virtual != var->yres_virtual) ||
|
|
1172 memcmp (&disp->var.red, &var->red, sizeof (var->red)) ||
|
|
1173 memcmp (&disp->var.green, &var->green, sizeof (var->green)) ||
|
|
1174 memcmp (&disp->var.blue, &var->blue, sizeof (var->blue)));
|
|
1175 }
|
|
1176
|
|
1177 memcpy (&v, var, sizeof (v));
|
|
1178
|
|
1179 switch (v.bits_per_pixel) {
|
|
1180 #ifdef FBCON_HAS_CFB8
|
|
1181 case 8:
|
|
1182 v.bits_per_pixel = 8;
|
|
1183 disp->dispsw = accel ? &fbcon_radeon8 : &fbcon_cfb8;
|
|
1184 nom = den = 1;
|
|
1185 disp->line_length = v.xres_virtual;
|
|
1186 disp->visual = FB_VISUAL_PSEUDOCOLOR;
|
|
1187 v.red.offset = v.green.offset = v.blue.offset = 0;
|
|
1188 v.red.length = v.green.length = v.blue.length = 8;
|
|
1189 break;
|
|
1190 #endif
|
|
1191
|
|
1192 #ifdef FBCON_HAS_CFB16
|
|
1193 case 16:
|
|
1194 v.bits_per_pixel = 16;
|
|
1195 disp->dispsw = &fbcon_cfb16;
|
|
1196 disp->dispsw_data = &rinfo->con_cmap.cfb16;
|
|
1197 nom = 2;
|
|
1198 den = 1;
|
|
1199 disp->line_length = v.xres_virtual * 2;
|
|
1200 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1201 v.red.offset = 11;
|
|
1202 v.green.offset = 5;
|
|
1203 v.blue.offset = 0;
|
|
1204 v.red.length = 5;
|
|
1205 v.green.length = 6;
|
|
1206 v.blue.length = 5;
|
|
1207 break;
|
|
1208 #endif
|
|
1209
|
|
1210 #ifdef FBCON_HAS_CFB32
|
|
1211 case 32:
|
|
1212 v.bits_per_pixel = 32;
|
|
1213 disp->dispsw = &fbcon_cfb32;
|
|
1214 disp->dispsw_data = rinfo->con_cmap.cfb32;
|
|
1215 nom = 4;
|
|
1216 den = 1;
|
|
1217 disp->line_length = v.xres_virtual * 4;
|
|
1218 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1219 v.red.offset = 16;
|
|
1220 v.green.offset = 8;
|
|
1221 v.blue.offset = 0;
|
|
1222 v.red.length = v.blue.length = v.green.length = 8;
|
|
1223 break;
|
|
1224 #endif
|
|
1225 default:
|
|
1226 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
|
|
1227 var->xres, var->yres, var->bits_per_pixel);
|
|
1228 return -EINVAL;
|
|
1229 }
|
|
1230
|
|
1231 if (v.xres * nom / den * v.yres > (rinfo->video_ram)) {
|
|
1232 printk ("radeonfb: mode %dx%dx%d rejected, not enough video ram\n",
|
|
1233 var->xres, var->yres, var->bits_per_pixel);
|
|
1234 return -EINVAL;
|
|
1235 }
|
|
1236
|
|
1237 if (v.xres_virtual == -1 && v.yres_virtual == -1) {
|
|
1238 printk ("radeonfb: using maximum available virtual resolution\n");
|
|
1239 for (i = 0; modes[i].xres != -1; i++) {
|
|
1240 if (modes[i].xres * nom / den * modes[i].yres < (rinfo->video_ram/2))
|
|
1241 break;
|
|
1242 }
|
|
1243 if (modes[i].xres == -1) {
|
|
1244 printk ("radeonfb: could not find a virtual res\n");
|
|
1245 return -EINVAL;
|
|
1246 }
|
|
1247 v.xres_virtual = modes[i].xres;
|
|
1248 v.yres_virtual = modes[i].yres;
|
|
1249
|
|
1250 printk ("radeonfb: virtual resolution set to maximum of %dx%d\n",
|
|
1251 v.xres_virtual, v.yres_virtual);
|
|
1252 }
|
|
1253
|
|
1254 if (v.xoffset < 0)
|
|
1255 v.xoffset = 0;
|
|
1256 if (v.yoffset < 0)
|
|
1257 v.yoffset = 0;
|
|
1258
|
|
1259 if (v.xoffset > v.xres_virtual - v.xres)
|
|
1260 v.xoffset = v.xres_virtual - v.xres - 1;
|
|
1261
|
|
1262 if (v.yoffset > v.yres_virtual - v.yres)
|
|
1263 v.yoffset = v.yres_virtual - v.yres - 1;
|
|
1264
|
|
1265 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
|
|
1266 v.transp.offset = v.transp.length =
|
|
1267 v.transp.msb_right = 0;
|
|
1268
|
|
1269 switch (v.activate & FB_ACTIVATE_MASK) {
|
|
1270 case FB_ACTIVATE_TEST:
|
|
1271 return 0;
|
|
1272 case FB_ACTIVATE_NXTOPEN:
|
|
1273 case FB_ACTIVATE_NOW:
|
|
1274 break;
|
|
1275 default:
|
|
1276 return -EINVAL;
|
|
1277 }
|
|
1278
|
|
1279 disp->type = FB_TYPE_PACKED_PIXELS;
|
|
1280
|
|
1281 memcpy (&disp->var, &v, sizeof (v));
|
|
1282
|
|
1283 radeon_load_video_mode (rinfo, &v);
|
|
1284
|
|
1285 if (chgvar && info && info->changevar)
|
|
1286 info->changevar (con);
|
|
1287
|
|
1288 return 0;
|
|
1289 }
|
|
1290
|
|
1291
|
|
1292
|
|
1293 static int radeonfb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
1294 struct fb_info *info)
|
|
1295 {
|
|
1296 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1297 struct display *disp;
|
|
1298
|
|
1299 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1300
|
|
1301 if (con == rinfo->currcon) {
|
|
1302 int rc = fb_get_cmap (cmap, kspc, radeon_getcolreg, info);
|
|
1303 return rc;
|
|
1304 } else if (disp->cmap.len)
|
|
1305 fb_copy_cmap (&disp->cmap, cmap, kspc ? 0 : 2);
|
|
1306 else
|
|
1307 fb_copy_cmap (fb_default_cmap (radeon_get_cmap_len (&disp->var)),
|
|
1308 cmap, kspc ? 0 : 2);
|
|
1309
|
|
1310 return 0;
|
|
1311 }
|
|
1312
|
|
1313
|
|
1314
|
|
1315 static int radeonfb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
1316 struct fb_info *info)
|
|
1317 {
|
|
1318 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1319 struct display *disp;
|
|
1320 unsigned int cmap_len;
|
|
1321
|
|
1322 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1323
|
|
1324 cmap_len = radeon_get_cmap_len (&disp->var);
|
|
1325 if (disp->cmap.len != cmap_len) {
|
|
1326 int err = fb_alloc_cmap (&disp->cmap, cmap_len, 0);
|
|
1327 if (err)
|
|
1328 return err;
|
|
1329 }
|
|
1330
|
|
1331 if (con == rinfo->currcon) {
|
|
1332 int rc = fb_set_cmap (cmap, kspc, radeon_setcolreg, info);
|
|
1333 return rc;
|
|
1334 } else
|
|
1335 fb_copy_cmap (cmap, &disp->cmap, kspc ? 0 : 1);
|
|
1336
|
|
1337 return 0;
|
|
1338 }
|
|
1339
|
|
1340
|
|
1341
|
|
1342 static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con,
|
|
1343 struct fb_info *info)
|
|
1344 {
|
|
1345 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1346 struct display *disp;
|
|
1347 unsigned int base;
|
|
1348
|
|
1349 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1350
|
|
1351 if (var->xoffset > (var->xres_virtual - var->xres))
|
|
1352 return -EINVAL;
|
|
1353 if (var->yoffset > (var->yres_virtual - var->yres))
|
|
1354 return -EINVAL;
|
|
1355
|
|
1356 if (var->vmode & FB_VMODE_YWRAP) {
|
|
1357 if (var->yoffset < 0 ||
|
|
1358 var->yoffset >= disp->var.yres_virtual ||
|
|
1359 var->xoffset )
|
|
1360 return -EINVAL;
|
|
1361 } else {
|
|
1362 if (var->xoffset + disp->var.xres > disp->var.xres_virtual ||
|
|
1363 var->yoffset + disp->var.yres > disp->var.yres_virtual)
|
|
1364 return -EINVAL;
|
|
1365 }
|
|
1366
|
|
1367 base = var->yoffset * disp->line_length + var->xoffset;
|
|
1368
|
|
1369 disp->var.xoffset = var->xoffset;
|
|
1370 disp->var.yoffset = var->yoffset;
|
|
1371
|
|
1372 if (var->vmode & FB_VMODE_YWRAP)
|
|
1373 disp->var.vmode |= FB_VMODE_YWRAP;
|
|
1374 else
|
|
1375 disp->var.vmode &= ~FB_VMODE_YWRAP;
|
|
1376
|
|
1377 return 0;
|
|
1378 }
|
|
1379
|
|
1380
|
|
1381
|
|
1382 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
|
|
1383 unsigned long arg, int con, struct fb_info *info)
|
|
1384 {
|
|
1385 return -EINVAL;
|
|
1386 }
|
|
1387
|
|
1388
|
|
1389
|
|
1390 static int radeonfb_switch (int con, struct fb_info *info)
|
|
1391 {
|
|
1392 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1393 struct display *disp;
|
|
1394 struct fb_cmap *cmap;
|
|
1395 int switchcon = 0;
|
|
1396
|
|
1397 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1398
|
|
1399 if (rinfo->currcon >= 0) {
|
|
1400 cmap = &(rinfo->currcon_display->cmap);
|
|
1401 if (cmap->len)
|
|
1402 fb_get_cmap (cmap, 1, radeon_getcolreg, info);
|
|
1403 }
|
|
1404
|
|
1405 if ((disp->var.xres != rinfo->xres) ||
|
|
1406 (disp->var.yres != rinfo->yres) ||
|
|
1407 (disp->var.pixclock != rinfo->pixclock) ||
|
|
1408 (disp->var.bits_per_pixel != rinfo->depth))
|
|
1409 switchcon = 1;
|
|
1410
|
|
1411 if (switchcon) {
|
|
1412 rinfo->currcon = con;
|
|
1413 rinfo->currcon_display = disp;
|
|
1414 disp->var.activate = FB_ACTIVATE_NOW;
|
|
1415
|
|
1416 radeonfb_set_var (&disp->var, con, info);
|
|
1417 radeon_set_dispsw (rinfo);
|
|
1418 }
|
|
1419
|
|
1420 return 0;
|
|
1421 }
|
|
1422
|
|
1423
|
|
1424
|
|
1425 static int radeonfb_updatevar (int con, struct fb_info *info)
|
|
1426 {
|
|
1427 int rc;
|
|
1428
|
|
1429 rc = (con < 0) ? -EINVAL : radeonfb_pan_display (&fb_display[con].var,
|
|
1430 con, info);
|
|
1431
|
|
1432 return rc;
|
|
1433 }
|
|
1434
|
|
1435 static void radeonfb_blank (int blank, struct fb_info *info)
|
|
1436 {
|
|
1437 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1438 u8 mode = 0;
|
|
1439
|
|
1440 switch (blank) {
|
|
1441 case 0:
|
|
1442 /* unblank */
|
|
1443 mode = 0;
|
|
1444 break;
|
|
1445 case 1:
|
|
1446 /* blank */
|
|
1447 mode = ((INREG8(CRTC_EXT_CNTL + 1) & 3) | 4);
|
|
1448 break;
|
|
1449 case 2:
|
|
1450 case 3:
|
|
1451 case 4:
|
|
1452 mode = blank | 4;
|
|
1453 break;
|
|
1454 }
|
|
1455
|
|
1456 OUTREG8(CRTC_EXT_CNTL + 1, mode);
|
|
1457 }
|
|
1458
|
|
1459
|
|
1460
|
|
1461 static int radeon_get_cmap_len (const struct fb_var_screeninfo *var)
|
|
1462 {
|
|
1463 int rc = 16; /* reasonable default */
|
|
1464
|
|
1465 switch (var->bits_per_pixel) {
|
|
1466 case 8:
|
|
1467 rc = 256;
|
|
1468 break;
|
|
1469 case 16:
|
|
1470 rc = 64;
|
|
1471 break;
|
|
1472 default:
|
|
1473 rc = 32;
|
|
1474 break;
|
|
1475 }
|
|
1476
|
|
1477 return rc;
|
|
1478 }
|
|
1479
|
|
1480
|
|
1481
|
|
1482 static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green,
|
|
1483 unsigned *blue, unsigned *transp,
|
|
1484 struct fb_info *info)
|
|
1485 {
|
|
1486 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1487
|
|
1488 if (regno > 255)
|
|
1489 return 1;
|
|
1490
|
|
1491 *red = (rinfo->palette[regno].red<<8) | rinfo->palette[regno].red;
|
|
1492 *green = (rinfo->palette[regno].green<<8) | rinfo->palette[regno].green;
|
|
1493 *blue = (rinfo->palette[regno].blue<<8) | rinfo->palette[regno].blue;
|
|
1494 *transp = 0;
|
|
1495
|
|
1496 return 0;
|
|
1497 }
|
|
1498
|
|
1499
|
|
1500
|
|
1501 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
|
|
1502 unsigned blue, unsigned transp, struct fb_info *info)
|
|
1503 {
|
|
1504 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1505 u32 pindex, col;
|
|
1506
|
|
1507 if (regno > 255)
|
|
1508 return 1;
|
|
1509
|
|
1510 red >>= 8;
|
|
1511 green >>= 8;
|
|
1512 blue >>= 8;
|
|
1513 rinfo->palette[regno].red = red;
|
|
1514 rinfo->palette[regno].green = green;
|
|
1515 rinfo->palette[regno].blue = blue;
|
|
1516
|
|
1517 /* init gamma for hicolor */
|
|
1518 if ((rinfo->depth > 8) && (regno == 0)) {
|
|
1519 int i;
|
|
1520 u32 tmp;
|
|
1521
|
|
1522 for (i=0; i<255; i++) {
|
|
1523 OUTREG(PALETTE_INDEX, i);
|
|
1524 tmp = (i << 16) | (i << 8) | i;
|
|
1525 radeon_fifo_wait(32);
|
|
1526 OUTREG(PALETTE_DATA, tmp);
|
|
1527 }
|
|
1528 }
|
|
1529
|
|
1530 /* default */
|
|
1531 pindex = regno;
|
|
1532 col = (red << 16) | (green << 8) | blue;
|
|
1533
|
|
1534 if (rinfo->depth == 16) {
|
|
1535 pindex = regno << 3;
|
|
1536
|
|
1537 if ((rinfo->depth == 16) && (regno >= 32)) {
|
|
1538 pindex -= 252;
|
|
1539
|
|
1540 col = (rinfo->palette[regno >> 1].red << 16) |
|
|
1541 (green << 8) |
|
|
1542 (rinfo->palette[regno >> 1].blue);
|
|
1543 } else {
|
|
1544 col = (red << 16) | (green << 8) | blue;
|
|
1545 }
|
|
1546 }
|
|
1547
|
|
1548 OUTREG8(PALETTE_INDEX, pindex);
|
|
1549 radeon_fifo_wait(32);
|
|
1550 OUTREG(PALETTE_DATA, col);
|
|
1551
|
|
1552 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
|
|
1553 if (regno < 32) {
|
|
1554 switch (rinfo->depth) {
|
|
1555 #ifdef FBCON_HAS_CFB16
|
|
1556 case 16:
|
|
1557 rinfo->con_cmap.cfb16[regno] = (regno << 10) | (regno << 5) |
|
|
1558 regno;
|
|
1559 break;
|
|
1560 #endif
|
|
1561 #ifdef FBCON_HAS_CFB32
|
|
1562 case 32: {
|
|
1563 u32 i;
|
|
1564
|
|
1565 i = (regno << 8) | regno;
|
|
1566 rinfo->con_cmap.cfb32[regno] = (i << 16) | i;
|
|
1567 break;
|
|
1568 }
|
|
1569 #endif
|
|
1570 }
|
|
1571 }
|
|
1572 #endif
|
|
1573 return 0;
|
|
1574 }
|
|
1575
|
|
1576
|
|
1577
|
|
1578 static void radeon_save_state (struct radeonfb_info *rinfo,
|
|
1579 struct radeon_regs *save)
|
|
1580 {
|
|
1581 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
|
|
1582 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
|
|
1583 save->dac_cntl = INREG(DAC_CNTL);
|
|
1584 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
|
|
1585 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
|
|
1586 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
|
|
1587 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
|
|
1588 save->crtc_pitch = INREG(CRTC_PITCH);
|
|
1589 }
|
|
1590
|
|
1591
|
|
1592
|
|
1593 static void radeon_load_video_mode (struct radeonfb_info *rinfo,
|
|
1594 struct fb_var_screeninfo *mode)
|
|
1595 {
|
|
1596 struct radeon_regs newmode;
|
|
1597 int hTotal, vTotal, hSyncStart, hSyncEnd,
|
|
1598 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
|
|
1599 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
|
|
1600 u32 dotClock = 1000000000 / mode->pixclock,
|
|
1601 sync, h_sync_pol, v_sync_pol;
|
|
1602 int freq = dotClock / 10; /* x 100 */
|
|
1603 int xclk_freq, vclk_freq, xclk_per_trans, xclk_per_trans_precise;
|
|
1604 int useable_precision, roff, ron;
|
|
1605 int min_bits, format = 0;
|
|
1606 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
|
|
1607
|
|
1608 rinfo->xres = mode->xres;
|
|
1609 rinfo->yres = mode->yres;
|
|
1610 rinfo->pixclock = mode->pixclock;
|
|
1611
|
|
1612 hSyncStart = mode->xres + mode->right_margin;
|
|
1613 hSyncEnd = hSyncStart + mode->hsync_len;
|
|
1614 hTotal = hSyncEnd + mode->left_margin;
|
|
1615
|
|
1616 vSyncStart = mode->yres + mode->lower_margin;
|
|
1617 vSyncEnd = vSyncStart + mode->vsync_len;
|
|
1618 vTotal = vSyncEnd + mode->upper_margin;
|
|
1619
|
|
1620 sync = mode->sync;
|
|
1621 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
|
|
1622 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
|
|
1623
|
|
1624 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
|
|
1625 hSyncStart, hSyncEnd, hTotal);
|
|
1626 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
|
|
1627 vSyncStart, vSyncEnd, vTotal);
|
|
1628
|
|
1629 hsync_wid = (hSyncEnd - hSyncStart) / 8;
|
|
1630 vsync_wid = vSyncEnd - vSyncStart;
|
|
1631 if (hsync_wid == 0)
|
|
1632 hsync_wid = 1;
|
|
1633 else if (hsync_wid > 0x3f) /* max */
|
|
1634 hsync_wid = 0x3f;
|
|
1635
|
|
1636 if (vsync_wid == 0)
|
|
1637 vsync_wid = 1;
|
|
1638 else if (vsync_wid > 0x1f) /* max */
|
|
1639 vsync_wid = 0x1f;
|
|
1640
|
|
1641 if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
|
|
1642 hSyncPol = 1;
|
|
1643 else
|
|
1644 hSyncPol = 0;
|
|
1645
|
|
1646 if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
|
|
1647 vSyncPol = 1;
|
|
1648 else
|
|
1649 vSyncPol = 0;
|
|
1650
|
|
1651 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
|
|
1652
|
|
1653 switch (mode->bits_per_pixel) {
|
|
1654 case 8:
|
|
1655 format = DST_8BPP;
|
|
1656 bytpp = 1;
|
|
1657 break;
|
|
1658 case 16:
|
|
1659 format = DST_16BPP;
|
|
1660 bytpp = 2;
|
|
1661 break;
|
|
1662 case 24:
|
|
1663 format = DST_24BPP;
|
|
1664 bytpp = 3;
|
|
1665 break;
|
|
1666 case 32:
|
|
1667 format = DST_32BPP;
|
|
1668 bytpp = 4;
|
|
1669 break;
|
|
1670 }
|
|
1671
|
|
1672 hsync_fudge = hsync_adj_tab[format-1];
|
|
1673 hsync_start = hSyncStart - 8 + hsync_fudge;
|
|
1674
|
|
1675 newmode.crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
|
|
1676 (format << 8);
|
|
1677
|
|
1678 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
|
|
1679
|
|
1680 newmode.dac_cntl = INREG(DAC_CNTL) | DAC_MASK_ALL | DAC_VGA_ADR_EN |
|
|
1681 DAC_8BIT_EN;
|
|
1682
|
|
1683 newmode.crtc_h_total_disp = ((((hTotal / 8) - 1) & 0xffff) |
|
|
1684 (((mode->xres / 8) - 1) << 16));
|
|
1685
|
|
1686 newmode.crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
|
|
1687 (hsync_wid << 16) | (hSyncPol << 23));
|
|
1688
|
|
1689 newmode.crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
|
|
1690 ((mode->yres - 1) << 16);
|
|
1691
|
|
1692 newmode.crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
|
|
1693 (vsync_wid << 16) | (vSyncPol << 23));
|
|
1694
|
|
1695 newmode.crtc_pitch = (mode->xres >> 3);
|
|
1696
|
|
1697 rinfo->pitch = ((mode->xres * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
|
|
1698 & ~(0x3f)) / 64;
|
|
1699
|
|
1700 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
|
|
1701 newmode.crtc_h_total_disp, newmode.crtc_h_sync_strt_wid);
|
|
1702 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
|
|
1703 newmode.crtc_v_total_disp, newmode.crtc_v_sync_strt_wid);
|
|
1704
|
|
1705 newmode.xres = mode->xres;
|
|
1706 newmode.yres = mode->yres;
|
|
1707
|
|
1708 rinfo->bpp = mode->bits_per_pixel;
|
|
1709
|
|
1710 if (freq > rinfo->pll.ppll_max)
|
|
1711 freq = rinfo->pll.ppll_max;
|
|
1712 if (freq*12 < rinfo->pll.ppll_min)
|
|
1713 freq = rinfo->pll.ppll_min / 12;
|
|
1714
|
|
1715 {
|
|
1716 struct {
|
|
1717 int divider;
|
|
1718 int bitvalue;
|
|
1719 } *post_div,
|
|
1720 post_divs[] = {
|
|
1721 { 1, 0 },
|
|
1722 { 2, 1 },
|
|
1723 { 4, 2 },
|
|
1724 { 8, 3 },
|
|
1725 { 3, 4 },
|
|
1726 { 16, 5 },
|
|
1727 { 6, 6 },
|
|
1728 { 12, 7 },
|
|
1729 { 0, 0 },
|
|
1730 };
|
|
1731
|
|
1732 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
|
|
1733 rinfo->pll_output_freq = post_div->divider * freq;
|
|
1734 if (rinfo->pll_output_freq >= rinfo->pll.ppll_min &&
|
|
1735 rinfo->pll_output_freq <= rinfo->pll.ppll_max)
|
|
1736 break;
|
|
1737 }
|
|
1738
|
|
1739 rinfo->post_div = post_div->divider;
|
|
1740 rinfo->fb_div = round_div(rinfo->pll.ref_div*rinfo->pll_output_freq,
|
|
1741 rinfo->pll.ref_clk);
|
|
1742 newmode.ppll_ref_div = rinfo->pll.ref_div;
|
|
1743 newmode.ppll_div_3 = rinfo->fb_div | (post_div->bitvalue << 16);
|
|
1744 }
|
|
1745
|
|
1746 RTRACE("post div = 0x%x\n", rinfo->post_div);
|
|
1747 RTRACE("fb_div = 0x%x\n", rinfo->fb_div);
|
|
1748 RTRACE("ppll_div_3 = 0x%x\n", newmode.ppll_div_3);
|
|
1749
|
|
1750 /* DDA */
|
|
1751 vclk_freq = round_div(rinfo->pll.ref_clk * rinfo->fb_div,
|
|
1752 rinfo->pll.ref_div * rinfo->post_div);
|
|
1753 xclk_freq = rinfo->pll.xclk;
|
|
1754
|
|
1755 xclk_per_trans = round_div(xclk_freq * 128, vclk_freq * mode->bits_per_pixel);
|
|
1756
|
|
1757 min_bits = min_bits_req(xclk_per_trans);
|
|
1758 useable_precision = min_bits + 1;
|
|
1759
|
|
1760 xclk_per_trans_precise = round_div((xclk_freq * 128) << (11 - useable_precision),
|
|
1761 vclk_freq * mode->bits_per_pixel);
|
|
1762
|
|
1763 ron = (4 * rinfo->ram.mb + 3 * _max(rinfo->ram.trcd - 2, 0) +
|
|
1764 2 * rinfo->ram.trp + rinfo->ram.twr + rinfo->ram.cl + rinfo->ram.tr2w +
|
|
1765 xclk_per_trans) << (11 - useable_precision);
|
|
1766 roff = xclk_per_trans_precise * (32 - 4);
|
|
1767
|
|
1768 RTRACE("ron = %d, roff = %d\n", ron, roff);
|
|
1769 RTRACE("vclk_freq = %d, per = %d\n", vclk_freq, xclk_per_trans_precise);
|
|
1770
|
|
1771 if ((ron + rinfo->ram.rloop) >= roff) {
|
|
1772 printk("radeonfb: error ron out of range\n");
|
|
1773 return;
|
|
1774 }
|
|
1775
|
|
1776 newmode.dda_config = (xclk_per_trans_precise |
|
|
1777 (useable_precision << 16) |
|
|
1778 (rinfo->ram.rloop << 20));
|
|
1779 newmode.dda_on_off = (ron << 16) | roff;
|
|
1780
|
|
1781 /* do it! */
|
|
1782 radeon_write_mode (rinfo, &newmode);
|
|
1783
|
|
1784 return;
|
|
1785 }
|
|
1786
|
|
1787
|
|
1788
|
|
1789 static void radeon_write_mode (struct radeonfb_info *rinfo,
|
|
1790 struct radeon_regs *mode)
|
|
1791 {
|
|
1792 int i;
|
|
1793
|
|
1794 /* blank screen */
|
|
1795 OUTREG8(CRTC_EXT_CNTL + 1, 4);
|
|
1796
|
|
1797 for (i=0; i<9; i++)
|
|
1798 OUTREG(common_regs[i].reg, common_regs[i].val);
|
|
1799
|
|
1800 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
|
|
1801 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
|
|
1802 CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
|
|
1803 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
|
|
1804 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
|
|
1805 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
|
|
1806 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
|
|
1807 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
|
|
1808 OUTREG(CRTC_OFFSET, 0);
|
|
1809 OUTREG(CRTC_OFFSET_CNTL, 0);
|
|
1810 OUTREG(CRTC_PITCH, mode->crtc_pitch);
|
|
1811
|
|
1812 while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=
|
|
1813 PPLL_DIV_SEL_MASK) {
|
|
1814 OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, 0xffff);
|
|
1815 }
|
|
1816
|
|
1817 OUTPLLP(PPLL_CNTL, PPLL_RESET, 0xffff);
|
|
1818
|
|
1819 while ((INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=
|
|
1820 (mode->ppll_ref_div & PPLL_REF_DIV_MASK)) {
|
|
1821 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
|
|
1822 }
|
|
1823
|
|
1824 while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=
|
|
1825 (mode->ppll_div_3 & PPLL_FB3_DIV_MASK)) {
|
|
1826 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
|
|
1827 }
|
|
1828
|
|
1829 while ((INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=
|
|
1830 (mode->ppll_div_3 & PPLL_POST3_DIV_MASK)) {
|
|
1831 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
|
|
1832 }
|
|
1833
|
|
1834 OUTPLL(HTOTAL_CNTL, 0);
|
|
1835
|
|
1836 OUTPLLP(PPLL_CNTL, 0, ~PPLL_RESET);
|
|
1837
|
|
1838 OUTREG(DDA_CONFIG, mode->dda_config);
|
|
1839 OUTREG(DDA_ON_OFF, mode->dda_on_off);
|
|
1840
|
|
1841 /* unblank screen */
|
|
1842 OUTREG8(CRTC_EXT_CNTL + 1, 0);
|
|
1843
|
|
1844 return;
|
|
1845 }
|
|
1846
|
|
1847
|
|
1848
|
|
1849 /*
|
|
1850 * text console acceleration
|
|
1851 */
|
|
1852
|
|
1853
|
|
1854 static void fbcon_radeon_bmove(struct display *p, int srcy, int srcx,
|
|
1855 int dsty, int dstx, int height, int width)
|
|
1856 {
|
|
1857 struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
|
|
1858 u32 dp_cntl = DST_LAST_PEL;
|
|
1859
|
|
1860 srcx *= fontwidth(p);
|
|
1861 srcy *= fontheight(p);
|
|
1862 dstx *= fontwidth(p);
|
|
1863 dsty *= fontheight(p);
|
|
1864 width *= fontwidth(p);
|
|
1865 height *= fontheight(p);
|
|
1866
|
|
1867 if (srcy < dsty) {
|
|
1868 srcy += height - 1;
|
|
1869 dsty += height - 1;
|
|
1870 } else
|
|
1871 dp_cntl |= DST_Y_TOP_TO_BOTTOM;
|
|
1872
|
|
1873 if (srcx < dstx) {
|
|
1874 srcx += width - 1;
|
|
1875 dstx += width - 1;
|
|
1876 } else
|
|
1877 dp_cntl |= DST_X_LEFT_TO_RIGHT;
|
|
1878
|
|
1879 radeon_fifo_wait(6);
|
|
1880 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
1881 GMC_BRUSH_NONE |
|
|
1882 GMC_SRC_DATATYPE_COLOR |
|
|
1883 ROP3_S |
|
|
1884 DP_SRC_SOURCE_MEMORY));
|
|
1885 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
1886 OUTREG(DP_CNTL, dp_cntl);
|
|
1887 OUTREG(SRC_Y_X, (srcy << 16) | srcx);
|
|
1888 OUTREG(DST_Y_X, (dsty << 16) | dstx);
|
|
1889 OUTREG(DST_HEIGHT_WIDTH, (height << 16) | width);
|
|
1890 }
|
|
1891
|
|
1892
|
|
1893
|
|
1894 static void fbcon_radeon_clear(struct vc_data *conp, struct display *p,
|
|
1895 int srcy, int srcx, int height, int width)
|
|
1896 {
|
|
1897 struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
|
|
1898 u32 clr;
|
|
1899 u32 temp;
|
|
1900
|
|
1901 clr = attr_bgcol_ec(p, conp);
|
|
1902 clr |= (clr << 8);
|
|
1903 clr |= (clr << 16);
|
|
1904
|
|
1905 srcx *= fontwidth(p);
|
|
1906 srcy *= fontheight(p);
|
|
1907 width *= fontwidth(p);
|
|
1908 height *= fontheight(p);
|
|
1909
|
|
1910 radeon_fifo_wait(6);
|
|
1911 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
1912 GMC_BRUSH_SOLID_COLOR |
|
|
1913 GMC_SRC_DATATYPE_COLOR |
|
|
1914 ROP3_P));
|
|
1915 OUTREG(DP_BRUSH_FRGD_CLR, clr);
|
|
1916 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
1917 OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
|
|
1918 OUTREG(DST_Y_X, (srcy << 16) | srcx);
|
|
1919 OUTREG(DST_WIDTH_HEIGHT, (width << 16) | height);
|
|
1920 }
|
|
1921
|
|
1922
|
|
1923
|
|
1924
|
|
1925 #ifdef FBCON_HAS_CFB8
|
|
1926 static struct display_switch fbcon_radeon8 = {
|
|
1927 setup: fbcon_cfb8_setup,
|
|
1928 bmove: fbcon_radeon_bmove,
|
|
1929 clear: fbcon_cfb8_clear,
|
|
1930 putc: fbcon_cfb8_putc,
|
|
1931 putcs: fbcon_cfb8_putcs,
|
|
1932 revc: fbcon_cfb8_revc,
|
|
1933 clear_margins: fbcon_cfb8_clear_margins,
|
|
1934 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
|
|
1935 };
|
|
1936 #endif
|