Mercurial > mplayer.hg
annotate cpudetect.c @ 2268:72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
author | arpi |
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date | Fri, 19 Oct 2001 00:40:19 +0000 |
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children | c26a9eff0993 |
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1 #include "config.h" |
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2 #include "cpudetect.h" |
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3 |
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4 #ifdef ARCH_X86 |
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5 |
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6 #include <stdio.h> |
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7 |
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8 #ifdef __FreeBSD__ |
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9 #include <sys/types.h> |
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10 #include <sys/sysctl.h> |
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11 #endif |
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12 |
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13 #ifdef __linux__ |
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14 #include <signal.h> |
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15 #endif |
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16 |
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17 #define X86_FXSR_MAGIC |
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18 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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19 * help understanding how to use it. Thanks to the Mesa |
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20 * team for SSE support detection and more cpu detect code. |
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21 */ |
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22 |
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23 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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24 |
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25 CpuCaps gCpuCaps; |
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26 static void check_os_katmai_support( void ); |
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27 |
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28 #if 0 |
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29 static int has_cpuid() |
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30 { |
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31 int a, c; |
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32 __asm __volatile( |
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33 "pushl %%ebx;" |
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34 /* Test for the CPUID command. If the ID Flag bit in EFLAGS |
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35 * (bit 21) is writable, the CPUID command is present */ |
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36 "pushfl;" |
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37 "popl %%eax;" |
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38 "movl %%ecx, %%eax;" |
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39 "xorl %%eax, 0x00200000;" |
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40 "push %%eax;" |
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41 "popfl;" |
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42 "pushfl;" |
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43 "popl %%eax;" |
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44 "popl %%ebx" |
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45 : "=a" (a), "=c" (c) |
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46 : |
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47 : "cx" |
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48 ); |
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49 /* FIXME: I have no clue on intel assembly. */ |
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50 return (a==c); |
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51 } |
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52 #endif |
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53 |
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54 static void |
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55 do_cpuid(unsigned int ax, unsigned int *p) |
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56 { |
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57 __asm __volatile( |
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58 "cpuid;" |
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59 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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60 : "0" (ax) |
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61 ); |
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62 } |
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63 |
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64 |
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65 void GetCpuCaps( CpuCaps *caps) |
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66 { |
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67 unsigned int regs[4]; |
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68 unsigned int regs2[4]; |
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69 |
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70 bzero(caps, sizeof(*caps)); |
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71 /*if (!has_cpuid()) |
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72 return;*/ |
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73 do_cpuid(0x00000000, regs); |
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74 if (regs[0]>0x00000001) { |
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75 do_cpuid(0x00000001, regs2); |
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76 switch ((regs2[0] >> 8)&0xf) { |
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77 case 3: |
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78 caps->cpuType=CPUTYPE_I386; |
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79 break; |
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80 case 4: |
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81 caps->cpuType=CPUTYPE_I486; |
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82 break; |
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83 case 5: |
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84 caps->cpuType=CPUTYPE_I586; |
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85 break; |
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86 case 6: |
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87 caps->cpuType=CPUTYPE_I586; |
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88 break; |
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89 default: |
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90 printf("Unknown cpu type, default to i386\n"); |
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91 break; |
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92 } |
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93 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; |
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94 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; |
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95 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; |
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96 /* FIXME: Does SSE2 need more OS support, too? */ |
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97 #if defined(__linux__) || defined(__FreeBSD__) |
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98 if (caps->hasSSE) |
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99 check_os_katmai_support(); |
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100 if (!caps->hasSSE) |
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101 caps->hasSSE2 = 0; |
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102 #else |
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103 caps->hasSSE=0; |
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104 caps->hasSSE2 = 0; |
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105 #endif |
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106 /* FIXME: Are MMX2 ops on the same set of processors as SSE? Do they need OS support?*/ |
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107 caps->hasMMX2 = caps->hasSSE; |
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108 } |
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109 if (memcmp(®s[1], "AuthenticAMD", 12)) { |
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110 do_cpuid(0x80000000, regs); |
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111 if (regs[0]>0x80000001) { |
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112 do_cpuid(0x80000001, regs2); |
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113 /*caps->hasMMX2 = regs[3] & (1 << 23 );*/ |
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114 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; |
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115 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; |
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116 } |
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117 } |
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118 printf("cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
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119 gCpuCaps.hasMMX, |
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120 gCpuCaps.hasMMX2, |
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121 gCpuCaps.hasSSE, |
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122 gCpuCaps.hasSSE2, |
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123 gCpuCaps.has3DNow, |
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124 gCpuCaps.has3DNowExt ); |
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125 |
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126 } |
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127 |
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128 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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129 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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130 { |
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131 printf( "SIGILL, " ); |
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132 |
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133 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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134 * instructions are 3 bytes long. We must increment the instruction |
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135 * pointer manually to avoid repeated execution of the offending |
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136 * instruction. |
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137 * |
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138 * If the SIGILL is caused by a divide-by-zero when unmasked |
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139 * exceptions aren't supported, the SIMD FPU status and control |
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140 * word will be restored at the end of the test, so we don't need |
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141 * to worry about doing it here. Besides, we may not be able to... |
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142 */ |
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143 sc.eip += 3; |
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144 |
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145 gCpuCaps.hasSSE=0; |
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146 } |
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147 |
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148 static void sigfpe_handler_sse( int signal, struct sigcontext sc ) |
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149 { |
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150 printf( "SIGFPE, " ); |
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151 |
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152 if ( sc.fpstate->magic != 0xffff ) { |
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153 /* Our signal context has the extended FPU state, so reset the |
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154 * divide-by-zero exception mask and clear the divide-by-zero |
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155 * exception bit. |
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156 */ |
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157 sc.fpstate->mxcsr |= 0x00000200; |
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158 sc.fpstate->mxcsr &= 0xfffffffb; |
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159 } else { |
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160 /* If we ever get here, we're completely hosed. |
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161 */ |
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162 printf( "\n\n" ); |
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163 printf( "SSE enabling test failed badly!" ); |
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164 } |
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165 } |
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166 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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167 |
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168 /* If we're running on a processor that can do SSE, let's see if we |
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169 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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170 * haven't been configured for a Pentium III but are running on one, |
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171 * and RedHat patched 2.2 kernels that have broken exception handling |
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172 * support for user space apps that do SSE. |
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173 */ |
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174 static void check_os_katmai_support( void ) |
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175 { |
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176 #if defined(__FreeBSD__) |
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177 int has_sse=0, ret; |
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178 size_t len=sizeof(has_sse); |
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179 |
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180 ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0); |
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181 if (ret || !has_sse) |
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182 gCpuCaps.hasSSE=0; |
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183 |
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184 #elif defined(__linux__) |
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185 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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186 struct sigaction saved_sigill; |
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187 struct sigaction saved_sigfpe; |
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188 |
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189 /* Save the original signal handlers. |
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190 */ |
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191 sigaction( SIGILL, NULL, &saved_sigill ); |
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192 sigaction( SIGFPE, NULL, &saved_sigfpe ); |
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193 |
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194 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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195 signal( SIGFPE, (void (*)(int))sigfpe_handler_sse ); |
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196 |
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197 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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198 * supports the extended FPU save and restore required for SSE. If |
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199 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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200 * doesn't support Streaming SIMD Exceptions, even if the processor |
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201 * does. |
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202 */ |
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203 if ( gCpuCaps.hasSSE ) { |
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204 printf( "Testing OS support for SSE... " ); |
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205 |
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206 __asm __volatile ("xorps %%xmm0, %%xmm0"); |
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207 |
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208 if ( gCpuCaps.hasSSE ) { |
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209 printf( "yes.\n" ); |
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210 } else { |
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211 printf( "no!\n" ); |
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212 } |
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213 } |
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214 |
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215 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if |
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216 * it supports unmasked SIMD FPU exceptions. If we unmask the |
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217 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS |
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218 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE |
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219 * as expected, we're okay but we need to clean up after it. |
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220 * |
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221 * Are we being too stringent in our requirement that the OS support |
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222 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by |
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223 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98 |
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224 * doesn't even support them. We at least know the user-space SSE |
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225 * support is good in kernels that do support unmasked exceptions, |
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226 * and therefore to be safe I'm going to leave this test in here. |
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227 */ |
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228 if ( gCpuCaps.hasSSE ) { |
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229 printf( "Testing OS support for SSE unmasked exceptions... " ); |
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230 |
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231 test_os_katmai_exception_support(); |
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232 |
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233 if ( gCpuCaps.hasSSE ) { |
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234 printf( "yes.\n" ); |
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235 } else { |
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236 printf( "no!\n" ); |
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237 } |
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238 } |
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239 |
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240 /* Restore the original signal handlers. |
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241 */ |
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242 sigaction( SIGILL, &saved_sigill, NULL ); |
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243 sigaction( SIGFPE, &saved_sigfpe, NULL ); |
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244 |
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245 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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246 * safe to go ahead and hook out the SSE code throughout Mesa. |
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247 */ |
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248 if ( gCpuCaps.hasSSE ) { |
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249 printf( "Tests of OS support for SSE passed.\n" ); |
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250 } else { |
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251 printf( "Tests of OS support for SSE failed!\n" ); |
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252 } |
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253 #else |
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254 /* We can't use POSIX signal handling to test the availability of |
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255 * SSE, so we disable it by default. |
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256 */ |
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257 printf( "Cannot test OS support for SSE, disabling to be safe.\n" ); |
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258 gCpuCaps.hasSSE=0; |
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259 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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260 #else |
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261 /* Do nothing on other platforms for now. |
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262 */ |
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263 message( "Not testing OS support for SSE, leaving disabled.\n" ); |
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264 gCpuCaps.hasSSE=0; |
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265 #endif /* __linux__ */ |
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266 } |
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267 #endif /* ARCH_X86 */ |