Mercurial > mplayer.hg
annotate TOOLS/cpuinfo.c @ 19337:79b3a37b3b98
Don't crash if audio init fails.
author | uau |
---|---|
date | Sat, 05 Aug 2006 18:23:10 +0000 |
parents | a163f6de7bdc |
children | 1ffb54bae960 |
rev | line source |
---|---|
12960 | 1 /* small utility to extract CPU information |
17041 | 2 Used by configure to set CPU optimization levels on some operating |
3 systems where /proc/cpuinfo is non-existent or unreliable. */ | |
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4 |
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5 #include <stdio.h> |
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6 #include <sys/time.h> |
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7 #include <stdlib.h> |
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8 #include <string.h> |
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9 #include <unistd.h> |
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10 |
18910 | 11 #if defined(__MINGW32__) && (__MINGW32_MAJOR_VERSION <= 3) && (__MINGW32_MINOR_VERSION < 10) |
9764 | 12 #include <sys/timeb.h> |
17041 | 13 void gettimeofday(struct timeval* t,void* timezone) { |
14 struct timeb timebuffer; | |
15 ftime( &timebuffer ); | |
16 t->tv_sec=timebuffer.time; | |
17 t->tv_usec=1000*timebuffer.millitm; | |
9764 | 18 } |
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19 #endif |
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20 #ifdef __MINGW32__ |
9764 | 21 #define MISSING_USLEEP |
22 #define sleep(t) _sleep(1000*t); | |
23 #endif | |
24 | |
13612 | 25 #ifdef __BEOS__ |
26 #define usleep(t) snooze(t) | |
27 #endif | |
28 | |
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29 #ifdef M_UNIX |
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30 typedef long long int64_t; |
17041 | 31 #define MISSING_USLEEP |
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32 #else |
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33 #include <inttypes.h> |
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34 #endif |
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35 |
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36 |
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37 typedef struct cpuid_regs { |
17041 | 38 unsigned int eax; |
39 unsigned int ebx; | |
40 unsigned int ecx; | |
41 unsigned int edx; | |
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42 } cpuid_regs_t; |
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43 |
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44 static cpuid_regs_t |
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45 cpuid(int func) { |
17041 | 46 cpuid_regs_t regs; |
47 #define CPUID ".byte 0x0f, 0xa2; " | |
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48 #ifdef __x86_64__ |
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49 asm("mov %%rbx, %%rsi\n\t" |
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50 #else |
18517 | 51 asm("mov %%ebx, %%esi\n\t" |
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52 #endif |
18517 | 53 CPUID"\n\t" |
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54 #ifdef __x86_64__ |
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55 "xchg %%rsi, %%rbx\n\t" |
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56 #else |
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57 "xchg %%esi, %%ebx\n\t" |
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58 #endif |
18517 | 59 : "=a" (regs.eax), "=S" (regs.ebx), "=c" (regs.ecx), "=d" (regs.edx) |
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60 : "0" (func)); |
17041 | 61 return regs; |
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62 } |
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63 |
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64 |
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65 static int64_t |
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66 rdtsc(void) |
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67 { |
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68 uint64_t i; |
17041 | 69 #define RDTSC ".byte 0x0f, 0x31; " |
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70 asm volatile (RDTSC : "=A"(i) : ); |
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71 return i; |
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72 } |
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73 |
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74 static const char* |
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75 brandname(int i) |
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76 { |
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77 const static char* brandmap[] = { |
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78 NULL, |
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79 "Intel(R) Celeron(R) processor", |
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80 "Intel(R) Pentium(R) III processor", |
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81 "Intel(R) Pentium(R) III Xeon(tm) processor", |
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82 "Intel(R) Pentium(R) III processor", |
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83 NULL, |
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84 "Mobile Intel(R) Pentium(R) III processor-M", |
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85 "Mobile Intel(R) Celeron(R) processor" |
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86 }; |
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87 |
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88 if (i >= sizeof(brandmap)) |
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89 return NULL; |
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90 else |
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91 return brandmap[i]; |
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92 } |
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93 |
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94 static void |
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95 store32(char *d, unsigned int v) |
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96 { |
17041 | 97 d[0] = v & 0xff; |
98 d[1] = (v >> 8) & 0xff; | |
99 d[2] = (v >> 16) & 0xff; | |
100 d[3] = (v >> 24) & 0xff; | |
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101 } |
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102 |
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103 |
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104 int |
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105 main(int argc, char **argv) |
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106 { |
17041 | 107 cpuid_regs_t regs, regs_ext; |
108 char idstr[13]; | |
109 unsigned max_cpuid; | |
110 unsigned max_ext_cpuid; | |
111 unsigned int amd_flags; | |
112 unsigned int amd_flags2; | |
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113 const char *model_name = NULL; |
17041 | 114 int i; |
115 char processor_name[49]; | |
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116 |
17041 | 117 regs = cpuid(0); |
118 max_cpuid = regs.eax; | |
119 /* printf("%d CPUID function codes\n", max_cpuid+1); */ | |
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120 |
17041 | 121 store32(idstr+0, regs.ebx); |
122 store32(idstr+4, regs.edx); | |
123 store32(idstr+8, regs.ecx); | |
124 idstr[12] = 0; | |
125 printf("vendor_id\t: %s\n", idstr); | |
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126 |
17041 | 127 regs_ext = cpuid((1<<31) + 0); |
128 max_ext_cpuid = regs_ext.eax; | |
129 if (max_ext_cpuid >= (1<<31) + 1) { | |
130 regs_ext = cpuid((1<<31) + 1); | |
131 amd_flags = regs_ext.edx; | |
132 amd_flags2 = regs_ext.ecx; | |
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133 |
17041 | 134 if (max_ext_cpuid >= (1<<31) + 4) { |
135 for (i = 2; i <= 4; i++) { | |
136 regs_ext = cpuid((1<<31) + i); | |
137 store32(processor_name + (i-2)*16, regs_ext.eax); | |
138 store32(processor_name + (i-2)*16 + 4, regs_ext.ebx); | |
139 store32(processor_name + (i-2)*16 + 8, regs_ext.ecx); | |
140 store32(processor_name + (i-2)*16 + 12, regs_ext.edx); | |
141 } | |
142 processor_name[48] = 0; | |
143 model_name = processor_name; | |
144 } | |
145 } else { | |
146 amd_flags = 0; | |
147 amd_flags2 = 0; | |
148 } | |
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149 |
17041 | 150 if (max_cpuid >= 1) { |
151 static struct { | |
152 int bit; | |
153 char *desc;; | |
154 char *description; | |
155 } cap[] = { | |
156 { 0, "fpu", "Floating-point unit on-chip" }, | |
157 { 1, "vme", "Virtual Mode Enhancements" }, | |
158 { 2, "de", "Debugging Extension" }, | |
159 { 3, "pse", "Page Size Extension" }, | |
160 { 4, "tsc", "Time Stamp Counter" }, | |
161 { 5, "msr", "Pentium Processor MSR" }, | |
162 { 6, "pae", "Physical Address Extension" }, | |
163 { 7, "mce", "Machine Check Exception" }, | |
164 { 8, "cx8", "CMPXCHG8B Instruction Supported" }, | |
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165 { 9, "apic", "On-chip APIC Hardware Enabled" }, |
17041 | 166 { 11, "sep", "SYSENTER and SYSEXIT" }, |
167 { 12, "mtrr", "Memory Type Range Registers" }, | |
168 { 13, "pge", "PTE Global Bit" }, | |
169 { 14, "mca", "Machine Check Architecture" }, | |
170 { 15, "cmov", "Conditional Move/Compare Instruction" }, | |
171 { 16, "pat", "Page Attribute Table" }, | |
172 { 17, "pse36", "Page Size Extension 36-bit" }, | |
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173 { 18, "pn", "Processor Serial Number" }, |
17041 | 174 { 19, "cflsh", "CFLUSH instruction" }, |
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175 { 21, "dts", "Debug Store" }, |
17041 | 176 { 22, "acpi", "Thermal Monitor and Clock Ctrl" }, |
177 { 23, "mmx", "MMX Technology" }, | |
178 { 24, "fxsr", "FXSAVE/FXRSTOR" }, | |
179 { 25, "sse", "SSE Extensions" }, | |
180 { 26, "sse2", "SSE2 Extensions" }, | |
181 { 27, "ss", "Self Snoop" }, | |
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182 { 28, "ht", "Multi-threading" }, |
17041 | 183 { 29, "tm", "Therm. Monitor" }, |
184 { 30, "ia64", "IA-64 Processor" }, | |
185 { 31, "pbe", "Pend. Brk. EN." }, | |
186 { -1 } | |
187 }; | |
188 static struct { | |
189 int bit; | |
190 char *desc; | |
191 char *description; | |
192 } cap2[] = { | |
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193 { 0, "pni", "SSE3 Extensions" }, |
17041 | 194 { 3, "monitor", "MONITOR/MWAIT" }, |
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195 { 4, "ds_cpl", "CPL Qualified Debug Store" }, |
17041 | 196 { 5, "vmx", "Virtual Machine Extensions" }, |
197 { 7, "est", "Enhanced Intel SpeedStep Technology" }, | |
198 { 8, "tm2", "Thermal Monitor 2" }, | |
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199 { 10, "cid", "L1 Context ID" }, |
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200 { 13, "cx16", "CMPXCHG16B Available" }, |
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201 { 14, "xtpr", "xTPR Disable" }, |
17041 | 202 { -1 } |
203 }; | |
204 static struct { | |
205 int bit; | |
206 char *desc;; | |
207 char *description; | |
208 } cap_amd[] = { | |
209 { 11, "syscall", "SYSCALL and SYSRET" }, | |
210 { 19, "mp", "MP Capable" }, | |
211 { 20, "nx", "No-Execute Page Protection" }, | |
212 { 22, "mmxext","MMX Technology (AMD Extensions)" }, | |
213 { 25, "fxsr_opt", "Fast FXSAVE/FXRSTOR" }, | |
214 { 27, "rdtscp", "RDTSCP Instruction" }, | |
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215 { 29, "lm", "Long Mode Capable" }, |
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216 { 30, "3dnowext","3DNow! Extensions" }, |
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217 { 31, "3dnow", "3DNow!" }, |
17041 | 218 { -1 } |
219 }; | |
220 static struct { | |
221 int bit; | |
222 char *desc; | |
223 char *description; | |
224 } cap_amd2[] = { | |
225 { 0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode" }, | |
226 { 1, "cmp_legacy", "Chip Multi-Core" }, | |
227 { 2, "svm", "Secure Virtual Machine" }, | |
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228 { 4, "cr8legacy", "CR8 Available in Legacy Mode" }, |
17041 | 229 { -1 } |
230 }; | |
231 unsigned int family, model, stepping; | |
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232 |
17041 | 233 regs = cpuid(1); |
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234 family = (regs.eax >> 8) & 0xf; |
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235 model = (regs.eax >> 4) & 0xf; |
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236 stepping = regs.eax & 0xf; |
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237 |
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238 if (family == 0xf) |
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239 { |
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240 family += (regs.eax >> 20) & 0xff; |
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241 model += ((regs.eax >> 16) & 0xf) << 4; |
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242 } |
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243 |
17041 | 244 printf("cpu family\t: %d\n" |
245 "model\t\t: %d\n" | |
246 "stepping\t: %d\n" , | |
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247 family, |
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248 model, |
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249 stepping); |
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250 |
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251 if (strstr(idstr, "Intel") && !model_name) { |
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252 if (family == 6 && model == 0xb && stepping == 1) |
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253 model_name = "Intel (R) Celeron (R) processor"; |
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254 else |
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255 model_name = brandname(regs.ebx & 0xf); |
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256 } |
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257 |
17041 | 258 printf("flags\t\t:"); |
259 for (i = 0; cap[i].bit >= 0; i++) { | |
260 if (regs.edx & (1 << cap[i].bit)) { | |
261 printf(" %s", cap[i].desc); | |
262 } | |
263 } | |
264 for (i = 0; cap2[i].bit >= 0; i++) { | |
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265 if (regs.ecx & (1 << cap2[i].bit)) { |
17041 | 266 printf(" %s", cap2[i].desc); |
267 } | |
268 } | |
269 /* k6_mtrr is supported by some AMD K6-2/K6-III CPUs but | |
270 it is not indicated by a CPUID feature bit, so we | |
271 have to check the family, model and stepping instead. */ | |
272 if (strstr(idstr, "AMD") && | |
273 family == 5 && | |
274 (model >= 9 || model == 8 && stepping >= 8)) | |
275 printf(" %s", "k6_mtrr"); | |
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276 /* similar for cyrix_arr. */ |
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277 if (strstr(idstr, "Cyrix") && |
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278 (family == 5 && model < 4 || family == 6)) |
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279 printf(" %s", "cyrix_arr"); |
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280 /* as well as centaur_mcr. */ |
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281 if (strstr(idstr, "Centaur") && |
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282 family == 5) |
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283 printf(" %s", "centaur_mcr"); |
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284 |
17041 | 285 for (i = 0; cap_amd[i].bit >= 0; i++) { |
286 if (amd_flags & (1 << cap_amd[i].bit)) { | |
287 printf(" %s", cap_amd[i].desc); | |
288 } | |
289 } | |
290 for (i = 0; cap_amd2[i].bit >= 0; i++) { | |
291 if (amd_flags2 & (1 << cap_amd2[i].bit)) { | |
292 printf(" %s", cap_amd2[i].desc); | |
293 } | |
294 } | |
295 printf("\n"); | |
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296 |
17041 | 297 if (regs.edx & (1 << 4)) { |
298 int64_t tsc_start, tsc_end; | |
299 struct timeval tv_start, tv_end; | |
300 int usec_delay; | |
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301 |
17041 | 302 tsc_start = rdtsc(); |
303 gettimeofday(&tv_start, NULL); | |
304 #ifdef MISSING_USLEEP | |
305 sleep(1); | |
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306 #else |
17041 | 307 usleep(100000); |
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308 #endif |
17041 | 309 tsc_end = rdtsc(); |
310 gettimeofday(&tv_end, NULL); | |
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311 |
17041 | 312 usec_delay = 1000000 * (tv_end.tv_sec - tv_start.tv_sec) |
313 + (tv_end.tv_usec - tv_start.tv_usec); | |
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314 |
17041 | 315 printf("cpu MHz\t\t: %.3f\n", |
316 (double)(tsc_end-tsc_start) / usec_delay); | |
317 } | |
318 } | |
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319 |
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320 printf("model name\t: "); |
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321 if (model_name) |
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322 printf("%s\n", model_name); |
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323 else |
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324 printf("Unknown %s CPU\n", idstr); |
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325 } |