Mercurial > mplayer.hg
annotate vidix/nvidia_vid.c @ 25317:7f3cb5408f28
Fixed VIDIX color bug that was introduced when Radeon VIDIX driver
was synchronized with vidix.sf.net.
The red color was saturating.
Corrected value fixes the issue and restore the color to the level
it used to have before synchronization.
Meaning of the value remains unknow but was retrieved from
register's value of a Radeon 9000 card, so it may need further testing.
Patch by Guillaume Lecerf (foxcore at gmail dot com)
author | ben |
---|---|
date | Mon, 10 Dec 2007 19:27:46 +0000 |
parents | f89d135bcae0 |
children | fbc5aa38f1f0 |
rev | line source |
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22850 | 1 /* |
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2 * VIDIX driver for nVidia chipsets. |
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3 * Copyright (C) 2003-2004 Sascha Sommer |
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4 * |
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5 * This file is part of MPlayer. |
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6 * |
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7 * MPlayer is free software; you can redistribute it and/or modify |
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8 * it under the terms of the GNU General Public License as published by |
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9 * the Free Software Foundation; either version 2 of the License, or |
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10 * (at your option) any later version. |
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11 * |
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12 * MPlayer is distributed in the hope that it will be useful, |
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 * GNU General Public License for more details. |
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16 * |
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17 * You should have received a copy of the GNU General Public License |
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18 * along with MPlayer; if not, write to the Free Software |
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19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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20 * |
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21 * This file is based on sources from RIVATV (rivatv.sf.net) |
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22 * Multi buffer support and TNT2 fixes by Dmitry Baryshkov. |
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23 */ |
22850 | 24 |
25 #include <errno.h> | |
26 #include <stdio.h> | |
27 #include <stdlib.h> | |
28 #include <string.h> | |
29 #include <math.h> | |
30 #include <inttypes.h> | |
31 #include <unistd.h> | |
32 | |
33 | |
34 #include "vidix.h" | |
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35 #include "vidixlib.h" |
22850 | 36 #include "fourcc.h" |
22901 | 37 #include "dha.h" |
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38 #include "pci_ids.h" |
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39 #include "pci_names.h" |
22905 | 40 #include "config.h" |
41 #include "libavutil/common.h" | |
42 #include "mpbswap.h" | |
22850 | 43 |
44 | |
23055 | 45 static pciinfo_t pci_info; |
22850 | 46 |
47 | |
48 #define MAX_FRAMES 3 | |
49 #define NV04_BES_SIZE 1024*2000*4 | |
50 | |
51 | |
52 static vidix_capability_t nvidia_cap = { | |
53 "NVIDIA RIVA OVERLAY DRIVER", | |
54 "Sascha Sommer <saschasommer@freenet.de>", | |
55 TYPE_OUTPUT, | |
56 { 0, 0, 0, 0 }, | |
57 2046, | |
58 2046, | |
59 4, | |
60 4, | |
61 -1, | |
62 FLAG_UPSCALER|FLAG_DOWNSCALER, | |
63 VENDOR_NVIDIA2, | |
64 -1, | |
65 { 0, 0, 0, 0 } | |
66 }; | |
67 | |
68 #define NV_ARCH_03 0x03 | |
69 #define NV_ARCH_04 0x04 | |
70 #define NV_ARCH_10 0x10 | |
71 #define NV_ARCH_20 0x20 | |
72 #define NV_ARCH_30 0x30 | |
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73 #define NV_ARCH_40 0x40 |
22850 | 74 |
75 // since no useful information whatsoever is passed | |
76 // to the equalizer functions we need this | |
77 static struct { | |
78 uint32_t lum; // luminance (brightness + contrast) | |
79 uint32_t chrom; // chrominance (saturation + hue) | |
80 uint8_t red_off; // for NV03/NV04 | |
81 uint8_t green_off; | |
82 uint8_t blue_off; | |
83 vidix_video_eq_t vals; | |
84 } eq; | |
85 | |
86 struct nvidia_cards { | |
87 unsigned short chip_id; | |
88 unsigned short arch; | |
89 }; | |
90 | |
91 | |
92 static struct nvidia_cards nvidia_card_ids[] = { | |
93 /*NV03*/ | |
94 {DEVICE_NVIDIA2_RIVA128, NV_ARCH_03}, | |
95 {DEVICE_NVIDIA2_RIVA128ZX,NV_ARCH_03}, | |
96 /*NV04*/ | |
97 {DEVICE_NVIDIA_NV4_RIVA_TNT,NV_ARCH_04}, | |
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98 {DEVICE_NVIDIA_NV5_RIVA_TNT2_TNT2,NV_ARCH_04}, |
22850 | 99 {DEVICE_NVIDIA_NV5_RIVA_TNT2,NV_ARCH_04}, |
100 {DEVICE_NVIDIA_NV5_RIVA_TNT22,NV_ARCH_04}, | |
101 {DEVICE_NVIDIA_NV5_RIVA_TNT23,NV_ARCH_04}, | |
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102 {DEVICE_NVIDIA_NV6_VANTA_VANTA_LT,NV_ARCH_04}, |
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103 {DEVICE_NVIDIA_NV5M64_RIVA_TNT2,NV_ARCH_04}, |
22850 | 104 {DEVICE_NVIDIA_NV6_VANTA,NV_ARCH_04}, |
105 {DEVICE_NVIDIA_NV6_VANTA2,NV_ARCH_04}, | |
106 {DEVICE_NVIDIA2_TNT,NV_ARCH_04}, | |
107 {DEVICE_NVIDIA2_TNT2,NV_ARCH_04}, | |
108 {DEVICE_NVIDIA2_VTNT2,NV_ARCH_04}, | |
109 {DEVICE_NVIDIA2_UTNT2 ,NV_ARCH_04}, | |
110 {DEVICE_NVIDIA2_ITNT2,NV_ARCH_04}, | |
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111 {DEVICE_NVIDIA_NV5_ALADDIN_TNT2,NV_ARCH_04}, |
22850 | 112 /*NV10*/ |
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113 {DEVICE_NVIDIA_NV18_GEFORCE_PCX,NV_ARCH_10}, |
22850 | 114 {DEVICE_NVIDIA_NV10_GEFORCE_256,NV_ARCH_10}, |
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115 {DEVICE_NVIDIA_NV10DDR_GEFORCE_256,NV_ARCH_10}, |
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116 {DEVICE_NVIDIA_NV10GL_QUADRO,NV_ARCH_10}, |
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117 {DEVICE_NVIDIA_NV11_GEFORCE2_MX_MX,NV_ARCH_10}, |
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118 {DEVICE_NVIDIA_NV11DDR_GEFORCE2_MX,NV_ARCH_10}, |
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119 {DEVICE_NVIDIA_NV11DDR_GEFORCE2_MX,NV_ARCH_10}, |
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120 {DEVICE_NVIDIA_NV11_GEFORCE2_GO,NV_ARCH_10}, |
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121 {DEVICE_NVIDIA_NV11GL_QUADRO2_MXR_EX_GO,NV_ARCH_10}, |
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122 {DEVICE_NVIDIA_NV15_GEFORCE2_GTS_PRO,NV_ARCH_10}, |
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123 {DEVICE_NVIDIA_NV15DDR_GEFORCE2_TI,NV_ARCH_10}, |
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124 {DEVICE_NVIDIA_NV15BR_GEFORCE2_ULTRA,NV_ARCH_10}, |
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125 {DEVICE_NVIDIA_NV15GL_QUADRO2_PRO,NV_ARCH_10}, |
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126 {DEVICE_NVIDIA_NV17_GEFORCE4_MX,NV_ARCH_10}, |
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127 {DEVICE_NVIDIA_NV17_GEFORCE4_MX2,NV_ARCH_10}, |
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128 {DEVICE_NVIDIA_NV17_GEFORCE4_MX3,NV_ARCH_10}, |
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129 {DEVICE_NVIDIA_NV17_GEFORCE4_MX4,NV_ARCH_10}, |
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130 {DEVICE_NVIDIA_NV17_GEFORCE4_440,NV_ARCH_10}, |
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131 {DEVICE_NVIDIA_NV17_GEFORCE4_420,NV_ARCH_10}, |
22850 | 132 {DEVICE_NVIDIA_NV17_GEFORCE4_4202,NV_ARCH_10}, |
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133 {DEVICE_NVIDIA_NV17_GEFORCE4_460,NV_ARCH_10}, |
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134 {DEVICE_NVIDIA_NV17GL_QUADRO4_550,NV_ARCH_10}, |
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135 {DEVICE_NVIDIA_NV17_GEFORCE4_4203,NV_ARCH_10}, |
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136 {DEVICE_NVIDIA_NV17GL_QUADRO4_200_400,NV_ARCH_10}, |
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137 {DEVICE_NVIDIA_NV17GL_QUADRO4_5502,NV_ARCH_10}, |
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138 {DEVICE_NVIDIA_NV17GL_QUADRO4_550,NV_ARCH_10}, |
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139 {DEVICE_NVIDIA_NV17_GEFORCE4_410,NV_ARCH_10}, |
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140 {DEVICE_NVIDIA_NV18_GEFORCE4_MX,NV_ARCH_10}, |
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141 {DEVICE_NVIDIA_NV18_GEFORCE4_MX2,NV_ARCH_10}, |
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142 {DEVICE_NVIDIA_NV18_GEFORCE4_MX3,NV_ARCH_10}, |
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143 {DEVICE_NVIDIA_NV18_GEFORCE4_MX4,NV_ARCH_10}, |
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144 {DEVICE_NVIDIA_NV18_GEFORCE4_MX5,NV_ARCH_10}, |
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145 {DEVICE_NVIDIA_NV18M_GEFORCE4_448,NV_ARCH_10}, |
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146 {DEVICE_NVIDIA_NV18M_GEFORCE4_488,NV_ARCH_10}, |
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147 {DEVICE_NVIDIA_NV18GL_QUADRO_FX,NV_ARCH_10}, |
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148 {DEVICE_NVIDIA_NV18GL_QUADRO4_580,NV_ARCH_10}, |
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149 {DEVICE_NVIDIA_NV18GL_QUADRO4_NVS,NV_ARCH_10}, |
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150 {DEVICE_NVIDIA_NV18GL_QUADRO4_380,NV_ARCH_10}, |
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151 {DEVICE_NVIDIA_NV18M_GEFORCE4_4482,NV_ARCH_10}, |
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152 {DEVICE_NVIDIA_NVCRUSH11_GEFORCE2_MX,NV_ARCH_10}, |
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153 {DEVICE_NVIDIA_NV18_GEFORCE4_MX5,NV_ARCH_10}, |
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154 {DEVICE_NVIDIA_NV18_GEFORCE_PCX,NV_ARCH_10}, |
22850 | 155 /*NV20*/ |
156 {DEVICE_NVIDIA_NV20_GEFORCE3,NV_ARCH_20}, | |
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157 {DEVICE_NVIDIA_NV20_GEFORCE3_TI,NV_ARCH_20}, |
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158 {DEVICE_NVIDIA_NV20_GEFORCE3_TI2,NV_ARCH_20}, |
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159 {DEVICE_NVIDIA_NV20DCC_QUADRO_DCC,NV_ARCH_20}, |
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160 {DEVICE_NVIDIA_NV25_GEFORCE4_TI,NV_ARCH_20}, |
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161 {DEVICE_NVIDIA_NV25_GEFORCE4_TI2,NV_ARCH_20}, |
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162 {DEVICE_NVIDIA_NV25_GEFORCE4_TI3,NV_ARCH_20}, |
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163 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4,NV_ARCH_20}, |
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164 {DEVICE_NVIDIA_NV25GL_QUADRO4_900,NV_ARCH_20}, |
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165 {DEVICE_NVIDIA_NV25GL_QUADRO4_750,NV_ARCH_20}, |
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166 {DEVICE_NVIDIA_NV25GL_QUADRO4_700,NV_ARCH_20}, |
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167 {DEVICE_NVIDIA_NV28_GEFORCE4_TI,NV_ARCH_20}, |
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168 {DEVICE_NVIDIA_NV28_GEFORCE4_TI2,NV_ARCH_20}, |
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169 {DEVICE_NVIDIA_NV28_GEFORCE4_TI3,NV_ARCH_20}, |
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170 {DEVICE_NVIDIA_NV28_GEFORCE4_TI4,NV_ARCH_20}, |
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171 {DEVICE_NVIDIA_NV28GL_QUADRO4_980,NV_ARCH_20}, |
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172 {DEVICE_NVIDIA_NV28GL_QUADRO4_780,NV_ARCH_20}, |
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173 {DEVICE_NVIDIA_NV28GLM_QUADRO4_700,NV_ARCH_20}, |
22850 | 174 /*NV30*/ |
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changeset
|
175 {DEVICE_NVIDIA_NV30_GEFORCE_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
176 {DEVICE_NVIDIA_NV30_GEFORCE_FX2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
177 {DEVICE_NVIDIA_NV30_GEFORCE_FX3,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
178 {DEVICE_NVIDIA_NV30GL_QUADRO_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
179 {DEVICE_NVIDIA_NV30GL_QUADRO_FX2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
180 {DEVICE_NVIDIA_NV31_GEFORCE_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
181 {DEVICE_NVIDIA_NV31_GEFORCE_FX2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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changeset
|
182 {DEVICE_NVIDIA_NV31,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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changeset
|
183 {DEVICE_NVIDIA_NV31_GEFORCE_FX3,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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changeset
|
184 {DEVICE_NVIDIA_NV31M,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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changeset
|
185 {DEVICE_NVIDIA_NV31M_PRO,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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changeset
|
186 {DEVICE_NVIDIA_NV31M_GEFORCE_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
187 {DEVICE_NVIDIA_NV31M_GEFORCE_FX2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
188 {DEVICE_NVIDIA_NVIDIA_QUADRO_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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changeset
|
189 {DEVICE_NVIDIA_NV31GLM,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
190 {DEVICE_NVIDIA_NV31GLM_PRO,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
191 {DEVICE_NVIDIA_NV31GLM_PRO2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
192 {DEVICE_NVIDIA_NV34_GEFORCE_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
193 {DEVICE_NVIDIA_NV34_GEFORCE_FX2,NV_ARCH_30}, |
22850 | 194 {DEVICE_NVIDIA_NV34_GEFORCE_FX3,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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|
195 {DEVICE_NVIDIA_NV34_GEFORCE_FX4,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
196 {DEVICE_NVIDIA_NV34M_GEFORCE_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
197 {DEVICE_NVIDIA_NV34M_GEFORCE_FX2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
198 {DEVICE_NVIDIA_NV34_GEFORCE_FX5,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
199 {DEVICE_NVIDIA_NV34_GEFORCE_FX6,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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changeset
|
200 {DEVICE_NVIDIA_NV34M_GEFORCE_FX3,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
201 {DEVICE_NVIDIA_NV34M_GEFORCE_FX4,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
202 {DEVICE_NVIDIA_NV34GL_QUADRO_NVS,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
203 {DEVICE_NVIDIA_NV34GL_QUADRO_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
204 {DEVICE_NVIDIA_NV34GLM_GEFORCE_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
205 {DEVICE_NVIDIA_NV34_GEFORCE_FX7,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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changeset
|
206 {DEVICE_NVIDIA_NV34GL,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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changeset
|
207 {DEVICE_NVIDIA_NV35_GEFORCE_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
208 {DEVICE_NVIDIA_NV35_GEFORCE_FX2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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changeset
|
209 {DEVICE_NVIDIA_NV35_GEFORCE_FX3,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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changeset
|
210 {DEVICE_NVIDIA_NV38_GEFORCE_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
211 {DEVICE_NVIDIA_NV35_GEFORCE_FX4,NV_ARCH_30}, |
22850 | 212 {DEVICE_NVIDIA_NV35GL_QUADRO_FX,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
213 {DEVICE_NVIDIA_NV35GL_QUADRO_FX2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
214 {DEVICE_NVIDIA_NV35_GEFORCE_PCX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
215 {DEVICE_NVIDIA_NV36_1_GEFORCE_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
216 {DEVICE_NVIDIA_NV36_2_GEFORCE_FX,NV_ARCH_30}, |
22850 | 217 {DEVICE_NVIDIA_NV36_GEFORCE_FX,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
218 {DEVICE_NVIDIA_NV36_4_GEFORCE_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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changeset
|
219 {DEVICE_NVIDIA_NV36_5,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
220 {DEVICE_NVIDIA_NV36_GEFORCE_FX2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
221 {DEVICE_NVIDIA_NV36_GEFORCE_FX3,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
222 {DEVICE_NVIDIA_NV36_GEFORCE_PCX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
223 {DEVICE_NVIDIA_NV36M_PRO,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
224 {DEVICE_NVIDIA_NV36MAP,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
225 {DEVICE_NVIDIA_NV36_QUADRO_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
226 {DEVICE_NVIDIA_NV36GL_QUADRO_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
227 {DEVICE_NVIDIA_NV36GL,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
228 {DEVICE_NVIDIA_NV36_GEFORCE_PCX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
229 {DEVICE_NVIDIA_NV35_GEFORCE_PCX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
230 {DEVICE_NVIDIA_NV37GL_QUADRO_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
231 {DEVICE_NVIDIA_NV37GL_QUADRO_FX2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
232 {DEVICE_NVIDIA_NV38GL_QUADRO_FX,NV_ARCH_30}, |
22880
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
233 /* NV40: GeForce 6x00 to 7x00 */ |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
234 {DEVICE_NVIDIA_NV40_GEFORCE_6800,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
235 {DEVICE_NVIDIA_NV40_GEFORCE_68002,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
236 {DEVICE_NVIDIA_NV40_2_GEFORCE_6800,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
237 {DEVICE_NVIDIA_NV40_3,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
238 {DEVICE_NVIDIA_NV40_GEFORCE_68003,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
239 {DEVICE_NVIDIA_NV40_GEFORCE_68004,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
240 {DEVICE_NVIDIA_NV40_GEFORCE_68005,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
241 {DEVICE_NVIDIA_NV40_GEFORCE_68006,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
242 {DEVICE_NVIDIA_NV40_GEFORCE_68007,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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changeset
|
243 {DEVICE_NVIDIA_NV40_GEFORCE_68008,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
244 {DEVICE_NVIDIA_NV40_GEFORCE_68009,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
245 {DEVICE_NVIDIA_NV40_GEFORCE_680010,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
246 {DEVICE_NVIDIA_NV40_GEFORCE_680011,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
247 {DEVICE_NVIDIA_NV40_GEFORCE_680012,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
248 {DEVICE_NVIDIA_NV40_GEFORCE_68008,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
249 {DEVICE_NVIDIA_NV40GL,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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changeset
|
250 {DEVICE_NVIDIA_NV40GL_QUADRO_FX,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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changeset
|
251 {DEVICE_NVIDIA_NV40GL_QUADRO_FX2,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
252 {DEVICE_NVIDIA_NV41_GEFORCE_6800,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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changeset
|
253 {DEVICE_NVIDIA_NV41_1_GEFORCE_6800,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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changeset
|
254 {DEVICE_NVIDIA_NV41_2_GEFORCE_6800,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
255 {DEVICE_NVIDIA_NV41_8_GEFORCE_GO,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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changeset
|
256 {DEVICE_NVIDIA_NV41_9_GEFORCE_GO,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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changeset
|
257 {DEVICE_NVIDIA_NV41_QUADRO_FX,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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changeset
|
258 {DEVICE_NVIDIA_NV41_QUADRO_FX2,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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changeset
|
259 {DEVICE_NVIDIA_NV41GL_QUADRO_FX,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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changeset
|
260 {DEVICE_NVIDIA_NV41GL_QUADRO_FX,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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diff
changeset
|
261 {DEVICE_NVIDIA_NV40_GEFORCE_6800_GEFORCE,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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diff
changeset
|
262 {DEVICE_NVIDIA_NV43_GEFORCE_6600_GEFORCE,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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diff
changeset
|
263 {DEVICE_NVIDIA_NV43_GEFORCE_6600_GEFORCE2,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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diff
changeset
|
264 {DEVICE_NVIDIA_NV43_GEFORCE_6200,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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changeset
|
265 {DEVICE_NVIDIA_NV43_GEFORCE_62002,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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changeset
|
266 {DEVICE_NVIDIA_NV43_GEFORCE_6600,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
267 {DEVICE_NVIDIA_NV43_GEFORCE_66002,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
268 {DEVICE_NVIDIA_NV43_GEFORCE_66003,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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changeset
|
269 {DEVICE_NVIDIA_NV43_GEFORCE_66004,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
270 {DEVICE_NVIDIA_NV43_GEFORCE_66005,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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changeset
|
271 {DEVICE_NVIDIA_NV43_GEFORCE_GO,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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diff
changeset
|
272 {DEVICE_NVIDIA_NV43_GEFORCE_GO2,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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diff
changeset
|
273 {DEVICE_NVIDIA_NV43_GEFORCE_GO3,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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diff
changeset
|
274 {DEVICE_NVIDIA_NV43_GEFORCE_GO4,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
22874
diff
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275 {DEVICE_NVIDIA_NV43_GEFORCE_GO5,NV_ARCH_40}, |
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276 {DEVICE_NVIDIA_NV43_GEFORCE_GO6,NV_ARCH_40}, |
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277 {DEVICE_NVIDIA_NV43_GEFORCE_6610,NV_ARCH_40}, |
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278 {DEVICE_NVIDIA_NV43GL_QUADRO_FX,NV_ARCH_40}, |
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279 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE,NV_ARCH_40}, |
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280 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE2,NV_ARCH_40}, |
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281 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE3,NV_ARCH_40}, |
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282 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE4,NV_ARCH_40}, |
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283 {DEVICE_NVIDIA_C51G_GEFORCE_6100,NV_ARCH_40}, |
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284 {DEVICE_NVIDIA_C51PV_GEFORCE_6150,NV_ARCH_40}, |
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285 {DEVICE_NVIDIA_NV44_GEFORCE_6200,NV_ARCH_40}, |
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286 {DEVICE_NVIDIA_NV44_GEFORCE_62002,NV_ARCH_40}, |
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287 {DEVICE_NVIDIA_NV44_GEFORCE_62003,NV_ARCH_40}, |
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288 {DEVICE_NVIDIA_NV44_GEFORCE_GO,NV_ARCH_40}, |
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289 {DEVICE_NVIDIA_NV44_QUADRO_NVS,NV_ARCH_40}, |
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290 {DEVICE_NVIDIA_GEFORCE_GO_6200,NV_ARCH_40}, |
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291 {DEVICE_NVIDIA_NV44A_GEFORCE_6200,NV_ARCH_40}, |
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292 {DEVICE_NVIDIA_NV45GL_QUADRO_FX,NV_ARCH_40}, |
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293 {DEVICE_NVIDIA_GEFORCE_GO_7200,NV_ARCH_40}, |
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294 {DEVICE_NVIDIA_QUADRO_NVS_110M,NV_ARCH_40}, |
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295 {DEVICE_NVIDIA_GEFORCE_GO_7400,NV_ARCH_40}, |
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296 {DEVICE_NVIDIA_QUADRO_NVS_110M2,NV_ARCH_40}, |
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297 {DEVICE_NVIDIA_QUADRO_FX_350,NV_ARCH_40}, |
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298 {DEVICE_NVIDIA_G70_GEFORCE_7300,NV_ARCH_40}, |
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299 {DEVICE_NVIDIA_GEFORCE_7300_GS,NV_ARCH_40}, |
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300 {DEVICE_NVIDIA_G70_GEFORCE_7600,NV_ARCH_40}, |
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301 {DEVICE_NVIDIA_G70_GEFORCE_76002,NV_ARCH_40}, |
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302 {DEVICE_NVIDIA_GEFORCE_7600_GS,NV_ARCH_40}, |
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303 {DEVICE_NVIDIA_G70_GEFORCE_GO,NV_ARCH_40}, |
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304 {DEVICE_NVIDIA_QUADRO_FX_560,NV_ARCH_40}, |
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305 {DEVICE_NVIDIA_G70_GEFORCE_7800,NV_ARCH_40}, |
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306 {DEVICE_NVIDIA_G70_GEFORCE_78002,NV_ARCH_40}, |
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307 {DEVICE_NVIDIA_G70_GEFORCE_78003,NV_ARCH_40}, |
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308 {DEVICE_NVIDIA_G70_GEFORCE_78004,NV_ARCH_40}, |
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309 {DEVICE_NVIDIA_G70_GEFORCE_78005,NV_ARCH_40}, |
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310 {DEVICE_NVIDIA_GEFORCE_GO_7800,NV_ARCH_40}, |
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311 {DEVICE_NVIDIA_GEFORCE_7900_GTX,NV_ARCH_40}, |
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312 {DEVICE_NVIDIA_GEFORCE_7900_GT,NV_ARCH_40}, |
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313 {DEVICE_NVIDIA_GEFORCE_7900_GS,NV_ARCH_40}, |
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314 {DEVICE_NVIDIA_GEFORCE_GO_7900,NV_ARCH_40}, |
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315 {DEVICE_NVIDIA_GEFORCE_GO_79002,NV_ARCH_40}, |
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316 {DEVICE_NVIDIA_GE_FORCE_GO,NV_ARCH_40}, |
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317 {DEVICE_NVIDIA_G70GL_QUADRO_FX4500,NV_ARCH_40}, |
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318 {DEVICE_NVIDIA_G71_QUADRO_FX,NV_ARCH_40}, |
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319 {DEVICE_NVIDIA_G71_QUADRO_FX2,NV_ARCH_40} |
22850 | 320 }; |
321 | |
322 | |
323 static int find_chip(unsigned chip_id){ | |
324 unsigned i; | |
325 for(i = 0;i < sizeof(nvidia_card_ids)/sizeof(struct nvidia_cards);i++) | |
326 { | |
327 if(chip_id == nvidia_card_ids[i].chip_id)return i; | |
328 } | |
329 return -1; | |
330 } | |
331 | |
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332 static int nv_probe(int verbose, int force){ |
22850 | 333 pciinfo_t lst[MAX_PCI_DEVICES]; |
334 unsigned i,num_pci; | |
335 int err; | |
336 | |
337 if (force) | |
338 printf("[nvidia_vid]: warning: forcing not supported yet!\n"); | |
339 err = pci_scan(lst,&num_pci); | |
340 if(err){ | |
341 printf("[nvidia_vid] Error occurred during pci scan: %s\n",strerror(err)); | |
342 return err; | |
343 } | |
344 else { | |
345 err = ENXIO; | |
346 for(i=0; i < num_pci; i++){ | |
347 if(lst[i].vendor == VENDOR_NVIDIA2 || lst[i].vendor == VENDOR_NVIDIA){ | |
348 int idx; | |
349 const char *dname; | |
350 idx = find_chip(lst[i].device); | |
351 if(idx == -1) | |
352 continue; | |
353 dname = pci_device_name(lst[i].vendor, lst[i].device); | |
354 dname = dname ? dname : "Unknown chip"; | |
355 printf("[nvidia_vid] Found chip: %s\n", dname); | |
356 if ((lst[i].command & PCI_COMMAND_IO) == 0){ | |
357 printf("[nvidia_vid] Device is disabled, ignoring\n"); | |
358 continue; | |
359 } | |
360 nvidia_cap.device_id = lst[i].device; | |
361 err = 0; | |
362 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); | |
363 break; | |
364 } | |
365 } | |
366 } | |
367 if(err && verbose) printf("[nvidia_vid] Can't find chip\n"); | |
368 return err; | |
369 } | |
370 | |
371 | |
372 | |
373 | |
374 /* | |
375 * PCI-Memory IO access macros. | |
376 */ | |
377 | |
378 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") | |
379 | |
380 #undef VID_WR08 | |
381 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) | |
382 #undef VID_RD08 | |
383 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) | |
384 | |
385 #undef VID_WR32 | |
386 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=val; }) | |
387 #undef VID_RD32 | |
388 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) | |
389 | |
390 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) | |
391 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) | |
392 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) | |
393 | |
394 | |
395 | |
396 | |
397 | |
398 | |
399 struct rivatv_chip { | |
400 volatile uint32_t *PMC; /* general control */ | |
401 volatile uint32_t *PME; /* multimedia port */ | |
402 volatile uint32_t *PFB; /* framebuffer control */ | |
403 volatile uint32_t *PVIDEO; /* overlay control */ | |
404 volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ | |
405 volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ | |
406 volatile uint32_t *PRAMIN; /* instance memory */ | |
407 volatile uint32_t *PRAMHT; /* hash table */ | |
408 volatile uint32_t *PRAMFC; /* fifo context table */ | |
409 volatile uint32_t *PRAMRO; /* fifo runout table */ | |
410 volatile uint32_t *PFIFO; /* fifo control region */ | |
411 volatile uint32_t *FIFO; /* fifo channels (USER) */ | |
412 volatile uint32_t *PGRAPH; /* graphics engine */ | |
413 | |
414 unsigned long fbsize; /* framebuffer size */ | |
415 int arch; /* compatible NV_ARCH_XX define */ | |
416 int realarch; /* real architecture */ | |
417 void (* lock) (struct rivatv_chip *, int); | |
418 }; | |
419 typedef struct rivatv_chip rivatv_chip; | |
420 | |
421 | |
422 struct rivatv_info { | |
423 unsigned int use_colorkey; | |
424 unsigned int colorkey; /* saved xv colorkey*/ | |
425 unsigned int vidixcolorkey; /*currently used colorkey*/ | |
426 unsigned int depth; | |
427 unsigned int format; | |
428 unsigned int pitch; | |
429 unsigned int width,height; | |
430 unsigned int d_width,d_height; /*scaled width && height*/ | |
431 unsigned int wx,wy; /*window x && y*/ | |
432 unsigned int screen_x; /*screen width*/ | |
433 unsigned int screen_y; /*screen height*/ | |
434 unsigned long buffer_size; /* size of the image buffer */ | |
435 struct rivatv_chip chip; /* NV architecture structure */ | |
436 void* video_base; /* virtual address of control region */ | |
437 void* control_base; /* virtual address of fb region */ | |
438 void* picture_base; /* direct pointer to video picture */ | |
439 unsigned long picture_offset; /* offset of video picture in frame buffer */ | |
440 // struct rivatv_dma dma; /* DMA structure */ | |
441 unsigned int cur_frame; | |
442 unsigned int num_frames; /* number of buffers */ | |
443 int bps; /* bytes per line */ | |
444 }; | |
445 typedef struct rivatv_info rivatv_info; | |
446 | |
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447 uint8_t nvReadVGA (struct rivatv_chip *chip, int index) { |
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448 VID_WR08 (chip->PCIO, 0x3D4, index); |
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449 return VID_RD08 (chip->PCIO, 0x3D5); |
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450 } |
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451 |
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452 void nvWriteVGA (struct rivatv_chip *chip, int index, int data) { |
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453 VID_WR08 (chip->PCIO, 0x3D4, index); |
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454 VID_WR08 (chip->PCIO, 0x3D5, data); |
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455 } |
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456 |
22850 | 457 //framebuffer size funcs |
458 static unsigned long rivatv_fbsize_nv03 (struct rivatv_chip *chip){ | |
459 if (VID_RD32 (chip->PFB, 0) & 0x00000020) { | |
460 if (((VID_RD32 (chip->PMC, 0) & 0xF0) == 0x20) | |
461 && ((VID_RD32 (chip->PMC, 0) & 0x0F) >= 0x02)) { | |
462 /* SDRAM 128 ZX. */ | |
463 return ((1 << (VID_RD32 (chip->PFB, 0) & 0x03)) * 1024 * 1024); | |
464 } | |
465 else { | |
466 return 1024 * 1024 * 8; | |
467 } | |
468 } | |
469 else { | |
470 /* SGRAM 128. */ | |
471 switch (VID_RD32(chip->PFB, 0) & 0x00000003) { | |
472 case 0: | |
473 return 1024 * 1024 * 8; | |
474 break; | |
475 case 2: | |
476 return 1024 * 1024 * 4; | |
477 break; | |
478 default: | |
479 return 1024 * 1024 * 2; | |
480 break; | |
481 } | |
482 } | |
483 } | |
484 static unsigned long rivatv_fbsize_nv04 (struct rivatv_chip *chip){ | |
485 if (VID_RD32 (chip->PFB, 0) & 0x00000100) { | |
486 return ((VID_RD32 (chip->PFB, 0) >> 12) & 0x0F) * 1024 * 1024 * 2 | |
487 + 1024 * 1024 * 2; | |
488 } else { | |
489 switch (VID_RD32 (chip->PFB, 0) & 0x00000003) { | |
490 case 0: | |
491 return 1024 * 1024 * 32; | |
492 break; | |
493 case 1: | |
494 return 1024 * 1024 * 4; | |
495 break; | |
496 case 2: | |
497 return 1024 * 1024 * 8; | |
498 break; | |
499 case 3: | |
500 default: | |
501 return 1024 * 1024 * 16; | |
502 break; | |
503 } | |
504 } | |
505 } | |
506 | |
507 static unsigned long rivatv_fbsize_nv10 (struct rivatv_chip *chip){ | |
508 return VID_RD32 (chip->PFB, 0x20C) & 0xFFF00000; | |
509 } | |
510 | |
511 //lock funcs | |
512 static void rivatv_lock_nv03 (struct rivatv_chip *chip, int LockUnlock){ | |
513 VID_WR08 (chip->PVIO, 0x3C4, 0x06); | |
514 VID_WR08 (chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57); | |
515 } | |
516 | |
517 static void rivatv_lock_nv04 (struct rivatv_chip *chip, int LockUnlock){ | |
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518 rivatv_lock_nv03 (chip, LockUnlock); |
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519 nvWriteVGA (chip, 0x1F, LockUnlock ? 0x99 : 0x57); |
22850 | 520 } |
521 | |
522 | |
523 | |
524 | |
525 /* Enable PFB (Framebuffer), PVIDEO (Overlay unit) and PME (Mediaport) if neccessary. */ | |
526 static void rivatv_enable_PMEDIA (struct rivatv_info *info){ | |
527 uint32_t reg; | |
528 | |
529 /* switch off interrupts once for a while */ | |
530 // VID_WR32 (info->chip.PME, 0x200140, 0x00); | |
531 // VID_WR32 (info->chip.PMC, 0x000140, 0x00); | |
532 | |
533 reg = VID_RD32 (info->chip.PMC, 0x000200); | |
534 | |
535 /* NV3 (0x10100010): NV03_PMC_ENABLE_PMEDIA, NV03_PMC_ENABLE_PFB, NV03_PMC_ENABLE_PVIDEO */ | |
536 | |
537 if ((reg & 0x10100010) != 0x10100010) { | |
538 printf("PVIDEO and PFB disabled, enabling...\n"); | |
539 VID_OR32 (info->chip.PMC, 0x000200, 0x10100010); | |
540 } | |
541 | |
542 /* save the current colorkey */ | |
543 switch (info->chip.arch ) { | |
544 case NV_ARCH_10: | |
545 case NV_ARCH_20: | |
546 case NV_ARCH_30: | |
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547 case NV_ARCH_40: |
22850 | 548 /* NV_PVIDEO_COLOR_KEY */ |
549 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0xB00); | |
550 break; | |
551 case NV_ARCH_03: | |
552 case NV_ARCH_04: | |
553 /* NV_PVIDEO_KEY */ | |
554 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0x240); | |
555 break; | |
556 } | |
557 | |
558 | |
559 /* re-enable interrupts again */ | |
560 // VID_WR32 (info->chip.PMC, 0x000140, 0x01); | |
561 // VID_WR32 (info->chip.PME, 0x200140, 0x01); | |
562 } | |
563 | |
564 /* Stop overlay video. */ | |
565 static void rivatv_overlay_stop (struct rivatv_info *info) { | |
566 switch (info->chip.arch ) { | |
567 case NV_ARCH_10: | |
568 case NV_ARCH_20: | |
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569 case NV_ARCH_30: |
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570 case NV_ARCH_40: |
22850 | 571 /* NV_PVIDEO_COLOR_KEY */ |
572 /* Xv-Extension-Hack: Restore previously saved value. */ | |
573 VID_WR32 (info->chip.PVIDEO, 0xB00, info->colorkey); | |
574 /* NV_PVIDEO_STOP */ | |
575 VID_OR32 (info->chip.PVIDEO, 0x704, 0x11); | |
576 /* NV_PVIDEO_BUFFER */ | |
577 VID_AND32 (info->chip.PVIDEO, 0x700, ~0x11); | |
578 /* NV_PVIDEO_INTR_EN_BUFFER */ | |
579 // VID_AND32 (info->chip.PVIDEO, 0x140, ~0x11); | |
580 break; | |
581 case NV_ARCH_03: | |
582 case NV_ARCH_04: | |
583 /* NV_PVIDEO_KEY */ | |
584 VID_WR32 (info->chip.PVIDEO, 0x240, info->colorkey); | |
585 /* NV_PVIDEO_OVERLAY_VIDEO_OFF */ | |
586 VID_AND32 (info->chip.PVIDEO, 0x244, ~0x01); | |
587 /* NV_PVIDEO_INTR_EN_0_NOTIFY */ | |
588 // VID_AND32 (info->chip.PVIDEO, 0x140, ~0x01); | |
589 /* NV_PVIDEO_OE_STATE */ | |
590 VID_WR32 (info->chip.PVIDEO, 0x224, 0); | |
591 /* NV_PVIDEO_SU_STATE */ | |
592 VID_WR32 (info->chip.PVIDEO, 0x228, 0); | |
593 /* NV_PVIDEO_RM_STATE */ | |
594 VID_WR32 (info->chip.PVIDEO, 0x22C, 0); | |
595 break; | |
596 } | |
597 } | |
598 | |
599 /* Get pan offset of the physical screen. */ | |
600 static uint32_t rivatv_overlay_pan (struct rivatv_info *info){ | |
601 uint32_t pan; | |
602 info->chip.lock (&info->chip, 0); | |
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603 pan = nvReadVGA (&info->chip, 0x0D); |
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604 pan |= nvReadVGA (&info->chip, 0x0C) << 8; |
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605 pan |= (nvReadVGA (&info->chip, 0x19) & 0x1F) << 16; |
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606 pan |= (nvReadVGA (&info->chip, 0x2D) & 0x60) << 16; |
22850 | 607 return pan << 2; |
608 } | |
609 | |
610 /* Compute and set colorkey depending on the colour depth. */ | |
611 static void rivatv_overlay_colorkey (rivatv_info* info, unsigned int chromakey){ | |
612 uint32_t r, g, b, key = 0; | |
613 | |
614 r = (chromakey & 0x00FF0000) >> 16; | |
615 g = (chromakey & 0x0000FF00) >> 8; | |
616 b = chromakey & 0x000000FF; | |
617 switch (info->depth) { | |
618 case 15: | |
619 key = ((r >> 3) << 10) | ((g >> 3) << 5) | ((b >> 3)); | |
620 #ifndef WIN32 | |
621 key = key | 0x00008000; | |
622 #endif | |
623 break; | |
624 case 16: // XXX unchecked | |
625 key = ((r >> 3) << 11) | ((g >> 2) << 5) | ((b >> 3)); | |
626 #ifndef WIN32 | |
627 key = key | 0x00008000; | |
628 #endif | |
629 break; | |
630 case 24: // XXX unchecked, maybe swap order of masking - FIXME Can the card be in 24 bit mode anyway? | |
631 key = (chromakey & 0x00FFFFFF) | 0x00800000; | |
632 break; | |
633 case 32: | |
634 key = chromakey; | |
635 #ifndef WIN32 | |
636 key = key | 0x80000000; | |
637 #endif | |
638 break; | |
639 } | |
640 //printf("[nvidia_vid] depth=%d %08X \n", info->depth, chromakey); | |
641 switch (info->chip.arch) { | |
642 case NV_ARCH_10: | |
643 case NV_ARCH_20: | |
644 case NV_ARCH_30: | |
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645 case NV_ARCH_40: |
22850 | 646 VID_WR32 (info->chip.PVIDEO, 0xB00, key); |
647 break; | |
648 case NV_ARCH_03: | |
649 case NV_ARCH_04: | |
650 VID_WR32 (info->chip.PVIDEO, 0x240, key); | |
651 break; | |
652 } | |
653 } | |
654 | |
655 static void nv_getscreenproperties(struct rivatv_info *info){ | |
656 uint32_t bpp=0,x; | |
657 info->chip.lock(&info->chip, 0); | |
658 /*get screen depth*/ | |
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659 bpp = nvReadVGA (&info->chip, 0x28) & 0x3; |
22850 | 660 if((bpp == 2) && (VID_RD32(info->chip.PVIDEO,0x600) & 0x00001000) == 0x0)info->depth=15; |
661 else info->depth = 0x04 << bpp; | |
662 /*get screen width*/ | |
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663 info->screen_x = nvReadVGA (&info->chip, 0x1); |
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664 /* NV_PCRTC_HORIZ_EXTRA_DISPLAY_END_8 */ |
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665 info->screen_x |= (nvReadVGA (&info->chip, 0x2D) & 0x02) << 7; |
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666 info->screen_x = (info->screen_x + 1) << 3; |
22850 | 667 /*get screen height*/ |
668 /* get first 8 bits in VT_DISPLAY_END*/ | |
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669 info->screen_y = nvReadVGA (&info->chip, 0x12); |
22850 | 670 /* get 9th bit in CRTC_OVERFLOW*/ |
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671 info->screen_y |= (nvReadVGA (&info->chip, 0x07) & 0x02) << 7; |
22850 | 672 /* and the 10th in CRTC_OVERFLOW*/ |
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673 info->screen_y |= (nvReadVGA (&info->chip, 0x07) & 0x40) << 3; |
22850 | 674 ++info->screen_y; |
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675 |
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676 if(info->chip.arch >= NV_ARCH_10){ |
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677 /* NV_PCRTC_EXTRA_VERT_DISPLAY_END_10 */ |
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678 info->screen_y |= (nvReadVGA (&info->chip, 0x25) & 0x02) << 9; |
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679 /* NV_PCRTC_???_VERT_DISPLAY_END_11 */ |
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680 info->screen_y |= (nvReadVGA (&info->chip, 0x41) & 0x04) << 9; |
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681 } |
22850 | 682 |
683 /* NV_PCRTC_OFFSET */ | |
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684 x = nvReadVGA (&info->chip, 0x13); |
22850 | 685 /* NV_PCRTC_REPAINT0_OFFSET_10_8 */ |
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686 x |= (nvReadVGA (&info->chip, 0x19) & 0xE0) << 3; |
22850 | 687 /* NV_PCRTC_EXTRA_OFFSET_11 */ |
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688 x |= (nvReadVGA (&info->chip, 0x25) & 0x20) << 6; x <<= 3; |
22850 | 689 info->bps = x * bpp; |
690 } | |
691 | |
692 | |
693 | |
694 | |
695 /* Start overlay video. */ | |
696 static void rivatv_overlay_start (struct rivatv_info *info,int bufno){ | |
697 uint32_t base, size, offset, xscale, yscale, pan; | |
698 uint32_t value; | |
699 int x=info->wx, y=info->wy; | |
700 int lwidth=info->d_width, lheight=info->d_height; | |
701 | |
702 size = info->buffer_size; | |
703 base = info->picture_offset; | |
704 offset = bufno*size; | |
705 /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/ | |
706 nv_getscreenproperties(info); | |
707 | |
708 if(info->depth){ | |
709 /* get pan offset of the physical screen */ | |
710 pan = rivatv_overlay_pan (info); | |
711 /* adjust window position depending on the pan offset */ | |
712 if (info->bps != 0) | |
713 { | |
714 x = info->wx - (pan % info->bps) * 8 / info->depth; | |
715 y = info->wy - (pan / info->bps); | |
716 } | |
717 } else { | |
718 // we can't adjust the window position correctly in textmode | |
719 // setting y to 8 seems to work ok, though | |
720 if(info->chip.arch < NV_ARCH_10 && y < 8) y = 8; | |
721 } | |
722 | |
723 /* adjust negative output window variables */ | |
724 if (x < 0) { | |
725 lwidth = info->d_width + x; | |
726 offset += (-x * info->width / info->d_width) << 1; | |
727 // offset += (-window->x * port->vld_width / window->width) << 1; | |
728 x = 0; | |
729 } | |
730 if (y < 0) { | |
731 lheight = info->d_height + y; | |
732 offset += (-y * info->height / info->d_height * info->width) << 1; | |
733 // offset += (-window->y * port->vld_height / window->height * port->org_width) << 1; | |
734 y = 0; | |
735 } | |
736 | |
737 switch (info->chip.arch) { | |
738 case NV_ARCH_10: | |
739 case NV_ARCH_20: | |
740 case NV_ARCH_30: | |
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741 case NV_ARCH_40: |
22850 | 742 |
743 /* NV_PVIDEO_BASE */ | |
744 VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base + offset); | |
745 //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base); | |
746 /* NV_PVIDEO_LIMIT */ | |
747 VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + offset + size - 1); | |
748 //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1); | |
749 | |
750 /* extra code for NV20 && NV30 architectures */ | |
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751 if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30 || info->chip.arch == NV_ARCH_40) { |
22850 | 752 VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base + offset); |
753 //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base); | |
754 VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + offset + size - 1); | |
755 //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1); | |
756 } | |
757 | |
758 /* NV_PVIDEO_LUMINANCE */ | |
759 VID_WR32 (info->chip.PVIDEO, 0x910 + 0, eq.lum); | |
760 //VID_WR32 (info->chip.PVIDEO, 0x910 + 4, 0x00001000); | |
761 /* NV_PVIDEO_CHROMINANCE */ | |
762 VID_WR32 (info->chip.PVIDEO, 0x918 + 0, eq.chrom); | |
763 //VID_WR32 (info->chip.PVIDEO, 0x918 + 4, 0x00001000); | |
764 | |
765 /* NV_PVIDEO_OFFSET */ | |
766 VID_WR32 (info->chip.PVIDEO, 0x920 + 0, 0x0); | |
767 //VID_WR32 (info->chip.PVIDEO, 0x920 + 4, offset + pitch); | |
768 /* NV_PVIDEO_SIZE_IN */ | |
769 VID_WR32 (info->chip.PVIDEO, 0x928 + 0, ((info->height) << 16) | info->width); | |
770 //VID_WR32 (info->chip.PVIDEO, 0x928 + 4, ((port->org_height/2) << 16) | port->org_width); | |
771 /* NV_PVIDEO_POINT_IN */ | |
772 VID_WR32 (info->chip.PVIDEO, 0x930 + 0, 0x00000000); | |
773 //VID_WR32 (info->chip.PVIDEO, 0x930 + 4, 0x00000000); | |
774 /* NV_PVIDEO_DS_DX_RATIO */ | |
775 VID_WR32 (info->chip.PVIDEO, 0x938 + 0, (info->width << 20) / info->d_width); | |
776 //VID_WR32 (info->chip.PVIDEO, 0x938 + 4, (port->org_width << 20) / window->width); | |
777 /* NV_PVIDEO_DT_DY_RATIO */ | |
778 VID_WR32 (info->chip.PVIDEO, 0x940 + 0, ((info->height) << 20) / info->d_height); | |
779 //VID_WR32 (info->chip.PVIDEO, 0x940 + 4, ((port->org_height/2) << 20) / window->height); | |
780 | |
781 /* NV_PVIDEO_POINT_OUT */ | |
782 VID_WR32 (info->chip.PVIDEO, 0x948 + 0, ((y + 0) << 16) | x); | |
783 //VID_WR32 (info->chip.PVIDEO, 0x948 + 4, ((y + 0) << 16) | x); | |
784 /* NV_PVIDEO_SIZE_OUT */ | |
785 VID_WR32 (info->chip.PVIDEO, 0x950 + 0, (lheight << 16) | lwidth); | |
786 //VID_WR32 (info->chip.PVIDEO, 0x950 + 4, (height << 16) | width); | |
787 | |
788 /* NV_PVIDEO_FORMAT */ | |
789 value = info->pitch; | |
790 if(info->use_colorkey)value |= 1 << 20; | |
791 if(info->format == IMGFMT_YUY2)value |= 1 << 16; | |
792 VID_WR32 (info->chip.PVIDEO, 0x958 + 0, value); | |
793 //VID_WR32 (info->chip.PVIDEO, 0x958 + 4, (pitch << 1) | 0x00100000); | |
794 | |
795 /* NV_PVIDEO_INTR_EN_BUFFER */ | |
796 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01/*0x11*/); | |
797 /* NV_PVIDEO_STOP */ | |
798 VID_WR32 (info->chip.PVIDEO, 0x704,0x0); | |
799 /* NV_PVIDEO_BUFFER */ | |
800 VID_WR32 (info->chip.PVIDEO, 0x700, 0x01/*0x11*/); | |
801 break; | |
802 | |
803 case NV_ARCH_03: | |
804 case NV_ARCH_04: | |
805 | |
806 | |
807 /* NV_PVIDEO_OE_STATE */ | |
808 VID_WR32 (info->chip.PVIDEO, 0x224, 0); | |
809 /* NV_PVIDEO_SU_STATE */ | |
810 VID_WR32 (info->chip.PVIDEO, 0x228, 0); | |
811 /* NV_PVIDEO_RM_STATE */ | |
812 VID_WR32 (info->chip.PVIDEO, 0x22C, 0); | |
813 | |
814 /* NV_PVIDEO_BUFF0_START_ADDRESS */ | |
815 VID_WR32 (info->chip.PVIDEO, 0x20C + 0, base + offset + 0); | |
816 VID_WR32 (info->chip.PVIDEO, 0x20C + 4, base + offset + 0); | |
817 /* NV_PVIDEO_BUFF0_PITCH_LENGTH */ | |
818 VID_WR32 (info->chip.PVIDEO, 0x214 + 0, info->pitch); | |
819 VID_WR32 (info->chip.PVIDEO, 0x214 + 4, info->pitch); | |
820 | |
821 /* NV_PVIDEO_WINDOW_START */ | |
822 VID_WR32 (info->chip.PVIDEO, 0x230, (y << 16) | x); | |
823 /* NV_PVIDEO_WINDOW_SIZE */ | |
824 VID_WR32 (info->chip.PVIDEO, 0x234, (lheight << 16) | lwidth); | |
825 /* NV_PVIDEO_STEP_SIZE */ | |
826 yscale = ((info->height - 1) << 11) / (info->d_height - 1); | |
827 xscale = ((info->width - 1) << 11) / (info->d_width - 1); | |
828 VID_WR32 (info->chip.PVIDEO, 0x200, (yscale << 16) | xscale); | |
829 | |
830 /* NV_PVIDEO_RED_CSC_OFFSET */ | |
831 VID_WR32 (info->chip.PVIDEO, 0x280, eq.red_off); | |
832 /* NV_PVIDEO_GREEN_CSC_OFFSET */ | |
833 VID_WR32 (info->chip.PVIDEO, 0x284, eq.green_off); | |
834 /* NV_PVIDEO_BLUE_CSC_OFFSET */ | |
835 VID_WR32 (info->chip.PVIDEO, 0x288, eq.blue_off); | |
836 /* NV_PVIDEO_CSC_ADJUST */ | |
837 VID_WR32 (info->chip.PVIDEO, 0x28C, 0x00000); /* No colour correction! */ | |
838 | |
839 /* NV_PVIDEO_CONTROL_Y (BLUR_ON, LINE_HALF) */ | |
840 VID_WR32 (info->chip.PVIDEO, 0x204, 0x001); | |
841 /* NV_PVIDEO_CONTROL_X (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */ | |
842 VID_WR32 (info->chip.PVIDEO, 0x208, 0x111); /*directx overlay 0x110 */ | |
843 | |
844 /* NV_PVIDEO_FIFO_BURST_LENGTH */ | |
845 VID_WR32 (info->chip.PVIDEO, 0x23C, 0x03); | |
846 /* NV_PVIDEO_FIFO_THRES_SIZE */ | |
847 VID_WR32 (info->chip.PVIDEO, 0x238, 0x38); /*windows uses 0x40*/ | |
848 | |
849 /* NV_PVIDEO_BUFF0_OFFSET */ | |
850 VID_WR32 (info->chip.PVIDEO, 0x21C + 0, 0); | |
851 VID_WR32 (info->chip.PVIDEO, 0x21C + 4, 0); | |
852 | |
853 /* NV_PVIDEO_INTR_EN_0_NOTIFY_ENABLED */ | |
854 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01); | |
855 | |
856 /* NV_PVIDEO_OVERLAY (KEY_ON, VIDEO_ON, FORMAT_CCIR) */ | |
857 value = 0x1; /*video on*/ | |
858 if(info->format==IMGFMT_YUY2)value |= 0x100; | |
859 if(info->use_colorkey)value |=0x10; | |
860 VID_WR32 (info->chip.PVIDEO, 0x244, value); | |
861 | |
862 /* NV_PVIDEO_SU_STATE */ | |
863 VID_XOR32 (info->chip.PVIDEO, 0x228, 1 << 16); | |
864 break; | |
865 } | |
866 /*set colorkey*/ | |
867 rivatv_overlay_colorkey(info,info->vidixcolorkey); | |
868 | |
869 } | |
870 | |
871 | |
872 | |
873 | |
874 | |
875 | |
876 | |
877 static rivatv_info* info; | |
878 | |
879 | |
880 | |
881 | |
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882 static int nv_init(void){ |
22850 | 883 int mtrr; |
884 info = calloc(1,sizeof(rivatv_info)); | |
885 info->control_base = map_phys_mem(pci_info.base0, 0x00C00000 + 0x00008000); | |
886 info->chip.arch = nvidia_card_ids[find_chip(pci_info.device)].arch; | |
887 printf("[nvidia_vid] arch %x register base %p\n",info->chip.arch,info->control_base); | |
888 info->chip.PFIFO = (uint32_t *) (info->control_base + 0x00002000); | |
889 info->chip.FIFO = (uint32_t *) (info->control_base + 0x00800000); | |
890 info->chip.PMC = (uint32_t *) (info->control_base + 0x00000000); | |
891 info->chip.PFB = (uint32_t *) (info->control_base + 0x00100000); | |
892 info->chip.PME = (uint32_t *) (info->control_base + 0x00000000); | |
893 info->chip.PCIO = (uint8_t *) (info->control_base + 0x00601000); | |
894 info->chip.PVIO = (uint8_t *) (info->control_base + 0x000C0000); | |
895 info->chip.PGRAPH = (uint32_t *) (info->control_base + 0x00400000); | |
896 /* setup chip specific functions */ | |
897 switch (info->chip.arch) { | |
898 case NV_ARCH_03: | |
899 info->chip.lock = rivatv_lock_nv03; | |
900 info->chip.fbsize = rivatv_fbsize_nv03 (&info->chip); | |
901 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); | |
902 break; | |
903 case NV_ARCH_04: | |
904 info->chip.lock = rivatv_lock_nv04; | |
905 info->chip.fbsize = rivatv_fbsize_nv04 (&info->chip); | |
906 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); | |
907 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); | |
908 break; | |
909 case NV_ARCH_10: | |
910 case NV_ARCH_20: | |
911 case NV_ARCH_30: | |
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912 case NV_ARCH_40: |
22850 | 913 info->chip.lock = rivatv_lock_nv04; |
914 info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip); | |
915 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); | |
916 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000); | |
917 break; | |
918 } | |
919 switch (info->chip.arch) { | |
920 case NV_ARCH_03: | |
921 { | |
922 /* This maps framebuffer @6MB, thus 2MB are left for video. */ | |
923 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
924 /* This may trash your screen for resolutions greater than 1024x768, sorry. */ | |
925 info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1); | |
926 info->picture_base = info->video_base + info->picture_offset; | |
927 info->chip.PRAMIN = (uint32_t *) (info->video_base + 0x00C00000); | |
928 break; | |
929 } | |
930 case NV_ARCH_04: | |
931 case NV_ARCH_10: | |
932 case NV_ARCH_20: | |
933 case NV_ARCH_30: | |
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934 case NV_ARCH_40: |
22850 | 935 { |
936 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
937 info->picture_offset = info->chip.fbsize - NV04_BES_SIZE; | |
938 if(info->chip.fbsize > 16*1024*1024) | |
939 info->picture_offset -= NV04_BES_SIZE; | |
940 // info->picture_base = (unsigned long)map_phys_mem(pci_info.base1+info->picture_offset,NV04_BES_SIZE); | |
941 info->picture_base = info->video_base + info->picture_offset; | |
942 break; | |
943 } | |
944 } | |
945 | |
946 printf("[nvidia_vid] detected memory size %u MB\n",(uint32_t)(info->chip.fbsize /1024/1024)); | |
947 | |
948 if ((mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB))!= 0) | |
949 printf("[nvidia_vid] unable to setup MTRR: %s\n", strerror(mtrr)); | |
950 else | |
951 printf("[nvidia_vid] MTRR set up\n"); | |
952 | |
953 nv_getscreenproperties(info); | |
954 if(!info->depth)printf("[nvidia_vid] text mode: %ux%u\n",info->screen_x,info->screen_y); | |
955 else printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x,info->screen_y, info->depth); | |
956 | |
957 | |
958 rivatv_enable_PMEDIA(info); | |
959 info->cur_frame = 0; | |
960 info->use_colorkey = 0; | |
961 | |
962 eq.lum = 0x00001000; | |
963 eq.chrom = 0x00001000; | |
964 memset(&eq.vals, 0, sizeof(vidix_video_eq_t)); | |
965 eq.vals.cap = VEQ_CAP_BRIGHTNESS; | |
966 if (info->chip.arch > NV_ARCH_04) | |
967 eq.vals.cap |= VEQ_CAP_CONTRAST | VEQ_CAP_SATURATION | VEQ_CAP_HUE; | |
968 eq.red_off = 0x69; | |
969 eq.green_off = 0x3e; | |
970 eq.blue_off = 0x89; | |
971 return 0; | |
972 } | |
973 | |
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974 static void nv_destroy(void){ |
22850 | 975 unmap_phys_mem(info->control_base ,0x00C00000 + 0x00008000); |
976 unmap_phys_mem(info->video_base, info->chip.fbsize); | |
977 free(info); | |
978 } | |
979 | |
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980 static int nv_get_caps(vidix_capability_t *to){ |
22850 | 981 memcpy(to, &nvidia_cap, sizeof(vidix_capability_t)); |
982 return 0; | |
983 } | |
984 | |
985 inline static int is_supported_fourcc(uint32_t fourcc) | |
986 { | |
987 if (fourcc == IMGFMT_UYVY || fourcc == IMGFMT_YUY2) | |
988 return 1; | |
989 else | |
990 return 0; | |
991 } | |
992 | |
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993 static int nv_query_fourcc(vidix_fourcc_t *to){ |
22850 | 994 if(is_supported_fourcc(to->fourcc)){ |
23060 | 995 to->depth = VID_DEPTH_ALL; |
22850 | 996 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; |
997 return 0; | |
998 } | |
999 else to->depth = to->flags = 0; | |
1000 return ENOSYS; | |
1001 } | |
1002 | |
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1003 static int nv_config_playback(vidix_playback_t *vinfo){ |
22850 | 1004 uint32_t i; |
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1005 // printf("called %s\n", __FUNCTION__); |
22850 | 1006 if (! is_supported_fourcc(vinfo->fourcc)) |
1007 return ENOSYS; | |
1008 | |
1009 info->width = vinfo->src.w; | |
1010 info->height = vinfo->src.h; | |
1011 | |
1012 info->d_width = vinfo->dest.w; | |
1013 info->d_height = vinfo->dest.h; | |
1014 info->wx = vinfo->dest.x; | |
1015 info->wy = vinfo->dest.y; | |
1016 info->format = vinfo->fourcc; | |
1017 | |
1018 printf("[nvidia_vid] setting up a %dx%d-%dx%d video window (src %dx%d), format 0x%X\n", | |
1019 info->d_width, info->d_height, info->wx, info->wy, info->width, info->height, vinfo->fourcc); | |
1020 | |
1021 | |
1022 vinfo->dga_addr=info->picture_base; | |
1023 | |
1024 switch (vinfo->fourcc) | |
1025 { | |
1026 case IMGFMT_YUY2: | |
1027 case IMGFMT_UYVY: | |
1028 | |
1029 vinfo->dest.pitch.y = 64; | |
1030 vinfo->dest.pitch.u = 0; | |
1031 vinfo->dest.pitch.v = 0; | |
1032 | |
1033 vinfo->offset.y = 0; | |
1034 vinfo->offset.v = 0; | |
1035 vinfo->offset.u = 0; | |
1036 info->pitch = ((info->width << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1); | |
1037 vinfo->frame_size = info->pitch * info->height; | |
1038 break; | |
1039 } | |
1040 info->buffer_size = vinfo->frame_size; | |
1041 info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; | |
1042 if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; | |
1043 // vinfo->num_frames = 1; | |
1044 // printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); | |
1045 for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; | |
1046 return 0; | |
1047 } | |
1048 | |
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1049 static int nv_playback_on(void){ |
22850 | 1050 rivatv_overlay_start(info,info->cur_frame); |
1051 return 0; | |
1052 } | |
1053 | |
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1054 static int nv_playback_off(void){ |
22850 | 1055 rivatv_overlay_stop(info); |
1056 return 0; | |
1057 } | |
1058 | |
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1059 static int nv_set_gkeys( const vidix_grkey_t * grkey){ |
22850 | 1060 if (grkey->ckey.op == CKEY_FALSE) |
1061 { | |
1062 info->use_colorkey = 0; | |
1063 printf("[nvidia_vid] colorkeying disabled\n"); | |
1064 } | |
1065 else { | |
1066 info->use_colorkey = 1; | |
1067 info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); | |
1068 printf("[nvidia_vid] set colorkey 0x%x\n",info->vidixcolorkey); | |
1069 } | |
1070 if(info->d_width && info->d_height)rivatv_overlay_start(info,0); | |
1071 return 0; | |
1072 } | |
1073 | |
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1074 static int nv_frame_sel(unsigned int frame){ |
22850 | 1075 // printf("selecting buffer %d\n", frame); |
1076 rivatv_overlay_start(info, frame); | |
1077 if (info->num_frames >= 1) | |
1078 info->cur_frame = frame/*(frame+1)%info->num_frames*/; | |
1079 return 0; | |
1080 } | |
1081 | |
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1082 static int nv_set_eq(const vidix_video_eq_t *eq_parm) { |
22850 | 1083 double angle; |
1084 int16_t chrom_cos, chrom_sin; | |
1085 if (eq_parm->cap & VEQ_CAP_BRIGHTNESS) | |
1086 eq.vals.brightness = eq_parm->brightness; | |
1087 if (eq_parm->cap & VEQ_CAP_CONTRAST) | |
1088 eq.vals.contrast = eq_parm->contrast; | |
1089 if (eq_parm->cap & VEQ_CAP_SATURATION) | |
1090 eq.vals.saturation = eq_parm->saturation; | |
1091 if (eq_parm->cap & VEQ_CAP_HUE) | |
1092 eq.vals.hue = eq_parm->hue; | |
1093 eq.lum = (((eq.vals.brightness * 512 + 500) / 1000) << 16) | | |
1094 ((((eq.vals.contrast + 1000) * 8191 + 1000) / 2000) & 0xffff); | |
1095 angle = (double)eq.vals.hue / 1000.0 * 3.1415927; | |
1096 chrom_cos = ((eq.vals.saturation + 1000) * 8191 * cos(angle) + 1000) / 2000; | |
1097 chrom_sin = ((eq.vals.saturation + 1000) * 8191 * sin(angle) + 1000) / 2000; | |
1098 eq.chrom = chrom_sin << 16 | chrom_cos; | |
1099 eq.red_off = 0x69 - eq.vals.brightness * 62 / 1000; | |
1100 eq.green_off = 0x3e + eq.vals.brightness * 62 / 1000; | |
1101 eq.blue_off = 0x89 - eq.vals.brightness * 62 / 1000; | |
1102 return 0; | |
1103 } | |
1104 | |
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1105 static int nv_get_eq(vidix_video_eq_t *eq_parm) { |
22850 | 1106 memcpy(eq_parm, &eq.vals, sizeof(vidix_video_eq_t)); |
1107 return 0; | |
1108 } | |
1109 | |
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1110 VDXDriver nvidia_drv = { |
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1111 "nvidia", |
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1112 NULL, |
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1113 .probe = nv_probe, |
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1114 .get_caps = nv_get_caps, |
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1115 .query_fourcc = nv_query_fourcc, |
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1116 .init = nv_init, |
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1117 .destroy = nv_destroy, |
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1118 .config_playback = nv_config_playback, |
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1119 .playback_on = nv_playback_on, |
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1120 .playback_off = nv_playback_off, |
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1121 .frame_sel = nv_frame_sel, |
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1122 .get_eq = nv_get_eq, |
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1123 .set_eq = nv_set_eq, |
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1124 .set_gkey = nv_set_gkeys, |
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1125 }; |
24568 | 1126 |
1127 | |
1128 #if 0 | |
1129 //gcc -o nvidia_vid nvidia_vid.c -I ../ -lm ../vidix/libvidix.a | |
1130 | |
1131 int main(int argc,char* argv[]){ | |
1132 if(nv_probe(0,0)){ | |
1133 printf("no supported chip found\n"); | |
1134 return 1; | |
1135 } | |
1136 if(nv_init()){ | |
1137 printf("could not init\n"); | |
1138 return 1; | |
1139 } | |
1140 if(info->chip.arch >= NV_ARCH_10){ | |
1141 printf("NV_PVIDEO_BASE (0x900) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x900)); | |
1142 printf("NV_PVIDEO_LIMIT (0x908) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x908)); | |
1143 printf("NV_PVIDEO_OFFSET (0x920) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x920)); | |
1144 printf("NV_PVIDEO_FORMAT (0x958) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x958)); | |
1145 printf("NV_PVIDEO_STOP (0x704) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x704)); | |
1146 printf("NV_PVIDEO_BUFFER (0x700) 0x%x\n",VID_RD32(info->chip.PVIDEO, 0x700)); | |
1147 } | |
1148 | |
1149 nv_destroy(); | |
1150 return 0; | |
1151 } | |
1152 | |
1153 #endif | |
1154 |