Mercurial > mplayer.hg
annotate drivers/mga_vid.c @ 2262:8cae22120633
gpl fix?
author | arpi |
---|---|
date | Thu, 18 Oct 2001 20:52:33 +0000 |
parents | ae67940c9d12 |
children | 1c573fed42dd |
rev | line source |
---|---|
1 | 1 // YUY2 support (see config.format) added by A'rpi/ESP-team |
57 | 2 // double buffering added by A'rpi/ESP-team |
3 | |
4 // Set this value, if autodetection fails! (video ram size in megabytes) | |
91 | 5 // #define MGA_MEMORY_SIZE 16 |
1 | 6 |
68 | 7 //#define MGA_ALLOW_IRQ |
8 | |
9 #define MGA_VSYNC_POS 2 | |
10 | |
1 | 11 /* |
12 * | |
13 * mga_vid.c | |
14 * | |
15 * Copyright (C) 1999 Aaron Holtzman | |
16 * | |
17 * Module skeleton based on gutted agpgart module by Jeff Hartmann | |
18 * <slicer@ionet.net> | |
19 * | |
20 * Matrox MGA G200/G400 YUV Video Interface module Version 0.1.0 | |
21 * | |
22 * BES == Back End Scaler | |
23 * | |
24 * This software has been released under the terms of the GNU Public | |
25 * license. See http://www.gnu.org/copyleft/gpl.html for details. | |
26 */ | |
27 | |
28 //It's entirely possible this major conflicts with something else | |
29 /* mknod /dev/mga_vid c 178 0 */ | |
30 | |
31 #include <linux/config.h> | |
32 #include <linux/version.h> | |
33 #include <linux/module.h> | |
34 #include <linux/types.h> | |
35 #include <linux/kernel.h> | |
36 #include <linux/sched.h> | |
37 #include <linux/mm.h> | |
38 #include <linux/string.h> | |
39 #include <linux/errno.h> | |
40 #include <linux/malloc.h> | |
41 #include <linux/pci.h> | |
63 | 42 #include <linux/ioport.h> |
1 | 43 #include <linux/init.h> |
44 | |
45 #include "mga_vid.h" | |
46 | |
47 #ifdef CONFIG_MTRR | |
48 #include <asm/mtrr.h> | |
49 #endif | |
50 | |
51 #include <asm/uaccess.h> | |
52 #include <asm/system.h> | |
53 #include <asm/io.h> | |
54 | |
55 #define TRUE 1 | |
56 #define FALSE 0 | |
57 | |
58 #define MGA_VID_MAJOR 178 | |
59 | |
57 | 60 //#define MGA_VIDMEM_SIZE mga_ram_size |
1 | 61 |
62 #ifndef PCI_DEVICE_ID_MATROX_G200_PCI | |
63 #define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520 | |
64 #endif | |
65 | |
66 #ifndef PCI_DEVICE_ID_MATROX_G200_AGP | |
67 #define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521 | |
68 #endif | |
69 | |
70 #ifndef PCI_DEVICE_ID_MATROX_G400 | |
71 #define PCI_DEVICE_ID_MATROX_G400 0x0525 | |
72 #endif | |
73 | |
1989 | 74 #ifndef PCI_DEVICE_ID_MATROX_G550 |
75 #define PCI_DEVICE_ID_MATROX_G550 0x2527 | |
76 #endif | |
77 | |
1 | 78 MODULE_AUTHOR("Aaron Holtzman <aholtzma@engr.uvic.ca>"); |
2262 | 79 #ifdef MODULE_LICENSE |
80 MODULE_LICENSE("GPL"); | |
81 #endif | |
1 | 82 |
83 typedef struct bes_registers_s | |
84 { | |
85 //BES Control | |
86 uint32_t besctl; | |
87 //BES Global control | |
88 uint32_t besglobctl; | |
89 //Luma control (brightness and contrast) | |
90 uint32_t beslumactl; | |
91 //Line pitch | |
92 uint32_t bespitch; | |
93 | |
94 //Buffer A-1 Chroma 3 plane org | |
95 uint32_t besa1c3org; | |
96 //Buffer A-1 Chroma org | |
97 uint32_t besa1corg; | |
98 //Buffer A-1 Luma org | |
99 uint32_t besa1org; | |
100 | |
101 //Buffer A-2 Chroma 3 plane org | |
102 uint32_t besa2c3org; | |
103 //Buffer A-2 Chroma org | |
104 uint32_t besa2corg; | |
105 //Buffer A-2 Luma org | |
106 uint32_t besa2org; | |
107 | |
108 //Buffer B-1 Chroma 3 plane org | |
109 uint32_t besb1c3org; | |
110 //Buffer B-1 Chroma org | |
111 uint32_t besb1corg; | |
112 //Buffer B-1 Luma org | |
113 uint32_t besb1org; | |
114 | |
115 //Buffer B-2 Chroma 3 plane org | |
116 uint32_t besb2c3org; | |
117 //Buffer B-2 Chroma org | |
118 uint32_t besb2corg; | |
119 //Buffer B-2 Luma org | |
120 uint32_t besb2org; | |
121 | |
122 //BES Horizontal coord | |
123 uint32_t beshcoord; | |
124 //BES Horizontal inverse scaling [5.14] | |
125 uint32_t beshiscal; | |
126 //BES Horizontal source start [10.14] (for scaling) | |
127 uint32_t beshsrcst; | |
128 //BES Horizontal source ending [10.14] (for scaling) | |
129 uint32_t beshsrcend; | |
130 //BES Horizontal source last | |
131 uint32_t beshsrclst; | |
132 | |
133 | |
134 //BES Vertical coord | |
135 uint32_t besvcoord; | |
136 //BES Vertical inverse scaling [5.14] | |
137 uint32_t besviscal; | |
138 //BES Field 1 vertical source last position | |
139 uint32_t besv1srclst; | |
140 //BES Field 1 weight start | |
141 uint32_t besv1wght; | |
142 //BES Field 2 vertical source last position | |
143 uint32_t besv2srclst; | |
144 //BES Field 2 weight start | |
145 uint32_t besv2wght; | |
146 | |
147 } bes_registers_t; | |
148 | |
149 static bes_registers_t regs; | |
150 static uint32_t mga_vid_in_use = 0; | |
151 static uint32_t is_g400 = 0; | |
152 static uint32_t vid_src_ready = 0; | |
153 static uint32_t vid_overlay_on = 0; | |
154 | |
155 static uint8_t *mga_mmio_base = 0; | |
156 static uint32_t mga_mem_base = 0; | |
157 | |
57 | 158 static int mga_src_base = 0; // YUV buffer position in video memory |
159 | |
160 static uint32_t mga_ram_size = 0; // how much megabytes videoram we have | |
1 | 161 |
95 | 162 //static int mga_force_memsize = 0; |
90 | 163 |
95 | 164 MODULE_PARM(mga_ram_size, "i"); |
90 | 165 |
1 | 166 static struct pci_dev *pci_dev; |
167 | |
168 static mga_vid_config_t mga_config; | |
169 | |
2086 | 170 static int colkey_saved=0; |
171 static int colkey_on=0; | |
172 static unsigned char colkey_color[4]; | |
173 static unsigned char colkey_mask[4]; | |
174 | |
48 | 175 static int mga_irq = -1; |
1 | 176 |
177 //All register offsets are converted to word aligned offsets (32 bit) | |
178 //because we want all our register accesses to be 32 bits | |
179 #define VCOUNT 0x1e20 | |
180 | |
181 #define PALWTADD 0x3c00 // Index register for X_DATAREG port | |
182 #define X_DATAREG 0x3c0a | |
183 | |
184 #define XMULCTRL 0x19 | |
185 #define BPP_8 0x00 | |
186 #define BPP_15 0x01 | |
187 #define BPP_16 0x02 | |
188 #define BPP_24 0x03 | |
189 #define BPP_32_DIR 0x04 | |
190 #define BPP_32_PAL 0x07 | |
191 | |
192 #define XCOLMSK 0x40 | |
193 #define X_COLKEY 0x42 | |
194 #define XKEYOPMODE 0x51 | |
195 #define XCOLMSK0RED 0x52 | |
196 #define XCOLMSK0GREEN 0x53 | |
197 #define XCOLMSK0BLUE 0x54 | |
198 #define XCOLKEY0RED 0x55 | |
199 #define XCOLKEY0GREEN 0x56 | |
200 #define XCOLKEY0BLUE 0x57 | |
201 | |
202 // Backend Scaler registers | |
203 #define BESCTL 0x3d20 | |
204 #define BESGLOBCTL 0x3dc0 | |
205 #define BESLUMACTL 0x3d40 | |
206 #define BESPITCH 0x3d24 | |
48 | 207 |
1 | 208 #define BESA1C3ORG 0x3d60 |
209 #define BESA1CORG 0x3d10 | |
210 #define BESA1ORG 0x3d00 | |
48 | 211 |
1 | 212 #define BESA2C3ORG 0x3d64 |
213 #define BESA2CORG 0x3d14 | |
214 #define BESA2ORG 0x3d04 | |
48 | 215 |
1 | 216 #define BESB1C3ORG 0x3d68 |
217 #define BESB1CORG 0x3d18 | |
218 #define BESB1ORG 0x3d08 | |
48 | 219 |
1 | 220 #define BESB2C3ORG 0x3d6C |
221 #define BESB2CORG 0x3d1C | |
222 #define BESB2ORG 0x3d0C | |
48 | 223 |
1 | 224 #define BESHCOORD 0x3d28 |
225 #define BESHISCAL 0x3d30 | |
226 #define BESHSRCEND 0x3d3C | |
227 #define BESHSRCLST 0x3d50 | |
228 #define BESHSRCST 0x3d38 | |
229 #define BESV1WGHT 0x3d48 | |
230 #define BESV2WGHT 0x3d4c | |
231 #define BESV1SRCLST 0x3d54 | |
232 #define BESV2SRCLST 0x3d58 | |
233 #define BESVISCAL 0x3d34 | |
234 #define BESVCOORD 0x3d2c | |
235 #define BESSTATUS 0x3dc4 | |
236 | |
48 | 237 #define CRTCX 0x1fd4 |
238 #define CRTCD 0x1fd5 | |
239 #define IEN 0x1e1c | |
240 #define ICLEAR 0x1e18 | |
241 #define STATUS 0x1e14 | |
242 | |
243 static int mga_next_frame=0; | |
1 | 244 |
245 static void mga_vid_frame_sel(int frame) | |
246 { | |
48 | 247 if ( mga_irq != -1 ) { |
248 mga_next_frame=frame; | |
249 } else { | |
250 | |
1 | 251 //we don't need the vcount protection as we're only hitting |
252 //one register (and it doesn't seem to be double buffered) | |
253 regs.besctl = (regs.besctl & ~0x07000000) + (frame << 25); | |
254 writel( regs.besctl, mga_mmio_base + BESCTL ); | |
68 | 255 |
256 // writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), | |
257 writel( regs.besglobctl + (MGA_VSYNC_POS<<16), | |
258 mga_mmio_base + BESGLOBCTL); | |
259 | |
48 | 260 } |
1 | 261 } |
262 | |
263 | |
2086 | 264 static void mga_vid_write_regs(int restore) |
1 | 265 { |
266 //Make sure internal registers don't get updated until we're done | |
267 writel( (readl(mga_mmio_base + VCOUNT)-1)<<16, | |
268 mga_mmio_base + BESGLOBCTL); | |
269 | |
270 // color or coordinate keying | |
2086 | 271 |
272 if(restore && colkey_saved){ | |
273 // restore it | |
274 colkey_saved=0; | |
275 | |
276 printk("mga_vid: Restoring colorkey (ON: %d %02X:%02X:%02X)\n", | |
277 colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]); | |
278 | |
279 // Set color key registers: | |
280 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); | |
281 writeb( colkey_on, mga_mmio_base + X_DATAREG); | |
282 | |
283 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); | |
284 writeb( colkey_color[0], mga_mmio_base + X_DATAREG); | |
285 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); | |
286 writeb( colkey_color[1], mga_mmio_base + X_DATAREG); | |
287 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); | |
288 writeb( colkey_color[2], mga_mmio_base + X_DATAREG); | |
289 writeb( X_COLKEY, mga_mmio_base + PALWTADD); | |
290 writeb( colkey_color[3], mga_mmio_base + X_DATAREG); | |
291 | |
292 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); | |
293 writeb( colkey_mask[0], mga_mmio_base + X_DATAREG); | |
294 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); | |
295 writeb( colkey_mask[1], mga_mmio_base + X_DATAREG); | |
296 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); | |
297 writeb( colkey_mask[2], mga_mmio_base + X_DATAREG); | |
298 writeb( XCOLMSK, mga_mmio_base + PALWTADD); | |
299 writeb( colkey_mask[3], mga_mmio_base + X_DATAREG); | |
300 | |
301 } else if(!colkey_saved){ | |
302 // save it | |
303 colkey_saved=1; | |
304 // Get color key registers: | |
305 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); | |
306 colkey_on=(unsigned char)readb(mga_mmio_base + X_DATAREG) & 1; | |
307 | |
308 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); | |
309 colkey_color[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
310 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); | |
311 colkey_color[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
312 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); | |
313 colkey_color[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
314 writeb( X_COLKEY, mga_mmio_base + PALWTADD); | |
315 colkey_color[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
316 | |
317 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); | |
318 colkey_mask[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
319 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); | |
320 colkey_mask[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
321 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); | |
322 colkey_mask[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
323 writeb( XCOLMSK, mga_mmio_base + PALWTADD); | |
324 colkey_mask[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
325 | |
326 printk("mga_vid: Saved colorkey (ON: %d %02X:%02X:%02X)\n", | |
327 colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]); | |
328 | |
329 } | |
330 | |
331 if(!restore){ | |
1 | 332 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); |
333 writeb( mga_config.colkey_on, mga_mmio_base + X_DATAREG); | |
334 if ( mga_config.colkey_on ) | |
335 { | |
336 uint32_t r=0, g=0, b=0; | |
337 | |
338 writeb( XMULCTRL, mga_mmio_base + PALWTADD); | |
339 switch (readb (mga_mmio_base + X_DATAREG)) | |
340 { | |
341 case BPP_8: | |
342 /* Need to look up the color index, just using | |
343 color 0 for now. */ | |
344 break; | |
345 | |
346 case BPP_15: | |
347 r = mga_config.colkey_red >> 3; | |
348 g = mga_config.colkey_green >> 3; | |
349 b = mga_config.colkey_blue >> 3; | |
350 break; | |
351 | |
352 case BPP_16: | |
353 r = mga_config.colkey_red >> 3; | |
354 g = mga_config.colkey_green >> 2; | |
355 b = mga_config.colkey_blue >> 3; | |
356 break; | |
357 | |
358 case BPP_24: | |
359 case BPP_32_DIR: | |
360 case BPP_32_PAL: | |
361 r = mga_config.colkey_red; | |
362 g = mga_config.colkey_green; | |
363 b = mga_config.colkey_blue; | |
364 break; | |
365 } | |
366 | |
367 // Disable color keying on alpha channel | |
368 writeb( XCOLMSK, mga_mmio_base + PALWTADD); | |
369 writeb( 0x00, mga_mmio_base + X_DATAREG); | |
370 writeb( X_COLKEY, mga_mmio_base + PALWTADD); | |
371 writeb( 0x00, mga_mmio_base + X_DATAREG); | |
372 | |
2086 | 373 |
1 | 374 // Set up color key registers |
375 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); | |
376 writeb( r, mga_mmio_base + X_DATAREG); | |
377 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); | |
378 writeb( g, mga_mmio_base + X_DATAREG); | |
379 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); | |
380 writeb( b, mga_mmio_base + X_DATAREG); | |
381 | |
382 // Set up color key mask registers | |
383 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); | |
384 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
385 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); | |
386 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
387 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); | |
388 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
389 } | |
390 | |
2086 | 391 } |
392 | |
1 | 393 // Backend Scaler |
394 writel( regs.besctl, mga_mmio_base + BESCTL); | |
395 if(is_g400) | |
396 writel( regs.beslumactl, mga_mmio_base + BESLUMACTL); | |
397 writel( regs.bespitch, mga_mmio_base + BESPITCH); | |
398 | |
399 writel( regs.besa1org, mga_mmio_base + BESA1ORG); | |
400 writel( regs.besa1corg, mga_mmio_base + BESA1CORG); | |
48 | 401 writel( regs.besa2org, mga_mmio_base + BESA2ORG); |
402 writel( regs.besa2corg, mga_mmio_base + BESA2CORG); | |
1 | 403 writel( regs.besb1org, mga_mmio_base + BESB1ORG); |
404 writel( regs.besb1corg, mga_mmio_base + BESB1CORG); | |
48 | 405 writel( regs.besb2org, mga_mmio_base + BESB2ORG); |
406 writel( regs.besb2corg, mga_mmio_base + BESB2CORG); | |
1 | 407 if(is_g400) |
408 { | |
409 writel( regs.besa1c3org, mga_mmio_base + BESA1C3ORG); | |
48 | 410 writel( regs.besa2c3org, mga_mmio_base + BESA2C3ORG); |
1 | 411 writel( regs.besb1c3org, mga_mmio_base + BESB1C3ORG); |
48 | 412 writel( regs.besb2c3org, mga_mmio_base + BESB2C3ORG); |
1 | 413 } |
414 | |
415 writel( regs.beshcoord, mga_mmio_base + BESHCOORD); | |
416 writel( regs.beshiscal, mga_mmio_base + BESHISCAL); | |
417 writel( regs.beshsrcst, mga_mmio_base + BESHSRCST); | |
418 writel( regs.beshsrcend, mga_mmio_base + BESHSRCEND); | |
419 writel( regs.beshsrclst, mga_mmio_base + BESHSRCLST); | |
420 | |
421 writel( regs.besvcoord, mga_mmio_base + BESVCOORD); | |
422 writel( regs.besviscal, mga_mmio_base + BESVISCAL); | |
48 | 423 |
1 | 424 writel( regs.besv1srclst, mga_mmio_base + BESV1SRCLST); |
425 writel( regs.besv1wght, mga_mmio_base + BESV1WGHT); | |
48 | 426 writel( regs.besv2srclst, mga_mmio_base + BESV2SRCLST); |
427 writel( regs.besv2wght, mga_mmio_base + BESV2WGHT); | |
1 | 428 |
429 //update the registers somewhere between 1 and 2 frames from now. | |
430 writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), | |
431 mga_mmio_base + BESGLOBCTL); | |
432 | |
77 | 433 #if 0 |
61 | 434 printk(KERN_DEBUG "mga_vid: wrote BES registers\n"); |
435 printk(KERN_DEBUG "mga_vid: BESCTL = 0x%08x\n", | |
1 | 436 readl(mga_mmio_base + BESCTL)); |
61 | 437 printk(KERN_DEBUG "mga_vid: BESGLOBCTL = 0x%08x\n", |
1 | 438 readl(mga_mmio_base + BESGLOBCTL)); |
61 | 439 printk(KERN_DEBUG "mga_vid: BESSTATUS= 0x%08x\n", |
1 | 440 readl(mga_mmio_base + BESSTATUS)); |
77 | 441 #endif |
1 | 442 } |
443 | |
444 static int mga_vid_set_config(mga_vid_config_t *config) | |
445 { | |
446 int x, y, sw, sh, dw, dh; | |
447 int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights; | |
57 | 448 int frame_size=config->frame_size; |
1 | 449 x = config->x_org; |
450 y = config->y_org; | |
451 sw = config->src_width; | |
452 sh = config->src_height; | |
453 dw = config->dest_width; | |
454 dh = config->dest_height; | |
455 | |
61 | 456 printk(KERN_DEBUG "mga_vid: Setting up a %dx%d+%d+%d video window (src %dx%d) format %X\n", |
1 | 457 dw, dh, x, y, sw, sh, config->format); |
458 | |
459 //FIXME check that window is valid and inside desktop | |
460 | |
461 //FIXME figure out a better way to allocate memory on card | |
462 //allocate 2 megs | |
463 //mga_src_base = mga_mem_base + (MGA_VIDMEM_SIZE-2) * 0x100000; | |
57 | 464 //mga_src_base = (MGA_VIDMEM_SIZE-3) * 0x100000; |
1 | 465 |
466 | |
467 //Setup the BES registers for a three plane 4:2:0 video source | |
468 | |
466 | 469 regs.besglobctl = 0; |
470 | |
1 | 471 switch(config->format){ |
472 case MGA_VID_FORMAT_YV12: | |
470 | 473 case MGA_VID_FORMAT_I420: |
474 case MGA_VID_FORMAT_IYUV: | |
1 | 475 regs.besctl = 1 // BES enabled |
476 + (0<<6) // even start polarity | |
477 + (1<<10) // x filtering enabled | |
478 + (1<<11) // y filtering enabled | |
479 + (1<<16) // chroma upsampling | |
480 + (1<<17) // 4:2:0 mode | |
481 + (1<<18); // dither enabled | |
466 | 482 #if 0 |
1 | 483 if(is_g400) |
484 { | |
485 //zoom disabled, zoom filter disabled, 420 3 plane format, proc amp | |
486 //disabled, rgb mode disabled | |
487 regs.besglobctl = (1<<5); | |
488 } | |
489 else | |
490 { | |
491 //zoom disabled, zoom filter disabled, Cb samples in 0246, Cr | |
492 //in 1357, BES register update on besvcnt | |
466 | 493 regs.besglobctl = 0; |
1 | 494 } |
466 | 495 #endif |
1 | 496 break; |
497 | |
498 case MGA_VID_FORMAT_YUY2: | |
499 regs.besctl = 1 // BES enabled | |
500 + (0<<6) // even start polarity | |
501 + (1<<10) // x filtering enabled | |
502 + (1<<11) // y filtering enabled | |
503 + (1<<16) // chroma upsampling | |
504 + (0<<17) // 4:2:2 mode | |
505 + (1<<18); // dither enabled | |
506 | |
507 regs.besglobctl = 0; // YUY2 format selected | |
508 break; | |
466 | 509 |
510 case MGA_VID_FORMAT_UYVY: | |
511 regs.besctl = 1 // BES enabled | |
512 + (0<<6) // even start polarity | |
513 + (1<<10) // x filtering enabled | |
514 + (1<<11) // y filtering enabled | |
515 + (1<<16) // chroma upsampling | |
516 + (0<<17) // 4:2:2 mode | |
517 + (1<<18); // dither enabled | |
518 | |
519 regs.besglobctl = 1<<6; // UYVY format selected | |
520 break; | |
521 | |
1 | 522 default: |
61 | 523 printk(KERN_ERR "mga_vid: Unsupported pixel format: 0x%X\n",config->format); |
1 | 524 return -1; |
525 } | |
526 | |
527 | |
528 //Disable contrast and brightness control | |
466 | 529 regs.besglobctl |= (1<<5) + (1<<7); |
1 | 530 regs.beslumactl = (0x7f << 16) + (0x80<<0); |
531 regs.beslumactl = 0x80<<0; | |
532 | |
533 //Setup destination window boundaries | |
534 besleft = x > 0 ? x : 0; | |
535 bestop = y > 0 ? y : 0; | |
536 regs.beshcoord = (besleft<<16) + (x + dw-1); | |
537 regs.besvcoord = (bestop<<16) + (y + dh-1); | |
538 | |
539 //Setup source dimensions | |
540 regs.beshsrclst = (sw - 1) << 16; | |
541 regs.bespitch = (sw + 31) & ~31 ; | |
542 | |
543 //Setup horizontal scaling | |
544 ifactor = ((sw-1)<<14)/(dw-1); | |
545 ofsleft = besleft - x; | |
546 | |
547 regs.beshiscal = ifactor<<2; | |
548 regs.beshsrcst = (ofsleft*ifactor)<<2; | |
549 regs.beshsrcend = regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2); | |
550 | |
551 //Setup vertical scaling | |
552 ifactor = ((sh-1)<<14)/(dh-1); | |
553 ofstop = bestop - y; | |
554 | |
555 regs.besviscal = ifactor<<2; | |
556 | |
557 baseadrofs = ((ofstop*regs.besviscal)>>16)*regs.bespitch; | |
57 | 558 //frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2; |
1 | 559 regs.besa1org = (uint32_t) mga_src_base + baseadrofs; |
48 | 560 regs.besa2org = (uint32_t) mga_src_base + baseadrofs + 1*frame_size; |
561 regs.besb1org = (uint32_t) mga_src_base + baseadrofs + 2*frame_size; | |
562 regs.besb2org = (uint32_t) mga_src_base + baseadrofs + 3*frame_size; | |
1 | 563 |
470 | 564 if(config->format==MGA_VID_FORMAT_YV12 |
565 ||config->format==MGA_VID_FORMAT_IYUV | |
566 ||config->format==MGA_VID_FORMAT_I420 | |
567 ){ | |
57 | 568 // planar YUV frames: |
1 | 569 if (is_g400) |
570 baseadrofs = (((ofstop*regs.besviscal)/4)>>16)*regs.bespitch; | |
571 else | |
572 baseadrofs = (((ofstop*regs.besviscal)/2)>>16)*regs.bespitch; | |
573 | |
470 | 574 if(config->format==MGA_VID_FORMAT_YV12){ |
1 | 575 regs.besa1corg = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; |
48 | 576 regs.besa2corg = (uint32_t) mga_src_base + baseadrofs + 1*frame_size + regs.bespitch * sh; |
577 regs.besb1corg = (uint32_t) mga_src_base + baseadrofs + 2*frame_size + regs.bespitch * sh; | |
578 regs.besb2corg = (uint32_t) mga_src_base + baseadrofs + 3*frame_size + regs.bespitch * sh; | |
1 | 579 regs.besa1c3org = regs.besa1corg + ((regs.bespitch * sh) / 4); |
48 | 580 regs.besa2c3org = regs.besa2corg + ((regs.bespitch * sh) / 4); |
1 | 581 regs.besb1c3org = regs.besb1corg + ((regs.bespitch * sh) / 4); |
48 | 582 regs.besb2c3org = regs.besb2corg + ((regs.bespitch * sh) / 4); |
470 | 583 } else { |
584 regs.besa1c3org = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; | |
585 regs.besa2c3org = (uint32_t) mga_src_base + baseadrofs + 1*frame_size + regs.bespitch * sh; | |
586 regs.besb1c3org = (uint32_t) mga_src_base + baseadrofs + 2*frame_size + regs.bespitch * sh; | |
587 regs.besb2c3org = (uint32_t) mga_src_base + baseadrofs + 3*frame_size + regs.bespitch * sh; | |
588 regs.besa1corg = regs.besa1c3org + ((regs.bespitch * sh) / 4); | |
589 regs.besa2corg = regs.besa2c3org + ((regs.bespitch * sh) / 4); | |
590 regs.besb1corg = regs.besb1c3org + ((regs.bespitch * sh) / 4); | |
591 regs.besb2corg = regs.besb2c3org + ((regs.bespitch * sh) / 4); | |
592 } | |
593 | |
57 | 594 } |
1 | 595 |
596 weight = ofstop * (regs.besviscal >> 2); | |
597 weights = weight < 0 ? 1 : 0; | |
48 | 598 regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2); |
599 regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF); | |
1 | 600 |
2086 | 601 mga_vid_write_regs(0); |
1 | 602 return 0; |
603 } | |
604 | |
68 | 605 #ifdef MGA_ALLOW_IRQ |
606 | |
48 | 607 static void enable_irq(){ |
608 long int cc; | |
609 | |
610 cc = readl(mga_mmio_base + IEN); | |
63 | 611 // printk(KERN_ALERT "*** !!! IRQREG = %d\n", (int)(cc&0xff)); |
48 | 612 |
613 writeb( 0x11, mga_mmio_base + CRTCX); | |
614 | |
615 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ | |
616 writeb(0x00, mga_mmio_base + CRTCD ); /* enable on */ | |
617 writeb(0x10, mga_mmio_base + CRTCD ); /* clear = 1 */ | |
618 | |
619 writel( regs.besglobctl , mga_mmio_base + BESGLOBCTL); | |
620 | |
621 } | |
622 | |
623 static void disable_irq(){ | |
624 | |
625 writeb( 0x11, mga_mmio_base + CRTCX); | |
626 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ | |
627 | |
628 } | |
629 | |
630 void mga_handle_irq(int irq, void *dev_id, struct pt_regs *pregs) { | |
631 // static int frame=0; | |
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632 // static int counter=0; |
48 | 633 long int cc; |
634 // if ( ! mga_enabled_flag ) return; | |
635 | |
68 | 636 // printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT)); |
637 | |
48 | 638 //printk("mga_interrupt #%d\n", irq); |
639 | |
640 if ( irq != -1 ) { | |
641 | |
642 cc = readl(mga_mmio_base + STATUS); | |
643 if ( ! (cc & 0x10) ) return; /* vsyncpen */ | |
644 // debug_irqcnt++; | |
645 } | |
646 | |
647 // if ( debug_irqignore ) { | |
648 // debug_irqignore = 0; | |
649 | |
650 | |
651 /* | |
652 if ( mga_conf_deinterlace ) { | |
653 if ( mga_first_field ) { | |
654 // printk("mga_interrupt first field\n"); | |
655 if ( syncfb_interrupt() ) | |
656 mga_first_field = 0; | |
657 } else { | |
658 // printk("mga_interrupt second field\n"); | |
659 mga_select_buffer( mga_current_field | 2 ); | |
660 mga_first_field = 1; | |
661 } | |
662 } else { | |
663 syncfb_interrupt(); | |
664 } | |
665 */ | |
666 | |
667 // frame=(frame+1)&1; | |
668 regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25); | |
669 writel( regs.besctl, mga_mmio_base + BESCTL ); | |
670 | |
671 #if 0 | |
672 ++counter; | |
673 if(!(counter&63)){ | |
674 printk("mga irq counter = %d\n",counter); | |
675 } | |
676 #endif | |
677 | |
678 // } else { | |
679 // debug_irqignore = 1; | |
680 // } | |
681 | |
682 if ( irq != -1 ) { | |
683 writeb( 0x11, mga_mmio_base + CRTCX); | |
684 writeb( 0, mga_mmio_base + CRTCD ); | |
685 writeb( 0x10, mga_mmio_base + CRTCD ); | |
686 } | |
687 | |
688 // writel( regs.besglobctl, mga_mmio_base + BESGLOBCTL); | |
689 | |
690 | |
691 return; | |
692 | |
693 } | |
694 | |
68 | 695 #endif |
1 | 696 |
697 static int mga_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) | |
698 { | |
699 int frame; | |
700 | |
701 switch(cmd) | |
702 { | |
703 case MGA_VID_CONFIG: | |
704 //FIXME remove | |
68 | 705 // printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT)); |
61 | 706 printk(KERN_DEBUG "mga_mmio_base = %p\n",mga_mmio_base); |
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707 printk(KERN_DEBUG "mga_mem_base = %08x\n",mga_mem_base); |
1 | 708 //FIXME remove |
709 | |
61 | 710 printk(KERN_DEBUG "mga_vid: Received configuration\n"); |
1 | 711 |
712 if(copy_from_user(&mga_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t))) | |
713 { | |
61 | 714 printk(KERN_ERR "mga_vid: failed copy from userspace\n"); |
1 | 715 return(-EFAULT); |
716 } | |
57 | 717 if(mga_config.version != MGA_VID_VERSION){ |
61 | 718 printk(KERN_ERR "mga_vid: incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,mga_config.version); |
57 | 719 return(-EFAULT); |
720 } | |
721 | |
722 if(mga_config.frame_size==0 || mga_config.frame_size>1024*768*2){ | |
61 | 723 printk(KERN_ERR "mga_vid: illegal frame_size: %d\n",mga_config.frame_size); |
57 | 724 return(-EFAULT); |
725 } | |
726 | |
727 if(mga_config.num_frames<1 || mga_config.num_frames>4){ | |
61 | 728 printk(KERN_ERR "mga_vid: illegal num_frames: %d\n",mga_config.num_frames); |
57 | 729 return(-EFAULT); |
730 } | |
731 | |
732 mga_src_base = (mga_ram_size*0x100000-mga_config.num_frames*mga_config.frame_size); | |
733 if(mga_src_base<0){ | |
61 | 734 printk(KERN_ERR "mga_vid: not enough memory for frames!\n"); |
57 | 735 return(-EFAULT); |
736 } | |
737 mga_src_base &= (~0xFFFF); // 64k boundary | |
61 | 738 printk(KERN_DEBUG "mga YUV buffer base: 0x%X\n", mga_src_base); |
57 | 739 |
1 | 740 if (is_g400) |
741 mga_config.card_type = MGA_G400; | |
742 else | |
743 mga_config.card_type = MGA_G200; | |
744 | |
745 mga_config.ram_size = mga_ram_size; | |
746 | |
747 if (copy_to_user((mga_vid_config_t *) arg, &mga_config, sizeof(mga_vid_config_t))) | |
748 { | |
61 | 749 printk(KERN_ERR "mga_vid: failed copy to userspace\n"); |
1 | 750 return(-EFAULT); |
751 } | |
752 return mga_vid_set_config(&mga_config); | |
753 break; | |
754 | |
755 case MGA_VID_ON: | |
61 | 756 printk(KERN_DEBUG "mga_vid: Video ON\n"); |
1 | 757 vid_src_ready = 1; |
758 if(vid_overlay_on) | |
759 { | |
760 regs.besctl |= 1; | |
2086 | 761 mga_vid_write_regs(0); |
1 | 762 } |
68 | 763 #ifdef MGA_ALLOW_IRQ |
48 | 764 if ( mga_irq != -1 ) enable_irq(); |
68 | 765 #endif |
48 | 766 mga_next_frame=0; |
1 | 767 break; |
768 | |
769 case MGA_VID_OFF: | |
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770 printk(KERN_DEBUG "mga_vid: Video OFF (ioctl)\n"); |
1 | 771 vid_src_ready = 0; |
68 | 772 #ifdef MGA_ALLOW_IRQ |
48 | 773 if ( mga_irq != -1 ) disable_irq(); |
68 | 774 #endif |
1 | 775 regs.besctl &= ~1; |
466 | 776 regs.besglobctl &= ~(1<<6); // UYVY format selected |
2086 | 777 mga_vid_write_regs(0); |
1 | 778 break; |
779 | |
780 case MGA_VID_FSEL: | |
781 if(copy_from_user(&frame,(int *) arg,sizeof(int))) | |
782 { | |
61 | 783 printk(KERN_ERR "mga_vid: FSEL failed copy from userspace\n"); |
1 | 784 return(-EFAULT); |
785 } | |
786 | |
787 mga_vid_frame_sel(frame); | |
788 break; | |
789 | |
790 default: | |
61 | 791 printk(KERN_ERR "mga_vid: Invalid ioctl\n"); |
1 | 792 return (-EINVAL); |
793 } | |
794 | |
795 return 0; | |
796 } | |
797 | |
798 | |
799 static int mga_vid_find_card(void) | |
800 { | |
801 struct pci_dev *dev = NULL; | |
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802 unsigned int card_option; |
1 | 803 |
1989 | 804 if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G550, NULL))) |
805 { | |
806 is_g400 = 1; | |
807 printk(KERN_INFO "mga_vid: Found MGA G550\n"); | |
808 } | |
809 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400, NULL))) | |
1 | 810 { |
811 is_g400 = 1; | |
77 | 812 printk(KERN_INFO "mga_vid: Found MGA G400/G450\n"); |
1 | 813 } |
814 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, NULL))) | |
815 { | |
816 is_g400 = 0; | |
63 | 817 printk(KERN_INFO "mga_vid: Found MGA G200 AGP\n"); |
1 | 818 } |
819 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_PCI, NULL))) | |
820 { | |
821 is_g400 = 0; | |
63 | 822 printk(KERN_INFO "mga_vid: Found MGA G200 PCI\n"); |
1 | 823 } |
824 else | |
825 { | |
61 | 826 printk(KERN_ERR "mga_vid: No supported cards found\n"); |
1 | 827 return FALSE; |
828 } | |
829 | |
830 pci_dev = dev; | |
48 | 831 |
832 mga_irq = pci_dev->irq; | |
1 | 833 |
834 #if LINUX_VERSION_CODE >= 0x020300 | |
835 mga_mmio_base = ioremap_nocache(dev->resource[1].start,0x4000); | |
836 mga_mem_base = dev->resource[0].start; | |
837 #else | |
838 mga_mmio_base = ioremap_nocache(dev->base_address[1] & PCI_BASE_ADDRESS_MEM_MASK,0x4000); | |
839 mga_mem_base = dev->base_address[0] & PCI_BASE_ADDRESS_MEM_MASK; | |
840 #endif | |
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841 printk(KERN_INFO "mga_vid: MMIO at 0x%p IRQ: %d framebuffer: 0x%08X\n", mga_mmio_base, mga_irq, mga_mem_base); |
1 | 842 |
843 pci_read_config_dword(dev, 0x40, &card_option); | |
77 | 844 printk(KERN_INFO "mga_vid: OPTION word: 0x%08X mem: 0x%02X %s\n", card_option, |
845 (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM"); | |
1 | 846 |
57 | 847 // temp = (card_option >> 10) & 0x17; |
848 | |
95 | 849 if (mga_ram_size) { |
850 printk(KERN_INFO "mga_vid: RAMSIZE forced to %d MB\n", mga_ram_size); | |
91 | 851 } else { |
90 | 852 |
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853 #ifdef MGA_MEMORY_SIZE |
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854 mga_ram_size = MGA_MEMORY_SIZE; |
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855 printk(KERN_INFO "mga_vid: hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); |
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856 |
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857 #else |
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858 |
95 | 859 if (is_g400){ |
75 | 860 switch((card_option>>10)&0x17){ |
861 // SDRAM: | |
862 case 0x00: | |
863 case 0x04: mga_ram_size = 16; break; | |
105 | 864 case 0x03: mga_ram_size = 32; break; |
75 | 865 // SGRAM: |
866 case 0x10: | |
867 case 0x14: mga_ram_size = 32; break; | |
868 case 0x11: | |
869 case 0x12: mga_ram_size = 16; break; | |
870 default: | |
871 mga_ram_size = 16; | |
872 printk(KERN_INFO "mga_vid: Couldn't detect RAMSIZE, assuming 16MB!"); | |
873 } | |
95 | 874 }else{ |
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875 switch((card_option>>10)&0x17){ |
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876 // case 0x10: |
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877 // case 0x13: mga_ram_size = 8; break; |
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878 default: mga_ram_size = 8; |
64 | 879 } |
95 | 880 } |
64 | 881 #if 0 |
95 | 882 // printk("List resources -----------\n"); |
883 for(temp=0;temp<DEVICE_COUNT_RESOURCE;temp++){ | |
884 struct resource *res=&pci_dev->resource[temp]; | |
885 if(res->flags){ | |
886 int size=(1+res->end-res->start)>>20; | |
887 printk(KERN_DEBUG "res %d: start: 0x%X end: 0x%X (%d MB) flags=0x%X\n",temp,res->start,res->end,size,res->flags); | |
888 if(res->flags&(IORESOURCE_MEM|IORESOURCE_PREFETCH)){ | |
889 if(size>mga_ram_size && size<=64) mga_ram_size=size; | |
890 } | |
891 } | |
57 | 892 } |
64 | 893 #endif |
95 | 894 printk(KERN_INFO "mga_vid: detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); |
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895 #endif |
95 | 896 } |
57 | 897 |
48 | 898 |
68 | 899 #ifdef MGA_ALLOW_IRQ |
48 | 900 if ( mga_irq != -1 ) { |
901 int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq); | |
902 if ( tmp ) { | |
61 | 903 printk(KERN_INFO "syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp); |
48 | 904 mga_irq=-1; |
905 } else { | |
61 | 906 printk(KERN_DEBUG "syncfb (mga): registered irq %d\n", mga_irq); |
48 | 907 } |
908 } else { | |
61 | 909 printk(KERN_INFO "syncfb (mga): No valid irq was found\n"); |
48 | 910 mga_irq=-1; |
911 } | |
68 | 912 #else |
913 printk(KERN_INFO "syncfb (mga): IRQ disabled in mga_vid.c\n"); | |
914 mga_irq=-1; | |
915 #endif | |
48 | 916 |
1 | 917 return TRUE; |
918 } | |
919 | |
920 | |
921 static ssize_t mga_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) | |
922 { | |
923 return -EINVAL; | |
924 } | |
925 | |
926 static ssize_t mga_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) | |
927 { | |
928 return -EINVAL; | |
929 } | |
930 | |
931 static int mga_vid_mmap(struct file *file, struct vm_area_struct *vma) | |
932 { | |
933 | |
61 | 934 printk(KERN_DEBUG "mga_vid: mapping video memory into userspace\n"); |
57 | 935 if(remap_page_range(vma->vm_start, mga_mem_base + mga_src_base, |
1 | 936 vma->vm_end - vma->vm_start, vma->vm_page_prot)) |
937 { | |
63 | 938 printk(KERN_ERR "mga_vid: error mapping video memory\n"); |
1 | 939 return(-EAGAIN); |
940 } | |
941 | |
942 return(0); | |
943 } | |
944 | |
945 static int mga_vid_release(struct inode *inode, struct file *file) | |
946 { | |
947 //Close the window just in case | |
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948 printk(KERN_DEBUG "mga_vid: Video OFF (release)\n"); |
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949 |
1 | 950 vid_src_ready = 0; |
951 regs.besctl &= ~1; | |
466 | 952 regs.besglobctl &= ~(1<<6); // UYVY format selected |
2086 | 953 // mga_config.colkey_on=0; //!!! |
954 mga_vid_write_regs(1); | |
1 | 955 mga_vid_in_use = 0; |
956 | |
93 | 957 MOD_DEC_USE_COUNT; |
1 | 958 return 0; |
959 } | |
960 | |
961 static long long mga_vid_lseek(struct file *file, long long offset, int origin) | |
962 { | |
963 return -ESPIPE; | |
964 } | |
965 | |
966 static int mga_vid_open(struct inode *inode, struct file *file) | |
967 { | |
968 int minor = MINOR(inode->i_rdev); | |
969 | |
970 if(minor != 0) | |
971 return(-ENXIO); | |
972 | |
973 if(mga_vid_in_use == 1) | |
974 return(-EBUSY); | |
975 | |
976 mga_vid_in_use = 1; | |
93 | 977 MOD_INC_USE_COUNT; |
1 | 978 return(0); |
979 } | |
980 | |
981 #if LINUX_VERSION_CODE >= 0x020400 | |
982 static struct file_operations mga_vid_fops = | |
983 { | |
984 llseek: mga_vid_lseek, | |
985 read: mga_vid_read, | |
986 write: mga_vid_write, | |
987 ioctl: mga_vid_ioctl, | |
988 mmap: mga_vid_mmap, | |
989 open: mga_vid_open, | |
990 release: mga_vid_release | |
991 }; | |
992 #else | |
993 static struct file_operations mga_vid_fops = | |
994 { | |
995 mga_vid_lseek, | |
996 mga_vid_read, | |
997 mga_vid_write, | |
998 NULL, | |
999 NULL, | |
1000 mga_vid_ioctl, | |
1001 mga_vid_mmap, | |
1002 mga_vid_open, | |
1003 NULL, | |
1004 mga_vid_release | |
1005 }; | |
1006 #endif | |
1007 | |
1008 | |
1009 /* | |
1010 * Main Initialization Function | |
1011 */ | |
1012 | |
1013 static int mga_vid_initialize(void) | |
1014 { | |
1015 mga_vid_in_use = 0; | |
1016 | |
77 | 1017 // printk(KERN_INFO "Matrox MGA G200/G400 YUV Video interface v0.01 (c) Aaron Holtzman \n"); |
1018 printk(KERN_INFO "Matrox MGA G200/G400/G450 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n"); | |
90 | 1019 |
95 | 1020 if (mga_ram_size) { |
1021 if (mga_ram_size<4 || mga_ram_size>64) { | |
1022 printk(KERN_ERR "mga_vid: invalid RAMSIZE: %d MB\n", mga_ram_size); | |
90 | 1023 return -EINVAL; |
1024 } | |
1025 } | |
1026 | |
1 | 1027 if(register_chrdev(MGA_VID_MAJOR, "mga_vid", &mga_vid_fops)) |
1028 { | |
61 | 1029 printk(KERN_ERR "mga_vid: unable to get major: %d\n", MGA_VID_MAJOR); |
1 | 1030 return -EIO; |
1031 } | |
1032 | |
1033 if (!mga_vid_find_card()) | |
1034 { | |
61 | 1035 printk(KERN_ERR "mga_vid: no supported devices found\n"); |
1 | 1036 unregister_chrdev(MGA_VID_MAJOR, "mga_vid"); |
1037 return -EINVAL; | |
1038 } | |
1039 | |
1040 return(0); | |
1041 } | |
1042 | |
1043 int init_module(void) | |
1044 { | |
1045 return mga_vid_initialize(); | |
1046 } | |
1047 | |
1048 void cleanup_module(void) | |
1049 { | |
48 | 1050 |
68 | 1051 #ifdef MGA_ALLOW_IRQ |
48 | 1052 if ( mga_irq != -1) |
1053 free_irq(mga_irq, &mga_irq); | |
68 | 1054 #endif |
48 | 1055 |
1 | 1056 if(mga_mmio_base) |
1057 iounmap(mga_mmio_base); | |
1058 | |
1059 //FIXME turn off BES | |
63 | 1060 printk(KERN_INFO "mga_vid: Cleaning up module\n"); |
1 | 1061 unregister_chrdev(MGA_VID_MAJOR, "mga_vid"); |
1062 } | |
1063 |