Mercurial > mplayer.hg
annotate vidix/drivers/radeon_vid.c @ 4030:922241968c63
Embedding vidix
author | nick |
---|---|
date | Mon, 07 Jan 2002 09:28:22 +0000 |
parents | 7a9c22d1d984 |
children | 94602bcd13d0 |
rev | line source |
---|---|
3996 | 1 /* |
2 radeon_vid - VIDIX based video driver for Radeon and Rage128 chips | |
4030 | 3 Copyrights 2002 Nick Kurshev. This file is based on sources from |
4 GATOS (gatos.sf.net) and X11 (www.xfree86.org) | |
5 Licence: GPL | |
3996 | 6 */ |
7 | |
8 #include <linux/pci_ids.h> | |
9 #include <errno.h> | |
10 #include <stdio.h> | |
11 #include <stdlib.h> | |
12 #include <string.h> | |
13 #include <math.h> | |
4003
92c59012249d
stdint.h replaced by inttypes.h (used more frequently in the sources)
pl
parents:
3996
diff
changeset
|
14 #include <inttypes.h> |
3996 | 15 #include "../vidix.h" |
16 #include "../fourcc.h" | |
17 #include "../../libdha/libdha.h" | |
18 #include "radeon.h" | |
19 | |
20 #ifdef RAGE128 | |
21 #define RADEON_MSG "Rage128_vid:" | |
22 #define X_ADJUST 0 | |
23 #else | |
24 #define RADEON_MSG "Radeon_vid:" | |
25 #define X_ADJUST 8 | |
26 #ifndef RADEON | |
27 #define RADEON | |
28 #endif | |
29 #endif | |
30 | |
4030 | 31 static int __verbose = 0; |
4015 | 32 |
3996 | 33 typedef struct bes_registers_s |
34 { | |
35 /* base address of yuv framebuffer */ | |
36 uint32_t yuv_base; | |
37 uint32_t fourcc; | |
38 uint32_t dest_bpp; | |
39 /* YUV BES registers */ | |
40 uint32_t reg_load_cntl; | |
41 uint32_t h_inc; | |
42 uint32_t step_by; | |
43 uint32_t y_x_start; | |
44 uint32_t y_x_end; | |
45 uint32_t v_inc; | |
46 uint32_t p1_blank_lines_at_top; | |
47 uint32_t p23_blank_lines_at_top; | |
48 uint32_t vid_buf_pitch0_value; | |
49 uint32_t vid_buf_pitch1_value; | |
50 uint32_t p1_x_start_end; | |
51 uint32_t p2_x_start_end; | |
52 uint32_t p3_x_start_end; | |
53 uint32_t base_addr; | |
54 uint32_t vid_buf0_base_adrs; | |
55 /* These ones are for auto flip: maybe in the future */ | |
56 uint32_t vid_buf1_base_adrs; | |
57 uint32_t vid_buf2_base_adrs; | |
58 uint32_t vid_buf3_base_adrs; | |
59 uint32_t vid_buf4_base_adrs; | |
60 uint32_t vid_buf5_base_adrs; | |
61 | |
62 uint32_t p1_v_accum_init; | |
63 uint32_t p1_h_accum_init; | |
64 uint32_t p23_v_accum_init; | |
65 uint32_t p23_h_accum_init; | |
66 uint32_t scale_cntl; | |
67 uint32_t exclusive_horz; | |
68 uint32_t auto_flip_cntl; | |
69 uint32_t filter_cntl; | |
70 uint32_t key_cntl; | |
71 uint32_t test; | |
72 /* Configurable stuff */ | |
73 int double_buff; | |
74 | |
75 int brightness; | |
76 int saturation; | |
77 | |
78 int ckey_on; | |
79 uint32_t graphics_key_clr; | |
80 uint32_t graphics_key_msk; | |
81 | |
82 int deinterlace_on; | |
83 uint32_t deinterlace_pattern; | |
84 | |
85 } bes_registers_t; | |
86 | |
87 typedef struct video_registers_s | |
88 { | |
89 const char * sname; | |
90 uint32_t name; | |
91 uint32_t value; | |
92 }video_registers_t; | |
93 | |
94 static bes_registers_t besr; | |
95 #ifndef RAGE128 | |
96 static int IsR200=0; | |
97 #endif | |
98 #define DECLARE_VREG(name) { #name, name, 0 } | |
99 static video_registers_t vregs[] = | |
100 { | |
101 DECLARE_VREG(VIDEOMUX_CNTL), | |
102 DECLARE_VREG(VIPPAD_MASK), | |
103 DECLARE_VREG(VIPPAD1_A), | |
104 DECLARE_VREG(VIPPAD1_EN), | |
105 DECLARE_VREG(VIPPAD1_Y), | |
106 DECLARE_VREG(OV0_Y_X_START), | |
107 DECLARE_VREG(OV0_Y_X_END), | |
108 DECLARE_VREG(OV0_PIPELINE_CNTL), | |
109 DECLARE_VREG(OV0_EXCLUSIVE_HORZ), | |
110 DECLARE_VREG(OV0_EXCLUSIVE_VERT), | |
111 DECLARE_VREG(OV0_REG_LOAD_CNTL), | |
112 DECLARE_VREG(OV0_SCALE_CNTL), | |
113 DECLARE_VREG(OV0_V_INC), | |
114 DECLARE_VREG(OV0_P1_V_ACCUM_INIT), | |
115 DECLARE_VREG(OV0_P23_V_ACCUM_INIT), | |
116 DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), | |
117 DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), | |
118 #ifdef RADEON | |
119 DECLARE_VREG(OV0_BASE_ADDR), | |
120 #endif | |
121 DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), | |
122 DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), | |
123 DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), | |
124 DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), | |
125 DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), | |
126 DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), | |
127 DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), | |
128 DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), | |
129 DECLARE_VREG(OV0_AUTO_FLIP_CNTL), | |
130 DECLARE_VREG(OV0_DEINTERLACE_PATTERN), | |
131 DECLARE_VREG(OV0_SUBMIT_HISTORY), | |
132 DECLARE_VREG(OV0_H_INC), | |
133 DECLARE_VREG(OV0_STEP_BY), | |
134 DECLARE_VREG(OV0_P1_H_ACCUM_INIT), | |
135 DECLARE_VREG(OV0_P23_H_ACCUM_INIT), | |
136 DECLARE_VREG(OV0_P1_X_START_END), | |
137 DECLARE_VREG(OV0_P2_X_START_END), | |
138 DECLARE_VREG(OV0_P3_X_START_END), | |
139 DECLARE_VREG(OV0_FILTER_CNTL), | |
140 DECLARE_VREG(OV0_FOUR_TAP_COEF_0), | |
141 DECLARE_VREG(OV0_FOUR_TAP_COEF_1), | |
142 DECLARE_VREG(OV0_FOUR_TAP_COEF_2), | |
143 DECLARE_VREG(OV0_FOUR_TAP_COEF_3), | |
144 DECLARE_VREG(OV0_FOUR_TAP_COEF_4), | |
145 DECLARE_VREG(OV0_FLAG_CNTL), | |
146 #ifdef RAGE128 | |
147 DECLARE_VREG(OV0_COLOUR_CNTL), | |
148 #else | |
149 DECLARE_VREG(OV0_SLICE_CNTL), | |
150 #endif | |
151 DECLARE_VREG(OV0_VID_KEY_CLR), | |
152 DECLARE_VREG(OV0_VID_KEY_MSK), | |
153 DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), | |
154 DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), | |
155 DECLARE_VREG(OV0_KEY_CNTL), | |
156 DECLARE_VREG(OV0_TEST), | |
157 DECLARE_VREG(OV0_LIN_TRANS_A), | |
158 DECLARE_VREG(OV0_LIN_TRANS_B), | |
159 DECLARE_VREG(OV0_LIN_TRANS_C), | |
160 DECLARE_VREG(OV0_LIN_TRANS_D), | |
161 DECLARE_VREG(OV0_LIN_TRANS_E), | |
162 DECLARE_VREG(OV0_LIN_TRANS_F), | |
163 DECLARE_VREG(OV0_GAMMA_0_F), | |
164 DECLARE_VREG(OV0_GAMMA_10_1F), | |
165 DECLARE_VREG(OV0_GAMMA_20_3F), | |
166 DECLARE_VREG(OV0_GAMMA_40_7F), | |
167 DECLARE_VREG(OV0_GAMMA_380_3BF), | |
168 DECLARE_VREG(OV0_GAMMA_3C0_3FF), | |
169 DECLARE_VREG(SUBPIC_CNTL), | |
170 DECLARE_VREG(SUBPIC_DEFCOLCON), | |
171 DECLARE_VREG(SUBPIC_Y_X_START), | |
172 DECLARE_VREG(SUBPIC_Y_X_END), | |
173 DECLARE_VREG(SUBPIC_V_INC), | |
174 DECLARE_VREG(SUBPIC_H_INC), | |
175 DECLARE_VREG(SUBPIC_BUF0_OFFSET), | |
176 DECLARE_VREG(SUBPIC_BUF1_OFFSET), | |
177 DECLARE_VREG(SUBPIC_LC0_OFFSET), | |
178 DECLARE_VREG(SUBPIC_LC1_OFFSET), | |
179 DECLARE_VREG(SUBPIC_PITCH), | |
180 DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), | |
181 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), | |
182 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), | |
183 DECLARE_VREG(SUBPIC_PALETTE_INDEX), | |
184 DECLARE_VREG(SUBPIC_PALETTE_DATA), | |
185 DECLARE_VREG(SUBPIC_H_ACCUM_INIT), | |
186 DECLARE_VREG(SUBPIC_V_ACCUM_INIT), | |
187 DECLARE_VREG(IDCT_RUNS), | |
188 DECLARE_VREG(IDCT_LEVELS), | |
189 DECLARE_VREG(IDCT_AUTH_CONTROL), | |
190 DECLARE_VREG(IDCT_AUTH), | |
191 DECLARE_VREG(IDCT_CONTROL) | |
192 }; | |
4030 | 193 |
3996 | 194 static void * radeon_mmio_base = 0; |
195 static void * radeon_mem_base = 0; | |
196 static int32_t radeon_overlay_off = 0; | |
197 static uint32_t radeon_ram_size = 0; | |
198 | |
4012 | 199 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) |
200 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
201 | |
202 #define INREG8(addr) GETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr) | |
203 #define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr,val) | |
204 #define INREG(addr) GETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr) | |
205 #define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,val) | |
3996 | 206 #define OUTREGP(addr,val,mask) \ |
207 do { \ | |
208 unsigned int _tmp = INREG(addr); \ | |
209 _tmp &= (mask); \ | |
210 _tmp |= (val); \ | |
211 OUTREG(addr, _tmp); \ | |
212 } while (0) | |
213 | |
214 static uint32_t radeon_vid_get_dbpp( void ) | |
215 { | |
216 uint32_t dbpp,retval; | |
217 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; | |
218 switch(dbpp) | |
219 { | |
220 case DST_8BPP: retval = 8; break; | |
221 case DST_15BPP: retval = 15; break; | |
222 case DST_16BPP: retval = 16; break; | |
223 case DST_24BPP: retval = 24; break; | |
224 default: retval=32; break; | |
225 } | |
226 return retval; | |
227 } | |
228 | |
229 static int radeon_is_dbl_scan( void ) | |
230 { | |
231 return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; | |
232 } | |
233 | |
234 static int radeon_is_interlace( void ) | |
235 { | |
236 return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; | |
237 } | |
238 | |
239 static __inline__ void radeon_engine_flush ( void ) | |
240 { | |
241 int i; | |
242 | |
243 /* initiate flush */ | |
244 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, | |
245 ~RB2D_DC_FLUSH_ALL); | |
246 | |
247 for (i=0; i < 2000000; i++) { | |
248 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) | |
249 break; | |
250 } | |
251 } | |
252 | |
253 | |
254 static __inline__ void _radeon_fifo_wait (unsigned entries) | |
255 { | |
256 int i; | |
257 | |
258 for (i=0; i<2000000; i++) | |
259 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) | |
260 return; | |
261 } | |
262 | |
263 | |
264 static __inline__ void _radeon_engine_idle ( void ) | |
265 { | |
266 int i; | |
267 | |
268 /* ensure FIFO is empty before waiting for idle */ | |
269 _radeon_fifo_wait (64); | |
270 | |
271 for (i=0; i<2000000; i++) { | |
272 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { | |
273 radeon_engine_flush (); | |
274 return; | |
275 } | |
276 } | |
277 } | |
278 | |
279 #define radeon_engine_idle() _radeon_engine_idle() | |
280 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) | |
281 | |
282 | |
283 #ifndef RAGE128 | |
284 /* Reference color space transform data */ | |
285 typedef struct tagREF_TRANSFORM | |
286 { | |
287 float RefLuma; | |
288 float RefRCb; | |
289 float RefRCr; | |
290 float RefGCb; | |
291 float RefGCr; | |
292 float RefBCb; | |
293 float RefBCr; | |
294 } REF_TRANSFORM; | |
295 | |
296 /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ | |
297 REF_TRANSFORM trans[2] = | |
298 { | |
299 {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ | |
300 {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ | |
301 }; | |
302 /**************************************************************************** | |
303 * SetTransform * | |
304 * Function: Calculates and sets color space transform from supplied * | |
305 * reference transform, gamma, brightness, contrast, hue and * | |
306 * saturation. * | |
307 * Inputs: bright - brightness * | |
308 * cont - contrast * | |
309 * sat - saturation * | |
310 * hue - hue * | |
311 * ref - index to the table of refernce transforms * | |
312 * Outputs: NONE * | |
313 ****************************************************************************/ | |
314 | |
315 static void radeon_set_transform(float bright, float cont, float sat, | |
316 float hue, unsigned ref) | |
317 { | |
318 float OvHueSin, OvHueCos; | |
319 float CAdjLuma, CAdjOff; | |
320 float CAdjRCb, CAdjRCr; | |
321 float CAdjGCb, CAdjGCr; | |
322 float CAdjBCb, CAdjBCr; | |
323 float OvLuma, OvROff, OvGOff, OvBOff; | |
324 float OvRCb, OvRCr; | |
325 float OvGCb, OvGCr; | |
326 float OvBCb, OvBCr; | |
327 float Loff = 64.0; | |
328 float Coff = 512.0f; | |
329 | |
330 uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; | |
331 uint32_t dwOvRCb, dwOvRCr; | |
332 uint32_t dwOvGCb, dwOvGCr; | |
333 uint32_t dwOvBCb, dwOvBCr; | |
334 | |
335 if (ref >= 2) return; | |
336 | |
337 OvHueSin = sin((double)hue); | |
338 OvHueCos = cos((double)hue); | |
339 | |
340 CAdjLuma = cont * trans[ref].RefLuma; | |
341 CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; | |
342 | |
343 CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; | |
344 CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; | |
345 CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); | |
346 CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); | |
347 CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; | |
348 CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; | |
349 | |
350 #if 0 /* default constants */ | |
351 CAdjLuma = 1.16455078125; | |
352 | |
353 CAdjRCb = 0.0; | |
354 CAdjRCr = 1.59619140625; | |
355 CAdjGCb = -0.39111328125; | |
356 CAdjGCr = -0.8125; | |
357 CAdjBCb = 2.01708984375; | |
358 CAdjBCr = 0; | |
359 #endif | |
360 OvLuma = CAdjLuma; | |
361 OvRCb = CAdjRCb; | |
362 OvRCr = CAdjRCr; | |
363 OvGCb = CAdjGCb; | |
364 OvGCr = CAdjGCr; | |
365 OvBCb = CAdjBCb; | |
366 OvBCr = CAdjBCr; | |
367 OvROff = CAdjOff - | |
368 OvLuma * Loff - (OvRCb + OvRCr) * Coff; | |
369 OvGOff = CAdjOff - | |
370 OvLuma * Loff - (OvGCb + OvGCr) * Coff; | |
371 OvBOff = CAdjOff - | |
372 OvLuma * Loff - (OvBCb + OvBCr) * Coff; | |
373 #if 0 /* default constants */ | |
374 OvROff = -888.5; | |
375 OvGOff = 545; | |
376 OvBOff = -1104; | |
377 #endif | |
378 | |
379 dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; | |
380 dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; | |
381 dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; | |
382 if(!IsR200) | |
383 { | |
384 dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; | |
385 dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; | |
386 dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; | |
387 dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; | |
388 dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; | |
389 dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; | |
390 dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; | |
391 } | |
392 else | |
393 { | |
394 dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; | |
395 dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; | |
396 dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; | |
397 dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; | |
398 dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; | |
399 dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; | |
400 dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; | |
401 } | |
402 | |
403 OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); | |
404 OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); | |
405 OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); | |
406 OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); | |
407 OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); | |
408 OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); | |
409 } | |
410 | |
411 /* Gamma curve definition */ | |
412 typedef struct | |
413 { | |
414 unsigned int gammaReg; | |
415 unsigned int gammaSlope; | |
416 unsigned int gammaOffset; | |
417 }GAMMA_SETTINGS; | |
418 | |
419 /* Recommended gamma curve parameters */ | |
420 GAMMA_SETTINGS r200_def_gamma[18] = | |
421 { | |
422 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
423 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
424 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
425 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
426 {OV0_GAMMA_80_BF, 0x100, 0x0100}, | |
427 {OV0_GAMMA_C0_FF, 0x100, 0x0100}, | |
428 {OV0_GAMMA_100_13F, 0x100, 0x0200}, | |
429 {OV0_GAMMA_140_17F, 0x100, 0x0200}, | |
430 {OV0_GAMMA_180_1BF, 0x100, 0x0300}, | |
431 {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, | |
432 {OV0_GAMMA_200_23F, 0x100, 0x0400}, | |
433 {OV0_GAMMA_240_27F, 0x100, 0x0400}, | |
434 {OV0_GAMMA_280_2BF, 0x100, 0x0500}, | |
435 {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, | |
436 {OV0_GAMMA_300_33F, 0x100, 0x0600}, | |
437 {OV0_GAMMA_340_37F, 0x100, 0x0600}, | |
438 {OV0_GAMMA_380_3BF, 0x100, 0x0700}, | |
439 {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} | |
440 }; | |
441 | |
442 GAMMA_SETTINGS r100_def_gamma[6] = | |
443 { | |
444 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
445 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
446 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
447 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
448 {OV0_GAMMA_380_3BF, 0x100, 0x0100}, | |
449 {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} | |
450 }; | |
451 | |
452 static void make_default_gamma_correction( void ) | |
453 { | |
454 size_t i; | |
455 if(!IsR200){ | |
456 OUTREG(OV0_LIN_TRANS_A, 0x12A00000); | |
457 OUTREG(OV0_LIN_TRANS_B, 0x199018FE); | |
458 OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); | |
459 OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); | |
460 OUTREG(OV0_LIN_TRANS_E, 0x12A02050); | |
461 OUTREG(OV0_LIN_TRANS_F, 0x0000174E); | |
462 for(i=0; i<6; i++){ | |
463 OUTREG(r100_def_gamma[i].gammaReg, | |
464 (r100_def_gamma[i].gammaSlope<<16) | | |
465 r100_def_gamma[i].gammaOffset); | |
466 } | |
467 } | |
468 else{ | |
469 OUTREG(OV0_LIN_TRANS_A, 0x12a00000); | |
470 OUTREG(OV0_LIN_TRANS_B, 0x1990190e); | |
471 OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); | |
472 OUTREG(OV0_LIN_TRANS_D, 0xf3000442); | |
473 OUTREG(OV0_LIN_TRANS_E, 0x12a02040); | |
474 OUTREG(OV0_LIN_TRANS_F, 0x175f); | |
475 | |
476 /* Default Gamma, | |
477 Of 18 segments for gamma cure, all segments in R200 are programmable, | |
478 while only lower 4 and upper 2 segments are programmable in Radeon*/ | |
479 for(i=0; i<18; i++){ | |
480 OUTREG(r200_def_gamma[i].gammaReg, | |
481 (r200_def_gamma[i].gammaSlope<<16) | | |
482 r200_def_gamma[i].gammaOffset); | |
483 } | |
484 } | |
485 } | |
486 #endif | |
487 | |
488 static void radeon_vid_make_default(void) | |
489 { | |
490 #ifdef RAGE128 | |
491 OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brihgtness and saturation for Rage128 */ | |
492 #else | |
493 make_default_gamma_correction(); | |
494 #endif | |
495 besr.deinterlace_pattern = 0x900AAAAA; | |
496 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
497 besr.deinterlace_on=1; | |
498 besr.double_buff=1; | |
499 } | |
500 | |
501 | |
502 unsigned vixGetVersion( void ) { return VIDIX_VERSION; } | |
503 | |
504 struct ati_card_id_s | |
505 { | |
506 const unsigned id; | |
507 const char name[17]; | |
508 }; | |
509 | |
510 const struct ati_card_id_s ati_card_ids[]= | |
511 { | |
512 #ifdef RAGE128 | |
513 /* | |
514 This driver should be compatible with Rage128 (pro) chips. | |
515 (include adaptive deinterlacing!!!). | |
516 Moreover: the same logic can be used with Mach64 chips. | |
517 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
518 but they are incompatible by i/o ports. So if enthusiasts will want | |
519 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
520 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
521 fourccs (422 and 420 formats only). | |
522 */ | |
523 /* Rage128 Pro GL */ | |
524 { PCI_DEVICE_ID_ATI_Rage128_PA, "R128Pro PA" }, | |
525 { PCI_DEVICE_ID_ATI_Rage128_PB, "R128Pro PB" }, | |
526 { PCI_DEVICE_ID_ATI_Rage128_PC, "R128Pro PC" }, | |
527 { PCI_DEVICE_ID_ATI_Rage128_PD, "R128Pro PD" }, | |
528 { PCI_DEVICE_ID_ATI_Rage128_PE, "R128Pro PE" }, | |
529 { PCI_DEVICE_ID_ATI_RAGE128_PF, "R128Pro PF" }, | |
530 /* Rage128 Pro VR */ | |
531 { PCI_DEVICE_ID_ATI_RAGE128_PG, "R128Pro PG" }, | |
532 { PCI_DEVICE_ID_ATI_RAGE128_PH, "R128Pro PH" }, | |
533 { PCI_DEVICE_ID_ATI_RAGE128_PI, "R128Pro PI" }, | |
534 { PCI_DEVICE_ID_ATI_RAGE128_PJ, "R128Pro PJ" }, | |
535 { PCI_DEVICE_ID_ATI_RAGE128_PK, "R128Pro PK" }, | |
536 { PCI_DEVICE_ID_ATI_RAGE128_PL, "R128Pro PL" }, | |
537 { PCI_DEVICE_ID_ATI_RAGE128_PM, "R128Pro PM" }, | |
538 { PCI_DEVICE_ID_ATI_RAGE128_PN, "R128Pro PN" }, | |
539 { PCI_DEVICE_ID_ATI_RAGE128_PO, "R128Pro PO" }, | |
540 { PCI_DEVICE_ID_ATI_RAGE128_PP, "R128Pro PP" }, | |
541 { PCI_DEVICE_ID_ATI_RAGE128_PQ, "R128Pro PQ" }, | |
542 { PCI_DEVICE_ID_ATI_RAGE128_PR, "R128Pro PR" }, | |
543 { PCI_DEVICE_ID_ATI_RAGE128_TR, "R128Pro TR" }, | |
544 { PCI_DEVICE_ID_ATI_RAGE128_PS, "R128Pro PS" }, | |
545 { PCI_DEVICE_ID_ATI_RAGE128_PT, "R128Pro PT" }, | |
546 { PCI_DEVICE_ID_ATI_RAGE128_PU, "R128Pro PU" }, | |
547 { PCI_DEVICE_ID_ATI_RAGE128_PV, "R128Pro PV" }, | |
548 { PCI_DEVICE_ID_ATI_RAGE128_PW, "R128Pro PW" }, | |
549 { PCI_DEVICE_ID_ATI_RAGE128_PX, "R128Pro PX" }, | |
550 /* Rage128 GL */ | |
551 { PCI_DEVICE_ID_ATI_RAGE128_RE, "R128 RE" }, | |
552 { PCI_DEVICE_ID_ATI_RAGE128_RF, "R128 RF" }, | |
553 { PCI_DEVICE_ID_ATI_RAGE128_RG, "R128 RG" }, | |
554 { PCI_DEVICE_ID_ATI_RAGE128_RH, "R128 RH" }, | |
555 { PCI_DEVICE_ID_ATI_RAGE128_RI, "R128 RI" }, | |
556 /* Rage128 VR */ | |
557 { PCI_DEVICE_ID_ATI_RAGE128_RK, "R128 RK" }, | |
558 { PCI_DEVICE_ID_ATI_RAGE128_RL, "R128 RL" }, | |
559 { PCI_DEVICE_ID_ATI_RAGE128_RM, "R128 RM" }, | |
560 { PCI_DEVICE_ID_ATI_RAGE128_RN, "R128 RN" }, | |
561 { PCI_DEVICE_ID_ATI_RAGE128_RO, "R128 RO" }, | |
562 /* Rage128 M3 */ | |
563 { PCI_DEVICE_ID_ATI_RAGE128_LE, "R128 M3 LE" }, | |
564 { PCI_DEVICE_ID_ATI_RAGE128_LF, "R128 M3 LF" }, | |
565 /* Rage128 Pro Ultra */ | |
566 { PCI_DEVICE_ID_ATI_RAGE128_U1, "R128Pro U1" }, | |
567 { PCI_DEVICE_ID_ATI_RAGE128_U2, "R128Pro U2" }, | |
568 { PCI_DEVICE_ID_ATI_RAGE128_U3, "R128Pro U3" } | |
569 #else | |
570 /* Radeons (indeed: Rage 256 Pro ;) */ | |
571 { PCI_DEVICE_ID_RADEON_QD, "Radeon QD " }, | |
572 { PCI_DEVICE_ID_RADEON_QE, "Radeon QE " }, | |
573 { PCI_DEVICE_ID_RADEON_QF, "Radeon QF " }, | |
574 { PCI_DEVICE_ID_RADEON_QG, "Radeon QG " }, | |
575 { PCI_DEVICE_ID_RADEON_QY, "Radeon VE QY " }, | |
576 { PCI_DEVICE_ID_RADEON_QZ, "Radeon VE QZ " }, | |
577 { PCI_DEVICE_ID_RADEON_LY, "Radeon M6 LY " }, | |
578 { PCI_DEVICE_ID_RADEON_LZ, "Radeon M6 LZ " }, | |
579 { PCI_DEVICE_ID_RADEON_LW, "Radeon M7 LW " }, | |
580 { PCI_DEVICE_ID_R200_QL, "Radeon2 8500 QL " }, | |
581 { PCI_DEVICE_ID_R200_BB, "Radeon2 8500 AIW" }, | |
582 { PCI_DEVICE_ID_RV200_QW, "Radeon2 7500 QW " } | |
583 #endif | |
584 }; | |
585 | |
586 static int find_chip(unsigned chip_id) | |
587 { | |
588 unsigned i; | |
589 for(i = 0;i < sizeof(ati_card_ids)/sizeof(struct ati_card_id_s);i++) | |
590 { | |
591 if(chip_id == ati_card_ids[i].id) return i; | |
592 } | |
593 return -1; | |
594 } | |
595 | |
596 pciinfo_t pci_info; | |
597 static int probed=0; | |
598 | |
599 vidix_capability_t def_cap = | |
600 { | |
601 #ifdef RAGE128 | |
602 "BES driver for rage128 cards", | |
603 #else | |
604 "BES driver for radeon cards", | |
605 #endif | |
606 TYPE_OUTPUT | TYPE_FX, | |
607 0, | |
608 1, | |
609 0, | |
610 0, | |
611 1024, | |
612 768, | |
613 4, | |
614 4, | |
615 -1, | |
616 FLAG_UPSCALER | FLAG_DOWNSCALER, | |
617 1002, | |
618 0, | |
619 { 0, 0, 0, 0} | |
620 }; | |
621 | |
622 | |
623 int vixProbe( int verbose ) | |
624 { | |
625 pciinfo_t lst[MAX_PCI_DEVICES]; | |
626 unsigned i,num_pci; | |
627 int err; | |
4030 | 628 __verbose = verbose; |
3996 | 629 err = pci_scan(lst,&num_pci); |
630 if(err) | |
631 { | |
632 printf(RADEON_MSG" Error occured during pci scan: %s\n",strerror(err)); | |
633 return err; | |
634 } | |
635 else | |
636 { | |
637 err = ENXIO; | |
638 for(i=0;i<num_pci;i++) | |
639 { | |
640 if(lst[i].vendor == PCI_VENDOR_ID_ATI) | |
641 { | |
642 int idx; | |
643 idx = find_chip(lst[i].device); | |
644 if(idx == -1) continue; | |
645 printf(RADEON_MSG" Found chip: %s\n",ati_card_ids[idx].name); | |
646 #ifndef RAGE128 | |
647 if(ati_card_ids[idx].id == PCI_DEVICE_ID_R200_QL || | |
648 ati_card_ids[idx].id == PCI_DEVICE_ID_R200_BB || | |
649 ati_card_ids[idx].id == PCI_DEVICE_ID_RV200_QW) IsR200 = 1; | |
650 #endif | |
651 def_cap.device_id = ati_card_ids[idx].id; | |
652 err = 0; | |
653 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); | |
654 probed=1; | |
655 break; | |
656 } | |
657 } | |
658 } | |
659 if(err && verbose) printf(RADEON_MSG" Can't find chip\n"); | |
660 return err; | |
661 } | |
662 | |
663 int vixInit( void ) | |
664 { | |
4012 | 665 if(!probed) |
666 { | |
667 printf(RADEON_MSG" Driver was not probed but is being initializing\n"); | |
668 return EINTR; | |
669 } | |
670 if((radeon_mmio_base = map_phys_mem(pci_info.base2,0xFFFF))==(void *)-1) return ENOMEM; | |
3996 | 671 radeon_ram_size = INREG(CONFIG_MEMSIZE); |
672 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ | |
673 radeon_ram_size &= CONFIG_MEMSIZE_MASK; | |
674 if((radeon_mem_base = map_phys_mem(pci_info.base0,radeon_ram_size))==(void *)-1) return ENOMEM; | |
675 radeon_vid_make_default(); | |
676 printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); | |
677 return 0; | |
678 } | |
679 | |
680 void vixDestroy( void ) | |
681 { | |
682 unmap_phys_mem(radeon_mem_base,radeon_ram_size); | |
683 unmap_phys_mem(radeon_mmio_base,0x7FFF); | |
684 } | |
685 | |
686 int vixGetCapability(vidix_capability_t *to) | |
687 { | |
688 memcpy(to,&def_cap,sizeof(vidix_capability_t)); | |
689 return 0; | |
690 } | |
691 | |
692 uint32_t supported_fourcc[] = | |
693 { | |
694 IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV, | |
695 IMGFMT_UYVY, IMGFMT_YUY2 | |
696 }; | |
697 | |
698 __inline__ static int is_supported_fourcc(uint32_t fourcc) | |
699 { | |
700 unsigned i; | |
701 for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++) | |
702 { | |
703 if(fourcc==supported_fourcc[i]) return 1; | |
704 } | |
705 return 0; | |
706 } | |
707 | |
708 int vixQueryFourcc(vidix_fourcc_t *to) | |
709 { | |
710 if(is_supported_fourcc(to->fourcc)) | |
711 { | |
712 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
713 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
714 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
715 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
716 VID_DEPTH_32BPP; | |
717 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK; | |
718 return 0; | |
719 } | |
4015 | 720 else to->depth = to->flags = 0; |
3996 | 721 return ENOSYS; |
722 } | |
723 | |
724 static void radeon_vid_dump_regs( void ) | |
725 { | |
726 size_t i; | |
4015 | 727 printf(RADEON_MSG"*** Begin of DRIVER variables dump ***\n"); |
728 printf(RADEON_MSG"radeon_mmio_base=%p\n",radeon_mmio_base); | |
729 printf(RADEON_MSG"radeon_mem_base=%p\n",radeon_mem_base); | |
730 printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off); | |
731 printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size); | |
732 printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n"); | |
3996 | 733 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) |
4015 | 734 printf(RADEON_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); |
735 printf(RADEON_MSG"*** End of OV0 registers dump ***\n"); | |
3996 | 736 } |
737 | |
738 static void radeon_vid_stop_video( void ) | |
739 { | |
740 radeon_engine_idle(); | |
741 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
742 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
743 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
744 OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); | |
745 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); | |
746 OUTREG(OV0_TEST, 0); | |
747 } | |
748 | |
749 static void radeon_vid_display_video( void ) | |
750 { | |
751 int bes_flags; | |
752 radeon_fifo_wait(2); | |
753 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
754 radeon_engine_idle(); | |
755 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
756 radeon_fifo_wait(15); | |
757 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); | |
758 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
759 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
760 | |
761 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
762 #ifdef RAGE128 | |
763 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | | |
764 (besr.saturation << 8) | | |
765 (besr.saturation << 16)); | |
766 #endif | |
767 radeon_fifo_wait(2); | |
768 if(besr.ckey_on) | |
769 { | |
770 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); | |
771 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
772 OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_EQ|VIDEO_KEY_FN_FALSE|CMP_MIX_OR); | |
773 } | |
774 else | |
775 { | |
776 OUTREG(OV0_GRAPHICS_KEY_MSK, 0ULL); | |
777 OUTREG(OV0_GRAPHICS_KEY_CLR, 0ULL); | |
778 OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_NE); | |
779 } | |
780 | |
781 OUTREG(OV0_H_INC, besr.h_inc); | |
782 OUTREG(OV0_STEP_BY, besr.step_by); | |
783 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
784 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
785 OUTREG(OV0_V_INC, besr.v_inc); | |
786 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
787 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); | |
788 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); | |
789 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); | |
790 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); | |
791 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
792 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
793 #ifdef RADEON | |
794 OUTREG(OV0_BASE_ADDR, besr.base_addr); | |
795 #endif | |
796 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs); | |
797 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs); | |
798 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs); | |
799 radeon_fifo_wait(9); | |
800 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs); | |
801 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs); | |
802 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf5_base_adrs); | |
803 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); | |
804 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
805 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
806 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); | |
807 | |
808 bes_flags = SCALER_ENABLE | | |
809 SCALER_SMART_SWITCH | | |
810 #ifdef RADEON | |
811 SCALER_HORZ_PICK_NEAREST; | |
812 #else | |
813 SCALER_Y2R_TEMP | | |
814 SCALER_PIX_EXPAND; | |
815 #endif | |
816 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; | |
817 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
818 #ifdef RAGE128 | |
819 bes_flags |= SCALER_BURST_PER_PLANE; | |
820 #endif | |
821 switch(besr.fourcc) | |
822 { | |
823 case IMGFMT_RGB15: | |
824 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
825 case IMGFMT_RGB16: | |
826 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; | |
827 case IMGFMT_RGB24: | |
828 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
829 case IMGFMT_RGB32: | |
830 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
831 /* 4:1:0*/ | |
832 case IMGFMT_IF09: | |
833 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; | |
834 /* 4:2:0 */ | |
835 case IMGFMT_IYUV: | |
836 case IMGFMT_I420: | |
837 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; | |
838 break; | |
839 /* 4:2:2 */ | |
840 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; | |
841 case IMGFMT_YUY2: | |
842 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
843 } | |
844 OUTREG(OV0_SCALE_CNTL, bes_flags); | |
845 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
4030 | 846 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 847 } |
848 | |
4009 | 849 static unsigned radeon_query_pitch(unsigned fourcc) |
850 { | |
851 unsigned pitch; | |
852 switch(fourcc) | |
853 { | |
854 /* 4:2:0 */ | |
855 case IMGFMT_IYUV: | |
856 case IMGFMT_YV12: | |
857 case IMGFMT_I420: pitch = 32; break; | |
858 default: pitch = 16; break; | |
859 } | |
860 return pitch; | |
861 } | |
862 | |
3996 | 863 static int radeon_vid_init_video( vidix_playback_t *config ) |
864 { | |
865 uint32_t tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top; | |
866 int is_420; | |
867 radeon_vid_stop_video(); | |
868 left = config->src.x << 16; | |
869 top = config->src.y << 16; | |
870 src_h = config->src.h; | |
871 src_w = config->src.w; | |
872 is_420 = 0; | |
873 if(config->fourcc == IMGFMT_YV12 || | |
874 config->fourcc == IMGFMT_I420 || | |
875 config->fourcc == IMGFMT_IYUV) is_420 = 1; | |
876 switch(config->fourcc) | |
877 { | |
878 /* 4:2:0 */ | |
879 case IMGFMT_IYUV: | |
880 case IMGFMT_YV12: | |
881 case IMGFMT_I420: pitch = (src_w + 31) & ~31; | |
4015 | 882 config->dest.pitch.y = |
883 config->dest.pitch.u = | |
3996 | 884 config->dest.pitch.v = 32; |
885 break; | |
886 /* 4:2:2 */ | |
887 default: | |
888 case IMGFMT_UYVY: | |
889 case IMGFMT_YUY2: | |
890 pitch = ((src_w*2) + 15) & ~15; | |
891 config->dest.pitch.y = | |
892 config->dest.pitch.u = | |
893 config->dest.pitch.v = 16; | |
894 break; | |
895 } | |
896 dest_w = config->dest.w; | |
897 dest_h = config->dest.h; | |
898 if(radeon_is_dbl_scan()) dest_h *= 2; | |
899 else | |
900 if(radeon_is_interlace()) dest_h /= 2; | |
901 besr.dest_bpp = radeon_vid_get_dbpp(); | |
902 besr.fourcc = config->fourcc; | |
903 besr.v_inc = (src_h << 20) / dest_h; | |
904 h_inc = (src_w << 12) / dest_w; | |
905 step_by = 1; | |
906 | |
907 while(h_inc >= (2 << 12)) { | |
908 step_by++; | |
909 h_inc >>= 1; | |
910 } | |
911 | |
912 /* keep everything in 16.16 */ | |
4015 | 913 besr.base_addr = INREG(DISPLAY_BASE_ADDR); |
3996 | 914 if(is_420) |
915 { | |
916 uint32_t d1line,d2line,d3line; | |
917 d1line = top*pitch; | |
918 d2line = src_h*pitch+(d1line>>1); | |
919 d3line = d2line+((src_h*pitch)>>2); | |
920 d1line += (left >> 16) & ~15; | |
921 d2line += (left >> 17) & ~15; | |
922 d3line += (left >> 17) & ~15; | |
923 config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK; | |
4015 | 924 config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; |
925 config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; | |
3996 | 926 besr.vid_buf0_base_adrs=(radeon_overlay_off+config->offset.y); |
4015 | 927 besr.vid_buf1_base_adrs=(radeon_overlay_off+config->offset.v)|VIF_BUF1_PITCH_SEL; |
928 besr.vid_buf2_base_adrs=(radeon_overlay_off+config->offset.u)|VIF_BUF2_PITCH_SEL; | |
3996 | 929 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) |
930 { | |
931 uint32_t tmp; | |
932 tmp = besr.vid_buf1_base_adrs; | |
933 besr.vid_buf1_base_adrs = besr.vid_buf2_base_adrs; | |
934 besr.vid_buf2_base_adrs = tmp; | |
935 tmp = config->offset.u; | |
936 config->offset.u = config->offset.v; | |
937 config->offset.v = tmp; | |
938 } | |
939 } | |
940 else | |
941 { | |
942 besr.vid_buf0_base_adrs = radeon_overlay_off; | |
943 config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; | |
944 besr.vid_buf0_base_adrs += config->offset.y; | |
945 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs; | |
946 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs; | |
947 } | |
948 config->offsets[0] = 0; | |
949 config->offsets[1] = config->frame_size; | |
950 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; | |
951 besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs+config->frame_size; | |
952 besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs+config->frame_size; | |
953 | |
954 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); | |
955 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
956 ((tmp << 12) & 0xf0000000); | |
957 | |
958 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); | |
959 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
960 ((tmp << 12) & 0x70000000); | |
961 tmp = (top & 0x0000ffff) + 0x00018000; | |
962 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) | |
963 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
964 | |
965 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
966 besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) | |
967 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; | |
968 | |
969 leftUV = (left >> 17) & 15; | |
970 left = (left >> 16) & 15; | |
971 besr.h_inc = h_inc | ((h_inc >> 1) << 16); | |
972 besr.step_by = step_by | (step_by << 8); | |
973 besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16); | |
974 besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16); | |
975 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
976 if(is_420) | |
977 { | |
978 src_h = (src_h + 1) >> 1; | |
979 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
980 } | |
981 else besr.p23_blank_lines_at_top = 0; | |
982 besr.vid_buf_pitch0_value = pitch; | |
983 besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch; | |
984 besr.p1_x_start_end = (src_w+left-1)|(left<<16); | |
985 src_w>>=1; | |
986 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
987 besr.p3_x_start_end = besr.p2_x_start_end; | |
988 return 0; | |
989 } | |
990 | |
4009 | 991 static void radeon_compute_framesize(vidix_playback_t *info) |
992 { | |
993 unsigned pitch,awidth; | |
994 pitch = radeon_query_pitch(info->fourcc); | |
995 awidth = info->src.w + ((pitch-1) & ~(pitch-1)); | |
996 info->frame_size = awidth*info->src.h+(awidth*info->src.h)/2; | |
997 } | |
998 | |
3996 | 999 int vixConfigPlayback(vidix_playback_t *info) |
1000 { | |
1001 if(!is_supported_fourcc(info->fourcc)) return ENOSYS; | |
1002 if(info->num_frames>2) info->num_frames=2; | |
4009 | 1003 radeon_compute_framesize(info); |
3996 | 1004 radeon_overlay_off = radeon_ram_size - info->frame_size*info->num_frames; |
1005 radeon_overlay_off &= 0xffff0000; | |
1006 if(radeon_overlay_off < 0) return EINVAL; | |
1007 info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off; | |
1008 radeon_vid_init_video(info); | |
1009 return 0; | |
1010 } | |
1011 | |
1012 int vixPlaybackOn( void ) | |
1013 { | |
1014 radeon_vid_display_video(); | |
1015 return 0; | |
1016 } | |
1017 | |
1018 int vixPlaybackOff( void ) | |
1019 { | |
1020 radeon_vid_stop_video(); | |
1021 return 0; | |
1022 } | |
1023 | |
1024 int vixPlaybackFrameSel(unsigned frame) | |
1025 { | |
1026 uint32_t off0,off1,off2; | |
1027 /* if(!besr.double_buff) return; */ | |
1028 if(frame%2) | |
1029 { | |
1030 off0 = besr.vid_buf3_base_adrs; | |
1031 off1 = besr.vid_buf4_base_adrs; | |
1032 off2 = besr.vid_buf5_base_adrs; | |
1033 } | |
1034 else | |
1035 { | |
1036 off0 = besr.vid_buf0_base_adrs; | |
1037 off1 = besr.vid_buf1_base_adrs; | |
1038 off2 = besr.vid_buf2_base_adrs; | |
1039 } | |
1040 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1041 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1042 OUTREG(OV0_VID_BUF0_BASE_ADRS, off0); | |
1043 OUTREG(OV0_VID_BUF1_BASE_ADRS, off1); | |
1044 OUTREG(OV0_VID_BUF2_BASE_ADRS, off2); | |
1045 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
4030 | 1046 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1047 return 0; |
1048 } | |
1049 | |
1050 vidix_video_eq_t equal = { 0, 0, 0, 0, 0, 0, 0 }; | |
1051 | |
1052 int vixPlaybackGetEq( vidix_video_eq_t * eq) | |
1053 { | |
1054 memcpy(eq,&equal,sizeof(vidix_video_eq_t)); | |
1055 return 0; | |
1056 } | |
1057 | |
1058 int vixPlaybackSetEq( const vidix_video_eq_t * eq) | |
1059 { | |
1060 #ifdef RAGE128 | |
1061 int br,sat; | |
1062 #endif | |
1063 memcpy(&equal,eq,sizeof(vidix_video_eq_t)); | |
1064 #ifdef RAGE128 | |
1065 br = equal.brightness * 64 / 1000; | |
1066 sat = equal.saturation * 32 / 1000; | |
1067 if(sat < 0) sat = 0; | |
1068 OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); | |
1069 #else | |
1070 radeon_set_transform(equal.brightness,equal.contrast, | |
1071 equal.saturation,equal.hue,0); | |
1072 #endif | |
1073 return 0; | |
1074 } | |
1075 |