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22691
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1 ATI chips hacking
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2 =================
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3 Dedicated to ATI's hackers.
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4
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5 Preface
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6 ~~~~~~~
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7 This document will compare ATI chips only from point of DAC and video overlay.
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8 There are lots of difference from 3D point, dual-head support, tv-out support
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9 and many other things but it's already perfectly different story.
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10 This document doesn't include information about ATI AIW (All In Wonder) chips.
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11
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12 What are units on modern ATI chips:
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13 DAC - (Digital to Analog Convertor) controls CRTC, LCD, DFP monitor's output
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14 Consists from:
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15 PLL - (Programable line length) registers
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16 CRTC - CRT controller
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17 LCD/DFP scaler
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18 surface control
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19 DAC2 - controls CRTC, LCD, DFP monitor's output on second head
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20 TVDAC - controls Composite Video and Super Video output ports
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21 Consists from:
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22 TV_PLL
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23 TV scaler & sync unit
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24 TV format convertor (PAL/NTSC)
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25 TVCAP - controls Video-In port
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26 MPP - Miscellaneous peripheral port. (includes macrovision's filter - copy
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27 protection mechanism)
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28 OV - Video overlay (YUV BES) (include subpictures, gamma correction and
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29 adaptive deinterlacing)
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30 CAP0 - Video capturing
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31 CAP1 - Video capturing (second unit)
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32 RT - Rage theatre: video encoding and mixing
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33 MUX - video muxer
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34 MEM - PCI/AGP bus mastering
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35 2D - GUI engine
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36 3D - 3D-OpenGL engine (There are lots of stuff)
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37 I2C - I2C Bus control
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38
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39 This document is mainly related only with OV unit ;)
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40 Video decoding diagram:
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41
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42 RAM memory: [ App ] Copies YUV image to overlay memory
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43 | <-- (It's possible to program DMA here)
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44 overlay memory:[ OV ] performs scaling and YUVtoRGB convertion
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45 /\
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46 RGB memory: / \
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47 / [ macrovision ] performs copy protection filtering
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48 / \ (unneeded but presented by default thing;)
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49 [ CRTC/LCD/DFP DAC ] [ TV DAC ] convert RGB memory to CRTC and NTSC/PAL signals
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50 | |
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51 [CRTC/LCD/DFP Monitor] [TV-screen]
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52
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53 History
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54 ~~~~~~~
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55 What is history of ATI's chips? I can be wrong but below is my vision
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56 of this question:
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57
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58 0. I don't know any earlied chips :(
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59 1. Mach8
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60 2. Mach16
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61 3. Mach32
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62
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63 4. Mach64.
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64 It's first chip which has support from side of open
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65 source drivers. Set of mach64 chips is:
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66 mach64GX (ATI888GX00)
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67 mach64CX (ATI888CX00)
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68 mach64CT (ATI264CT)
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69 mach64ET (ATI264ET)
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70 mach64VTA3 (ATI264VT)
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71 mach64VTA4 (ATI264VT)
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72 mach64VTB (ATI264VTB)
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73 mach64VT4 (ATI264VT4)
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74
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75 5. 3D rage chips.
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76 It seems that these chips have fully compatible by GPU with Mach64
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77 which is extended by 3D possibilities. Set of 3D rage chips is:
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78 3D RAGE (GT)
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79 3D RAGE II+ (GTB)
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80 3D RAGE IIC (PCI)
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81 3D RAGE IIC (AGP)
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82 3D RAGE LT
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83 3D RAGE LT-G
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84 3D RAGE PRO (BGA, AGP)
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85 3D RAGE PRO (BGA, AGP, 1x only)
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86 3D RAGE PRO (BGA, PCI)
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87 3D RAGE PRO (PQFP, PCI)
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88 3D RAGE PRO (PQFP, PCI, limited 3D)
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89 3D RAGE (XL)
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90 3D RAGE LT PRO (AGP)
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91 3D RAGE LT PRO (PCI)
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92 3D RAGE Mobility (PCI)
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93 3D RAGE Mobility (AGP)
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94
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95 6. Rage128 chips.
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96 These chips have perfectly new GPU which supports memory mapped IO
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97 space for accelerating port access (It's main cause of incompatibility
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98 with mach64). Set of Rage128 chips is:
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99 Rage128 GL RE
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100 Rage128 GL RF
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101 Rage128 GL RG
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102 Rage128 GL RH
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103 Rage128 GL RI
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104 Rage128 VR RK
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105 Rage128 VR RL
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106 Rage128 VR RM
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107 Rage128 VR RN
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108 Rage128 VR RO
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109 Rage128 Mobility M3 LE
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110 Rage128 Mobility M3 LF
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111 7. Rage128Pro chips.
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112 These chips are successors of Rage128 ones.
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113 Rage128Pro GL PA
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114 Rage128Pro GL PB
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115 Rage128Pro GL PC
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116 Rage128Pro GL PD
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117 Rage128Pro GL PE
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118 Rage128Pro GL PF
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119 Rage128Pro VR PG
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120 Rage128Pro VR PH
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121 Rage128Pro VR PI
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122 Rage128Pro VR PJ
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123 Rage128Pro VR PK
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124 Rage128Pro VR PL
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125 Rage128Pro VR PM
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126 Rage128Pro VR PN
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127 Rage128Pro VR PO
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128 Rage128Pro VR PP
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129 Rage128Pro VR PQ
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130 Rage128Pro VR PR
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131 Rage128Pro VR TR
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132 Rage128Pro VR PS
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133 Rage128Pro VR PT
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134 Rage128Pro VR PU
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135 Rage128Pro VR PV
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136 Rage128Pro VR PW
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137 Rage128Pro VR PX
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138 Rage128Pro Ultra U1
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139 Rage128Pro Ultra U2
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140 Rage128Pro Ultra U3
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141
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142 8. Radeon chips.
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143 Indeed they could be named Rage256 Pro. (With minor changes is fully
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144 compatible with Rage128 chips).
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145 Radeon QD
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146 Radeon QE
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147 Radeon QF
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148 Radeon QG
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149 Radeon VE QY
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150 Radeon VE QZ
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151 Radeon M6 LY
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152 Radeon M6 LZ
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153 Radeon M7 LW
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154 9. Radeon2 chips.
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155 Indeed they could be named Rage512 Pro.
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156 Radeon2 8500 QL
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157 Radeon2 7500 QW
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158
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159 10. Radeon3 and newest are cooming soon, but I hope that they will be fully
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160 compatible with Radeon1 chips.
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161
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162 In Radeon famility there were introduced also FX chips: Radeon FX and
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163 Radeon2 8700 FX. Probably they have the same possibility as other Radeon
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164 but currently it's unknown for me.
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165
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166 What about video overlay and DAC?
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167 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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168
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169 Currently it's known that there is only difference between
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170 Mach64 and Rage128 compatible chips:
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171 - They have different logic of io ports programming!
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172 - They are incompatible by port numbers!
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173 But:
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174 - They use the same program logic from register's name point.
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175 (Indeed exists slight difference even between Radeon and Rage128
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176 chips. AFAIK only Radeon has OV0_SLICE_CNTL register which currently
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177 is not used by driver. But I know only its name ;). Also there
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178 is difference in slight adjust of BES position but it's configured
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179 by #ifdef blocks).
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180
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181 Please compare:
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182
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183 (The piece of Back-End Scaler programming)
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184
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185 Sample for Mach64 compatible chips:
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186 ***********************************
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187
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188 #define SPARSE_IO_BASE 0x03fcu
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189 #define SPARSE_IO_SELECT 0xfc00u
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190
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191 #define BLOCK_IO_BASE 0xff00u
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192 #define BLOCK_IO_SELECT 0x00fcu
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193
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194 #define MM_IO_SELECT 0x03fcu
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195 #define BLOCK_SELECT 0x0400u
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196 #define DWORD_SELECT (BLOCK_SELECT | MM_IO_SELECT)
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197
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198 #define IO_BYTE_SELECT 0x0003u
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199
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200 #define SPARSE_IO_PORT (SPARSE_IO_BASE | IO_BYTE_SELECT)
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201 #define BLOCK_IO_PORT (BLOCK_IO_BASE | IO_BYTE_SELECT)
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202
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203 #define IOPortTag(_SparseIOSelect, _BlockIOSelect) \
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204 (SetBits(_SparseIOSelect, SPARSE_IO_SELECT) | \
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205 SetBits(_BlockIOSelect, BLOCK_SELECT | MM_IO_SELECT))
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206 #define SparseIOTag(_IOSelect) IOPortTag(_IOSelect, 0)
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207 #define BlockIOTag(_IOSelect) IOPortTag(0, _IOSelect)
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208
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209 ...
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210
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211 #define OVERLAY_Y_X_START BlockIOTag(0x100u)
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212 #define OVERLAY_Y_X_END BlockIOTag(0x101u)
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213
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214 ...
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215
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216 #define OUTREG(_Register, _Value) \
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217 MMIO_OUT32(pATI->pBlock[GetBits(_Register, BLOCK_SELECT)], \
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218 (_Register) & MM_IO_SELECT, _Value)
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219
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220 ...
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221
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222 OUTREG(OVERLAY_Y_X_START,((drw_x)<<16)|(drw_y)|(1<<31));
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223 OUTREG(OVERLAY_Y_X_END,((drw_x+drw_w)<<16)|(drw_y+drw_h));
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224
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225
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226 Sample for Rage128 compatible chips:
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227 ************************************
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228
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229 #define OV0_Y_X_START 0x0400
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230 #define OV0_Y_X_END 0x0404
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231
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232 ...
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233
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234 #define INREG(addr) readl((rage_mmio_base)+addr)
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235 #define OUTREG(addr,val) writel(val, (rage_mmio_base)+addr)
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236
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237 ...
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238
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239 rage_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RAGE_REGSIZE);
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240
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241 ...
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242
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243 #ifdef RADEON
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244 #define X_ADJUST 8
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245 #else /* rage128 */
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246 #define X_ADJUST 0
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247 #endif
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248
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249 OUTREG(OV0_Y_X_START,(drw_x+X_ADJUST)|(drw_y<<16));
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250 OUTREG(OV0_Y_X_END,(drw_x+drw_w+X_ADJUST)|(drw_y+drw_h)<<16));
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251
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252 Thus - these chips have almost the same logic from register's name point.
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253 (except the fact that they have swapped 16-bit halfs).
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254 Yes - programming of Rage128 is much simpler of Mach64.
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255
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256
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257 What about other ATI's chips?
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258 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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259
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260 I suggest you have latest copy of GATOS-CVS:
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261 http://www.linuxvideo.org
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262 GATOS was designed and introduced as General ATI TV and Overlay Sowfware.
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263 You will be able to find out there a lots of useful hacking utilities
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264 (at location gatos-ati/gatos):
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265 gfxdump - Program for dumping graphics chips registers on Linux and Windows 9X.
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266 (it's more useful for Win9x to hack their values).
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267 xatitv - For working with tv-in (currently is under hard development)
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268 atitvout- For working with tv-out
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269 and lot of other stuff.
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270 BUT: After studing of Gatos and X11 stuffs I've found that they are bad
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271 optimized for movie playback.
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272 Please compare:
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273 radeon_vid - configures video overlay only once and provides DGA to it.
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274 (doesn't require to be MMX optimized)
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275 gatos and X11 - configures video overlay at every slice of frame, then
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276 performs unoptimized copying of source stuff to video memory
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277 often with using CopyMungedData (it's C-analog of YV12_to_YUY2)
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278 since there are lacks in yv12 support.
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279 (is not MMX optimized that's gladly accepted, but probably
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280 will be never optimized due portability).
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281
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282 hardware IDCT support diagram:
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283 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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284 |
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285 [ Video parser ] <---------- [ Transport demuxing ] --> [ Audio ]
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286 | | |
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287 [ Variable length decoder] |D |
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288 | |V |
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289 [ Inverse quantization ] |D |
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290 | | |
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291 -------|---[ video card ]---------+ |s |
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292 | | |u |
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293 [ Run level decode & de-zigzag ] | |b |
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294 | | |p |
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295 [ IDCT ] | |i |
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296 | | |c |
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297 [ Motion compensation ] | |t |
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298 | | |u |
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299 [ Advanced deinterlacing ] | |r |
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300 | | |e |
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301 [ Filtered X-Y scaling ] [SUBPIC]-|-----+s [ OSD ]
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302 | | | | |
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303 [ 4-bit alpha blending ] <---+ | +-------+
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304 | |
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305 [ YUV to RGB conversion ] |
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306 -------|--------------------------+
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307 TV-screen or CRT-display
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308
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309
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310 Conslusion:
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311 ~~~~~~~~~~~
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312
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313 That's all folk!
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