Mercurial > mplayer.hg
changeset 22691:544914dadb52
Move files from radeon/ subdirectory here.
| author | diego |
|---|---|
| date | Sat, 17 Mar 2007 21:27:42 +0000 |
| parents | 8b0d9b0558e8 |
| children | 2ccbb18bc99f |
| files | drivers/Makefile drivers/README drivers/README.Ati drivers/README.Matrox drivers/generic_math.h drivers/hacking.ati drivers/radeon.h drivers/radeon/README drivers/radeon/generic_math.h drivers/radeon/hacking drivers/radeon/radeon.h drivers/radeon/radeon_vid.c drivers/radeon/radeon_vid.h drivers/radeon_vid.c drivers/radeon_vid.h |
| diffstat | 15 files changed, 4449 insertions(+), 4450 deletions(-) [+] |
line wrap: on
line diff
--- a/drivers/Makefile Sat Mar 17 21:21:04 2007 +0000 +++ b/drivers/Makefile Sat Mar 17 21:27:42 2007 +0000 @@ -4,16 +4,16 @@ CFLAGS = -O2 -D__KERNEL__ -DMODULE -I$(KERNEL_INCLUDES) -Wall -include $(KERNEL_INCLUDES)/linux/modversions.h -OBJS = mga_vid.o tdfx_vid.o radeon/radeon_vid.o radeon/rage128_vid.o +OBJS = mga_vid.o tdfx_vid.o radeon_vid.o rage128_vid.o all: $(OBJS) mga_vid_test tdfx_vid_test mga_vid.o: mga_vid.c mga_vid.h tdfx_vid.o: tdfx_vid.c 3dfx.h -radeon/radeon_vid.o: radeon/radeon_vid.c radeon/radeon.h radeon/radeon_vid.h -radeon/rage128_vid.o: radeon/radeon_vid.c radeon/radeon.h radeon/radeon_vid.h +radeon_vid.o: radeon_vid.c radeon.h radeon_vid.h +rage128_vid.o: radeon_vid.c radeon.h radeon_vid.h $(CC) $(CFLAGS) -DRAGE128 -c $< -o $@ -radeon/radeon_vid.o radeon/rage128_vid.o: +radeon_vid.o rage128_vid.o: CFLAGS += -fomit-frame-pointer -fno-strict-aliasing -fno-common -ffast-math %_test: %_test.c @@ -32,7 +32,6 @@ clean: rm -f *.o *~ mga_vid_test tdfx_vid_test - rm -f radeon/*.o radeon/*~ distclean: clean
--- a/drivers/README Sat Mar 17 21:21:04 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,46 +0,0 @@ -The code in this directory is the old mga_vid driver for Linux kernels -prior to 2.6. It does _not_ compile for version 2.6.x. - -For Linux kernel 2.6.x please get the newest version of the 2.6 port from -http://attila.kinali.ch/mga/ - - -mga_vid - MGA G200/G400 YUV Overlay kernel module - - Author: - Aaron Holtzman <aholtzma@ess.engr.uvic.ca>, Oct 1999 - - Contributions by: - Fredrik Vraalsen <vraalsen@cs.uiuc.edu> - Alan Cox <alan@lxorguk.ukuu.org.uk> - - WARNING ----- WARNING - -This code messes with your video card and your X server. It will probably -lock up your box, format your hard drive, and cause your brand new G400 -MAX to spout 6 inch flames. You have been warned. - - WARNING ----- WARNING - -What does this code do? - - mga_vid is a kernel module that utilitizes the Matrox G200/G400/G550 - video scaler/overlay unit to perform YUV->RGB colorspace conversion - and arbitrary video scaling. - - mga_vid is also a monster hack. - -How does mga_vid work? - - This kernel module sets up the BES (backend scaler) with appropriate - values based on parameters supplied via ioctl. It also maps a chunk of - video memory into userspace via mmap. This memory is stolen from X - (which may decide to write to it later). The application can then write - image data directly to the framebuffer (if it knows the right padding, - etc). - - -How do I know if mga_vid works on my system? - - There is a test application called mga_vid_test. This test code should - draw some nice 256x256 images for you if all is working well.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/drivers/README.Ati Sat Mar 17 21:27:42 2007 +0000 @@ -0,0 +1,121 @@ + framebuffer driver for ATI Radeon chipset video boards + ====================================================== + +These files are replacement for linux-2.4.x-ac.y drivers. +To use this driver you should have at least linux-2.4.5-ac.1 +then simply replace linux/drivers/video/radeon* with files +from this directory. +Note: since linux-2.4.10 this driver was moved from -ac to +Linus distribution. + +Alternative way: +~~~~~~~~~~~~~~~~ +Simply type two commands in this directory: +make +make install + +Anyway you should have 'framebuffer support' compiled into linux-kernel +and at least '8bpp packed pixel support' compiled and installed as module. +(But if you plan to use this module with MPlayer you also should have +16bpp, 24bpp and 32bpp pixel support compiled as modules). + + + Radeon video overlay + ==================== + +It was designed for MPlayer and currently can be used only by MPlayer. +It's RGB-YUV BES for Radeon cards (althrough there is experimental +support for Rage128 / Rage128pro chips). + +rage128_vid is contained within radeon_vid.c. As for a Rage128 framebuffer - +use the one from your Linux distribution. + +Installation: +~~~~~~~~~~~~~ + +Simply type two commands in this directory: +make +make install + +Using with MPlayer: +~~~~~~~~~~~~~~~~~~~ + +Currently there is only one way to use ATI's drivers: +mplayer -vo vesa:lvo:/dev/radeon_vid -<your vesa's options> filename +or +mplayer -vo vesa:lvo:/dev/rage128_vid -<your vesa's options> filename + +For YV12 formats you can use also: +mplayer -vo mga:/dev/radeon_vid -<your mga's option> filename + +but in this case you should load at least radeonfb driver from +this package. + +Configuring: +~~~~~~~~~~~~ + +You can tune some parameters with the following trick: +echo "parameter=value" > /dev/radeon_vid +Example (disables adaptive deinterlacing): +echo "deinterlace=off" > /dev/radeon_vid + +To know more about these parameters - try reading the /dev/radeon_vid file ;) +For example: +cat /dev/radeon_vid + +List of parameters: +~~~~~~~~~~~~~~~~~~~ +If you have Rage128 chip: +brightness=decval (-64:+63) changes brightness +saturation=decval (0:+31) changes saturation 0 == grayscale mode +else - if you have Radeon: +brightness=decval (-1000:+1000) -1000 == black screen +saturation=decval (-1000:+1000) -1000 == grayscaled mode +contrast=decval (-1000:+1000) -1000 == black screen +hue=decval (-1000:+1000) -1000 == +1000 (full circle) + all other values are within this range +Note: 0 is the default value for every parameter on Radeons. +WARNING: This driver violates the rule: "no float in the kernel". +So if you have problems then don't use color correction. + +double_buff=on/off enables/disables double buffering +deinterlace=on/off enables/disables adaptive deinterlacing +deinterlace_pattern=hexval defines deinterlacing pattern + +Driver parameters: +~~~~~~~~~~~~~~~~~~ + +You can use some additional parameters during module loading: +Example: +modprobe radeon_vid swap_fourcc=1 + +List of driver parameters: +~~~~~~~~~~~~~~~~~~~~~~~~~~ +mtrr=1/0 Configures MTRR (if available), default = 1. +swap_fourcc=1/0 Performs byte swapping of passed fourcc. + (It's required for compatibility with -vo mga.) + +To know more about driver parameters execute: +modinfo radeon_vid +or +modinfo rage128_vid + +Note: +~~~~~ +For command line of MPlayer: +You can pass only options with can be recognized by vo_vesa driver. +(Indeed radeon_vid and rage128_vid are stupid things and can only create +video overlay. Mode switching and other adjustments are performed by the +vo_vesa driver. This mean that they use the VESA BIOS as graphics server.) + +Conclusion: +~~~~~~~~~~~ +This stuff (radeon(rage128)_vid) currently doesn't support any standards. + +Full example: +~~~~~~~~~~~~~ +modprobe radeon_vid mtrr=1 +echo "deinterlace_pattern=F0055555" > /dev/radeon_vid +mplayer -vo vesa:lvo:/dev/radeon_vid -fs -zoom -bpp 32 filename + +Enjoy!
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/drivers/README.Matrox Sat Mar 17 21:27:42 2007 +0000 @@ -0,0 +1,46 @@ +The code in this directory is the old mga_vid driver for Linux kernels +prior to 2.6. It does _not_ compile for version 2.6.x. + +For Linux kernel 2.6.x please get the newest version of the 2.6 port from +http://attila.kinali.ch/mga/ + + +mga_vid - MGA G200/G400 YUV Overlay kernel module + + Author: + Aaron Holtzman <aholtzma@ess.engr.uvic.ca>, Oct 1999 + + Contributions by: + Fredrik Vraalsen <vraalsen@cs.uiuc.edu> + Alan Cox <alan@lxorguk.ukuu.org.uk> + + WARNING ----- WARNING + +This code messes with your video card and your X server. It will probably +lock up your box, format your hard drive, and cause your brand new G400 +MAX to spout 6 inch flames. You have been warned. + + WARNING ----- WARNING + +What does this code do? + + mga_vid is a kernel module that utilitizes the Matrox G200/G400/G550 + video scaler/overlay unit to perform YUV->RGB colorspace conversion + and arbitrary video scaling. + + mga_vid is also a monster hack. + +How does mga_vid work? + + This kernel module sets up the BES (backend scaler) with appropriate + values based on parameters supplied via ioctl. It also maps a chunk of + video memory into userspace via mmap. This memory is stolen from X + (which may decide to write to it later). The application can then write + image data directly to the framebuffer (if it knows the right padding, + etc). + + +How do I know if mga_vid works on my system? + + There is a test application called mga_vid_test. This test code should + draw some nice 256x256 images for you if all is working well.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/drivers/generic_math.h Sat Mar 17 21:27:42 2007 +0000 @@ -0,0 +1,258 @@ +/* + generic implementation of sin(x) and cos(x) functions. + Specially for Linux. + Licence: GPL + Copyright (C) 2002 Nick Kurshev +*/ + +#ifndef GENERIC_MATH_H +#define GENERIC_MATH_H + +typedef struct _gen_sincos +{ + double x; + double sinx; + double cosx; +}gen_sincos_t; + +static gen_sincos_t g_sincos[201] = { +{ -3.141600e+00, 7.346410e-06, -1.000000e-00 }, +{ -3.110184e+00, -3.140349e-02, -9.995068e-01 }, +{ -3.078768e+00, -6.278333e-02, -9.980272e-01 }, +{ -3.047352e+00, -9.410122e-02, -9.955626e-01 }, +{ -3.015936e+00, -1.253262e-01, -9.921156e-01 }, +{ -2.984520e+00, -1.564276e-01, -9.876894e-01 }, +{ -2.953104e+00, -1.873745e-01, -9.822885e-01 }, +{ -2.921688e+00, -2.181366e-01, -9.759183e-01 }, +{ -2.890272e+00, -2.486833e-01, -9.685848e-01 }, +{ -2.858856e+00, -2.789847e-01, -9.602956e-01 }, +{ -2.827440e+00, -3.090107e-01, -9.510586e-01 }, +{ -2.796024e+00, -3.387318e-01, -9.408830e-01 }, +{ -2.764608e+00, -3.681185e-01, -9.297789e-01 }, +{ -2.733192e+00, -3.971420e-01, -9.177572e-01 }, +{ -2.701776e+00, -4.257736e-01, -9.048297e-01 }, +{ -2.670360e+00, -4.539849e-01, -8.910094e-01 }, +{ -2.638944e+00, -4.817483e-01, -8.763097e-01 }, +{ -2.607528e+00, -5.090362e-01, -8.607451e-01 }, +{ -2.576112e+00, -5.358217e-01, -8.443312e-01 }, +{ -2.544696e+00, -5.620785e-01, -8.270839e-01 }, +{ -2.513280e+00, -5.877805e-01, -8.090204e-01 }, +{ -2.481864e+00, -6.129025e-01, -7.901586e-01 }, +{ -2.450448e+00, -6.374196e-01, -7.705169e-01 }, +{ -2.419032e+00, -6.613076e-01, -7.501148e-01 }, +{ -2.387616e+00, -6.845430e-01, -7.289724e-01 }, +{ -2.356200e+00, -7.071029e-01, -7.071107e-01 }, +{ -2.324784e+00, -7.289649e-01, -6.845511e-01 }, +{ -2.293368e+00, -7.501075e-01, -6.613159e-01 }, +{ -2.261952e+00, -7.705099e-01, -6.374281e-01 }, +{ -2.230536e+00, -7.901518e-01, -6.129112e-01 }, +{ -2.199120e+00, -8.090140e-01, -5.877894e-01 }, +{ -2.167704e+00, -8.270777e-01, -5.620876e-01 }, +{ -2.136288e+00, -8.443252e-01, -5.358310e-01 }, +{ -2.104872e+00, -8.607395e-01, -5.090457e-01 }, +{ -2.073456e+00, -8.763043e-01, -4.817579e-01 }, +{ -2.042040e+00, -8.910044e-01, -4.539948e-01 }, +{ -2.010624e+00, -9.048251e-01, -4.257835e-01 }, +{ -1.979208e+00, -9.177528e-01, -3.971521e-01 }, +{ -1.947792e+00, -9.297748e-01, -3.681288e-01 }, +{ -1.916376e+00, -9.408793e-01, -3.387421e-01 }, +{ -1.884960e+00, -9.510552e-01, -3.090212e-01 }, +{ -1.853544e+00, -9.602925e-01, -2.789953e-01 }, +{ -1.822128e+00, -9.685821e-01, -2.486940e-01 }, +{ -1.790712e+00, -9.759158e-01, -2.181473e-01 }, +{ -1.759296e+00, -9.822865e-01, -1.873854e-01 }, +{ -1.727880e+00, -9.876877e-01, -1.564385e-01 }, +{ -1.696464e+00, -9.921142e-01, -1.253372e-01 }, +{ -1.665048e+00, -9.955616e-01, -9.411219e-02 }, +{ -1.633632e+00, -9.980265e-01, -6.279433e-02 }, +{ -1.602216e+00, -9.995064e-01, -3.141450e-02 }, +{ -1.570800e+00, -1.000000e-00, -3.673205e-06 }, +{ -1.539384e+00, -9.995067e-01, 3.140716e-02 }, +{ -1.507968e+00, -9.980269e-01, 6.278700e-02 }, +{ -1.476552e+00, -9.955623e-01, 9.410488e-02 }, +{ -1.445136e+00, -9.921151e-01, 1.253299e-01 }, +{ -1.413720e+00, -9.876889e-01, 1.564312e-01 }, +{ -1.382304e+00, -9.822879e-01, 1.873781e-01 }, +{ -1.350888e+00, -9.759175e-01, 2.181402e-01 }, +{ -1.319472e+00, -9.685839e-01, 2.486869e-01 }, +{ -1.288056e+00, -9.602945e-01, 2.789882e-01 }, +{ -1.256640e+00, -9.510574e-01, 3.090142e-01 }, +{ -1.225224e+00, -9.408817e-01, 3.387352e-01 }, +{ -1.193808e+00, -9.297775e-01, 3.681220e-01 }, +{ -1.162392e+00, -9.177557e-01, 3.971454e-01 }, +{ -1.130976e+00, -9.048282e-01, 4.257769e-01 }, +{ -1.099560e+00, -8.910077e-01, 4.539882e-01 }, +{ -1.068144e+00, -8.763079e-01, 4.817515e-01 }, +{ -1.036728e+00, -8.607433e-01, 5.090393e-01 }, +{ -1.005312e+00, -8.443292e-01, 5.358248e-01 }, +{ -9.738960e-01, -8.270819e-01, 5.620815e-01 }, +{ -9.424800e-01, -8.090183e-01, 5.877835e-01 }, +{ -9.110640e-01, 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9.602935e-01 }, +{ -2.513280e-01, -2.486905e-01, 9.685830e-01 }, +{ -2.199120e-01, -2.181437e-01, 9.759166e-01 }, +{ -1.884960e-01, -1.873817e-01, 9.822872e-01 }, +{ -1.570800e-01, -1.564348e-01, 9.876883e-01 }, +{ -1.256640e-01, -1.253335e-01, 9.921147e-01 }, +{ -9.424800e-02, -9.410853e-02, 9.955619e-01 }, +{ -6.283200e-02, -6.279067e-02, 9.980267e-01 }, +{ -3.141600e-02, -3.141083e-02, 9.995066e-01 }, +{ 0.000000e+00, 0.000000e+00, 1.000000e+00 }, +{ 3.141600e-02, 3.141083e-02, 9.995066e-01 }, +{ 6.283200e-02, 6.279067e-02, 9.980267e-01 }, +{ 9.424800e-02, 9.410853e-02, 9.955619e-01 }, +{ 1.256640e-01, 1.253335e-01, 9.921147e-01 }, +{ 1.570800e-01, 1.564348e-01, 9.876883e-01 }, +{ 1.884960e-01, 1.873817e-01, 9.822872e-01 }, +{ 2.199120e-01, 2.181437e-01, 9.759166e-01 }, +{ 2.513280e-01, 2.486905e-01, 9.685830e-01 }, +{ 2.827440e-01, 2.789917e-01, 9.602935e-01 }, +{ 3.141600e-01, 3.090177e-01, 9.510563e-01 }, +{ 3.455760e-01, 3.387387e-01, 9.408805e-01 }, +{ 3.769920e-01, 3.681254e-01, 9.297762e-01 }, +{ 4.084080e-01, 3.971488e-01, 9.177542e-01 }, +{ 4.398240e-01, 4.257802e-01, 9.048266e-01 }, +{ 4.712400e-01, 4.539915e-01, 8.910060e-01 }, +{ 5.026560e-01, 4.817547e-01, 8.763061e-01 }, +{ 5.340720e-01, 5.090425e-01, 8.607414e-01 }, +{ 5.654880e-01, 5.358279e-01, 8.443272e-01 }, +{ 5.969040e-01, 5.620845e-01, 8.270798e-01 }, +{ 6.283200e-01, 5.877864e-01, 8.090161e-01 }, +{ 6.597360e-01, 6.129083e-01, 7.901541e-01 }, +{ 6.911520e-01, 6.374252e-01, 7.705122e-01 }, +{ 7.225680e-01, 6.613131e-01, 7.501100e-01 }, +{ 7.539840e-01, 6.845484e-01, 7.289674e-01 }, +{ 7.854000e-01, 7.071081e-01, 7.071055e-01 }, +{ 8.168160e-01, 7.289699e-01, 6.845457e-01 }, +{ 8.482320e-01, 7.501124e-01, 6.613104e-01 }, +{ 8.796480e-01, 7.705146e-01, 6.374224e-01 }, +{ 9.110640e-01, 7.901563e-01, 6.129054e-01 }, +{ 9.424800e-01, 8.090183e-01, 5.877835e-01 }, +{ 9.738960e-01, 8.270819e-01, 5.620815e-01 }, +{ 1.005312e+00, 8.443292e-01, 5.358248e-01 }, +{ 1.036728e+00, 8.607433e-01, 5.090393e-01 }, +{ 1.068144e+00, 8.763079e-01, 4.817515e-01 }, +{ 1.099560e+00, 8.910077e-01, 4.539882e-01 }, +{ 1.130976e+00, 9.048282e-01, 4.257769e-01 }, +{ 1.162392e+00, 9.177557e-01, 3.971454e-01 }, +{ 1.193808e+00, 9.297775e-01, 3.681220e-01 }, +{ 1.225224e+00, 9.408817e-01, 3.387352e-01 }, +{ 1.256640e+00, 9.510574e-01, 3.090142e-01 }, +{ 1.288056e+00, 9.602945e-01, 2.789882e-01 }, +{ 1.319472e+00, 9.685839e-01, 2.486869e-01 }, +{ 1.350888e+00, 9.759175e-01, 2.181402e-01 }, +{ 1.382304e+00, 9.822879e-01, 1.873781e-01 }, +{ 1.413720e+00, 9.876889e-01, 1.564312e-01 }, +{ 1.445136e+00, 9.921151e-01, 1.253299e-01 }, +{ 1.476552e+00, 9.955623e-01, 9.410488e-02 }, +{ 1.507968e+00, 9.980269e-01, 6.278700e-02 }, +{ 1.539384e+00, 9.995067e-01, 3.140716e-02 }, +{ 1.570800e+00, 1.000000e-00, -3.673205e-06 }, +{ 1.602216e+00, 9.995064e-01, -3.141450e-02 }, +{ 1.633632e+00, 9.980265e-01, -6.279433e-02 }, +{ 1.665048e+00, 9.955616e-01, -9.411219e-02 }, +{ 1.696464e+00, 9.921142e-01, -1.253372e-01 }, +{ 1.727880e+00, 9.876877e-01, -1.564385e-01 }, +{ 1.759296e+00, 9.822865e-01, -1.873854e-01 }, +{ 1.790712e+00, 9.759158e-01, -2.181473e-01 }, +{ 1.822128e+00, 9.685821e-01, -2.486940e-01 }, +{ 1.853544e+00, 9.602925e-01, -2.789953e-01 }, +{ 1.884960e+00, 9.510552e-01, -3.090212e-01 }, +{ 1.916376e+00, 9.408793e-01, -3.387421e-01 }, +{ 1.947792e+00, 9.297748e-01, -3.681288e-01 }, +{ 1.979208e+00, 9.177528e-01, -3.971521e-01 }, +{ 2.010624e+00, 9.048251e-01, -4.257835e-01 }, +{ 2.042040e+00, 8.910044e-01, -4.539948e-01 }, +{ 2.073456e+00, 8.763043e-01, -4.817579e-01 }, +{ 2.104872e+00, 8.607395e-01, -5.090457e-01 }, +{ 2.136288e+00, 8.443252e-01, -5.358310e-01 }, +{ 2.167704e+00, 8.270777e-01, -5.620876e-01 }, +{ 2.199120e+00, 8.090140e-01, -5.877894e-01 }, +{ 2.230536e+00, 7.901518e-01, -6.129112e-01 }, +{ 2.261952e+00, 7.705099e-01, -6.374281e-01 }, +{ 2.293368e+00, 7.501075e-01, -6.613159e-01 }, +{ 2.324784e+00, 7.289649e-01, -6.845511e-01 }, +{ 2.356200e+00, 7.071029e-01, -7.071107e-01 }, +{ 2.387616e+00, 6.845430e-01, -7.289724e-01 }, +{ 2.419032e+00, 6.613076e-01, -7.501148e-01 }, +{ 2.450448e+00, 6.374196e-01, -7.705169e-01 }, +{ 2.481864e+00, 6.129025e-01, -7.901586e-01 }, +{ 2.513280e+00, 5.877805e-01, -8.090204e-01 }, +{ 2.544696e+00, 5.620785e-01, -8.270839e-01 }, +{ 2.576112e+00, 5.358217e-01, -8.443312e-01 }, +{ 2.607528e+00, 5.090362e-01, -8.607451e-01 }, +{ 2.638944e+00, 4.817483e-01, -8.763097e-01 }, +{ 2.670360e+00, 4.539849e-01, -8.910094e-01 }, +{ 2.701776e+00, 4.257736e-01, -9.048297e-01 }, +{ 2.733192e+00, 3.971420e-01, -9.177572e-01 }, +{ 2.764608e+00, 3.681185e-01, -9.297789e-01 }, +{ 2.796024e+00, 3.387318e-01, -9.408830e-01 }, +{ 2.827440e+00, 3.090107e-01, -9.510586e-01 }, +{ 2.858856e+00, 2.789847e-01, -9.602956e-01 }, +{ 2.890272e+00, 2.486833e-01, -9.685848e-01 }, +{ 2.921688e+00, 2.181366e-01, -9.759183e-01 }, +{ 2.953104e+00, 1.873745e-01, -9.822885e-01 }, +{ 2.984520e+00, 1.564276e-01, -9.876894e-01 }, +{ 3.015936e+00, 1.253262e-01, -9.921156e-01 }, +{ 3.047352e+00, 9.410122e-02, -9.955626e-01 }, +{ 3.078768e+00, 6.278333e-02, -9.980272e-01 }, +{ 3.110184e+00, 3.140349e-02, -9.995068e-01 }, +{ 3.141600e+00, -7.346410e-06, -1.000000e-00 } +}; + +# define M_PI 3.14159265358979323846 /* pi */ + +static double inline gen_sin(double x) +{ + int i; + if(x < 0) while(x < -M_PI) x+= M_PI; + else while(x > M_PI) x-= M_PI; + for(i=0;i<sizeof(g_sincos)/sizeof(gen_sincos_t)-1;i++) + { + if(x>=g_sincos[i].x && x <= g_sincos[i+1].x) + { + return (g_sincos[i+1].sinx-g_sincos[i].sinx)*(x-g_sincos[i].x)/(g_sincos[i+1].x-g_sincos[i].x)+g_sincos[i].sinx; + } + } + return x<0?1:-1; +} +#undef sin +#define sin(x) gen_sin(x) + +static double inline gen_cos(double x) +{ + int i; + if(x < 0) while(x < -M_PI) x+= M_PI; + else while(x > M_PI) x-= M_PI; + for(i=0;i<sizeof(g_sincos)/sizeof(gen_sincos_t)-1;i++) + { + if(x>=g_sincos[i].x && x <= g_sincos[i+1].x) + { + return (g_sincos[i+1].cosx-g_sincos[i].cosx)*(x-g_sincos[i].x)/(g_sincos[i+1].x-g_sincos[i].x)+g_sincos[i].cosx; + } + } + return x<0?1:-1; +} +#undef cos +#define cos(x) gen_cos(x) + +#endif \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/drivers/hacking.ati Sat Mar 17 21:27:42 2007 +0000 @@ -0,0 +1,313 @@ + ATI chips hacking + ================= + Dedicated to ATI's hackers. + +Preface +~~~~~~~ +This document will compare ATI chips only from point of DAC and video overlay. +There are lots of difference from 3D point, dual-head support, tv-out support +and many other things but it's already perfectly different story. +This document doesn't include information about ATI AIW (All In Wonder) chips. + +What are units on modern ATI chips: +DAC - (Digital to Analog Convertor) controls CRTC, LCD, DFP monitor's output + Consists from: + PLL - (Programable line length) registers + CRTC - CRT controller + LCD/DFP scaler + surface control +DAC2 - controls CRTC, LCD, DFP monitor's output on second head +TVDAC - controls Composite Video and Super Video output ports + Consists from: + TV_PLL + TV scaler & sync unit + TV format convertor (PAL/NTSC) +TVCAP - controls Video-In port +MPP - Miscellaneous peripheral port. (includes macrovision's filter - copy + protection mechanism) +OV - Video overlay (YUV BES) (include subpictures, gamma correction and + adaptive deinterlacing) +CAP0 - Video capturing +CAP1 - Video capturing (second unit) +RT - Rage theatre: video encoding and mixing +MUX - video muxer +MEM - PCI/AGP bus mastering +2D - GUI engine +3D - 3D-OpenGL engine (There are lots of stuff) +I2C - I2C Bus control + +This document is mainly related only with OV unit ;) +Video decoding diagram: + +RAM memory: [ App ] Copies YUV image to overlay memory + | <-- (It's possible to program DMA here) +overlay memory:[ OV ] performs scaling and YUVtoRGB convertion + /\ +RGB memory: / \ + / [ macrovision ] performs copy protection filtering + / \ (unneeded but presented by default thing;) + [ CRTC/LCD/DFP DAC ] [ TV DAC ] convert RGB memory to CRTC and NTSC/PAL signals + | | + [CRTC/LCD/DFP Monitor] [TV-screen] + +History +~~~~~~~ + What is history of ATI's chips? I can be wrong but below is my vision +of this question: + +0. I don't know any earlied chips :( +1. Mach8 +2. Mach16 +3. Mach32 + +4. Mach64. + It's first chip which has support from side of open + source drivers. Set of mach64 chips is: + mach64GX (ATI888GX00) + mach64CX (ATI888CX00) + mach64CT (ATI264CT) + mach64ET (ATI264ET) + mach64VTA3 (ATI264VT) + mach64VTA4 (ATI264VT) + mach64VTB (ATI264VTB) + mach64VT4 (ATI264VT4) + +5. 3D rage chips. + It seems that these chips have fully compatible by GPU with Mach64 + which is extended by 3D possibilities. Set of 3D rage chips is: + 3D RAGE (GT) + 3D RAGE II+ (GTB) + 3D RAGE IIC (PCI) + 3D RAGE IIC (AGP) + 3D RAGE LT + 3D RAGE LT-G + 3D RAGE PRO (BGA, AGP) + 3D RAGE PRO (BGA, AGP, 1x only) + 3D RAGE PRO (BGA, PCI) + 3D RAGE PRO (PQFP, PCI) + 3D RAGE PRO (PQFP, PCI, limited 3D) + 3D RAGE (XL) + 3D RAGE LT PRO (AGP) + 3D RAGE LT PRO (PCI) + 3D RAGE Mobility (PCI) + 3D RAGE Mobility (AGP) + +6. Rage128 chips. + These chips have perfectly new GPU which supports memory mapped IO + space for accelerating port access (It's main cause of incompatibility + with mach64). Set of Rage128 chips is: + Rage128 GL RE + Rage128 GL RF + Rage128 GL RG + Rage128 GL RH + Rage128 GL RI + Rage128 VR RK + Rage128 VR RL + Rage128 VR RM + Rage128 VR RN + Rage128 VR RO + Rage128 Mobility M3 LE + Rage128 Mobility M3 LF +7. Rage128Pro chips. + These chips are successors of Rage128 ones. + Rage128Pro GL PA + Rage128Pro GL PB + Rage128Pro GL PC + Rage128Pro GL PD + Rage128Pro GL PE + Rage128Pro GL PF + Rage128Pro VR PG + Rage128Pro VR PH + Rage128Pro VR PI + Rage128Pro VR PJ + Rage128Pro VR PK + Rage128Pro VR PL + Rage128Pro VR PM + Rage128Pro VR PN + Rage128Pro VR PO + Rage128Pro VR PP + Rage128Pro VR PQ + Rage128Pro VR PR + Rage128Pro VR TR + Rage128Pro VR PS + Rage128Pro VR PT + Rage128Pro VR PU + Rage128Pro VR PV + Rage128Pro VR PW + Rage128Pro VR PX + Rage128Pro Ultra U1 + Rage128Pro Ultra U2 + Rage128Pro Ultra U3 + +8. Radeon chips. + Indeed they could be named Rage256 Pro. (With minor changes is fully + compatible with Rage128 chips). + Radeon QD + Radeon QE + Radeon QF + Radeon QG + Radeon VE QY + Radeon VE QZ + Radeon M6 LY + Radeon M6 LZ + Radeon M7 LW +9. Radeon2 chips. + Indeed they could be named Rage512 Pro. + Radeon2 8500 QL + Radeon2 7500 QW + +10. Radeon3 and newest are cooming soon, but I hope that they will be fully + compatible with Radeon1 chips. + +In Radeon famility there were introduced also FX chips: Radeon FX and +Radeon2 8700 FX. Probably they have the same possibility as other Radeon +but currently it's unknown for me. + +What about video overlay and DAC? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Currently it's known that there is only difference between +Mach64 and Rage128 compatible chips: +- They have different logic of io ports programming! +- They are incompatible by port numbers! +But: +- They use the same program logic from register's name point. +(Indeed exists slight difference even between Radeon and Rage128 +chips. AFAIK only Radeon has OV0_SLICE_CNTL register which currently +is not used by driver. But I know only its name ;). Also there +is difference in slight adjust of BES position but it's configured +by #ifdef blocks). + +Please compare: + +(The piece of Back-End Scaler programming) + + Sample for Mach64 compatible chips: + *********************************** + +#define SPARSE_IO_BASE 0x03fcu +#define SPARSE_IO_SELECT 0xfc00u + +#define BLOCK_IO_BASE 0xff00u +#define BLOCK_IO_SELECT 0x00fcu + +#define MM_IO_SELECT 0x03fcu +#define BLOCK_SELECT 0x0400u +#define DWORD_SELECT (BLOCK_SELECT | MM_IO_SELECT) + +#define IO_BYTE_SELECT 0x0003u + +#define SPARSE_IO_PORT (SPARSE_IO_BASE | IO_BYTE_SELECT) +#define BLOCK_IO_PORT (BLOCK_IO_BASE | IO_BYTE_SELECT) + +#define IOPortTag(_SparseIOSelect, _BlockIOSelect) \ + (SetBits(_SparseIOSelect, SPARSE_IO_SELECT) | \ + SetBits(_BlockIOSelect, BLOCK_SELECT | MM_IO_SELECT)) +#define SparseIOTag(_IOSelect) IOPortTag(_IOSelect, 0) +#define BlockIOTag(_IOSelect) IOPortTag(0, _IOSelect) + +... + +#define OVERLAY_Y_X_START BlockIOTag(0x100u) +#define OVERLAY_Y_X_END BlockIOTag(0x101u) + +... + +#define OUTREG(_Register, _Value) \ + MMIO_OUT32(pATI->pBlock[GetBits(_Register, BLOCK_SELECT)], \ + (_Register) & MM_IO_SELECT, _Value) + +... + +OUTREG(OVERLAY_Y_X_START,((drw_x)<<16)|(drw_y)|(1<<31)); +OUTREG(OVERLAY_Y_X_END,((drw_x+drw_w)<<16)|(drw_y+drw_h)); + + + Sample for Rage128 compatible chips: + ************************************ + +#define OV0_Y_X_START 0x0400 +#define OV0_Y_X_END 0x0404 + +... + +#define INREG(addr) readl((rage_mmio_base)+addr) +#define OUTREG(addr,val) writel(val, (rage_mmio_base)+addr) + +... + +rage_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RAGE_REGSIZE); + +... + +#ifdef RADEON +#define X_ADJUST 8 +#else /* rage128 */ +#define X_ADJUST 0 +#endif + +OUTREG(OV0_Y_X_START,(drw_x+X_ADJUST)|(drw_y<<16)); +OUTREG(OV0_Y_X_END,(drw_x+drw_w+X_ADJUST)|(drw_y+drw_h)<<16)); + +Thus - these chips have almost the same logic from register's name point. +(except the fact that they have swapped 16-bit halfs). +Yes - programming of Rage128 is much simpler of Mach64. + + +What about other ATI's chips? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +I suggest you have latest copy of GATOS-CVS: +http://www.linuxvideo.org +GATOS was designed and introduced as General ATI TV and Overlay Sowfware. +You will be able to find out there a lots of useful hacking utilities +(at location gatos-ati/gatos): +gfxdump - Program for dumping graphics chips registers on Linux and Windows 9X. + (it's more useful for Win9x to hack their values). +xatitv - For working with tv-in (currently is under hard development) +atitvout- For working with tv-out +and lot of other stuff. +BUT: After studing of Gatos and X11 stuffs I've found that they are bad +optimized for movie playback. +Please compare: + radeon_vid - configures video overlay only once and provides DGA to it. + (doesn't require to be MMX optimized) + gatos and X11 - configures video overlay at every slice of frame, then + performs unoptimized copying of source stuff to video memory + often with using CopyMungedData (it's C-analog of YV12_to_YUY2) + since there are lacks in yv12 support. + (is not MMX optimized that's gladly accepted, but probably + will be never optimized due portability). + +hardware IDCT support diagram: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + | +[ Video parser ] <---------- [ Transport demuxing ] --> [ Audio ] + | | | +[ Variable length decoder] |D | + | |V | +[ Inverse quantization ] |D | + | | | +-------|---[ video card ]---------+ |s | + | | |u | +[ Run level decode & de-zigzag ] | |b | + | | |p | +[ IDCT ] | |i | + | | |c | +[ Motion compensation ] | |t | + | | |u | +[ Advanced deinterlacing ] | |r | + | | |e | +[ Filtered X-Y scaling ] [SUBPIC]-|-----+s [ OSD ] + | | | | | +[ 4-bit alpha blending ] <---+ | +-------+ + | | +[ YUV to RGB conversion ] | +-------|--------------------------+ +TV-screen or CRT-display + + +Conslusion: +~~~~~~~~~~~ + +That's all folk!
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/drivers/radeon.h Sat Mar 17 21:27:42 2007 +0000 @@ -0,0 +1,2046 @@ +/* + * radeon.h + * This software has been released under the terms of the GNU Public + * license. See http://www.gnu.org/copyleft/gpl.html for details. + * + * This collection of definition was written by Nick Kurshev + * It's based on radeonfb, X11, GATOS sources + * and partly compatible with Rage128 set (in OV0, CAP0, CAP1 parts) +*/ + +#ifndef _RADEON_H +#define _RADEON_H + + +/* radeon PCI ids */ +#define PCI_DEVICE_ID_RADEON_QD 0x5144 +#define PCI_DEVICE_ID_RADEON_QE 0x5145 +#define PCI_DEVICE_ID_RADEON_QF 0x5146 +#define PCI_DEVICE_ID_RADEON_QG 0x5147 +#define PCI_DEVICE_ID_RADEON_QY 0x5159 +#define PCI_DEVICE_ID_RADEON_QZ 0x515A +#define PCI_DEVICE_ID_RADEON_LY 0x4C59 +#define PCI_DEVICE_ID_RADEON_LZ 0x4C5A +#define PCI_DEVICE_ID_RADEON_LW 0x4C57 +#define PCI_DEVICE_ID_R200_QL 0x514C +#define PCI_DEVICE_ID_RV200_QW 0x5157 +#define PCI_DEVICE_ID_R200_BB 0x4242 + +#define RADEON_REGSIZE 0x4000 + + +#define MM_INDEX 0x0000 +/* MM_INDEX bit constants */ +# define MM_APER 0x80000000 +#define MM_DATA 0x0004 +#define BUS_CNTL 0x0030 +/* BUS_CNTL bit constants */ +# define BUS_DBL_RESYNC 0x00000001 +# define BUS_MSTR_RESET 0x00000002 +# define BUS_FLUSH_BUF 0x00000004 +# define BUS_STOP_REQ_DIS 0x00000008 +# define BUS_ROTATION_DIS 0x00000010 +# define BUS_MASTER_DIS 0x00000040 +# define BUS_ROM_WRT_EN 0x00000080 +# define BUS_DIS_ROM 0x00001000 +# define BUS_PCI_READ_RETRY_EN 0x00002000 +# define BUS_AGP_AD_STEPPING_EN 0x00004000 +# define BUS_PCI_WRT_RETRY_EN 0x00008000 +# define BUS_MSTR_RD_MULT 0x00100000 +# define BUS_MSTR_RD_LINE 0x00200000 +# define BUS_SUSPEND 0x00400000 +# define LAT_16X 0x00800000 +# define BUS_RD_DISCARD_EN 0x01000000 +# define BUS_RD_ABORT_EN 0x02000000 +# define BUS_MSTR_WS 0x04000000 +# define BUS_PARKING_DIS 0x08000000 +# define BUS_MSTR_DISCONNECT_EN 0x10000000 +# define BUS_WRT_BURST 0x20000000 +# define BUS_READ_BURST 0x40000000 +# define BUS_RDY_READ_DLY 0x80000000 +#define HI_STAT 0x004C +#define BUS_CNTL1 0x0034 +# define BUS_WAIT_ON_LOCK_EN (1 << 4) +#define I2C_CNTL_0 0x0090 +# define I2C_DONE (1<<0) +# define I2C_NACK (1<<1) +# define I2C_HALT (1<<2) +# define I2C_SOFT_RST (1<<5) +# define I2C_DRIVE_EN (1<<6) +# define I2C_DRIVE_SEL (1<<7) +# define I2C_START (1<<8) +# define I2C_STOP (1<<9) +# define I2C_RECEIVE (1<<10) +# define I2C_ABORT (1<<11) +# define I2C_GO (1<<12) +# define I2C_SEL (1<<16) +# define I2C_EN (1<<17) +#define I2C_CNTL_1 0x0094 +#define I2C_DATA 0x0098 +#define CONFIG_CNTL 0x00E0 +/* CONFIG_CNTL bit constants */ +# define CFG_VGA_RAM_EN 0x00000100 +#define CONFIG_MEMSIZE 0x00F8 +#define CONFIG_APER_0_BASE 0x0100 +#define CONFIG_APER_1_BASE 0x0104 +#define CONFIG_APER_SIZE 0x0108 +#define CONFIG_REG_1_BASE 0x010C +#define CONFIG_REG_APER_SIZE 0x0110 +#define PAD_AGPINPUT_DELAY 0x0164 +#define PAD_CTLR_STRENGTH 0x0168 +#define PAD_CTLR_UPDATE 0x016C +#define AGP_CNTL 0x0174 +# define AGP_APER_SIZE_256MB (0x00 << 0) +# define AGP_APER_SIZE_128MB (0x20 << 0) +# define AGP_APER_SIZE_64MB (0x30 << 0) +# define AGP_APER_SIZE_32MB (0x38 << 0) +# define AGP_APER_SIZE_16MB (0x3c << 0) +# define AGP_APER_SIZE_8MB (0x3e << 0) +# define AGP_APER_SIZE_4MB (0x3f << 0) +# define AGP_APER_SIZE_MASK (0x3f << 0) +#define AMCGPIO_A_REG 0x01a0 +#define AMCGPIO_EN_REG 0x01a8 +#define AMCGPIO_MASK 0x0194 +#define AMCGPIO_Y_REG 0x01a4 +#define BM_STATUS 0x0160 +#define MPP_TB_CONFIG 0x01c0 /* ? */ +#define MPP_GP_CONFIG 0x01c8 /* ? */ +#define VENDOR_ID 0x0F00 +#define DEVICE_ID 0x0F02 +#define COMMAND 0x0F04 +#define STATUS 0x0F06 +#define REVISION_ID 0x0F08 +#define REGPROG_INF 0x0F09 +#define SUB_CLASS 0x0F0A +#define CACHE_LINE 0x0F0C +#define LATENCY 0x0F0D +#define HEADER 0x0F0E +#define BIST 0x0F0F +#define REG_MEM_BASE 0x0F10 +#define REG_IO_BASE 0x0F14 +#define REG_REG_BASE 0x0F18 +#define ADAPTER_ID 0x0F2C +#define BIOS_ROM 0x0F30 +#define CAPABILITIES_PTR 0x0F34 +#define INTERRUPT_LINE 0x0F3C +#define INTERRUPT_PIN 0x0F3D +#define MIN_GRANT 0x0F3E +#define MAX_LATENCY 0x0F3F +#define ADAPTER_ID_W 0x0F4C +#define PMI_CAP_ID 0x0F50 +#define PMI_NXT_CAP_PTR 0x0F51 +#define PMI_PMC_REG 0x0F52 +#define PM_STATUS 0x0F54 +#define PMI_DATA 0x0F57 +#define AGP_CAP_ID 0x0F58 +#define AGP_STATUS 0x0F5C +# define AGP_1X_MODE 0x01 +# define AGP_2X_MODE 0x02 +# define AGP_4X_MODE 0x04 +# define AGP_MODE_MASK 0x07 +#define AGP_COMMAND 0x0F60 + +/* Video muxer unit */ +#define VIDEOMUX_CNTL 0x0190 +#define VIPPAD_MASK 0x0198 +#define VIPPAD1_A 0x01AC +#define VIPPAD1_EN 0x01B0 +#define VIPPAD1_Y 0x01B4 + +#define AIC_CTRL 0x01D0 +#define AIC_STAT 0x01D4 +#define AIC_PT_BASE 0x01D8 +#define AIC_LO_ADDR 0x01DC +#define AIC_HI_ADDR 0x01E0 +#define AIC_TLB_ADDR 0x01E4 +#define AIC_TLB_DATA 0x01E8 +#define DAC_CNTL 0x0058 +/* DAC_CNTL bit constants */ +# define DAC_8BIT_EN 0x00000100 +# define DAC_4BPP_PIX_ORDER 0x00000200 +# define DAC_CRC_EN 0x00080000 +# define DAC_MASK_ALL (0xff << 24) +# define DAC_VGA_ADR_EN (1 << 13) +# define DAC_RANGE_CNTL (3 << 0) +# define DAC_BLANKING (1 << 2) +#define DAC_CNTL2 0x007c +/* DAC_CNTL2 bit constants */ +# define DAC2_DAC_CLK_SEL (1 << 0) +# define DAC2_DAC2_CLK_SEL (1 << 1) +# define DAC2_PALETTE_ACC_CTL (1 << 5) +#define TV_DAC_CNTL 0x088c +/* TV_DAC_CNTL bit constants */ +# define TV_DAC_STD_MASK 0x0300 +# define TV_DAC_RDACPD (1 << 24) +# define TV_DAC_GDACPD (1 << 25) +# define TV_DAC_BDACPD (1 << 26) +#define CRTC_GEN_CNTL 0x0050 +/* CRTC_GEN_CNTL bit constants */ +# define CRTC_DBL_SCAN_EN 0x00000001 +# define CRTC_INTERLACE_EN (1 << 1) +# define CRTC_CSYNC_EN (1 << 4) +# define CRTC_CUR_EN 0x00010000 +# define CRTC_CUR_MODE_MASK (7 << 17) +# define CRTC_ICON_EN (1 << 20) +# define CRTC_EXT_DISP_EN (1 << 24) +# define CRTC_EN (1 << 25) +# define CRTC_DISP_REQ_EN_B (1 << 26) +#define CRTC2_GEN_CNTL 0x03f8 +/* CRTC2_GEN_CNTL bit constants */ +# define CRTC2_DBL_SCAN_EN (1 << 0) +# define CRTC2_INTERLACE_EN (1 << 1) +# define CRTC2_SYNC_TRISTAT (1 << 4) +# define CRTC2_HSYNC_TRISTAT (1 << 5) +# define CRTC2_VSYNC_TRISTAT (1 << 6) +# define CRTC2_CRT2_ON (1 << 7) +# define CRTC2_ICON_EN (1 << 15) +# define CRTC2_CUR_EN (1 << 16) +# define CRTC2_CUR_MODE_MASK (7 << 20) +# define CRTC2_DISP_DIS (1 << 23) +# define CRTC2_EN (1 << 25) +# define CRTC2_DISP_REQ_EN_B (1 << 26) +# define CRTC2_HSYNC_DIS (1 << 28) +# define CRTC2_VSYNC_DIS (1 << 29) +#define MEM_CNTL 0x0140 +/* MEM_CNTL bit constants */ +# define MEM_CTLR_STATUS_IDLE 0x00000000 +# define MEM_CTLR_STATUS_BUSY 0x00100000 +# define MEM_SEQNCR_STATUS_IDLE 0x00000000 +# define MEM_SEQNCR_STATUS_BUSY 0x00200000 +# define MEM_ARBITER_STATUS_IDLE 0x00000000 +# define MEM_ARBITER_STATUS_BUSY 0x00400000 +# define MEM_REQ_UNLOCK 0x00000000 +# define MEM_REQ_LOCK 0x00800000 +#define EXT_MEM_CNTL 0x0144 +#define MC_AGP_LOCATION 0x014C +#define MEM_IO_CNTL_A0 0x0178 +#define MEM_INIT_LATENCY_TIMER 0x0154 +#define MEM_SDRAM_MODE_REG 0x0158 +#define AGP_BASE 0x0170 +#define MEM_IO_CNTL_A1 0x017C +#define MEM_IO_CNTL_B0 0x0180 +#define MEM_IO_CNTL_B1 0x0184 +#define MC_DEBUG 0x0188 +#define MC_STATUS 0x0150 +#define MEM_IO_OE_CNTL 0x018C +#define MC_FB_LOCATION 0x0148 +#define HOST_PATH_CNTL 0x0130 +#define MEM_VGA_WP_SEL 0x0038 +#define MEM_VGA_RP_SEL 0x003C +#define HDP_DEBUG 0x0138 +#define SW_SEMAPHORE 0x013C +#define SURFACE_CNTL 0x0B00 +/* SURFACE_CNTL bit constants */ +# define SURF_TRANSLATION_DIS (1 << 8) +# define NONSURF_AP0_SWP_16BPP (1 << 20) +# define NONSURF_AP0_SWP_32BPP (2 << 20) +#define SURFACE0_LOWER_BOUND 0x0B04 +#define SURFACE1_LOWER_BOUND 0x0B14 +#define SURFACE2_LOWER_BOUND 0x0B24 +#define SURFACE3_LOWER_BOUND 0x0B34 +#define SURFACE4_LOWER_BOUND 0x0B44 +#define SURFACE5_LOWER_BOUND 0x0B54 +#define SURFACE6_LOWER_BOUND 0x0B64 +#define SURFACE7_LOWER_BOUND 0x0B74 +#define SURFACE0_UPPER_BOUND 0x0B08 +#define SURFACE1_UPPER_BOUND 0x0B18 +#define SURFACE2_UPPER_BOUND 0x0B28 +#define SURFACE3_UPPER_BOUND 0x0B38 +#define SURFACE4_UPPER_BOUND 0x0B48 +#define SURFACE5_UPPER_BOUND 0x0B58 +#define SURFACE6_UPPER_BOUND 0x0B68 +#define SURFACE7_UPPER_BOUND 0x0B78 +#define SURFACE0_INFO 0x0B0C +#define SURFACE1_INFO 0x0B1C +#define SURFACE2_INFO 0x0B2C +#define SURFACE3_INFO 0x0B3C +#define SURFACE4_INFO 0x0B4C +#define SURFACE5_INFO 0x0B5C +#define SURFACE6_INFO 0x0B6C +#define SURFACE7_INFO 0x0B7C +#define SURFACE_ACCESS_FLAGS 0x0BF8 +#define SURFACE_ACCESS_CLR 0x0BFC +#define GEN_INT_CNTL 0x0040 +#define GEN_INT_STATUS 0x0044 +# define VSYNC_INT_AK (1 << 2) +# define VSYNC_INT (1 << 2) +#define CRTC_EXT_CNTL 0x0054 +/* CRTC_EXT_CNTL bit constants */ +# define CRTC_VGA_XOVERSCAN (1 << 0) +# define VGA_ATI_LINEAR 0x00000008 +# define VGA_128KAP_PAGING 0x00000010 +# define XCRT_CNT_EN (1 << 6) +# define CRTC_HSYNC_DIS (1 << 8) +# define CRTC_VSYNC_DIS (1 << 9) +# define CRTC_DISPLAY_DIS (1 << 10) +# define CRTC_SYNC_TRISTAT (1 << 11) +# define CRTC_CRT_ON (1 << 15) +#define CRTC_EXT_CNTL_DPMS_BYTE 0x0055 +# define CRTC_HSYNC_DIS_BYTE (1 << 0) +# define CRTC_VSYNC_DIS_BYTE (1 << 1) +# define CRTC_DISPLAY_DIS_BYTE (1 << 2) +#define RB3D_CNTL 0x1C3C +#define WAIT_UNTIL 0x1720 +#define ISYNC_CNTL 0x1724 +#define RBBM_GUICNTL 0x172C +#define RBBM_STATUS 0x0E40 +# define RBBM_FIFOCNT_MASK 0x007f +# define RBBM_ACTIVE (1 << 31) +#define RBBM_STATUS_alt_1 0x1740 +#define RBBM_CNTL 0x00EC +#define RBBM_CNTL_alt_1 0x0E44 +#define RBBM_SOFT_RESET 0x00F0 +/* RBBM_SOFT_RESET bit constants */ +# define SOFT_RESET_CP (1 << 0) +# define SOFT_RESET_HI (1 << 1) +# define SOFT_RESET_SE (1 << 2) +# define SOFT_RESET_RE (1 << 3) +# define SOFT_RESET_PP (1 << 4) +# define SOFT_RESET_E2 (1 << 5) +# define SOFT_RESET_RB (1 << 6) +# define SOFT_RESET_HDP (1 << 7) +#define RBBM_SOFT_RESET_alt_1 0x0E48 +#define NQWAIT_UNTIL 0x0E50 +#define RBBM_DEBUG 0x0E6C +#define RBBM_CMDFIFO_ADDR 0x0E70 +#define RBBM_CMDFIFO_DATAL 0x0E74 +#define RBBM_CMDFIFO_DATAH 0x0E78 +#define RBBM_CMDFIFO_STAT 0x0E7C +#define CRTC_STATUS 0x005C +/* CRTC_STATUS bit constants */ +# define CRTC_VBLANK 0x00000001 +# define CRTC_VBLANK_SAVE ( 1 << 1) +#define GPIO_VGA_DDC 0x0060 +#define GPIO_DVI_DDC 0x0064 +#define GPIO_MONID 0x0068 +#define PALETTE_INDEX 0x00B0 +#define PALETTE_DATA 0x00B4 +#define PALETTE_30_DATA 0x00B8 +#define CRTC_H_TOTAL_DISP 0x0200 +# define CRTC_H_TOTAL (0x03ff << 0) +# define CRTC_H_TOTAL_SHIFT 0 +# define CRTC_H_DISP (0x01ff << 16) +# define CRTC_H_DISP_SHIFT 16 +#define CRTC2_H_TOTAL_DISP 0x0300 +# define CRTC2_H_TOTAL (0x03ff << 0) +# define CRTC2_H_TOTAL_SHIFT 0 +# define CRTC2_H_DISP (0x01ff << 16) +# define CRTC2_H_DISP_SHIFT 16 +#define CRTC_H_SYNC_STRT_WID 0x0204 +# define CRTC_H_SYNC_STRT_PIX (0x07 << 0) +# define CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) +# define CRTC_H_SYNC_STRT_CHAR_SHIFT 3 +# define CRTC_H_SYNC_WID (0x3f << 16) +# define CRTC_H_SYNC_WID_SHIFT 16 +# define CRTC_H_SYNC_POL (1 << 23) +#define CRTC2_H_SYNC_STRT_WID 0x0304 +# define CRTC2_H_SYNC_STRT_PIX (0x07 << 0) +# define CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) +# define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 +# define CRTC2_H_SYNC_WID (0x3f << 16) +# define CRTC2_H_SYNC_WID_SHIFT 16 +# define CRTC2_H_SYNC_POL (1 << 23) +#define CRTC_V_TOTAL_DISP 0x0208 +# define CRTC_V_TOTAL (0x07ff << 0) +# define CRTC_V_TOTAL_SHIFT 0 +# define CRTC_V_DISP (0x07ff << 16) +# define CRTC_V_DISP_SHIFT 16 +#define CRTC2_V_TOTAL_DISP 0x0308 +# define CRTC2_V_TOTAL (0x07ff << 0) +# define CRTC2_V_TOTAL_SHIFT 0 +# define CRTC2_V_DISP (0x07ff << 16) +# define CRTC2_V_DISP_SHIFT 16 +#define CRTC_V_SYNC_STRT_WID 0x020C +# define CRTC_V_SYNC_STRT (0x7ff << 0) +# define CRTC_V_SYNC_STRT_SHIFT 0 +# define CRTC_V_SYNC_WID (0x1f << 16) +# define CRTC_V_SYNC_WID_SHIFT 16 +# define CRTC_V_SYNC_POL (1 << 23) +#define CRTC2_V_SYNC_STRT_WID 0x030C +# define CRTC2_V_SYNC_STRT (0x7ff << 0) +# define CRTC2_V_SYNC_STRT_SHIFT 0 +# define CRTC2_V_SYNC_WID (0x1f << 16) +# define CRTC2_V_SYNC_WID_SHIFT 16 +# define CRTC2_V_SYNC_POL (1 << 23) +#define CRTC_VLINE_CRNT_VLINE 0x0210 +# define CRTC_CRNT_VLINE_MASK (0x7ff << 16) +#define CRTC2_VLINE_CRNT_VLINE 0x0310 +#define CRTC_CRNT_FRAME 0x0214 +#define CRTC2_CRNT_FRAME 0x0314 +#define CRTC_GUI_TRIG_VLINE 0x0218 +#define CRTC2_GUI_TRIG_VLINE 0x0318 +#define CRTC_DEBUG 0x021C +#define CRTC2_DEBUG 0x031C +#define CRTC_OFFSET_RIGHT 0x0220 +#define CRTC_OFFSET 0x0224 +#define CRTC2_OFFSET 0x0324 +#define CRTC_OFFSET_CNTL 0x0228 +# define CRTC_TILE_EN (1 << 15) +#define CRTC2_OFFSET_CNTL 0x0328 +# define CRTC2_TILE_EN (1 << 15) +#define CRTC_PITCH 0x022C +#define CRTC2_PITCH 0x032C +#define TMDS_CRC 0x02a0 +#define OVR_CLR 0x0230 +#define OVR_WID_LEFT_RIGHT 0x0234 +#define OVR_WID_TOP_BOTTOM 0x0238 +#define DISPLAY_BASE_ADDR 0x023C +#define SNAPSHOT_VH_COUNTS 0x0240 +#define SNAPSHOT_F_COUNT 0x0244 +#define N_VIF_COUNT 0x0248 +#define SNAPSHOT_VIF_COUNT 0x024C +#define FP_CRTC_H_TOTAL_DISP 0x0250 +#define FP_CRTC2_H_TOTAL_DISP 0x0350 +#define FP_CRTC_V_TOTAL_DISP 0x0254 +#define FP_CRTC2_V_TOTAL_DISP 0x0354 +# define FP_CRTC_H_TOTAL_MASK 0x000003ff +# define FP_CRTC_H_DISP_MASK 0x01ff0000 +# define FP_CRTC_V_TOTAL_MASK 0x00000fff +# define FP_CRTC_V_DISP_MASK 0x0fff0000 +# define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +# define FP_H_SYNC_WID_MASK 0x003f0000 +# define FP_V_SYNC_STRT_MASK 0x00000fff +# define FP_V_SYNC_WID_MASK 0x001f0000 +# define FP_CRTC_H_TOTAL_SHIFT 0x00000000 +# define FP_CRTC_H_DISP_SHIFT 0x00000010 +# define FP_CRTC_V_TOTAL_SHIFT 0x00000000 +# define FP_CRTC_V_DISP_SHIFT 0x00000010 +# define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +# define FP_H_SYNC_WID_SHIFT 0x00000010 +# define FP_V_SYNC_STRT_SHIFT 0x00000000 +# define FP_V_SYNC_WID_SHIFT 0x00000010 +#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 +#define CRT_CRTC_V_SYNC_STRT_WID 0x025C +#define CUR_OFFSET 0x0260 +#define CUR_HORZ_VERT_POSN 0x0264 +#define CUR_HORZ_VERT_OFF 0x0268 +/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ +# define CUR_LOCK 0x80000000 +#define CUR_CLR0 0x026C +#define CUR_CLR1 0x0270 +#define CUR2_OFFSET 0x0360 +#define CUR2_HORZ_VERT_POSN 0x0364 +#define CUR2_HORZ_VERT_OFF 0x0368 +# define CUR2_LOCK (1 << 31) +#define CUR2_CLR0 0x036c +#define CUR2_CLR1 0x0370 +#define FP_HORZ_VERT_ACTIVE 0x0278 +#define CRTC_MORE_CNTL 0x027C +#define DAC_EXT_CNTL 0x0280 +#define FP_GEN_CNTL 0x0284 +/* FP_GEN_CNTL bit constants */ +# define FP_FPON (1 << 0) +# define FP_TMDS_EN (1 << 2) +# define FP_EN_TMDS (1 << 7) +# define FP_DETECT_SENSE (1 << 8) +# define FP_SEL_CRTC2 (1 << 13) +# define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +# define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +# define FP_CRTC_DONT_SHADOW_HEND (1 << 17) +# define FP_CRTC_USE_SHADOW_VEND (1 << 18) +# define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +# define FP_DFP_SYNC_SEL (1 << 21) +# define FP_CRTC_LOCK_8DOT (1 << 22) +# define FP_CRT_SYNC_SEL (1 << 23) +# define FP_USE_SHADOW_EN (1 << 24) +# define FP_CRT_SYNC_ALT (1 << 26) +#define FP2_GEN_CNTL 0x0288 +/* FP2_GEN_CNTL bit constants */ +# define FP2_FPON (1 << 0) +# define FP2_TMDS_EN (1 << 2) +# define FP2_EN_TMDS (1 << 7) +# define FP2_DETECT_SENSE (1 << 8) +# define FP2_SEL_CRTC2 (1 << 13) +# define FP2_FP_POL (1 << 16) +# define FP2_LP_POL (1 << 17) +# define FP2_SCK_POL (1 << 18) +# define FP2_LCD_CNTL_MASK (7 << 19) +# define FP2_PAD_FLOP_EN (1 << 22) +# define FP2_CRC_EN (1 << 23) +# define FP2_CRC_READ_EN (1 << 24) +#define FP_HORZ_STRETCH 0x028C +#define FP_HORZ2_STRETCH 0x038C +# define HORZ_STRETCH_RATIO_MASK 0xffff +# define HORZ_STRETCH_RATIO_MAX 4096 +# define HORZ_PANEL_SIZE (0x1ff << 16) +# define HORZ_PANEL_SHIFT 16 +# define HORZ_STRETCH_PIXREP (0 << 25) +# define HORZ_STRETCH_BLEND (1 << 26) +# define HORZ_STRETCH_ENABLE (1 << 25) +# define HORZ_AUTO_RATIO (1 << 27) +# define HORZ_FP_LOOP_STRETCH (0x7 << 28) +# define HORZ_AUTO_RATIO_INC (1 << 31) +#define FP_VERT_STRETCH 0x0290 +#define FP_VERT2_STRETCH 0x0390 +# define VERT_PANEL_SIZE (0xfff << 12) +# define VERT_PANEL_SHIFT 12 +# define VERT_STRETCH_RATIO_MASK 0xfff +# define VERT_STRETCH_RATIO_SHIFT 0 +# define VERT_STRETCH_RATIO_MAX 4096 +# define VERT_STRETCH_ENABLE (1 << 25) +# define VERT_STRETCH_LINEREP (0 << 26) +# define VERT_STRETCH_BLEND (1 << 26) +# define VERT_AUTO_RATIO_EN (1 << 27) +# define VERT_STRETCH_RESERVED 0xf1000000 +#define FP_H_SYNC_STRT_WID 0x02C4 +#define FP_H2_SYNC_STRT_WID 0x03C4 +#define FP_V_SYNC_STRT_WID 0x02C8 +#define FP_V2_SYNC_STRT_WID 0x03C8 +#define LVDS_GEN_CNTL 0x02d0 +# define LVDS_ON (1 << 0) +# define LVDS_DISPLAY_DIS (1 << 1) +# define LVDS_PANEL_TYPE (1 << 2) +# define LVDS_PANEL_FORMAT (1 << 3) +# define LVDS_EN (1 << 7) +# define LVDS_DIGON (1 << 18) +# define LVDS_BLON (1 << 19) +# define LVDS_SEL_CRTC2 (1 << 23) +#define LVDS_PLL_CNTL 0x02d4 +# define HSYNC_DELAY_SHIFT 28 +# define HSYNC_DELAY_MASK (0xf << 28) +#define AUX_WINDOW_HORZ_CNTL 0x02D8 +#define AUX_WINDOW_VERT_CNTL 0x02DC +#define DDA_CONFIG 0x02e0 +#define DDA_ON_OFF 0x02e4 + +#define GRPH_BUFFER_CNTL 0x02F0 +#define VGA_BUFFER_CNTL 0x02F4 + +/* first overlay unit (there is only one) */ + +#define OV0_Y_X_START 0x0400 +#define OV0_Y_X_END 0x0404 +#define OV0_PIPELINE_CNTL 0x0408 +#define OV0_EXCLUSIVE_HORZ 0x0408 +# define EXCL_HORZ_START_MASK 0x000000ff +# define EXCL_HORZ_END_MASK 0x0000ff00 +# define EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 +# define EXCL_HORZ_EXCLUSIVE_EN 0x80000000 +#define OV0_EXCLUSIVE_VERT 0x040C +# define EXCL_VERT_START_MASK 0x000003ff +# define EXCL_VERT_END_MASK 0x03ff0000 +#define OV0_REG_LOAD_CNTL 0x0410 +# define REG_LD_CTL_LOCK 0x00000001L +# define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L +# define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L +# define REG_LD_CTL_LOCK_READBACK 0x00000008L +#define OV0_SCALE_CNTL 0x0420 +# define SCALER_PIX_EXPAND 0x00000001L +# define SCALER_Y2R_TEMP 0x00000002L +#ifdef RAGE128 +# define SCALER_HORZ_PICK_NEAREST 0x00000003L +# define SCALER_VERT_PICK_NEAREST 0x00000004L +#else +# define SCALER_HORZ_PICK_NEAREST 0x00000004L +# define SCALER_VERT_PICK_NEAREST 0x00000008L +#endif +# define SCALER_SIGNED_UV 0x00000010L +# define SCALER_GAMMA_SEL_MASK 0x00000060L +# define SCALER_GAMMA_SEL_BRIGHT 0x00000000L +# define SCALER_GAMMA_SEL_G22 0x00000020L +# define SCALER_GAMMA_SEL_G18 0x00000040L +# define SCALER_GAMMA_SEL_G14 0x00000060L +# define SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L +# define SCALER_SURFAC_FORMAT 0x00000f00L +# define SCALER_SOURCE_UNK0 0x00000000L /* 2 bpp ??? */ +# define SCALER_SOURCE_UNK1 0x00000100L /* 4 bpp ??? */ +# define SCALER_SOURCE_UNK2 0x00000200L /* 8 bpp ??? */ +# define SCALER_SOURCE_15BPP 0x00000300L +# define SCALER_SOURCE_16BPP 0x00000400L +# define SCALER_SOURCE_24BPP 0x00000500L +# define SCALER_SOURCE_32BPP 0x00000600L +# define SCALER_SOURCE_UNK3 0x00000700L /* 8BPP_RGB332 ??? */ +# define SCALER_SOURCE_UNK4 0x00000800L /* 8BPP_Y8 ??? */ +# define SCALER_SOURCE_YUV9 0x00000900L /* 8BPP_RGB8 */ +# define SCALER_SOURCE_YUV12 0x00000A00L +# define SCALER_SOURCE_VYUY422 0x00000B00L +# define SCALER_SOURCE_YVYU422 0x00000C00L +# define SCALER_SOURCE_UNK5 0x00000D00L /* ??? */ +# define SCALER_SOURCE_UNK6 0x00000E00L /* 32BPP_AYUV444 */ +# define SCALER_SOURCE_UNK7 0x00000F00L /* 16BPP_ARGB4444 */ +# define SCALER_ADAPTIVE_DEINT 0x00001000L +# define R200_SCALER_TEMPORAL_DEINT 0x00002000L +# define SCALER_UNKNOWN_FLAG1 0x00004000L /* ??? */ +# define SCALER_SMART_SWITCH 0x00008000L +#ifdef RAGE128 +# define SCALER_BURST_PER_PLANE 0x00ff0000L +#else +# define SCALER_BURST_PER_PLANE 0x007f0000L +#endif +# define SCALER_DOUBLE_BUFFER 0x01000000L +# define SCALER_UNKNOWN_FLAG3 0x02000000L /* ??? */ +# define SCALER_UNKNOWN_FLAG4 0x04000000L /* ??? */ +# define SCALER_DIS_LIMIT 0x08000000L +# define SCALER_PRG_LOAD_START 0x10000000L +# define SCALER_INT_EMU 0x20000000L +# define SCALER_ENABLE 0x40000000L +# define SCALER_SOFT_RESET 0x80000000L +#define OV0_V_INC 0x0424 +#define OV0_P1_V_ACCUM_INIT 0x0428 +# define OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L +# define OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L +#define OV0_P23_V_ACCUM_INIT 0x042C +# define OV0_P23_MAX_LN_IN_PER_LN_OUT 0x00000003L +# define OV0_P23_V_ACCUM_INIT_MASK 0x01ff8000L +#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 +# define P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL +# define P1_ACTIVE_LINES_M1 0x0fff0000L +#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 +# define P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL +# define P23_ACTIVE_LINES_M1 0x07ff0000L +#ifndef RAGE128 +#define OV0_BASE_ADDR 0x043C +#endif +#define OV0_VID_BUF0_BASE_ADRS 0x0440 +# define VIF_BUF0_PITCH_SEL 0x00000001L +# define VIF_BUF0_TILE_ADRS 0x00000002L +# define VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF1_BASE_ADRS 0x0444 +# define VIF_BUF1_PITCH_SEL 0x00000001L +# define VIF_BUF1_TILE_ADRS 0x00000002L +# define VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF2_BASE_ADRS 0x0448 +# define VIF_BUF2_PITCH_SEL 0x00000001L +# define VIF_BUF2_TILE_ADRS 0x00000002L +# define VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF3_BASE_ADRS 0x044C +# define VIF_BUF3_PITCH_SEL 0x00000001L +# define VIF_BUF3_TILE_ADRS 0x00000002L +# define VIF_BUF3_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF3_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF4_BASE_ADRS 0x0450 +# define VIF_BUF4_PITCH_SEL 0x00000001L +# define VIF_BUF4_TILE_ADRS 0x00000002L +# define VIF_BUF4_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF4_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF5_BASE_ADRS 0x0454 +# define VIF_BUF5_PITCH_SEL 0x00000001L +# define VIF_BUF5_TILE_ADRS 0x00000002L +# define VIF_BUF5_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF5_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define OV0_AUTO_FLIP_CNTL 0x0470 +# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 +# define OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 +# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 +# define OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 +# define OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 +# define OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 +# define OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 +# define OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 +# define OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 +# define OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 +#define OV0_DEINTERLACE_PATTERN 0x0474 +#define OV0_SUBMIT_HISTORY 0x0478 +#define OV0_H_INC 0x0480 +#define OV0_STEP_BY 0x0484 +#define OV0_P1_H_ACCUM_INIT 0x0488 +#define OV0_P23_H_ACCUM_INIT 0x048C +#define OV0_P1_X_START_END 0x0494 +#define OV0_P2_X_START_END 0x0498 +#define OV0_P3_X_START_END 0x049C +#define OV0_FILTER_CNTL 0x04A0 +# define FILTER_PROGRAMMABLE_COEF 0x00000000 +# define FILTER_HARDCODED_COEF 0x0000000F +# define FILTER_COEF_MASK 0x0000000F +/* other values allow us use hardcoded coefs for Y and + programmable for UV that's nosense. */ +/* + Top quality 4x4-tap filtered vertical and horizontal scaler. + It allows up to 64:1 upscaling and downscaling without + performance or quality degradation. +*/ +#define OV0_FOUR_TAP_COEF_0 0x04B0 +#define OV0_FOUR_TAP_COEF_1 0x04B4 +#define OV0_FOUR_TAP_COEF_2 0x04B8 +#define OV0_FOUR_TAP_COEF_3 0x04BC +#define OV0_FOUR_TAP_COEF_4 0x04C0 + +#define OV0_FLAG_CNTL 0x04DC +#ifdef RAGE128 +#define OV0_COLOUR_CNTL 0x04E0 +# define COLOUR_CNTL_BRIGHTNESS 0x0000007F +# define COLOUR_CNTL_SATURATION 0x001F1F00 +#else +/* NB: radeons have no COLOUR_CNTL register */ +#define OV0_SLICE_CNTL 0x04E0 +# define SLICE_CNTL_DISABLE 0x40000000 +#endif +/* Video and graphics keys allow alpha blending, color correction + and many other video effects */ +#define OV0_VID_KEY_CLR 0x04E4 +#define OV0_VID_KEY_MSK 0x04E8 +#define OV0_GRAPHICS_KEY_CLR 0x04EC +#define OV0_GRAPHICS_KEY_MSK 0x04F0 +#define OV0_KEY_CNTL 0x04F4 +# define VIDEO_KEY_FN_MASK 0x00000007L +# define VIDEO_KEY_FN_FALSE 0x00000000L +# define VIDEO_KEY_FN_TRUE 0x00000001L +# define VIDEO_KEY_FN_EQ 0x00000004L +# define VIDEO_KEY_FN_NE 0x00000005L +# define GRAPHIC_KEY_FN_MASK 0x00000070L +# define GRAPHIC_KEY_FN_FALSE 0x00000000L +# define GRAPHIC_KEY_FN_TRUE 0x00000010L +# define GRAPHIC_KEY_FN_EQ 0x00000040L +# define GRAPHIC_KEY_FN_NE 0x00000050L +# define CMP_MIX_MASK 0x00000100L +# define CMP_MIX_OR 0x00000000L +# define CMP_MIX_AND 0x00000100L +#define OV0_TEST 0x04F8 +#define OV0_LIN_TRANS_A 0x0D20 +#define OV0_LIN_TRANS_B 0x0D24 +#define OV0_LIN_TRANS_C 0x0D28 +#define OV0_LIN_TRANS_D 0x0D2C +#define OV0_LIN_TRANS_E 0x0D30 +#define OV0_LIN_TRANS_F 0x0D34 +#define OV0_GAMMA_0_F 0x0D40 +#define OV0_GAMMA_10_1F 0x0D44 +#define OV0_GAMMA_20_3F 0x0D48 +#define OV0_GAMMA_40_7F 0x0D4C +/* These registers exist on R200 only */ +#define OV0_GAMMA_80_BF 0x0E00 +#define OV0_GAMMA_C0_FF 0x0E04 +#define OV0_GAMMA_100_13F 0x0E08 +#define OV0_GAMMA_140_17F 0x0E0C +#define OV0_GAMMA_180_1BF 0x0E10 +#define OV0_GAMMA_1C0_1FF 0x0E14 +#define OV0_GAMMA_200_23F 0x0E18 +#define OV0_GAMMA_240_27F 0x0E1C +#define OV0_GAMMA_280_2BF 0x0E20 +#define OV0_GAMMA_2C0_2FF 0x0E24 +#define OV0_GAMMA_300_33F 0x0E28 +#define OV0_GAMMA_340_37F 0x0E2C +/* End of R200 specific definitions */ +#define OV0_GAMMA_380_3BF 0x0D50 +#define OV0_GAMMA_3C0_3FF 0x0D54 + +/* + IDCT ENGINE: + It's MPEG-2 hardware decoder which incorporates run-level decode, de-zigzag + and IDCT into an IDCT engine to complement the motion compensation engine. +*/ +#define IDCT_RUNS 0x1F80 +#define IDCT_LEVELS 0x1F84 +#define IDCT_AUTH_CONTROL 0x1F88 +#define IDCT_AUTH 0x1F8C +#define IDCT_CONTROL 0x1FBC + +#define SE_MC_SRC2_CNTL 0x19D4 +#define SE_MC_SRC1_CNTL 0x19D8 +#define SE_MC_DST_CNTL 0x19DC +#define SE_MC_CNTL_START 0x19E0 +#ifndef RAGE128 +#define SE_MC_BUF_BASE 0x19E4 +#define PP_MC_CONTEXT 0x19E8 +#define PP_MISC 0x1C14 +#endif +/* + SUBPICTURE UNIT: + Decompressing, scaling and alpha blending the compressed bitmap on the fly. + Provide optimal DVD subpicture qualtity. +*/ +#define SUBPIC_CNTL 0x0540 +#define SUBPIC_DEFCOLCON 0x0544 +#define SUBPIC_Y_X_START 0x054C +#define SUBPIC_Y_X_END 0x0550 +#define SUBPIC_V_INC 0x0554 +#define SUBPIC_H_INC 0x0558 +#define SUBPIC_BUF0_OFFSET 0x055C +#define SUBPIC_BUF1_OFFSET 0x0560 +#define SUBPIC_LC0_OFFSET 0x0564 +#define SUBPIC_LC1_OFFSET 0x0568 +#define SUBPIC_PITCH 0x056C +#define SUBPIC_BTN_HLI_COLCON 0x0570 +#define SUBPIC_BTN_HLI_Y_X_START 0x0574 +#define SUBPIC_BTN_HLI_Y_X_END 0x0578 +#define SUBPIC_PALETTE_INDEX 0x057C +#define SUBPIC_PALETTE_DATA 0x0580 +#define SUBPIC_H_ACCUM_INIT 0x0584 +#define SUBPIC_V_ACCUM_INIT 0x0588 + +#define CP_RB_BASE 0x0700 +#define CP_RB_CNTL 0x0704 +#define CP_RB_RPTR_ADDR 0x070C +#define CP_RB_RPTR 0x0710 +#define CP_RB_WPTR 0x0714 +#define CP_RB_WPTR_DELAY 0x0718 +#define CP_IB_BASE 0x0738 +#define CP_IB_BUFSZ 0x073C +#define CP_CSQ_CNTL 0x0740 +#define SCRATCH_UMSK 0x0770 +#define SCRATCH_ADDR 0x0774 +#define DMA_GUI_TABLE_ADDR 0x0780 +#define DMA_GUI_SRC_ADDR 0x0784 +#define DMA_GUI_DST_ADDR 0x0788 +#define DMA_GUI_COMMAND 0x078C +#define DMA_GUI_STATUS 0x0790 +#define DMA_GUI_ACT_DSCRPTR 0x0794 +#define DMA_VID_TABLE_ADDR 0x07A0 +#define DMA_VID_SRC_ADDR 0x07A4 +#define DMA_VID_DST_ADDR 0x07A8 +#define DMA_VID_COMMAND 0x07AC +#define DMA_VID_STATUS 0x07B0 +#define DMA_VID_ACT_DSCRPTR 0x07B4 +#define CP_ME_CNTL 0x07D0 +#define CP_ME_RAM_ADDR 0x07D4 +#define CP_ME_RAM_RADDR 0x07D8 +#define CP_ME_RAM_DATAH 0x07DC +#define CP_ME_RAM_DATAL 0x07E0 +#define CP_CSQ_ADDR 0x07F0 +#define CP_CSQ_DATA 0x07F4 +#define CP_CSQ_STAT 0x07F8 + +#define DISP_MISC_CNTL 0x0D00 +# define SOFT_RESET_GRPH_PP (1 << 0) +#define DAC_MACRO_CNTL 0x0D04 +#define DISP_PWR_MAN 0x0D08 +#define DISP_TEST_DEBUG_CNTL 0x0D10 +#define DISP_HW_DEBUG 0x0D14 +#define DAC_CRC_SIG1 0x0D18 +#define DAC_CRC_SIG2 0x0D1C + +/* first capture unit */ + +#define VID_BUFFER_CONTROL 0x0900 +#define CAP_INT_CNTL 0x0908 +#define CAP_INT_STATUS 0x090C +#define FCP_CNTL 0x0910 +#define CAP0_BUF0_OFFSET 0x0920 +#define CAP0_BUF1_OFFSET 0x0924 +#define CAP0_BUF0_EVEN_OFFSET 0x0928 +#define CAP0_BUF1_EVEN_OFFSET 0x092C +#define CAP0_BUF_PITCH 0x0930 +#define CAP0_V_WINDOW 0x0934 +#define CAP0_H_WINDOW 0x0938 +#define CAP0_VBI0_OFFSET 0x093C +#define CAP0_VBI1_OFFSET 0x0940 +#define CAP0_VBI_V_WINDOW 0x0944 +#define CAP0_VBI_H_WINDOW 0x0948 +#define CAP0_PORT_MODE_CNTL 0x094C +#define CAP0_TRIG_CNTL 0x0950 +#define CAP0_DEBUG 0x0954 +#define CAP0_CONFIG 0x0958 +# define CAP0_CONFIG_CONTINUOS 0x00000001 +# define CAP0_CONFIG_START_FIELD_EVEN 0x00000002 +# define CAP0_CONFIG_START_BUF_GET 0x00000004 +# define CAP0_CONFIG_START_BUF_SET 0x00000008 +# define CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 +# define CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 +# define CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 +# define CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 +# define CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 +# define CAP0_CONFIG_MIRROR_EN 0x00000200 +# define CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 +# define CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 +# define CAP0_CONFIG_ANC_DECODE_EN 0x00001000 +# define CAP0_CONFIG_VBI_EN 0x00002000 +# define CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 +# define CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 +# define CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 +# define CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 +# define CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 +# define CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 +# define CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 +# define CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 +# define CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 +# define CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 +# define CAP0_CONFIG_FORMAT_CCIR656 0x00800000 +# define CAP0_CONFIG_FORMAT_ZV 0x01000000 +# define CAP0_CONFIG_FORMAT_VIP 0x01800000 +# define CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 +# define CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 +# define CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 +# define CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 +# define CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 +# define CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 +#define CAP0_ANC_ODD_OFFSET 0x095C +#define CAP0_ANC_EVEN_OFFSET 0x0960 +#define CAP0_ANC_H_WINDOW 0x0964 +#define CAP0_VIDEO_SYNC_TEST 0x0968 +#define CAP0_ONESHOT_BUF_OFFSET 0x096C +#define CAP0_BUF_STATUS 0x0970 +#ifdef RAGE128 +#define CAP0_DWNSC_XRATIO 0x0978 +#define CAP0_XSHARPNESS 0x097C +#else +/* #define CAP0_DWNSC_XRATIO 0x0978 */ +/* #define CAP0_XSHARPNESS 0x097C */ +#endif +#define CAP0_VBI2_OFFSET 0x0980 +#define CAP0_VBI3_OFFSET 0x0984 +#define CAP0_ANC2_OFFSET 0x0988 +#define CAP0_ANC3_OFFSET 0x098C + +/* second capture unit */ + +#define CAP1_BUF0_OFFSET 0x0990 +#define CAP1_BUF1_OFFSET 0x0994 +#define CAP1_BUF0_EVEN_OFFSET 0x0998 +#define CAP1_BUF1_EVEN_OFFSET 0x099C + +#define CAP1_BUF_PITCH 0x09A0 +#define CAP1_V_WINDOW 0x09A4 +#define CAP1_H_WINDOW 0x09A8 +#define CAP1_VBI_ODD_OFFSET 0x09AC +#define CAP1_VBI_EVEN_OFFSET 0x09B0 +#define CAP1_VBI_V_WINDOW 0x09B4 +#define CAP1_VBI_H_WINDOW 0x09B8 +#define CAP1_PORT_MODE_CNTL 0x09BC +#define CAP1_TRIG_CNTL 0x09C0 +#define CAP1_DEBUG 0x09C4 +#define CAP1_CONFIG 0x09C8 +#define CAP1_ANC_ODD_OFFSET 0x09CC +#define CAP1_ANC_EVEN_OFFSET 0x09D0 +#define CAP1_ANC_H_WINDOW 0x09D4 +#define CAP1_VIDEO_SYNC_TEST 0x09D8 +#define CAP1_ONESHOT_BUF_OFFSET 0x09DC +#define CAP1_BUF_STATUS 0x09E0 +#define CAP1_DWNSC_XRATIO 0x09E8 +#define CAP1_XSHARPNESS 0x09EC + +#define DISP_MERGE_CNTL 0x0D60 +#define DISP_OUTPUT_CNTL 0x0D64 +# define DISP_DAC_SOURCE_MASK 0x03 +# define DISP_DAC_SOURCE_CRTC2 0x01 +#define DISP_LIN_TRANS_GRPH_A 0x0D80 +#define DISP_LIN_TRANS_GRPH_B 0x0D84 +#define DISP_LIN_TRANS_GRPH_C 0x0D88 +#define DISP_LIN_TRANS_GRPH_D 0x0D8C +#define DISP_LIN_TRANS_GRPH_E 0x0D90 +#define DISP_LIN_TRANS_GRPH_F 0x0D94 +#define DISP_LIN_TRANS_VID_A 0x0D98 +#define DISP_LIN_TRANS_VID_B 0x0D9C +#define DISP_LIN_TRANS_VID_C 0x0DA0 +#define DISP_LIN_TRANS_VID_D 0x0DA4 +#define DISP_LIN_TRANS_VID_E 0x0DA8 +#define DISP_LIN_TRANS_VID_F 0x0DAC +#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 +#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 +#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 +#define RMX_HORZ_PHASE 0x0DBC +#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 +#define DAC_BROAD_PULSE 0x0DC4 +#define DAC_SKEW_CLKS 0x0DC8 +#define DAC_INCR 0x0DCC +#define DAC_NEG_SYNC_LEVEL 0x0DD0 +#define DAC_POS_SYNC_LEVEL 0x0DD4 +#define DAC_BLANK_LEVEL 0x0DD8 +#define CLOCK_CNTL_INDEX 0x0008 +/* CLOCK_CNTL_INDEX bit constants */ +# define PLL_WR_EN 0x00000080 +# define PLL_DIV_SEL (3 << 8) +# define PLL2_DIV_SEL_MASK ~(3 << 8) +#define CLOCK_CNTL_DATA 0x000C +#define CP_RB_CNTL 0x0704 +#define CP_RB_BASE 0x0700 +#define CP_RB_RPTR_ADDR 0x070C +#define CP_RB_RPTR 0x0710 +#define CP_RB_WPTR 0x0714 +#define CP_RB_WPTR_DELAY 0x0718 +#define CP_IB_BASE 0x0738 +#define CP_IB_BUFSZ 0x073C +#define SCRATCH_REG0 0x15E0 +#define GUI_SCRATCH_REG0 0x15E0 +#define SCRATCH_REG1 0x15E4 +#define GUI_SCRATCH_REG1 0x15E4 +#define SCRATCH_REG2 0x15E8 +#define GUI_SCRATCH_REG2 0x15E8 +#define SCRATCH_REG3 0x15EC +#define GUI_SCRATCH_REG3 0x15EC +#define SCRATCH_REG4 0x15F0 +#define GUI_SCRATCH_REG4 0x15F0 +#define SCRATCH_REG5 0x15F4 +#define GUI_SCRATCH_REG5 0x15F4 +#define SCRATCH_UMSK 0x0770 +#define SCRATCH_ADDR 0x0774 +#define DP_BRUSH_FRGD_CLR 0x147C +#define DP_BRUSH_BKGD_CLR 0x1478 +#define DST_LINE_START 0x1600 +#define DST_LINE_END 0x1604 +#define SRC_OFFSET 0x15AC +#define SRC_PITCH 0x15B0 +#define SRC_TILE 0x1704 +#define SRC_PITCH_OFFSET 0x1428 +#define SRC_X 0x1414 +#define SRC_Y 0x1418 +#define DST_WIDTH_X 0x1588 +#define DST_HEIGHT_WIDTH_8 0x158C +#define SRC_X_Y 0x1590 +#define SRC_Y_X 0x1434 +#define DST_Y_X 0x1438 +#define DST_WIDTH_HEIGHT 0x1598 +#define DST_HEIGHT_WIDTH 0x143c +#define SRC_CLUT_ADDRESS 0x1780 +#define SRC_CLUT_DATA 0x1784 +#define SRC_CLUT_DATA_RD 0x1788 +#define HOST_DATA0 0x17C0 +#define HOST_DATA1 0x17C4 +#define HOST_DATA2 0x17C8 +#define HOST_DATA3 0x17CC +#define HOST_DATA4 0x17D0 +#define HOST_DATA5 0x17D4 +#define HOST_DATA6 0x17D8 +#define HOST_DATA7 0x17DC +#define HOST_DATA_LAST 0x17E0 +#define DP_SRC_ENDIAN 0x15D4 +#define DP_SRC_FRGD_CLR 0x15D8 +#define DP_SRC_BKGD_CLR 0x15DC +#define DP_WRITE_MASK 0x16cc +#define SC_LEFT 0x1640 +#define SC_RIGHT 0x1644 +#define SC_TOP 0x1648 +#define SC_BOTTOM 0x164C +#define SRC_SC_RIGHT 0x1654 +#define SRC_SC_BOTTOM 0x165C +#define DP_CNTL 0x16C0 +/* DP_CNTL bit constants */ +# define DST_X_RIGHT_TO_LEFT 0x00000000 +# define DST_X_LEFT_TO_RIGHT 0x00000001 +# define DST_Y_BOTTOM_TO_TOP 0x00000000 +# define DST_Y_TOP_TO_BOTTOM 0x00000002 +# define DST_X_MAJOR 0x00000000 +# define DST_Y_MAJOR 0x00000004 +# define DST_X_TILE 0x00000008 +# define DST_Y_TILE 0x00000010 +# define DST_LAST_PEL 0x00000020 +# define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 +# define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 +# define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 +# define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 +# define DST_BRES_SIGN 0x00000100 +# define DST_HOST_BIG_ENDIAN_EN 0x00000200 +# define DST_POLYLINE_NONLAST 0x00008000 +# define DST_RASTER_STALL 0x00010000 +# define DST_POLY_EDGE 0x00040000 +#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 +/* DP_CNTL_XDIR_YDIR_YMAJOR bit constants (short version of DP_CNTL) */ +# define DST_X_MAJOR_S 0x00000000 +# define DST_Y_MAJOR_S 0x00000001 +# define DST_Y_BOTTOM_TO_TOP_S 0x00000000 +# define DST_Y_TOP_TO_BOTTOM_S 0x00008000 +# define DST_X_RIGHT_TO_LEFT_S 0x00000000 +# define DST_X_LEFT_TO_RIGHT_S 0x80000000 +#define DP_DATATYPE 0x16C4 +/* DP_DATATYPE bit constants */ +# define DST_8BPP 0x00000002 +# define DST_15BPP 0x00000003 +# define DST_16BPP 0x00000004 +# define DST_24BPP 0x00000005 +# define DST_32BPP 0x00000006 +# define DST_8BPP_RGB332 0x00000007 +# define DST_8BPP_Y8 0x00000008 +# define DST_8BPP_RGB8 0x00000009 +# define DST_16BPP_VYUY422 0x0000000b +# define DST_16BPP_YVYU422 0x0000000c +# define DST_32BPP_AYUV444 0x0000000e +# define DST_16BPP_ARGB4444 0x0000000f +# define BRUSH_SOLIDCOLOR 0x00000d00 +# define SRC_MONO 0x00000000 +# define SRC_MONO_LBKGD 0x00010000 +# define SRC_DSTCOLOR 0x00030000 +# define BYTE_ORDER_MSB_TO_LSB 0x00000000 +# define BYTE_ORDER_LSB_TO_MSB 0x40000000 +# define DP_CONVERSION_TEMP 0x80000000 +# define HOST_BIG_ENDIAN_EN (1 << 29) +#define DP_MIX 0x16C8 +/* DP_MIX bit constants */ +# define DP_SRC_RECT 0x00000200 +# define DP_SRC_HOST 0x00000300 +# define DP_SRC_HOST_BYTEALIGN 0x00000400 +#define DP_WRITE_MSK 0x16CC +#define DP_XOP 0x17F8 +#define CLR_CMP_CLR_SRC 0x15C4 +#define CLR_CMP_CLR_DST 0x15C8 +#define CLR_CMP_CNTL 0x15C0 +/* CLR_CMP_CNTL bit constants */ +# define COMPARE_SRC_FALSE 0x00000000 +# define COMPARE_SRC_TRUE 0x00000001 +# define COMPARE_SRC_NOT_EQUAL 0x00000004 +# define COMPARE_SRC_EQUAL 0x00000005 +# define COMPARE_SRC_EQUAL_FLIP 0x00000007 +# define COMPARE_DST_FALSE 0x00000000 +# define COMPARE_DST_TRUE 0x00000100 +# define COMPARE_DST_NOT_EQUAL 0x00000400 +# define COMPARE_DST_EQUAL 0x00000500 +# define COMPARE_DESTINATION 0x00000000 +# define COMPARE_SOURCE 0x01000000 +# define COMPARE_SRC_AND_DST 0x02000000 +#define CLR_CMP_MSK 0x15CC +#define DSTCACHE_MODE 0x1710 +#define DSTCACHE_CTLSTAT 0x1714 +/* DSTCACHE_CTLSTAT bit constants */ +# define RB2D_DC_FLUSH (3 << 0) +# define RB2D_DC_FLUSH_ALL 0xf +# define RB2D_DC_BUSY (1 << 31) +#define DEFAULT_OFFSET 0x16e0 +#define DEFAULT_PITCH_OFFSET 0x16E0 +#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 +/* DEFAULT_SC_BOTTOM_RIGHT bit constants */ +# define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +# define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) +#define DP_GUI_MASTER_CNTL 0x146C +/* DP_GUI_MASTER_CNTL bit constants */ +# define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 +# define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 +# define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 +# define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 +# define GMC_SRC_CLIP_DEFAULT 0x00000000 +# define GMC_SRC_CLIP_LEAVE 0x00000004 +# define GMC_DST_CLIP_DEFAULT 0x00000000 +# define GMC_DST_CLIP_LEAVE 0x00000008 +# define GMC_BRUSH_8x8MONO 0x00000000 +# define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 +# define GMC_BRUSH_8x1MONO 0x00000020 +# define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 +# define GMC_BRUSH_1x8MONO 0x00000040 +# define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 +# define GMC_BRUSH_32x1MONO 0x00000060 +# define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 +# define GMC_BRUSH_32x32MONO 0x00000080 +# define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 +# define GMC_BRUSH_8x8COLOR 0x000000a0 +# define GMC_BRUSH_8x1COLOR 0x000000b0 +# define GMC_BRUSH_1x8COLOR 0x000000c0 +# define GMC_BRUSH_SOLID_COLOR 0x000000d0 +# define GMC_DST_8BPP 0x00000200 +# define GMC_DST_15BPP 0x00000300 +# define GMC_DST_16BPP 0x00000400 +# define GMC_DST_24BPP 0x00000500 +# define GMC_DST_32BPP 0x00000600 +# define GMC_DST_8BPP_RGB332 0x00000700 +# define GMC_DST_8BPP_Y8 0x00000800 +# define GMC_DST_8BPP_RGB8 0x00000900 +# define GMC_DST_16BPP_VYUY422 0x00000b00 +# define GMC_DST_16BPP_YVYU422 0x00000c00 +# define GMC_DST_32BPP_AYUV444 0x00000e00 +# define GMC_DST_16BPP_ARGB4444 0x00000f00 +# define GMC_SRC_MONO 0x00000000 +# define GMC_SRC_MONO_LBKGD 0x00001000 +# define GMC_SRC_DSTCOLOR 0x00003000 +# define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 +# define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 +# define GMC_DP_CONVERSION_TEMP_9300 0x00008000 +# define GMC_DP_CONVERSION_TEMP_6500 0x00000000 +# define GMC_DP_SRC_RECT 0x02000000 +# define GMC_DP_SRC_HOST 0x03000000 +# define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 +# define GMC_3D_FCN_EN_CLR 0x00000000 +# define GMC_3D_FCN_EN_SET 0x08000000 +# define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 +# define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 +# define GMC_AUX_CLIP_LEAVE 0x00000000 +# define GMC_AUX_CLIP_CLEAR 0x20000000 +# define GMC_WRITE_MASK_LEAVE 0x00000000 +# define GMC_WRITE_MASK_SET 0x40000000 +# define GMC_CLR_CMP_CNTL_DIS (1 << 28) +# define GMC_SRC_DATATYPE_COLOR (3 << 12) +# define ROP3_S 0x00cc0000 +# define ROP3_SRCCOPY 0x00cc0000 +# define ROP3_P 0x00f00000 +# define ROP3_PATCOPY 0x00f00000 +# define DP_SRC_SOURCE_MASK (7 << 24) +# define GMC_BRUSH_NONE (15 << 4) +# define DP_SRC_SOURCE_MEMORY (2 << 24) +# define GMC_BRUSH_SOLIDCOLOR 0x000000d0 +#define SC_TOP_LEFT 0x16EC +#define SC_BOTTOM_RIGHT 0x16F0 +#define SRC_SC_BOTTOM_RIGHT 0x16F4 +#define RB2D_DSTCACHE_CTLSTAT 0x342C +#define RB2D_DSTCACHE_MODE 0x3428 + +#define BASE_CODE 0x0f0b +#define RADEON_BIOS_0_SCRATCH 0x0010 +#define RADEON_BIOS_1_SCRATCH 0x0014 +#define RADEON_BIOS_2_SCRATCH 0x0018 +#define RADEON_BIOS_3_SCRATCH 0x001c +#define RADEON_BIOS_4_SCRATCH 0x0020 +#define RADEON_BIOS_5_SCRATCH 0x0024 +#define RADEON_BIOS_6_SCRATCH 0x0028 +#define RADEON_BIOS_7_SCRATCH 0x002c + + +#define CLK_PIN_CNTL 0x0001 +#define PPLL_CNTL 0x0002 +# define PPLL_RESET (1 << 0) +# define PPLL_SLEEP (1 << 1) +# define PPLL_ATOMIC_UPDATE_EN (1 << 16) +# define PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define PPLL_REF_DIV 0x0003 +# define PPLL_REF_DIV_MASK 0x03ff +# define PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define PPLL_DIV_0 0x0004 +#define PPLL_DIV_1 0x0005 +#define PPLL_DIV_2 0x0006 +#define PPLL_DIV_3 0x0007 +#define VCLK_ECP_CNTL 0x0008 +#define HTOTAL_CNTL 0x0009 +#define HTOTAL2_CNTL 0x002e /* PLL */ +#define M_SPLL_REF_FB_DIV 0x000a +#define AGP_PLL_CNTL 0x000b +#define SPLL_CNTL 0x000c +#define SCLK_CNTL 0x000d +#define MPLL_CNTL 0x000e +#define MCLK_CNTL 0x0012 +/* MCLK_CNTL bit constants */ +# define FORCEON_MCLKA (1 << 16) +# define FORCEON_MCLKB (1 << 17) +# define FORCEON_YCLKA (1 << 18) +# define FORCEON_YCLKB (1 << 19) +# define FORCEON_MC (1 << 20) +# define FORCEON_AIC (1 << 21) +#define PLL_TEST_CNTL 0x0013 +#define P2PLL_CNTL 0x002a /* P2PLL */ +# define P2PLL_RESET (1 << 0) +# define P2PLL_SLEEP (1 << 1) +# define P2PLL_ATOMIC_UPDATE_EN (1 << 16) +# define P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define P2PLL_DIV_0 0x002c +# define P2PLL_FB0_DIV_MASK 0x07ff +# define P2PLL_POST0_DIV_MASK 0x00070000 +#define P2PLL_REF_DIV 0x002B /* PLL */ +# define P2PLL_REF_DIV_MASK 0x03ff +# define P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ + +/* masks */ + +#define CONFIG_MEMSIZE_MASK 0x1f000000 +#define MEM_CFG_TYPE 0x40000000 +#define DST_OFFSET_MASK 0x003fffff +#define DST_PITCH_MASK 0x3fc00000 +#define DEFAULT_TILE_MASK 0xc0000000 +#define PPLL_DIV_SEL_MASK 0x00000300 +#define PPLL_FB3_DIV_MASK 0x000007ff +#define PPLL_POST3_DIV_MASK 0x00070000 + +#define GUI_ACTIVE 0x80000000 + +/* GEN_RESET_CNTL bit constants */ +#define SOFT_RESET_GUI 0x00000001 +#define SOFT_RESET_VCLK 0x00000100 +#define SOFT_RESET_PCLK 0x00000200 +#define SOFT_RESET_ECP 0x00000400 +#define SOFT_RESET_DISPENG_XCLK 0x00000800 + +/* RAGE THEATER REGISTERS */ + +#define DMA_VIPH0_COMMAND 0x0A00 +#define DMA_VIPH1_COMMAND 0x0A04 +#define DMA_VIPH2_COMMAND 0x0A08 +#define DMA_VIPH3_COMMAND 0x0A0C +#define DMA_VIPH_STATUS 0x0A10 +#define DMA_VIPH_CHUNK_0 0x0A18 +#define DMA_VIPH_CHUNK_1_VAL 0x0A1C +#define DMA_VIP0_TABLE_ADDR 0x0A20 +#define DMA_VIPH0_ACTIVE 0x0A24 +#define DMA_VIP1_TABLE_ADDR 0x0A30 +#define DMA_VIPH1_ACTIVE 0x0A34 +#define DMA_VIP2_TABLE_ADDR 0x0A40 +#define DMA_VIPH2_ACTIVE 0x0A44 +#define DMA_VIP3_TABLE_ADDR 0x0A50 +#define DMA_VIPH3_ACTIVE 0x0A54 +#define DMA_VIPH_ABORT 0x0A88 + +#define VIPH_CH0_DATA 0x0c00 +#define VIPH_CH1_DATA 0x0c04 +#define VIPH_CH2_DATA 0x0c08 +#define VIPH_CH3_DATA 0x0c0c +#define VIPH_CH0_ADDR 0x0c10 +#define VIPH_CH1_ADDR 0x0c14 +#define VIPH_CH2_ADDR 0x0c18 +#define VIPH_CH3_ADDR 0x0c1c +#define VIPH_CH0_SBCNT 0x0c20 +#define VIPH_CH1_SBCNT 0x0c24 +#define VIPH_CH2_SBCNT 0x0c28 +#define VIPH_CH3_SBCNT 0x0c2c +#define VIPH_CH0_ABCNT 0x0c30 +#define VIPH_CH1_ABCNT 0x0c34 +#define VIPH_CH2_ABCNT 0x0c38 +#define VIPH_CH3_ABCNT 0x0c3c +#define VIPH_CONTROL 0x0c40 +#define VIPH_DV_LAT 0x0c44 +#define VIPH_BM_CHUNK 0x0c48 +#define VIPH_DV_INT 0x0c4c +#define VIPH_TIMEOUT_STAT 0x0c50 + +#define VIPH_REG_DATA 0x0084 +#define VIPH_REG_ADDR 0x0080 + +/* Address Space Rage Theatre Registers (VIP Access) */ +#define VIP_VIP_VENDOR_DEVICE_ID 0x0000 +#define VIP_VIP_SUB_VENDOR_DEVICE_ID 0x0004 +#define VIP_VIP_COMMAND_STATUS 0x0008 +#define VIP_VIP_REVISION_ID 0x000c +#define VIP_HW_DEBUG 0x0010 +#define VIP_SW_SCRATCH 0x0014 +#define VIP_I2C_CNTL_0 0x0020 +#define VIP_I2C_CNTL_1 0x0024 +#define VIP_I2C_DATA 0x0028 +#define VIP_INT_CNTL 0x002c +#define VIP_GPIO_INOUT 0x0030 +#define VIP_GPIO_CNTL 0x0034 +#define VIP_CLKOUT_GPIO_CNTL 0x0038 +#define VIP_RIPINTF_PORT_CNTL 0x003c +#define VIP_ADC_CNTL 0x0400 +#define VIP_ADC_DEBUG 0x0404 +#define VIP_STANDARD_SELECT 0x0408 +#define VIP_THERMO2BIN_STATUS 0x040c +#define VIP_COMB_CNTL0 0x0440 +#define VIP_COMB_CNTL1 0x0444 +#define VIP_COMB_CNTL2 0x0448 +#define VIP_COMB_LINE_LENGTH 0x044c +#define VIP_NOISE_CNTL0 0x0450 +#define VIP_HS_PLINE 0x0480 +#define VIP_HS_DTOINC 0x0484 +#define VIP_HS_PLLGAIN 0x0488 +#define VIP_HS_MINMAXWIDTH 0x048c +#define VIP_HS_GENLOCKDELAY 0x0490 +#define VIP_HS_WINDOW_LIMIT 0x0494 +#define VIP_HS_WINDOW_OC_SPEED 0x0498 +#define VIP_HS_PULSE_WIDTH 0x049c +#define VIP_HS_PLL_ERROR 0x04a0 +#define VIP_HS_PLL_FS_PATH 0x04a4 +#define VIP_SG_BLACK_GATE 0x04c0 +#define VIP_SG_SYNCTIP_GATE 0x04c4 +#define VIP_SG_UVGATE_GATE 0x04c8 +#define VIP_LP_AGC_CLAMP_CNTL0 0x0500 +#define VIP_LP_AGC_CLAMP_CNTL1 0x0504 +#define VIP_LP_BRIGHTNESS 0x0508 +#define VIP_LP_CONTRAST 0x050c +#define VIP_LP_SLICE_LIMIT 0x0510 +#define VIP_LP_WPA_CNTL0 0x0514 +#define VIP_LP_WPA_CNTL1 0x0518 +#define VIP_LP_BLACK_LEVEL 0x051c +#define VIP_LP_SLICE_LEVEL 0x0520 +#define VIP_LP_SYNCTIP_LEVEL 0x0524 +#define VIP_LP_VERT_LOCKOUT 0x0528 +#define VIP_VS_DETECTOR_CNTL 0x0540 +#define VIP_VS_BLANKING_CNTL 0x0544 +#define VIP_VS_FIELD_ID_CNTL 0x0548 +#define VIP_VS_COUNTER_CNTL 0x054c +#define VIP_VS_FRAME_TOTAL 0x0550 +#define VIP_VS_LINE_COUNT 0x0554 +#define VIP_CP_PLL_CNTL0 0x0580 +#define VIP_CP_PLL_CNTL1 0x0584 +#define VIP_CP_HUE_CNTL 0x0588 +#define VIP_CP_BURST_GAIN 0x058c +#define VIP_CP_AGC_CNTL 0x0590 +#define VIP_CP_ACTIVE_GAIN 0x0594 +#define VIP_CP_PLL_STATUS0 0x0598 +#define VIP_CP_PLL_STATUS1 0x059c +#define VIP_CP_PLL_STATUS2 0x05a0 +#define VIP_CP_PLL_STATUS3 0x05a4 +#define VIP_CP_PLL_STATUS4 0x05a8 +#define VIP_CP_PLL_STATUS5 0x05ac +#define VIP_CP_PLL_STATUS6 0x05b0 +#define VIP_CP_PLL_STATUS7 0x05b4 +#define VIP_CP_DEBUG_FORCE 0x05b8 +#define VIP_CP_VERT_LOCKOUT 0x05bc +#define VIP_H_ACTIVE_WINDOW 0x05c0 +#define VIP_V_ACTIVE_WINDOW 0x05c4 +#define VIP_H_VBI_WINDOW 0x05c8 +#define VIP_V_VBI_WINDOW 0x05cc +#define VIP_VBI_CONTROL 0x05d0 +#define VIP_DECODER_DEBUG_CNTL 0x05d4 +#define VIP_SINGLE_STEP_DATA 0x05d8 +#define VIP_MASTER_CNTL 0x0040 +#define VIP_RGB_CNTL 0x0048 +#define VIP_CLKOUT_CNTL 0x004c +#define VIP_SYNC_CNTL 0x0050 +#define VIP_I2C_CNTL 0x0054 +#define VIP_HTOTAL 0x0080 +#define VIP_HDISP 0x0084 +#define VIP_HSIZE 0x0088 +#define VIP_HSTART 0x008c +#define VIP_HCOUNT 0x0090 +#define VIP_VTOTAL 0x0094 +#define VIP_VDISP 0x0098 +#define VIP_VCOUNT 0x009c +#define VIP_VFTOTAL 0x00a0 +#define VIP_DFCOUNT 0x00a4 +#define VIP_DFRESTART 0x00a8 +#define VIP_DHRESTART 0x00ac +#define VIP_DVRESTART 0x00b0 +#define VIP_SYNC_SIZE 0x00b4 +#define VIP_TV_PLL_FINE_CNTL 0x00b8 +#define VIP_CRT_PLL_FINE_CNTL 0x00bc +#define VIP_TV_PLL_CNTL 0x00c0 +#define VIP_CRT_PLL_CNTL 0x00c4 +#define VIP_PLL_CNTL0 0x00c8 +#define VIP_PLL_TEST_CNTL 0x00cc +#define VIP_CLOCK_SEL_CNTL 0x00d0 +#define VIP_VIN_PLL_CNTL 0x00d4 +#define VIP_VIN_PLL_FINE_CNTL 0x00d8 +#define VIP_AUD_PLL_CNTL 0x00e0 +#define VIP_AUD_PLL_FINE_CNTL 0x00e4 +#define VIP_AUD_CLK_DIVIDERS 0x00e8 +#define VIP_AUD_DTO_INCREMENTS 0x00ec +#define VIP_L54_PLL_CNTL 0x00f0 +#define VIP_L54_PLL_FINE_CNTL 0x00f4 +#define VIP_L54_DTO_INCREMENTS 0x00f8 +#define VIP_PLL_CNTL1 0x00fc +#define VIP_FRAME_LOCK_CNTL 0x0100 +#define VIP_SYNC_LOCK_CNTL 0x0104 +#define VIP_TVO_SYNC_PAT_ACCUM 0x0108 +#define VIP_TVO_SYNC_THRESHOLD 0x010c +#define VIP_TVO_SYNC_PAT_EXPECT 0x0110 +#define VIP_DELAY_ONE_MAP_A 0x0114 +#define VIP_DELAY_ONE_MAP_B 0x0118 +#define VIP_DELAY_ZERO_MAP_A 0x011c +#define VIP_DELAY_ZERO_MAP_B 0x0120 +#define VIP_TVO_DATA_DELAY_A 0x0140 +#define VIP_TVO_DATA_DELAY_B 0x0144 +#define VIP_HOST_READ_DATA 0x0180 +#define VIP_HOST_WRITE_DATA 0x0184 +#define VIP_HOST_RD_WT_CNTL 0x0188 +#define VIP_VSCALER_CNTL1 0x01c0 +#define VIP_TIMING_CNTL 0x01c4 +#define VIP_VSCALER_CNTL2 0x01c8 +#define VIP_Y_FALL_CNTL 0x01cc +#define VIP_Y_RISE_CNTL 0x01d0 +#define VIP_Y_SAW_TOOTH_CNTL 0x01d4 +#define VIP_UPSAMP_AND_GAIN_CNTL 0x01e0 +#define VIP_GAIN_LIMIT_SETTINGS 0x01e4 +#define VIP_LINEAR_GAIN_SETTINGS 0x01e8 +#define VIP_MODULATOR_CNTL1 0x0200 +#define VIP_MODULATOR_CNTL2 0x0204 +#define VIP_MV_MODE_CNTL 0x0208 +#define VIP_MV_STRIPE_CNTL 0x020c +#define VIP_MV_LEVEL_CNTL1 0x0210 +#define VIP_MV_LEVEL_CNTL2 0x0214 +#define VIP_PRE_DAC_MUX_CNTL 0x0240 +#define VIP_TV_DAC_CNTL 0x0280 +#define VIP_CRC_CNTL 0x02c0 +#define VIP_VIDEO_PORT_SIG 0x02c4 +#define VIP_VBI_CC_CNTL 0x02c8 +#define VIP_VBI_EDS_CNTL 0x02cc +#define VIP_VBI_20BIT_CNTL 0x02d0 +#define VIP_VBI_DTO_CNTL 0x02d4 +#define VIP_VBI_LEVEL_CNTL 0x02d8 +#define VIP_UV_ADR 0x0300 +#define VIP_MV_STATUS 0x0330 +#define VIP_UPSAMP_COEFF0_0 0x0340 +#define VIP_UPSAMP_COEFF0_1 0x0344 +#define VIP_UPSAMP_COEFF0_2 0x0348 +#define VIP_UPSAMP_COEFF1_0 0x034c +#define VIP_UPSAMP_COEFF1_1 0x0350 +#define VIP_UPSAMP_COEFF1_2 0x0354 +#define VIP_UPSAMP_COEFF2_0 0x0358 +#define VIP_UPSAMP_COEFF2_1 0x035c +#define VIP_UPSAMP_COEFF2_2 0x0360 +#define VIP_UPSAMP_COEFF3_0 0x0364 +#define VIP_UPSAMP_COEFF3_1 0x0368 +#define VIP_UPSAMP_COEFF3_2 0x036c +#define VIP_UPSAMP_COEFF4_0 0x0370 +#define VIP_UPSAMP_COEFF4_1 0x0374 +#define VIP_UPSAMP_COEFF4_2 0x0378 +#define VIP_TV_DTO_INCREMENTS 0x0390 +#define VIP_CRT_DTO_INCREMENTS 0x0394 +#define VIP_VSYNC_DIFF_CNTL 0x03a0 +#define VIP_VSYNC_DIFF_LIMITS 0x03a4 +#define VIP_VSYNC_DIFF_RD_DATA 0x03a8 +#define VIP_SCALER_IN_WINDOW 0x0618 +#define VIP_SCALER_OUT_WINDOW 0x061c +#define VIP_H_SCALER_CONTROL 0x0600 +#define VIP_V_SCALER_CONTROL 0x0604 +#define VIP_V_DEINTERLACE_CONTROL 0x0608 +#define VIP_VBI_SCALER_CONTROL 0x060c +#define VIP_DVS_PORT_CTRL 0x0610 +#define VIP_DVS_PORT_READBACK 0x0614 +#define VIP_FIFOA_CONFIG 0x0800 +#define VIP_FIFOB_CONFIG 0x0804 +#define VIP_FIFOC_CONFIG 0x0808 +#define VIP_SPDIF_PORT_CNTL 0x080c +#define VIP_SPDIF_CHANNEL_STAT 0x0810 +#define VIP_SPDIF_AC3_PREAMBLE 0x0814 +#define VIP_I2S_TRANSMIT_CNTL 0x0818 +#define VIP_I2S_RECEIVE_CNTL 0x081c +#define VIP_SPDIF_TX_CNT_REG 0x0820 +#define VIP_IIS_TX_CNT_REG 0x0824 + +/* Status defines */ +#define VIP_BUSY 0 +#define VIP_IDLE 1 +#define VIP_RESET 2 + +#define VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 +#define VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 +#define VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 +#define TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 + +#define RT_ATI_ID 0x4D541002 + +/* Register/Field values: */ +#define RT_COMP0 0x0 +#define RT_COMP1 0x1 +#define RT_COMP2 0x2 +#define RT_YF_COMP3 0x3 +#define RT_YR_COMP3 0x4 +#define RT_YCF_COMP4 0x5 +#define RT_YCR_COMP4 0x6 + +/* Video standard defines */ +#define RT_NTSC 0x0 +#define RT_PAL 0x1 +#define RT_SECAM 0x2 +#define extNONE 0x0000 +#define extNTSC 0x0100 +#define extRsvd 0x0200 +#define extPAL 0x0300 +#define extPAL_M 0x0400 +#define extPAL_N 0x0500 +#define extSECAM 0x0600 +#define extPAL_NCOMB 0x0700 +#define extNTSC_J 0x0800 +#define extNTSC_443 0x0900 +#define extPAL_BGHI 0x0A00 +#define extPAL_60 0x0B00 + /* these are used in MSP3430 */ +#define extPAL_DK1 0x0C00 +#define extPAL_AUTO 0x0D00 + +#define RT_FREF_2700 6 +#define RT_FREF_2950 5 + +#define RT_COMPOSITE 0x0 +#define RT_SVIDEO 0x1 + +#define RT_NORM_SHARPNESS 0x03 +#define RT_HIGH_SHARPNESS 0x0F + +#define RT_HUE_PAL_DEF 0x00 + +#define RT_DECINTERLACED 0x1 +#define RT_DECNONINTERLACED 0x0 + +#define NTSC_LINES 525 +#define PAL_SECAM_LINES 625 + +#define RT_ASYNC_ENABLE 0x0 +#define RT_ASYNC_DISABLE 0x1 +#define RT_ASYNC_RESET 0x1 + +#define RT_VINRST_ACTIVE 0x0 +#define RT_VINRST_RESET 0x1 +#define RT_L54RST_RESET 0x1 + +#define RT_REF_CLK 0x0 +#define RT_PLL_VIN_CLK 0x1 + +#define RT_VIN_ASYNC_RST 0x20 +#define RT_DVS_ASYNC_RST 0x80 + +#define RT_ADC_ENABLE 0x0 +#define RT_ADC_DISABLE 0x1 + +#define RT_DVSDIR_IN 0x0 +#define RT_DVSDIR_OUT 0x1 + +#define RT_DVSCLK_HIGH 0x0 +#define RT_DVSCLK_LOW 0x1 + +#define RT_DVSCLK_SEL_8FS 0x0 +#define RT_DVSCLK_SEL_27MHZ 0x1 + +#define RT_DVS_CONTSTREAM 0x1 +#define RT_DVS_NONCONTSTREAM 0x0 + +#define RT_DVSDAT_HIGH 0x0 +#define RT_DVSDAT_LOW 0x1 + +#define RT_ADC_CNTL_DEFAULT 0x03252338 + +/* COMB_CNTL0 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_NTSCM_COMB_CNTL0_SVIDEO 0x48540000 + +#define RT_PAL_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_PAL_COMB_CNTL0_SVIDEO 0x40348090 + +#define RT_SECAM_COMB_CNTL0_COMPOSITE 0xD0108090 /* instead of orig 0xD0088090 - eric*/ +#define RT_SECAM_COMB_CNTL0_SVIDEO 0x50148090 + +#define RT_PALN_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_PALN_COMB_CNTL0_SVIDEO 0x40348090 + +#define RT_PALM_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_PALM_COMB_CNTL0_SVIDEO 0x40348090 +/* End of filter settings. */ + +/* COMB_CNTL1 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_NTSCM_COMB_CNTL1_SVIDEO 0x00000081 + +#define RT_PAL_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_PAL_COMB_CNTL1_SVIDEO 0x000000A1 + +#define RT_SECAM_COMB_CNTL1_COMPOSITE 0x00000091 +#define RT_SECAM_COMB_CNTL1_SVIDEO 0x00000081 + +#define RT_PALN_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_PALN_COMB_CNTL1_SVIDEO 0x000000A1 + +#define RT_PALM_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_PALM_COMB_CNTL1_SVIDEO 0x000000A1 +/* End of filter settings. */ + +/* COMB_CNTL2 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_CNTL2_COMPOSITE 0x16161010 +#define RT_NTSCM_COMB_CNTL2_SVIDEO 0xFFFFFFFF + +#define RT_PAL_COMB_CNTL2_COMPOSITE 0x06080102 /* instead of 0x16161010 - Ivo */ +#define RT_PAL_COMB_CNTL2_SVIDEO 0x06080102 + +#define RT_SECAM_COMB_CNTL2_COMPOSITE 0xffffffff /* instead of 0x06080102 - eric */ +#define RT_SECAM_COMB_CNTL2_SVIDEO 0x06080102 + +#define RT_PALN_COMB_CNTL2_COMPOSITE 0x06080102 +#define RT_PALN_COMB_CNTL2_SVIDEO 0x06080102 + +#define RT_PALM_COMB_CNTL2_COMPOSITE 0x06080102 +#define RT_PALM_COMB_CNTL2_SVIDEO 0x06080102 +/* End of filter settings. */ + +/* COMB_LINE_LENGTH FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_LENGTH_COMPOSITE 0x0718038A +#define RT_NTSCM_COMB_LENGTH_SVIDEO 0x0718038A + +#define RT_PAL_COMB_LENGTH_COMPOSITE 0x08DA046B +#define RT_PAL_COMB_LENGTH_SVIDEO 0x08DA046B + +#define RT_SECAM_COMB_LENGTH_COMPOSITE 0x08DA046A +#define RT_SECAM_COMB_LENGTH_SVIDEO 0x08DA046A + +#define RT_PALN_COMB_LENGTH_COMPOSITE 0x07260391 +#define RT_PALN_COMB_LENGTH_SVIDEO 0x07260391 + +#define RT_PALM_COMB_LENGTH_COMPOSITE 0x07160389 +#define RT_PALM_COMB_LENGTH_SVIDEO 0x07160389 +/* End of filter settings. */ + +/* LP_AGC_CLAMP_CNTL0 */ +#define RT_NTSCM_SYNCTIP_REF0 0x00000037 +#define RT_NTSCM_SYNCTIP_REF1 0x00000029 +#define RT_NTSCM_CLAMP_REF 0x0000003B +#define RT_NTSCM_PEAKWHITE 0x000000FF +#define RT_NTSCM_VBI_PEAKWHITE 0x000000C2 + +#define RT_NTSCM_WPA_THRESHOLD 0x00000406 +#define RT_NTSCM_WPA_TRIGGER_LO 0x000000B3 + +#define RT_NTSCM_WPA_TRIGGER_HIGH 0x0000021B + +#define RT_NTSCM_LP_LOCKOUT_START 0x00000206 +#define RT_NTSCM_LP_LOCKOUT_END 0x00000021 +#define RT_NTSCM_CH_DTO_INC 0x00400000 +#define RT_NTSCM_CH_PLL_SGAIN 0x00000001 +#define RT_NTSCM_CH_PLL_FGAIN 0x00000002 + +#define RT_NTSCM_CR_BURST_GAIN 0x0000007A +#define RT_NTSCM_CB_BURST_GAIN 0x000000AC + +#define RT_NTSCM_CH_HEIGHT 0x000000CD +#define RT_NTSCM_CH_KILL_LEVEL 0x000000C0 +#define RT_NTSCM_CH_AGC_ERROR_LIM 0x00000002 +#define RT_NTSCM_CH_AGC_FILTER_EN 0x00000000 +#define RT_NTSCM_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_NTSCM_CRDR_ACTIVE_GAIN 0x0000007A +#define RT_NTSCM_CBDB_ACTIVE_GAIN 0x000000AC + +#define RT_NTSCM_VERT_LOCKOUT_START 0x00000207 +#define RT_NTSCM_VERT_LOCKOUT_END 0x0000000E + +#define RT_NTSCJ_SYNCTIP_REF0 0x00000004 +#define RT_NTSCJ_SYNCTIP_REF1 0x00000012 +#define RT_NTSCJ_CLAMP_REF 0x0000003B +#define RT_NTSCJ_PEAKWHITE 0x000000CB +#define RT_NTSCJ_VBI_PEAKWHITE 0x000000C2 +#define RT_NTSCJ_WPA_THRESHOLD 0x000004B0 +#define RT_NTSCJ_WPA_TRIGGER_LO 0x000000B4 +#define RT_NTSCJ_WPA_TRIGGER_HIGH 0x0000021C +#define RT_NTSCJ_LP_LOCKOUT_START 0x00000206 +#define RT_NTSCJ_LP_LOCKOUT_END 0x00000021 + +#define RT_NTSCJ_CR_BURST_GAIN 0x00000071 +#define RT_NTSCJ_CB_BURST_GAIN 0x0000009F +#define RT_NTSCJ_CH_HEIGHT 0x000000CD +#define RT_NTSCJ_CH_KILL_LEVEL 0x000000C0 +#define RT_NTSCJ_CH_AGC_ERROR_LIM 0x00000002 +#define RT_NTSCJ_CH_AGC_FILTER_EN 0x00000000 +#define RT_NTSCJ_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_NTSCJ_CRDR_ACTIVE_GAIN 0x00000071 +#define RT_NTSCJ_CBDB_ACTIVE_GAIN 0x0000009F +#define RT_NTSCJ_VERT_LOCKOUT_START 0x00000207 +#define RT_NTSCJ_VERT_LOCKOUT_END 0x0000000E + +#define RT_PAL_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ +#define RT_PAL_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ +#define RT_PAL_CLAMP_REF 0x0000003B +#define RT_PAL_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ +#define RT_PAL_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ +#define RT_PAL_WPA_THRESHOLD 0x59C /* instead of 0x000006A4 - Ivo */ + +#define RT_PAL_WPA_TRIGGER_LO 0x00000096 +#define RT_PAL_WPA_TRIGGER_HIGH 0x000001C2 +#define RT_PAL_LP_LOCKOUT_START 0x00000263 +#define RT_PAL_LP_LOCKOUT_END 0x0000002C + +#define RT_PAL_CH_DTO_INC 0x00400000 +#define RT_PAL_CH_PLL_SGAIN 1 /* instead of 0x00000002 - Ivo */ +#define RT_PAL_CH_PLL_FGAIN 2 /* instead of 0x00000001 - Ivo */ +#define RT_PAL_CR_BURST_GAIN 0x0000007A +#define RT_PAL_CB_BURST_GAIN 0x000000AB +#define RT_PAL_CH_HEIGHT 0x0000009C +#define RT_PAL_CH_KILL_LEVEL 4 /* instead of 0x00000090 - Ivo */ +#define RT_PAL_CH_AGC_ERROR_LIM 1 /* instead of 0x00000002 - Ivo */ +#define RT_PAL_CH_AGC_FILTER_EN 1 /* instead of 0x00000000 - Ivo */ +#define RT_PAL_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_PAL_CRDR_ACTIVE_GAIN 0x9E /* instead of 0x0000007A - Ivo */ +#define RT_PAL_CBDB_ACTIVE_GAIN 0xDF /* instead of 0x000000AB - Ivo */ +#define RT_PAL_VERT_LOCKOUT_START 0x00000269 +#define RT_PAL_VERT_LOCKOUT_END 0x00000012 + +#define RT_SECAM_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ +#define RT_SECAM_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ +#define RT_SECAM_CLAMP_REF 0x0000003B +#define RT_SECAM_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ +#define RT_SECAM_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ +#define RT_SECAM_WPA_THRESHOLD 0x57A /* instead of 0x6A4, instead of 0x0000059C is Ivo's value , -eric*/ + +#define RT_SECAM_WPA_TRIGGER_LO 0x96 /* instead of 0x0000026B - eric */ +#define RT_SECAM_WPA_TRIGGER_HIGH 0x000001C2 +#define RT_SECAM_LP_LOCKOUT_START 0x263 /* instead of 0x0000026B - eric */ +#define RT_SECAM_LP_LOCKOUT_END 0x2b /* instead of 0x0000002C -eric */ + +#define RT_SECAM_CH_DTO_INC 0x003E7A28 +#define RT_SECAM_CH_PLL_SGAIN 0x4 /* instead of 0x00000006 -Volodya */ +#define RT_SECAM_CH_PLL_FGAIN 0x7 /* instead of 0x00000006 -Volodya */ + +#define RT_SECAM_CR_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ +#define RT_SECAM_CB_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ +#define RT_SECAM_CH_HEIGHT 0x00000066 +#define RT_SECAM_CH_KILL_LEVEL 0x00000060 +#define RT_SECAM_CH_AGC_ERROR_LIM 0x00000003 +#define RT_SECAM_CH_AGC_FILTER_EN 0x00000000 +#define RT_SECAM_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_SECAM_CRDR_ACTIVE_GAIN 0x11B /* instead of 0x00000200 - eric */ +#define RT_SECAM_CBDB_ACTIVE_GAIN 0x15A /* instead of 0x00000200 - eric */ +#define RT_SECAM_VERT_LOCKOUT_START 0x00000269 +#define RT_SECAM_VERT_LOCKOUT_END 0x00000012 + +#define RT_PAL_VS_FIELD_BLANK_END 0x2A /* instead of 0x0000002C - Ivo*/ +#define RT_NTSCM_VS_FIELD_BLANK_END 0x0000000A + +#define RT_NTSCM_FIELD_IDLOCATION 0x00000105 +#define RT_PAL_FIELD_IDLOCATION 0x00000137 + +#define RT_NTSCM_H_ACTIVE_START 0x00000070 +#define RT_NTSCM_H_ACTIVE_END 0x00000363 + +#define RT_PAL_H_ACTIVE_START 0x0000009A +#define RT_PAL_H_ACTIVE_END 0x00000439 + +#define RT_NTSCM_V_ACTIVE_START ((22-4)*2+1) +#define RT_NTSCM_V_ACTIVE_END ((22+240-4)*2+1) + +#define RT_PAL_V_ACTIVE_START 0x2E /* instead of 0x00000023 (Same as SECAM) - Ivo */ +#define RT_PAL_V_ACTIVE_END 0x269 /* instead of 0x00000262 - Ivo */ + +/* VBI */ +#define RT_NTSCM_H_VBI_WIND_START 0x00000049 +#define RT_NTSCM_H_VBI_WIND_END 0x00000366 + +#define RT_PAL_H_VBI_WIND_START 0x00000084 +#define RT_PAL_H_VBI_WIND_END 0x0000041F + +#define RT_NTSCM_V_VBI_WIND_START fld_V_VBI_WIND_START_def +#define RT_NTSCM_V_VBI_WIND_END fld_V_VBI_WIND_END_def + +#define RT_PAL_V_VBI_WIND_START 0x8 /* instead of 0x0000000B - Ivo */ +#define RT_PAL_V_VBI_WIND_END 0x2D /* instead of 0x00000022 - Ivo */ + +#define RT_VBI_CAPTURE_EN 0x00000001 /* Enable */ +#define RT_VBI_CAPTURE_DIS 0x00000000 /* Disable */ +#define RT_RAW_CAPTURE 0x00000002 /* Use raw Video Capture. */ + +#define RT_NTSCM_VSYNC_INT_TRIGGER 0x2AA +#define RT_PALSEM_VSYNC_INT_TRIGGER 0x353 + +#define RT_NTSCM_VSYNC_INT_HOLD 0x17 +#define RT_PALSEM_VSYNC_INT_HOLD 0x1C + +#define RT_NTSCM_VS_FIELD_BLANK_START 0x206 +#define RT_PALSEM_VS_FIELD_BLANK_START 0x26D /* instead of 0x26C - Ivo */ + +#define RT_FIELD_FLIP_EN 0x4 +#define RT_V_FIELD_FLIP_INVERTED 0x2000 + +#define RT_NTSCM_H_IN_START 0x70 +#define RT_PAL_H_IN_START 154 /* instead of 144 - Ivo */ +#define RT_SECAM_H_IN_START 0x91 /* instead of 0x9A, Ivo value is 154, instead of 144 - Volodya, - eric */ +#define RT_NTSC_H_ACTIVE_SIZE 744 +#define RT_PAL_H_ACTIVE_SIZE 928 /* instead of 927 - Ivo */ +#define RT_SECAM_H_ACTIVE_SIZE 932 /* instead of 928, instead of 927 - Ivo, - eric */ +#define RT_NTSCM_V_IN_START (0x23) +#define RT_PAL_V_IN_START 44 /* instead of (45-6) - Ivo */ +#define RT_SECAM_V_IN_START 0x2C /* instead of (45-6) - Volodya */ +#define RT_NTSCM_V_ACTIVE_SIZE 480 +#define RT_PAL_V_ACTIVE_SIZE 572 /* instead of 575 - Ivo */ +#define RT_SECAM_V_ACTIVE_SIZE 570 /* instead of 572, instead of 575 - Ivo, - eric */ + +#define RT_NTSCM_WIN_CLOSE_LIMIT 0x4D +#define RT_NTSCJ_WIN_CLOSE_LIMIT 0x4D +#define RT_NTSC443_WIN_CLOSE_LIMIT 0x5F +#define RT_PALM_WIN_CLOSE_LIMIT 0x4D +#define RT_PALN_WIN_CLOSE_LIMIT 0x5F +#define RT_SECAM_WIN_CLOSE_LIMIT 0xC7 /* instead of 0x5F - eric */ + +#define RT_NTSCM_VS_FIELD_BLANK_START 0x206 + +#define RT_NTSCM_HS_PLL_SGAIN 0x5 +#define RT_NTSCM_HS_PLL_FGAIN 0x7 + +#define RT_NTSCM_H_OUT_WIND_WIDTH 0x2F4 +#define RT_NTSCM_V_OUT_WIND_HEIGHT 0xF0 + +#define TV 0x1 +#define LINEIN 0x2 +#define MUTE 0x3 + +#define DEC_COMPOSITE 0 +#define DEC_SVIDEO 1 +#define DEC_TUNER 2 + +#define DEC_NTSC 0 +#define DEC_PAL 1 +#define DEC_SECAM 2 +#define DEC_NTSC_J 8 + +#define DEC_SMOOTH 0 +#define DEC_SHARP 1 + +/* RT Register Field Defaults: */ +#define fld_tmpReg1_def 0x00000000 +#define fld_tmpReg2_def 0x00000001 +#define fld_tmpReg3_def 0x00000002 + +#define fld_LP_CONTRAST_def 0x0000006e +#define fld_LP_BRIGHTNESS_def 0x00003ff0 +#define fld_CP_HUE_CNTL_def 0x00000000 +#define fld_LUMA_FILTER_def 0x00000001 +#define fld_H_SCALE_RATIO_def 0x00010000 +#define fld_H_SHARPNESS_def 0x00000000 + +#define fld_V_SCALE_RATIO_def 0x00000800 +#define fld_V_DEINTERLACE_ON_def 0x00000001 +#define fld_V_BYPSS_def 0x00000000 +#define fld_V_DITHER_ON_def 0x00000001 +#define fld_EVENF_OFFSET_def 0x00000000 +#define fld_ODDF_OFFSET_def 0x00000000 + +#define fld_INTERLACE_DETECTED_def 0x00000000 + +#define fld_VS_LINE_COUNT_def 0x00000000 +#define fld_VS_DETECTED_LINES_def 0x00000000 +#define fld_VS_ITU656_VB_def 0x00000000 + +#define fld_VBI_CC_DATA_def 0x00000000 +#define fld_VBI_CC_WT_def 0x00000000 +#define fld_VBI_CC_WT_ACK_def 0x00000000 +#define fld_VBI_CC_HOLD_def 0x00000000 +#define fld_VBI_DECODE_EN_def 0x00000000 + +#define fld_VBI_CC_DTO_P_def 0x00001802 +#define fld_VBI_20BIT_DTO_P_def 0x0000155c + +#define fld_VBI_CC_LEVEL_def 0x0000003f +#define fld_VBI_20BIT_LEVEL_def 0x00000059 +#define fld_VBI_CLK_RUNIN_GAIN_def 0x0000010f + +#define fld_H_VBI_WIND_START_def 0x00000041 +#define fld_H_VBI_WIND_END_def 0x00000366 + +#define fld_V_VBI_WIND_START_def 0x0D +#define fld_V_VBI_WIND_END_def 0x24 + +#define fld_VBI_20BIT_DATA0_def 0x00000000 +#define fld_VBI_20BIT_DATA1_def 0x00000000 +#define fld_VBI_20BIT_WT_def 0x00000000 +#define fld_VBI_20BIT_WT_ACK_def 0x00000000 +#define fld_VBI_20BIT_HOLD_def 0x00000000 + +#define fld_VBI_CAPTURE_ENABLE_def 0x00000000 + +#define fld_VBI_EDS_DATA_def 0x00000000 +#define fld_VBI_EDS_WT_def 0x00000000 +#define fld_VBI_EDS_WT_ACK_def 0x00000000 +#define fld_VBI_EDS_HOLD_def 0x00000000 + +#define fld_VBI_SCALING_RATIO_def 0x00010000 +#define fld_VBI_ALIGNER_ENABLE_def 0x00000000 + +#define fld_H_ACTIVE_START_def 0x00000070 +#define fld_H_ACTIVE_END_def 0x000002f0 + +#define fld_V_ACTIVE_START_def ((22-4)*2+1) +#define fld_V_ACTIVE_END_def ((22+240-4)*2+2) + +#define fld_CH_HEIGHT_def 0x000000CD +#define fld_CH_KILL_LEVEL_def 0x000000C0 +#define fld_CH_AGC_ERROR_LIM_def 0x00000002 +#define fld_CH_AGC_FILTER_EN_def 0x00000000 +#define fld_CH_AGC_LOOP_SPEED_def 0x00000000 + +#define fld_HUE_ADJ_def 0x00000000 + +#define fld_STANDARD_SEL_def 0x00000000 +#define fld_STANDARD_YC_def 0x00000000 + +#define fld_ADC_PDWN_def 0x00000001 +#define fld_INPUT_SELECT_def 0x00000000 + +#define fld_ADC_PREFLO_def 0x00000003 +#define fld_H_SYNC_PULSE_WIDTH_def 0x00000000 +#define fld_HS_GENLOCKED_def 0x00000000 +#define fld_HS_SYNC_IN_WIN_def 0x00000000 + +#define fld_VIN_ASYNC_RST_def 0x00000001 +#define fld_DVS_ASYNC_RST_def 0x00000001 + +/* Vendor IDs: */ +#define fld_VIP_VENDOR_ID_def 0x00001002 +#define fld_VIP_DEVICE_ID_def 0x00004d54 +#define fld_VIP_REVISION_ID_def 0x00000001 + +/* AGC Delay Register */ +#define fld_BLACK_INT_START_def 0x00000031 +#define fld_BLACK_INT_LENGTH_def 0x0000000f + +#define fld_UV_INT_START_def 0x0000003b +#define fld_U_INT_LENGTH_def 0x0000000f +#define fld_V_INT_LENGTH_def 0x0000000f +#define fld_CRDR_ACTIVE_GAIN_def 0x0000007a +#define fld_CBDB_ACTIVE_GAIN_def 0x000000ac + +#define fld_DVS_DIRECTION_def 0x00000000 +#define fld_DVS_VBI_CARD8_SWAP_def 0x00000000 +#define fld_DVS_CLK_SELECT_def 0x00000000 +#define fld_CONTINUOUS_STREAM_def 0x00000000 +#define fld_DVSOUT_CLK_DRV_def 0x00000001 +#define fld_DVSOUT_DATA_DRV_def 0x00000001 + +#define fld_COMB_CNTL0_def 0x09438090 +#define fld_COMB_CNTL1_def 0x00000010 + +#define fld_COMB_CNTL2_def 0x16161010 +#define fld_COMB_LENGTH_def 0x0718038A + +#define fld_SYNCTIP_REF0_def 0x00000037 +#define fld_SYNCTIP_REF1_def 0x00000029 +#define fld_CLAMP_REF_def 0x0000003B +#define fld_AGC_PEAKWHITE_def 0x000000FF +#define fld_VBI_PEAKWHITE_def 0x000000D2 + +#define fld_WPA_THRESHOLD_def 0x000003B0 + +#define fld_WPA_TRIGGER_LO_def 0x000000B4 +#define fld_WPA_TRIGGER_HIGH_def 0x0000021C + +#define fld_LOCKOUT_START_def 0x00000206 +#define fld_LOCKOUT_END_def 0x00000021 + +#define fld_CH_DTO_INC_def 0x00400000 +#define fld_PLL_SGAIN_def 0x00000001 +#define fld_PLL_FGAIN_def 0x00000002 + +#define fld_CR_BURST_GAIN_def 0x0000007a +#define fld_CB_BURST_GAIN_def 0x000000ac + +#define fld_VERT_LOCKOUT_START_def 0x00000207 +#define fld_VERT_LOCKOUT_END_def 0x0000000E + +#define fld_H_IN_WIND_START_def 0x00000070 +#define fld_V_IN_WIND_START_def 0x00000027 + +#define fld_H_OUT_WIND_WIDTH_def 0x000002f4 + +#define fld_V_OUT_WIND_WIDTH_def 0x000000f0 + +#define fld_HS_LINE_TOTAL_def 0x0000038E + +#define fld_MIN_PULSE_WIDTH_def 0x0000002F +#define fld_MAX_PULSE_WIDTH_def 0x00000046 + +#define fld_WIN_CLOSE_LIMIT_def 0x0000004D +#define fld_WIN_OPEN_LIMIT_def 0x000001B7 + +#define fld_VSYNC_INT_TRIGGER_def 0x000002AA + +#define fld_VSYNC_INT_HOLD_def 0x0000001D + +#define fld_VIN_M0_def 0x00000039 +#define fld_VIN_N0_def 0x0000014c +#define fld_MNFLIP_EN_def 0x00000000 +#define fld_VIN_P_def 0x00000006 +#define fld_REG_CLK_SEL_def 0x00000000 + +#define fld_VIN_M1_def 0x00000000 +#define fld_VIN_N1_def 0x00000000 +#define fld_VIN_DRIVER_SEL_def 0x00000000 +#define fld_VIN_MNFLIP_REQ_def 0x00000000 +#define fld_VIN_MNFLIP_DONE_def 0x00000000 +#define fld_TV_LOCK_TO_VIN_def 0x00000000 +#define fld_TV_P_FOR_WINCLK_def 0x00000004 + +#define fld_VINRST_def 0x00000001 +#define fld_VIN_CLK_SEL_def 0x00000000 + +#define fld_VS_FIELD_BLANK_START_def 0x00000206 + +#define fld_VS_FIELD_BLANK_END_def 0x0000000A + +/*#define fld_VS_FIELD_IDLOCATION_def 0x00000105 */ +#define fld_VS_FIELD_IDLOCATION_def 0x00000001 +#define fld_VS_FRAME_TOTAL_def 0x00000217 + +#define fld_SYNC_TIP_START_def 0x00000372 +#define fld_SYNC_TIP_LENGTH_def 0x0000000F + +#define fld_GAIN_FORCE_DATA_def 0x00000000 +#define fld_GAIN_FORCE_EN_def 0x00000000 +#define fld_I_CLAMP_SEL_def 0x00000003 +#define fld_I_AGC_SEL_def 0x00000001 +#define fld_EXT_CLAMP_CAP_def 0x00000001 +#define fld_EXT_AGC_CAP_def 0x00000001 +#define fld_DECI_DITHER_EN_def 0x00000001 +#define fld_ADC_PREFHI_def 0x00000000 +#define fld_ADC_CH_GAIN_SEL_def 0x00000001 + +#define fld_HS_PLL_SGAIN_def 0x00000003 + +#define fld_NREn_def 0x00000000 +#define fld_NRGainCntl_def 0x00000000 +#define fld_NRBWTresh_def 0x00000000 +#define fld_NRGCTresh_def 0x00000000 +#define fld_NRCoefDespeclMode_def 0x00000000 + +#define fld_GPIO_5_OE_def 0x00000000 +#define fld_GPIO_6_OE_def 0x00000000 + +#define fld_GPIO_5_OUT_def 0x00000000 +#define fld_GPIO_6_OUT_def 0x00000000 + +/* End of field default values. */ + +#endif /* RADEON_H */
--- a/drivers/radeon/README Sat Mar 17 21:21:04 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,121 +0,0 @@ - framebuffer driver for ATI Radeon chipset video boards - ====================================================== - -These files are replacement for linux-2.4.x-ac.y drivers. -To use this driver you should have at least linux-2.4.5-ac.1 -then simply replace linux/drivers/video/radeon* with files -from this directory. -Note: since linux-2.4.10 this driver was moved from -ac to -Linus distribution. - -Alternative way: -~~~~~~~~~~~~~~~~ -Simply type two commands in this directory: -make -make install - -Anyway you should have 'framebuffer support' compiled into linux-kernel -and at least '8bpp packed pixel support' compiled and installed as module. -(But if you plan to use this module with MPlayer you also should have -16bpp, 24bpp and 32bpp pixel support compiled as modules). - - - Radeon video overlay - ==================== - -It was designed for MPlayer and currently can be used only by MPlayer. -It's RGB-YUV BES for Radeon cards (althrough there is experimental -support for Rage128 / Rage128pro chips). - -rage128_vid is contained within radeon_vid.c. As for a Rage128 framebuffer - -use the one from your Linux distribution. - -Installation: -~~~~~~~~~~~~~ - -Simply type two commands in this directory: -make -make install - -Using with MPlayer: -~~~~~~~~~~~~~~~~~~~ - -Currently there is only one way to use ATI's drivers: -mplayer -vo vesa:lvo:/dev/radeon_vid -<your vesa's options> filename -or -mplayer -vo vesa:lvo:/dev/rage128_vid -<your vesa's options> filename - -For YV12 formats you can use also: -mplayer -vo mga:/dev/radeon_vid -<your mga's option> filename - -but in this case you should load at least radeonfb driver from -this package. - -Configuring: -~~~~~~~~~~~~ - -You can tune some parameters with the following trick: -echo "parameter=value" > /dev/radeon_vid -Example (disables adaptive deinterlacing): -echo "deinterlace=off" > /dev/radeon_vid - -To know more about these parameters - try reading the /dev/radeon_vid file ;) -For example: -cat /dev/radeon_vid - -List of parameters: -~~~~~~~~~~~~~~~~~~~ -If you have Rage128 chip: -brightness=decval (-64:+63) changes brightness -saturation=decval (0:+31) changes saturation 0 == grayscale mode -else - if you have Radeon: -brightness=decval (-1000:+1000) -1000 == black screen -saturation=decval (-1000:+1000) -1000 == grayscaled mode -contrast=decval (-1000:+1000) -1000 == black screen -hue=decval (-1000:+1000) -1000 == +1000 (full circle) - all other values are within this range -Note: 0 is the default value for every parameter on Radeons. -WARNING: This driver violates the rule: "no float in the kernel". -So if you have problems then don't use color correction. - -double_buff=on/off enables/disables double buffering -deinterlace=on/off enables/disables adaptive deinterlacing -deinterlace_pattern=hexval defines deinterlacing pattern - -Driver parameters: -~~~~~~~~~~~~~~~~~~ - -You can use some additional parameters during module loading: -Example: -modprobe radeon_vid swap_fourcc=1 - -List of driver parameters: -~~~~~~~~~~~~~~~~~~~~~~~~~~ -mtrr=1/0 Configures MTRR (if available), default = 1. -swap_fourcc=1/0 Performs byte swapping of passed fourcc. - (It's required for compatibility with -vo mga.) - -To know more about driver parameters execute: -modinfo radeon_vid -or -modinfo rage128_vid - -Note: -~~~~~ -For command line of MPlayer: -You can pass only options with can be recognized by vo_vesa driver. -(Indeed radeon_vid and rage128_vid are stupid things and can only create -video overlay. Mode switching and other adjustments are performed by the -vo_vesa driver. This mean that they use the VESA BIOS as graphics server.) - -Conclusion: -~~~~~~~~~~~ -This stuff (radeon(rage128)_vid) currently doesn't support any standards. - -Full example: -~~~~~~~~~~~~~ -modprobe radeon_vid mtrr=1 -echo "deinterlace_pattern=F0055555" > /dev/radeon_vid -mplayer -vo vesa:lvo:/dev/radeon_vid -fs -zoom -bpp 32 filename - -Enjoy!
--- a/drivers/radeon/generic_math.h Sat Mar 17 21:21:04 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,258 +0,0 @@ -/* - generic implementation of sin(x) and cos(x) functions. - Specially for Linux. - Licence: GPL - Copyright (C) 2002 Nick Kurshev -*/ - -#ifndef GENERIC_MATH_H -#define GENERIC_MATH_H - -typedef struct _gen_sincos -{ - double x; - double sinx; - double cosx; -}gen_sincos_t; - -static gen_sincos_t g_sincos[201] = { -{ -3.141600e+00, 7.346410e-06, -1.000000e-00 }, -{ -3.110184e+00, -3.140349e-02, -9.995068e-01 }, -{ -3.078768e+00, -6.278333e-02, -9.980272e-01 }, -{ -3.047352e+00, -9.410122e-02, -9.955626e-01 }, -{ -3.015936e+00, -1.253262e-01, -9.921156e-01 }, -{ -2.984520e+00, -1.564276e-01, -9.876894e-01 }, -{ -2.953104e+00, -1.873745e-01, -9.822885e-01 }, -{ -2.921688e+00, -2.181366e-01, -9.759183e-01 }, -{ -2.890272e+00, -2.486833e-01, -9.685848e-01 }, -{ -2.858856e+00, -2.789847e-01, -9.602956e-01 }, -{ -2.827440e+00, -3.090107e-01, -9.510586e-01 }, -{ -2.796024e+00, -3.387318e-01, -9.408830e-01 }, -{ -2.764608e+00, -3.681185e-01, -9.297789e-01 }, -{ -2.733192e+00, -3.971420e-01, -9.177572e-01 }, -{ -2.701776e+00, -4.257736e-01, -9.048297e-01 }, -{ -2.670360e+00, -4.539849e-01, -8.910094e-01 }, -{ -2.638944e+00, -4.817483e-01, -8.763097e-01 }, -{ -2.607528e+00, -5.090362e-01, -8.607451e-01 }, -{ -2.576112e+00, -5.358217e-01, -8.443312e-01 }, -{ -2.544696e+00, -5.620785e-01, -8.270839e-01 }, -{ -2.513280e+00, -5.877805e-01, -8.090204e-01 }, -{ -2.481864e+00, -6.129025e-01, -7.901586e-01 }, -{ -2.450448e+00, -6.374196e-01, -7.705169e-01 }, -{ -2.419032e+00, -6.613076e-01, -7.501148e-01 }, -{ -2.387616e+00, -6.845430e-01, -7.289724e-01 }, -{ -2.356200e+00, -7.071029e-01, -7.071107e-01 }, -{ -2.324784e+00, -7.289649e-01, -6.845511e-01 }, -{ -2.293368e+00, -7.501075e-01, -6.613159e-01 }, -{ -2.261952e+00, -7.705099e-01, -6.374281e-01 }, -{ -2.230536e+00, -7.901518e-01, -6.129112e-01 }, -{ -2.199120e+00, -8.090140e-01, -5.877894e-01 }, -{ -2.167704e+00, -8.270777e-01, -5.620876e-01 }, -{ -2.136288e+00, -8.443252e-01, -5.358310e-01 }, -{ -2.104872e+00, -8.607395e-01, -5.090457e-01 }, -{ -2.073456e+00, -8.763043e-01, -4.817579e-01 }, -{ -2.042040e+00, -8.910044e-01, -4.539948e-01 }, -{ -2.010624e+00, -9.048251e-01, -4.257835e-01 }, -{ -1.979208e+00, -9.177528e-01, -3.971521e-01 }, -{ -1.947792e+00, -9.297748e-01, -3.681288e-01 }, -{ -1.916376e+00, -9.408793e-01, -3.387421e-01 }, -{ -1.884960e+00, -9.510552e-01, -3.090212e-01 }, -{ -1.853544e+00, -9.602925e-01, -2.789953e-01 }, -{ -1.822128e+00, -9.685821e-01, -2.486940e-01 }, -{ -1.790712e+00, -9.759158e-01, -2.181473e-01 }, -{ -1.759296e+00, -9.822865e-01, -1.873854e-01 }, -{ -1.727880e+00, -9.876877e-01, -1.564385e-01 }, -{ -1.696464e+00, -9.921142e-01, -1.253372e-01 }, -{ -1.665048e+00, -9.955616e-01, -9.411219e-02 }, -{ -1.633632e+00, -9.980265e-01, -6.279433e-02 }, -{ -1.602216e+00, -9.995064e-01, -3.141450e-02 }, -{ -1.570800e+00, -1.000000e-00, -3.673205e-06 }, -{ -1.539384e+00, -9.995067e-01, 3.140716e-02 }, -{ -1.507968e+00, -9.980269e-01, 6.278700e-02 }, -{ -1.476552e+00, -9.955623e-01, 9.410488e-02 }, -{ -1.445136e+00, -9.921151e-01, 1.253299e-01 }, -{ -1.413720e+00, -9.876889e-01, 1.564312e-01 }, -{ -1.382304e+00, -9.822879e-01, 1.873781e-01 }, -{ -1.350888e+00, -9.759175e-01, 2.181402e-01 }, -{ -1.319472e+00, -9.685839e-01, 2.486869e-01 }, -{ -1.288056e+00, -9.602945e-01, 2.789882e-01 }, -{ -1.256640e+00, -9.510574e-01, 3.090142e-01 }, -{ -1.225224e+00, -9.408817e-01, 3.387352e-01 }, -{ -1.193808e+00, -9.297775e-01, 3.681220e-01 }, -{ -1.162392e+00, -9.177557e-01, 3.971454e-01 }, -{ -1.130976e+00, -9.048282e-01, 4.257769e-01 }, -{ -1.099560e+00, -8.910077e-01, 4.539882e-01 }, -{ -1.068144e+00, -8.763079e-01, 4.817515e-01 }, -{ -1.036728e+00, -8.607433e-01, 5.090393e-01 }, -{ -1.005312e+00, -8.443292e-01, 5.358248e-01 }, -{ -9.738960e-01, -8.270819e-01, 5.620815e-01 }, -{ -9.424800e-01, -8.090183e-01, 5.877835e-01 }, -{ -9.110640e-01, -7.901563e-01, 6.129054e-01 }, -{ -8.796480e-01, -7.705146e-01, 6.374224e-01 }, -{ -8.482320e-01, -7.501124e-01, 6.613104e-01 }, -{ -8.168160e-01, -7.289699e-01, 6.845457e-01 }, -{ -7.854000e-01, -7.071081e-01, 7.071055e-01 }, -{ -7.539840e-01, -6.845484e-01, 7.289674e-01 }, -{ -7.225680e-01, -6.613131e-01, 7.501100e-01 }, -{ -6.911520e-01, -6.374252e-01, 7.705122e-01 }, -{ -6.597360e-01, -6.129083e-01, 7.901541e-01 }, -{ -6.283200e-01, -5.877864e-01, 8.090161e-01 }, -{ -5.969040e-01, -5.620845e-01, 8.270798e-01 }, -{ -5.654880e-01, -5.358279e-01, 8.443272e-01 }, -{ -5.340720e-01, -5.090425e-01, 8.607414e-01 }, -{ -5.026560e-01, -4.817547e-01, 8.763061e-01 }, -{ -4.712400e-01, -4.539915e-01, 8.910060e-01 }, -{ -4.398240e-01, -4.257802e-01, 9.048266e-01 }, -{ -4.084080e-01, -3.971488e-01, 9.177542e-01 }, -{ -3.769920e-01, -3.681254e-01, 9.297762e-01 }, -{ -3.455760e-01, -3.387387e-01, 9.408805e-01 }, -{ -3.141600e-01, -3.090177e-01, 9.510563e-01 }, -{ -2.827440e-01, -2.789917e-01, 9.602935e-01 }, -{ -2.513280e-01, -2.486905e-01, 9.685830e-01 }, -{ -2.199120e-01, -2.181437e-01, 9.759166e-01 }, -{ -1.884960e-01, -1.873817e-01, 9.822872e-01 }, -{ -1.570800e-01, -1.564348e-01, 9.876883e-01 }, -{ -1.256640e-01, -1.253335e-01, 9.921147e-01 }, -{ -9.424800e-02, -9.410853e-02, 9.955619e-01 }, -{ -6.283200e-02, -6.279067e-02, 9.980267e-01 }, -{ -3.141600e-02, -3.141083e-02, 9.995066e-01 }, -{ 0.000000e+00, 0.000000e+00, 1.000000e+00 }, -{ 3.141600e-02, 3.141083e-02, 9.995066e-01 }, -{ 6.283200e-02, 6.279067e-02, 9.980267e-01 }, -{ 9.424800e-02, 9.410853e-02, 9.955619e-01 }, -{ 1.256640e-01, 1.253335e-01, 9.921147e-01 }, -{ 1.570800e-01, 1.564348e-01, 9.876883e-01 }, -{ 1.884960e-01, 1.873817e-01, 9.822872e-01 }, -{ 2.199120e-01, 2.181437e-01, 9.759166e-01 }, -{ 2.513280e-01, 2.486905e-01, 9.685830e-01 }, -{ 2.827440e-01, 2.789917e-01, 9.602935e-01 }, -{ 3.141600e-01, 3.090177e-01, 9.510563e-01 }, -{ 3.455760e-01, 3.387387e-01, 9.408805e-01 }, -{ 3.769920e-01, 3.681254e-01, 9.297762e-01 }, -{ 4.084080e-01, 3.971488e-01, 9.177542e-01 }, -{ 4.398240e-01, 4.257802e-01, 9.048266e-01 }, -{ 4.712400e-01, 4.539915e-01, 8.910060e-01 }, -{ 5.026560e-01, 4.817547e-01, 8.763061e-01 }, -{ 5.340720e-01, 5.090425e-01, 8.607414e-01 }, -{ 5.654880e-01, 5.358279e-01, 8.443272e-01 }, -{ 5.969040e-01, 5.620845e-01, 8.270798e-01 }, -{ 6.283200e-01, 5.877864e-01, 8.090161e-01 }, -{ 6.597360e-01, 6.129083e-01, 7.901541e-01 }, -{ 6.911520e-01, 6.374252e-01, 7.705122e-01 }, -{ 7.225680e-01, 6.613131e-01, 7.501100e-01 }, -{ 7.539840e-01, 6.845484e-01, 7.289674e-01 }, -{ 7.854000e-01, 7.071081e-01, 7.071055e-01 }, -{ 8.168160e-01, 7.289699e-01, 6.845457e-01 }, -{ 8.482320e-01, 7.501124e-01, 6.613104e-01 }, -{ 8.796480e-01, 7.705146e-01, 6.374224e-01 }, -{ 9.110640e-01, 7.901563e-01, 6.129054e-01 }, -{ 9.424800e-01, 8.090183e-01, 5.877835e-01 }, -{ 9.738960e-01, 8.270819e-01, 5.620815e-01 }, -{ 1.005312e+00, 8.443292e-01, 5.358248e-01 }, -{ 1.036728e+00, 8.607433e-01, 5.090393e-01 }, -{ 1.068144e+00, 8.763079e-01, 4.817515e-01 }, -{ 1.099560e+00, 8.910077e-01, 4.539882e-01 }, -{ 1.130976e+00, 9.048282e-01, 4.257769e-01 }, -{ 1.162392e+00, 9.177557e-01, 3.971454e-01 }, -{ 1.193808e+00, 9.297775e-01, 3.681220e-01 }, -{ 1.225224e+00, 9.408817e-01, 3.387352e-01 }, -{ 1.256640e+00, 9.510574e-01, 3.090142e-01 }, -{ 1.288056e+00, 9.602945e-01, 2.789882e-01 }, -{ 1.319472e+00, 9.685839e-01, 2.486869e-01 }, -{ 1.350888e+00, 9.759175e-01, 2.181402e-01 }, -{ 1.382304e+00, 9.822879e-01, 1.873781e-01 }, -{ 1.413720e+00, 9.876889e-01, 1.564312e-01 }, -{ 1.445136e+00, 9.921151e-01, 1.253299e-01 }, -{ 1.476552e+00, 9.955623e-01, 9.410488e-02 }, -{ 1.507968e+00, 9.980269e-01, 6.278700e-02 }, -{ 1.539384e+00, 9.995067e-01, 3.140716e-02 }, -{ 1.570800e+00, 1.000000e-00, -3.673205e-06 }, -{ 1.602216e+00, 9.995064e-01, -3.141450e-02 }, -{ 1.633632e+00, 9.980265e-01, -6.279433e-02 }, -{ 1.665048e+00, 9.955616e-01, -9.411219e-02 }, -{ 1.696464e+00, 9.921142e-01, -1.253372e-01 }, -{ 1.727880e+00, 9.876877e-01, -1.564385e-01 }, -{ 1.759296e+00, 9.822865e-01, -1.873854e-01 }, -{ 1.790712e+00, 9.759158e-01, -2.181473e-01 }, -{ 1.822128e+00, 9.685821e-01, -2.486940e-01 }, -{ 1.853544e+00, 9.602925e-01, -2.789953e-01 }, -{ 1.884960e+00, 9.510552e-01, -3.090212e-01 }, -{ 1.916376e+00, 9.408793e-01, -3.387421e-01 }, -{ 1.947792e+00, 9.297748e-01, -3.681288e-01 }, -{ 1.979208e+00, 9.177528e-01, -3.971521e-01 }, -{ 2.010624e+00, 9.048251e-01, -4.257835e-01 }, -{ 2.042040e+00, 8.910044e-01, -4.539948e-01 }, -{ 2.073456e+00, 8.763043e-01, -4.817579e-01 }, -{ 2.104872e+00, 8.607395e-01, -5.090457e-01 }, -{ 2.136288e+00, 8.443252e-01, -5.358310e-01 }, -{ 2.167704e+00, 8.270777e-01, -5.620876e-01 }, -{ 2.199120e+00, 8.090140e-01, -5.877894e-01 }, -{ 2.230536e+00, 7.901518e-01, -6.129112e-01 }, -{ 2.261952e+00, 7.705099e-01, -6.374281e-01 }, -{ 2.293368e+00, 7.501075e-01, -6.613159e-01 }, -{ 2.324784e+00, 7.289649e-01, -6.845511e-01 }, -{ 2.356200e+00, 7.071029e-01, -7.071107e-01 }, -{ 2.387616e+00, 6.845430e-01, -7.289724e-01 }, -{ 2.419032e+00, 6.613076e-01, -7.501148e-01 }, -{ 2.450448e+00, 6.374196e-01, -7.705169e-01 }, -{ 2.481864e+00, 6.129025e-01, -7.901586e-01 }, -{ 2.513280e+00, 5.877805e-01, -8.090204e-01 }, -{ 2.544696e+00, 5.620785e-01, -8.270839e-01 }, -{ 2.576112e+00, 5.358217e-01, -8.443312e-01 }, -{ 2.607528e+00, 5.090362e-01, -8.607451e-01 }, -{ 2.638944e+00, 4.817483e-01, -8.763097e-01 }, -{ 2.670360e+00, 4.539849e-01, -8.910094e-01 }, -{ 2.701776e+00, 4.257736e-01, -9.048297e-01 }, -{ 2.733192e+00, 3.971420e-01, -9.177572e-01 }, -{ 2.764608e+00, 3.681185e-01, -9.297789e-01 }, -{ 2.796024e+00, 3.387318e-01, -9.408830e-01 }, -{ 2.827440e+00, 3.090107e-01, -9.510586e-01 }, -{ 2.858856e+00, 2.789847e-01, -9.602956e-01 }, -{ 2.890272e+00, 2.486833e-01, -9.685848e-01 }, -{ 2.921688e+00, 2.181366e-01, -9.759183e-01 }, -{ 2.953104e+00, 1.873745e-01, -9.822885e-01 }, -{ 2.984520e+00, 1.564276e-01, -9.876894e-01 }, -{ 3.015936e+00, 1.253262e-01, -9.921156e-01 }, -{ 3.047352e+00, 9.410122e-02, -9.955626e-01 }, -{ 3.078768e+00, 6.278333e-02, -9.980272e-01 }, -{ 3.110184e+00, 3.140349e-02, -9.995068e-01 }, -{ 3.141600e+00, -7.346410e-06, -1.000000e-00 } -}; - -# define M_PI 3.14159265358979323846 /* pi */ - -static double inline gen_sin(double x) -{ - int i; - if(x < 0) while(x < -M_PI) x+= M_PI; - else while(x > M_PI) x-= M_PI; - for(i=0;i<sizeof(g_sincos)/sizeof(gen_sincos_t)-1;i++) - { - if(x>=g_sincos[i].x && x <= g_sincos[i+1].x) - { - return (g_sincos[i+1].sinx-g_sincos[i].sinx)*(x-g_sincos[i].x)/(g_sincos[i+1].x-g_sincos[i].x)+g_sincos[i].sinx; - } - } - return x<0?1:-1; -} -#undef sin -#define sin(x) gen_sin(x) - -static double inline gen_cos(double x) -{ - int i; - if(x < 0) while(x < -M_PI) x+= M_PI; - else while(x > M_PI) x-= M_PI; - for(i=0;i<sizeof(g_sincos)/sizeof(gen_sincos_t)-1;i++) - { - if(x>=g_sincos[i].x && x <= g_sincos[i+1].x) - { - return (g_sincos[i+1].cosx-g_sincos[i].cosx)*(x-g_sincos[i].x)/(g_sincos[i+1].x-g_sincos[i].x)+g_sincos[i].cosx; - } - } - return x<0?1:-1; -} -#undef cos -#define cos(x) gen_cos(x) - -#endif \ No newline at end of file
--- a/drivers/radeon/hacking Sat Mar 17 21:21:04 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,313 +0,0 @@ - ATI chips hacking - ================= - Dedicated to ATI's hackers. - -Preface -~~~~~~~ -This document will compare ATI chips only from point of DAC and video overlay. -There are lots of difference from 3D point, dual-head support, tv-out support -and many other things but it's already perfectly different story. -This document doesn't include information about ATI AIW (All In Wonder) chips. - -What are units on modern ATI chips: -DAC - (Digital to Analog Convertor) controls CRTC, LCD, DFP monitor's output - Consists from: - PLL - (Programable line length) registers - CRTC - CRT controller - LCD/DFP scaler - surface control -DAC2 - controls CRTC, LCD, DFP monitor's output on second head -TVDAC - controls Composite Video and Super Video output ports - Consists from: - TV_PLL - TV scaler & sync unit - TV format convertor (PAL/NTSC) -TVCAP - controls Video-In port -MPP - Miscellaneous peripheral port. (includes macrovision's filter - copy - protection mechanism) -OV - Video overlay (YUV BES) (include subpictures, gamma correction and - adaptive deinterlacing) -CAP0 - Video capturing -CAP1 - Video capturing (second unit) -RT - Rage theatre: video encoding and mixing -MUX - video muxer -MEM - PCI/AGP bus mastering -2D - GUI engine -3D - 3D-OpenGL engine (There are lots of stuff) -I2C - I2C Bus control - -This document is mainly related only with OV unit ;) -Video decoding diagram: - -RAM memory: [ App ] Copies YUV image to overlay memory - | <-- (It's possible to program DMA here) -overlay memory:[ OV ] performs scaling and YUVtoRGB convertion - /\ -RGB memory: / \ - / [ macrovision ] performs copy protection filtering - / \ (unneeded but presented by default thing;) - [ CRTC/LCD/DFP DAC ] [ TV DAC ] convert RGB memory to CRTC and NTSC/PAL signals - | | - [CRTC/LCD/DFP Monitor] [TV-screen] - -History -~~~~~~~ - What is history of ATI's chips? I can be wrong but below is my vision -of this question: - -0. I don't know any earlied chips :( -1. Mach8 -2. Mach16 -3. Mach32 - -4. Mach64. - It's first chip which has support from side of open - source drivers. Set of mach64 chips is: - mach64GX (ATI888GX00) - mach64CX (ATI888CX00) - mach64CT (ATI264CT) - mach64ET (ATI264ET) - mach64VTA3 (ATI264VT) - mach64VTA4 (ATI264VT) - mach64VTB (ATI264VTB) - mach64VT4 (ATI264VT4) - -5. 3D rage chips. - It seems that these chips have fully compatible by GPU with Mach64 - which is extended by 3D possibilities. Set of 3D rage chips is: - 3D RAGE (GT) - 3D RAGE II+ (GTB) - 3D RAGE IIC (PCI) - 3D RAGE IIC (AGP) - 3D RAGE LT - 3D RAGE LT-G - 3D RAGE PRO (BGA, AGP) - 3D RAGE PRO (BGA, AGP, 1x only) - 3D RAGE PRO (BGA, PCI) - 3D RAGE PRO (PQFP, PCI) - 3D RAGE PRO (PQFP, PCI, limited 3D) - 3D RAGE (XL) - 3D RAGE LT PRO (AGP) - 3D RAGE LT PRO (PCI) - 3D RAGE Mobility (PCI) - 3D RAGE Mobility (AGP) - -6. Rage128 chips. - These chips have perfectly new GPU which supports memory mapped IO - space for accelerating port access (It's main cause of incompatibility - with mach64). Set of Rage128 chips is: - Rage128 GL RE - Rage128 GL RF - Rage128 GL RG - Rage128 GL RH - Rage128 GL RI - Rage128 VR RK - Rage128 VR RL - Rage128 VR RM - Rage128 VR RN - Rage128 VR RO - Rage128 Mobility M3 LE - Rage128 Mobility M3 LF -7. Rage128Pro chips. - These chips are successors of Rage128 ones. - Rage128Pro GL PA - Rage128Pro GL PB - Rage128Pro GL PC - Rage128Pro GL PD - Rage128Pro GL PE - Rage128Pro GL PF - Rage128Pro VR PG - Rage128Pro VR PH - Rage128Pro VR PI - Rage128Pro VR PJ - Rage128Pro VR PK - Rage128Pro VR PL - Rage128Pro VR PM - Rage128Pro VR PN - Rage128Pro VR PO - Rage128Pro VR PP - Rage128Pro VR PQ - Rage128Pro VR PR - Rage128Pro VR TR - Rage128Pro VR PS - Rage128Pro VR PT - Rage128Pro VR PU - Rage128Pro VR PV - Rage128Pro VR PW - Rage128Pro VR PX - Rage128Pro Ultra U1 - Rage128Pro Ultra U2 - Rage128Pro Ultra U3 - -8. Radeon chips. - Indeed they could be named Rage256 Pro. (With minor changes is fully - compatible with Rage128 chips). - Radeon QD - Radeon QE - Radeon QF - Radeon QG - Radeon VE QY - Radeon VE QZ - Radeon M6 LY - Radeon M6 LZ - Radeon M7 LW -9. Radeon2 chips. - Indeed they could be named Rage512 Pro. - Radeon2 8500 QL - Radeon2 7500 QW - -10. Radeon3 and newest are cooming soon, but I hope that they will be fully - compatible with Radeon1 chips. - -In Radeon famility there were introduced also FX chips: Radeon FX and -Radeon2 8700 FX. Probably they have the same possibility as other Radeon -but currently it's unknown for me. - -What about video overlay and DAC? -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Currently it's known that there is only difference between -Mach64 and Rage128 compatible chips: -- They have different logic of io ports programming! -- They are incompatible by port numbers! -But: -- They use the same program logic from register's name point. -(Indeed exists slight difference even between Radeon and Rage128 -chips. AFAIK only Radeon has OV0_SLICE_CNTL register which currently -is not used by driver. But I know only its name ;). Also there -is difference in slight adjust of BES position but it's configured -by #ifdef blocks). - -Please compare: - -(The piece of Back-End Scaler programming) - - Sample for Mach64 compatible chips: - *********************************** - -#define SPARSE_IO_BASE 0x03fcu -#define SPARSE_IO_SELECT 0xfc00u - -#define BLOCK_IO_BASE 0xff00u -#define BLOCK_IO_SELECT 0x00fcu - -#define MM_IO_SELECT 0x03fcu -#define BLOCK_SELECT 0x0400u -#define DWORD_SELECT (BLOCK_SELECT | MM_IO_SELECT) - -#define IO_BYTE_SELECT 0x0003u - -#define SPARSE_IO_PORT (SPARSE_IO_BASE | IO_BYTE_SELECT) -#define BLOCK_IO_PORT (BLOCK_IO_BASE | IO_BYTE_SELECT) - -#define IOPortTag(_SparseIOSelect, _BlockIOSelect) \ - (SetBits(_SparseIOSelect, SPARSE_IO_SELECT) | \ - SetBits(_BlockIOSelect, BLOCK_SELECT | MM_IO_SELECT)) -#define SparseIOTag(_IOSelect) IOPortTag(_IOSelect, 0) -#define BlockIOTag(_IOSelect) IOPortTag(0, _IOSelect) - -... - -#define OVERLAY_Y_X_START BlockIOTag(0x100u) -#define OVERLAY_Y_X_END BlockIOTag(0x101u) - -... - -#define OUTREG(_Register, _Value) \ - MMIO_OUT32(pATI->pBlock[GetBits(_Register, BLOCK_SELECT)], \ - (_Register) & MM_IO_SELECT, _Value) - -... - -OUTREG(OVERLAY_Y_X_START,((drw_x)<<16)|(drw_y)|(1<<31)); -OUTREG(OVERLAY_Y_X_END,((drw_x+drw_w)<<16)|(drw_y+drw_h)); - - - Sample for Rage128 compatible chips: - ************************************ - -#define OV0_Y_X_START 0x0400 -#define OV0_Y_X_END 0x0404 - -... - -#define INREG(addr) readl((rage_mmio_base)+addr) -#define OUTREG(addr,val) writel(val, (rage_mmio_base)+addr) - -... - -rage_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RAGE_REGSIZE); - -... - -#ifdef RADEON -#define X_ADJUST 8 -#else /* rage128 */ -#define X_ADJUST 0 -#endif - -OUTREG(OV0_Y_X_START,(drw_x+X_ADJUST)|(drw_y<<16)); -OUTREG(OV0_Y_X_END,(drw_x+drw_w+X_ADJUST)|(drw_y+drw_h)<<16)); - -Thus - these chips have almost the same logic from register's name point. -(except the fact that they have swapped 16-bit halfs). -Yes - programming of Rage128 is much simpler of Mach64. - - -What about other ATI's chips? -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -I suggest you have latest copy of GATOS-CVS: -http://www.linuxvideo.org -GATOS was designed and introduced as General ATI TV and Overlay Sowfware. -You will be able to find out there a lots of useful hacking utilities -(at location gatos-ati/gatos): -gfxdump - Program for dumping graphics chips registers on Linux and Windows 9X. - (it's more useful for Win9x to hack their values). -xatitv - For working with tv-in (currently is under hard development) -atitvout- For working with tv-out -and lot of other stuff. -BUT: After studing of Gatos and X11 stuffs I've found that they are bad -optimized for movie playback. -Please compare: - radeon_vid - configures video overlay only once and provides DGA to it. - (doesn't require to be MMX optimized) - gatos and X11 - configures video overlay at every slice of frame, then - performs unoptimized copying of source stuff to video memory - often with using CopyMungedData (it's C-analog of YV12_to_YUY2) - since there are lacks in yv12 support. - (is not MMX optimized that's gladly accepted, but probably - will be never optimized due portability). - -hardware IDCT support diagram: -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - | -[ Video parser ] <---------- [ Transport demuxing ] --> [ Audio ] - | | | -[ Variable length decoder] |D | - | |V | -[ Inverse quantization ] |D | - | | | --------|---[ video card ]---------+ |s | - | | |u | -[ Run level decode & de-zigzag ] | |b | - | | |p | -[ IDCT ] | |i | - | | |c | -[ Motion compensation ] | |t | - | | |u | -[ Advanced deinterlacing ] | |r | - | | |e | -[ Filtered X-Y scaling ] [SUBPIC]-|-----+s [ OSD ] - | | | | | -[ 4-bit alpha blending ] <---+ | +-------+ - | | -[ YUV to RGB conversion ] | --------|--------------------------+ -TV-screen or CRT-display - - -Conslusion: -~~~~~~~~~~~ - -That's all folk!
--- a/drivers/radeon/radeon.h Sat Mar 17 21:21:04 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2046 +0,0 @@ -/* - * radeon.h - * This software has been released under the terms of the GNU Public - * license. See http://www.gnu.org/copyleft/gpl.html for details. - * - * This collection of definition was written by Nick Kurshev - * It's based on radeonfb, X11, GATOS sources - * and partly compatible with Rage128 set (in OV0, CAP0, CAP1 parts) -*/ - -#ifndef _RADEON_H -#define _RADEON_H - - -/* radeon PCI ids */ -#define PCI_DEVICE_ID_RADEON_QD 0x5144 -#define PCI_DEVICE_ID_RADEON_QE 0x5145 -#define PCI_DEVICE_ID_RADEON_QF 0x5146 -#define PCI_DEVICE_ID_RADEON_QG 0x5147 -#define PCI_DEVICE_ID_RADEON_QY 0x5159 -#define PCI_DEVICE_ID_RADEON_QZ 0x515A -#define PCI_DEVICE_ID_RADEON_LY 0x4C59 -#define PCI_DEVICE_ID_RADEON_LZ 0x4C5A -#define PCI_DEVICE_ID_RADEON_LW 0x4C57 -#define PCI_DEVICE_ID_R200_QL 0x514C -#define PCI_DEVICE_ID_RV200_QW 0x5157 -#define PCI_DEVICE_ID_R200_BB 0x4242 - -#define RADEON_REGSIZE 0x4000 - - -#define MM_INDEX 0x0000 -/* MM_INDEX bit constants */ -# define MM_APER 0x80000000 -#define MM_DATA 0x0004 -#define BUS_CNTL 0x0030 -/* BUS_CNTL bit constants */ -# define BUS_DBL_RESYNC 0x00000001 -# define BUS_MSTR_RESET 0x00000002 -# define BUS_FLUSH_BUF 0x00000004 -# define BUS_STOP_REQ_DIS 0x00000008 -# define BUS_ROTATION_DIS 0x00000010 -# define BUS_MASTER_DIS 0x00000040 -# define BUS_ROM_WRT_EN 0x00000080 -# define BUS_DIS_ROM 0x00001000 -# define BUS_PCI_READ_RETRY_EN 0x00002000 -# define BUS_AGP_AD_STEPPING_EN 0x00004000 -# define BUS_PCI_WRT_RETRY_EN 0x00008000 -# define BUS_MSTR_RD_MULT 0x00100000 -# define BUS_MSTR_RD_LINE 0x00200000 -# define BUS_SUSPEND 0x00400000 -# define LAT_16X 0x00800000 -# define BUS_RD_DISCARD_EN 0x01000000 -# define BUS_RD_ABORT_EN 0x02000000 -# define BUS_MSTR_WS 0x04000000 -# define BUS_PARKING_DIS 0x08000000 -# define BUS_MSTR_DISCONNECT_EN 0x10000000 -# define BUS_WRT_BURST 0x20000000 -# define BUS_READ_BURST 0x40000000 -# define BUS_RDY_READ_DLY 0x80000000 -#define HI_STAT 0x004C -#define BUS_CNTL1 0x0034 -# define BUS_WAIT_ON_LOCK_EN (1 << 4) -#define I2C_CNTL_0 0x0090 -# define I2C_DONE (1<<0) -# define I2C_NACK (1<<1) -# define I2C_HALT (1<<2) -# define I2C_SOFT_RST (1<<5) -# define I2C_DRIVE_EN (1<<6) -# define I2C_DRIVE_SEL (1<<7) -# define I2C_START (1<<8) -# define I2C_STOP (1<<9) -# define I2C_RECEIVE (1<<10) -# define I2C_ABORT (1<<11) -# define I2C_GO (1<<12) -# define I2C_SEL (1<<16) -# define I2C_EN (1<<17) -#define I2C_CNTL_1 0x0094 -#define I2C_DATA 0x0098 -#define CONFIG_CNTL 0x00E0 -/* CONFIG_CNTL bit constants */ -# define CFG_VGA_RAM_EN 0x00000100 -#define CONFIG_MEMSIZE 0x00F8 -#define CONFIG_APER_0_BASE 0x0100 -#define CONFIG_APER_1_BASE 0x0104 -#define CONFIG_APER_SIZE 0x0108 -#define CONFIG_REG_1_BASE 0x010C -#define CONFIG_REG_APER_SIZE 0x0110 -#define PAD_AGPINPUT_DELAY 0x0164 -#define PAD_CTLR_STRENGTH 0x0168 -#define PAD_CTLR_UPDATE 0x016C -#define AGP_CNTL 0x0174 -# define AGP_APER_SIZE_256MB (0x00 << 0) -# define AGP_APER_SIZE_128MB (0x20 << 0) -# define AGP_APER_SIZE_64MB (0x30 << 0) -# define AGP_APER_SIZE_32MB (0x38 << 0) -# define AGP_APER_SIZE_16MB (0x3c << 0) -# define AGP_APER_SIZE_8MB (0x3e << 0) -# define AGP_APER_SIZE_4MB (0x3f << 0) -# define AGP_APER_SIZE_MASK (0x3f << 0) -#define AMCGPIO_A_REG 0x01a0 -#define AMCGPIO_EN_REG 0x01a8 -#define AMCGPIO_MASK 0x0194 -#define AMCGPIO_Y_REG 0x01a4 -#define BM_STATUS 0x0160 -#define MPP_TB_CONFIG 0x01c0 /* ? */ -#define MPP_GP_CONFIG 0x01c8 /* ? */ -#define VENDOR_ID 0x0F00 -#define DEVICE_ID 0x0F02 -#define COMMAND 0x0F04 -#define STATUS 0x0F06 -#define REVISION_ID 0x0F08 -#define REGPROG_INF 0x0F09 -#define SUB_CLASS 0x0F0A -#define CACHE_LINE 0x0F0C -#define LATENCY 0x0F0D -#define HEADER 0x0F0E -#define BIST 0x0F0F -#define REG_MEM_BASE 0x0F10 -#define REG_IO_BASE 0x0F14 -#define REG_REG_BASE 0x0F18 -#define ADAPTER_ID 0x0F2C -#define BIOS_ROM 0x0F30 -#define CAPABILITIES_PTR 0x0F34 -#define INTERRUPT_LINE 0x0F3C -#define INTERRUPT_PIN 0x0F3D -#define MIN_GRANT 0x0F3E -#define MAX_LATENCY 0x0F3F -#define ADAPTER_ID_W 0x0F4C -#define PMI_CAP_ID 0x0F50 -#define PMI_NXT_CAP_PTR 0x0F51 -#define PMI_PMC_REG 0x0F52 -#define PM_STATUS 0x0F54 -#define PMI_DATA 0x0F57 -#define AGP_CAP_ID 0x0F58 -#define AGP_STATUS 0x0F5C -# define AGP_1X_MODE 0x01 -# define AGP_2X_MODE 0x02 -# define AGP_4X_MODE 0x04 -# define AGP_MODE_MASK 0x07 -#define AGP_COMMAND 0x0F60 - -/* Video muxer unit */ -#define VIDEOMUX_CNTL 0x0190 -#define VIPPAD_MASK 0x0198 -#define VIPPAD1_A 0x01AC -#define VIPPAD1_EN 0x01B0 -#define VIPPAD1_Y 0x01B4 - -#define AIC_CTRL 0x01D0 -#define AIC_STAT 0x01D4 -#define AIC_PT_BASE 0x01D8 -#define AIC_LO_ADDR 0x01DC -#define AIC_HI_ADDR 0x01E0 -#define AIC_TLB_ADDR 0x01E4 -#define AIC_TLB_DATA 0x01E8 -#define DAC_CNTL 0x0058 -/* DAC_CNTL bit constants */ -# define DAC_8BIT_EN 0x00000100 -# define DAC_4BPP_PIX_ORDER 0x00000200 -# define DAC_CRC_EN 0x00080000 -# define DAC_MASK_ALL (0xff << 24) -# define DAC_VGA_ADR_EN (1 << 13) -# define DAC_RANGE_CNTL (3 << 0) -# define DAC_BLANKING (1 << 2) -#define DAC_CNTL2 0x007c -/* DAC_CNTL2 bit constants */ -# define DAC2_DAC_CLK_SEL (1 << 0) -# define DAC2_DAC2_CLK_SEL (1 << 1) -# define DAC2_PALETTE_ACC_CTL (1 << 5) -#define TV_DAC_CNTL 0x088c -/* TV_DAC_CNTL bit constants */ -# define TV_DAC_STD_MASK 0x0300 -# define TV_DAC_RDACPD (1 << 24) -# define TV_DAC_GDACPD (1 << 25) -# define TV_DAC_BDACPD (1 << 26) -#define CRTC_GEN_CNTL 0x0050 -/* CRTC_GEN_CNTL bit constants */ -# define CRTC_DBL_SCAN_EN 0x00000001 -# define CRTC_INTERLACE_EN (1 << 1) -# define CRTC_CSYNC_EN (1 << 4) -# define CRTC_CUR_EN 0x00010000 -# define CRTC_CUR_MODE_MASK (7 << 17) -# define CRTC_ICON_EN (1 << 20) -# define CRTC_EXT_DISP_EN (1 << 24) -# define CRTC_EN (1 << 25) -# define CRTC_DISP_REQ_EN_B (1 << 26) -#define CRTC2_GEN_CNTL 0x03f8 -/* CRTC2_GEN_CNTL bit constants */ -# define CRTC2_DBL_SCAN_EN (1 << 0) -# define CRTC2_INTERLACE_EN (1 << 1) -# define CRTC2_SYNC_TRISTAT (1 << 4) -# define CRTC2_HSYNC_TRISTAT (1 << 5) -# define CRTC2_VSYNC_TRISTAT (1 << 6) -# define CRTC2_CRT2_ON (1 << 7) -# define CRTC2_ICON_EN (1 << 15) -# define CRTC2_CUR_EN (1 << 16) -# define CRTC2_CUR_MODE_MASK (7 << 20) -# define CRTC2_DISP_DIS (1 << 23) -# define CRTC2_EN (1 << 25) -# define CRTC2_DISP_REQ_EN_B (1 << 26) -# define CRTC2_HSYNC_DIS (1 << 28) -# define CRTC2_VSYNC_DIS (1 << 29) -#define MEM_CNTL 0x0140 -/* MEM_CNTL bit constants */ -# define MEM_CTLR_STATUS_IDLE 0x00000000 -# define MEM_CTLR_STATUS_BUSY 0x00100000 -# define MEM_SEQNCR_STATUS_IDLE 0x00000000 -# define MEM_SEQNCR_STATUS_BUSY 0x00200000 -# define MEM_ARBITER_STATUS_IDLE 0x00000000 -# define MEM_ARBITER_STATUS_BUSY 0x00400000 -# define MEM_REQ_UNLOCK 0x00000000 -# define MEM_REQ_LOCK 0x00800000 -#define EXT_MEM_CNTL 0x0144 -#define MC_AGP_LOCATION 0x014C -#define MEM_IO_CNTL_A0 0x0178 -#define MEM_INIT_LATENCY_TIMER 0x0154 -#define MEM_SDRAM_MODE_REG 0x0158 -#define AGP_BASE 0x0170 -#define MEM_IO_CNTL_A1 0x017C -#define MEM_IO_CNTL_B0 0x0180 -#define MEM_IO_CNTL_B1 0x0184 -#define MC_DEBUG 0x0188 -#define MC_STATUS 0x0150 -#define MEM_IO_OE_CNTL 0x018C -#define MC_FB_LOCATION 0x0148 -#define HOST_PATH_CNTL 0x0130 -#define MEM_VGA_WP_SEL 0x0038 -#define MEM_VGA_RP_SEL 0x003C -#define HDP_DEBUG 0x0138 -#define SW_SEMAPHORE 0x013C -#define SURFACE_CNTL 0x0B00 -/* SURFACE_CNTL bit constants */ -# define SURF_TRANSLATION_DIS (1 << 8) -# define NONSURF_AP0_SWP_16BPP (1 << 20) -# define NONSURF_AP0_SWP_32BPP (2 << 20) -#define SURFACE0_LOWER_BOUND 0x0B04 -#define SURFACE1_LOWER_BOUND 0x0B14 -#define SURFACE2_LOWER_BOUND 0x0B24 -#define SURFACE3_LOWER_BOUND 0x0B34 -#define SURFACE4_LOWER_BOUND 0x0B44 -#define SURFACE5_LOWER_BOUND 0x0B54 -#define SURFACE6_LOWER_BOUND 0x0B64 -#define SURFACE7_LOWER_BOUND 0x0B74 -#define SURFACE0_UPPER_BOUND 0x0B08 -#define SURFACE1_UPPER_BOUND 0x0B18 -#define SURFACE2_UPPER_BOUND 0x0B28 -#define SURFACE3_UPPER_BOUND 0x0B38 -#define SURFACE4_UPPER_BOUND 0x0B48 -#define SURFACE5_UPPER_BOUND 0x0B58 -#define SURFACE6_UPPER_BOUND 0x0B68 -#define SURFACE7_UPPER_BOUND 0x0B78 -#define SURFACE0_INFO 0x0B0C -#define SURFACE1_INFO 0x0B1C -#define SURFACE2_INFO 0x0B2C -#define SURFACE3_INFO 0x0B3C -#define SURFACE4_INFO 0x0B4C -#define SURFACE5_INFO 0x0B5C -#define SURFACE6_INFO 0x0B6C -#define SURFACE7_INFO 0x0B7C -#define SURFACE_ACCESS_FLAGS 0x0BF8 -#define SURFACE_ACCESS_CLR 0x0BFC -#define GEN_INT_CNTL 0x0040 -#define GEN_INT_STATUS 0x0044 -# define VSYNC_INT_AK (1 << 2) -# define VSYNC_INT (1 << 2) -#define CRTC_EXT_CNTL 0x0054 -/* CRTC_EXT_CNTL bit constants */ -# define CRTC_VGA_XOVERSCAN (1 << 0) -# define VGA_ATI_LINEAR 0x00000008 -# define VGA_128KAP_PAGING 0x00000010 -# define XCRT_CNT_EN (1 << 6) -# define CRTC_HSYNC_DIS (1 << 8) -# define CRTC_VSYNC_DIS (1 << 9) -# define CRTC_DISPLAY_DIS (1 << 10) -# define CRTC_SYNC_TRISTAT (1 << 11) -# define CRTC_CRT_ON (1 << 15) -#define CRTC_EXT_CNTL_DPMS_BYTE 0x0055 -# define CRTC_HSYNC_DIS_BYTE (1 << 0) -# define CRTC_VSYNC_DIS_BYTE (1 << 1) -# define CRTC_DISPLAY_DIS_BYTE (1 << 2) -#define RB3D_CNTL 0x1C3C -#define WAIT_UNTIL 0x1720 -#define ISYNC_CNTL 0x1724 -#define RBBM_GUICNTL 0x172C -#define RBBM_STATUS 0x0E40 -# define RBBM_FIFOCNT_MASK 0x007f -# define RBBM_ACTIVE (1 << 31) -#define RBBM_STATUS_alt_1 0x1740 -#define RBBM_CNTL 0x00EC -#define RBBM_CNTL_alt_1 0x0E44 -#define RBBM_SOFT_RESET 0x00F0 -/* RBBM_SOFT_RESET bit constants */ -# define SOFT_RESET_CP (1 << 0) -# define SOFT_RESET_HI (1 << 1) -# define SOFT_RESET_SE (1 << 2) -# define SOFT_RESET_RE (1 << 3) -# define SOFT_RESET_PP (1 << 4) -# define SOFT_RESET_E2 (1 << 5) -# define SOFT_RESET_RB (1 << 6) -# define SOFT_RESET_HDP (1 << 7) -#define RBBM_SOFT_RESET_alt_1 0x0E48 -#define NQWAIT_UNTIL 0x0E50 -#define RBBM_DEBUG 0x0E6C -#define RBBM_CMDFIFO_ADDR 0x0E70 -#define RBBM_CMDFIFO_DATAL 0x0E74 -#define RBBM_CMDFIFO_DATAH 0x0E78 -#define RBBM_CMDFIFO_STAT 0x0E7C -#define CRTC_STATUS 0x005C -/* CRTC_STATUS bit constants */ -# define CRTC_VBLANK 0x00000001 -# define CRTC_VBLANK_SAVE ( 1 << 1) -#define GPIO_VGA_DDC 0x0060 -#define GPIO_DVI_DDC 0x0064 -#define GPIO_MONID 0x0068 -#define PALETTE_INDEX 0x00B0 -#define PALETTE_DATA 0x00B4 -#define PALETTE_30_DATA 0x00B8 -#define CRTC_H_TOTAL_DISP 0x0200 -# define CRTC_H_TOTAL (0x03ff << 0) -# define CRTC_H_TOTAL_SHIFT 0 -# define CRTC_H_DISP (0x01ff << 16) -# define CRTC_H_DISP_SHIFT 16 -#define CRTC2_H_TOTAL_DISP 0x0300 -# define CRTC2_H_TOTAL (0x03ff << 0) -# define CRTC2_H_TOTAL_SHIFT 0 -# define CRTC2_H_DISP (0x01ff << 16) -# define CRTC2_H_DISP_SHIFT 16 -#define CRTC_H_SYNC_STRT_WID 0x0204 -# define CRTC_H_SYNC_STRT_PIX (0x07 << 0) -# define CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) -# define CRTC_H_SYNC_STRT_CHAR_SHIFT 3 -# define CRTC_H_SYNC_WID (0x3f << 16) -# define CRTC_H_SYNC_WID_SHIFT 16 -# define CRTC_H_SYNC_POL (1 << 23) -#define CRTC2_H_SYNC_STRT_WID 0x0304 -# define CRTC2_H_SYNC_STRT_PIX (0x07 << 0) -# define CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) -# define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 -# define CRTC2_H_SYNC_WID (0x3f << 16) -# define CRTC2_H_SYNC_WID_SHIFT 16 -# define CRTC2_H_SYNC_POL (1 << 23) -#define CRTC_V_TOTAL_DISP 0x0208 -# define CRTC_V_TOTAL (0x07ff << 0) -# define CRTC_V_TOTAL_SHIFT 0 -# define CRTC_V_DISP (0x07ff << 16) -# define CRTC_V_DISP_SHIFT 16 -#define CRTC2_V_TOTAL_DISP 0x0308 -# define CRTC2_V_TOTAL (0x07ff << 0) -# define CRTC2_V_TOTAL_SHIFT 0 -# define CRTC2_V_DISP (0x07ff << 16) -# define CRTC2_V_DISP_SHIFT 16 -#define CRTC_V_SYNC_STRT_WID 0x020C -# define CRTC_V_SYNC_STRT (0x7ff << 0) -# define CRTC_V_SYNC_STRT_SHIFT 0 -# define CRTC_V_SYNC_WID (0x1f << 16) -# define CRTC_V_SYNC_WID_SHIFT 16 -# define CRTC_V_SYNC_POL (1 << 23) -#define CRTC2_V_SYNC_STRT_WID 0x030C -# define CRTC2_V_SYNC_STRT (0x7ff << 0) -# define CRTC2_V_SYNC_STRT_SHIFT 0 -# define CRTC2_V_SYNC_WID (0x1f << 16) -# define CRTC2_V_SYNC_WID_SHIFT 16 -# define CRTC2_V_SYNC_POL (1 << 23) -#define CRTC_VLINE_CRNT_VLINE 0x0210 -# define CRTC_CRNT_VLINE_MASK (0x7ff << 16) -#define CRTC2_VLINE_CRNT_VLINE 0x0310 -#define CRTC_CRNT_FRAME 0x0214 -#define CRTC2_CRNT_FRAME 0x0314 -#define CRTC_GUI_TRIG_VLINE 0x0218 -#define CRTC2_GUI_TRIG_VLINE 0x0318 -#define CRTC_DEBUG 0x021C -#define CRTC2_DEBUG 0x031C -#define CRTC_OFFSET_RIGHT 0x0220 -#define CRTC_OFFSET 0x0224 -#define CRTC2_OFFSET 0x0324 -#define CRTC_OFFSET_CNTL 0x0228 -# define CRTC_TILE_EN (1 << 15) -#define CRTC2_OFFSET_CNTL 0x0328 -# define CRTC2_TILE_EN (1 << 15) -#define CRTC_PITCH 0x022C -#define CRTC2_PITCH 0x032C -#define TMDS_CRC 0x02a0 -#define OVR_CLR 0x0230 -#define OVR_WID_LEFT_RIGHT 0x0234 -#define OVR_WID_TOP_BOTTOM 0x0238 -#define DISPLAY_BASE_ADDR 0x023C -#define SNAPSHOT_VH_COUNTS 0x0240 -#define SNAPSHOT_F_COUNT 0x0244 -#define N_VIF_COUNT 0x0248 -#define SNAPSHOT_VIF_COUNT 0x024C -#define FP_CRTC_H_TOTAL_DISP 0x0250 -#define FP_CRTC2_H_TOTAL_DISP 0x0350 -#define FP_CRTC_V_TOTAL_DISP 0x0254 -#define FP_CRTC2_V_TOTAL_DISP 0x0354 -# define FP_CRTC_H_TOTAL_MASK 0x000003ff -# define FP_CRTC_H_DISP_MASK 0x01ff0000 -# define FP_CRTC_V_TOTAL_MASK 0x00000fff -# define FP_CRTC_V_DISP_MASK 0x0fff0000 -# define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 -# define FP_H_SYNC_WID_MASK 0x003f0000 -# define FP_V_SYNC_STRT_MASK 0x00000fff -# define FP_V_SYNC_WID_MASK 0x001f0000 -# define FP_CRTC_H_TOTAL_SHIFT 0x00000000 -# define FP_CRTC_H_DISP_SHIFT 0x00000010 -# define FP_CRTC_V_TOTAL_SHIFT 0x00000000 -# define FP_CRTC_V_DISP_SHIFT 0x00000010 -# define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 -# define FP_H_SYNC_WID_SHIFT 0x00000010 -# define FP_V_SYNC_STRT_SHIFT 0x00000000 -# define FP_V_SYNC_WID_SHIFT 0x00000010 -#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 -#define CRT_CRTC_V_SYNC_STRT_WID 0x025C -#define CUR_OFFSET 0x0260 -#define CUR_HORZ_VERT_POSN 0x0264 -#define CUR_HORZ_VERT_OFF 0x0268 -/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ -# define CUR_LOCK 0x80000000 -#define CUR_CLR0 0x026C -#define CUR_CLR1 0x0270 -#define CUR2_OFFSET 0x0360 -#define CUR2_HORZ_VERT_POSN 0x0364 -#define CUR2_HORZ_VERT_OFF 0x0368 -# define CUR2_LOCK (1 << 31) -#define CUR2_CLR0 0x036c -#define CUR2_CLR1 0x0370 -#define FP_HORZ_VERT_ACTIVE 0x0278 -#define CRTC_MORE_CNTL 0x027C -#define DAC_EXT_CNTL 0x0280 -#define FP_GEN_CNTL 0x0284 -/* FP_GEN_CNTL bit constants */ -# define FP_FPON (1 << 0) -# define FP_TMDS_EN (1 << 2) -# define FP_EN_TMDS (1 << 7) -# define FP_DETECT_SENSE (1 << 8) -# define FP_SEL_CRTC2 (1 << 13) -# define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) -# define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) -# define FP_CRTC_DONT_SHADOW_HEND (1 << 17) -# define FP_CRTC_USE_SHADOW_VEND (1 << 18) -# define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) -# define FP_DFP_SYNC_SEL (1 << 21) -# define FP_CRTC_LOCK_8DOT (1 << 22) -# define FP_CRT_SYNC_SEL (1 << 23) -# define FP_USE_SHADOW_EN (1 << 24) -# define FP_CRT_SYNC_ALT (1 << 26) -#define FP2_GEN_CNTL 0x0288 -/* FP2_GEN_CNTL bit constants */ -# define FP2_FPON (1 << 0) -# define FP2_TMDS_EN (1 << 2) -# define FP2_EN_TMDS (1 << 7) -# define FP2_DETECT_SENSE (1 << 8) -# define FP2_SEL_CRTC2 (1 << 13) -# define FP2_FP_POL (1 << 16) -# define FP2_LP_POL (1 << 17) -# define FP2_SCK_POL (1 << 18) -# define FP2_LCD_CNTL_MASK (7 << 19) -# define FP2_PAD_FLOP_EN (1 << 22) -# define FP2_CRC_EN (1 << 23) -# define FP2_CRC_READ_EN (1 << 24) -#define FP_HORZ_STRETCH 0x028C -#define FP_HORZ2_STRETCH 0x038C -# define HORZ_STRETCH_RATIO_MASK 0xffff -# define HORZ_STRETCH_RATIO_MAX 4096 -# define HORZ_PANEL_SIZE (0x1ff << 16) -# define HORZ_PANEL_SHIFT 16 -# define HORZ_STRETCH_PIXREP (0 << 25) -# define HORZ_STRETCH_BLEND (1 << 26) -# define HORZ_STRETCH_ENABLE (1 << 25) -# define HORZ_AUTO_RATIO (1 << 27) -# define HORZ_FP_LOOP_STRETCH (0x7 << 28) -# define HORZ_AUTO_RATIO_INC (1 << 31) -#define FP_VERT_STRETCH 0x0290 -#define FP_VERT2_STRETCH 0x0390 -# define VERT_PANEL_SIZE (0xfff << 12) -# define VERT_PANEL_SHIFT 12 -# define VERT_STRETCH_RATIO_MASK 0xfff -# define VERT_STRETCH_RATIO_SHIFT 0 -# define VERT_STRETCH_RATIO_MAX 4096 -# define VERT_STRETCH_ENABLE (1 << 25) -# define VERT_STRETCH_LINEREP (0 << 26) -# define VERT_STRETCH_BLEND (1 << 26) -# define VERT_AUTO_RATIO_EN (1 << 27) -# define VERT_STRETCH_RESERVED 0xf1000000 -#define FP_H_SYNC_STRT_WID 0x02C4 -#define FP_H2_SYNC_STRT_WID 0x03C4 -#define FP_V_SYNC_STRT_WID 0x02C8 -#define FP_V2_SYNC_STRT_WID 0x03C8 -#define LVDS_GEN_CNTL 0x02d0 -# define LVDS_ON (1 << 0) -# define LVDS_DISPLAY_DIS (1 << 1) -# define LVDS_PANEL_TYPE (1 << 2) -# define LVDS_PANEL_FORMAT (1 << 3) -# define LVDS_EN (1 << 7) -# define LVDS_DIGON (1 << 18) -# define LVDS_BLON (1 << 19) -# define LVDS_SEL_CRTC2 (1 << 23) -#define LVDS_PLL_CNTL 0x02d4 -# define HSYNC_DELAY_SHIFT 28 -# define HSYNC_DELAY_MASK (0xf << 28) -#define AUX_WINDOW_HORZ_CNTL 0x02D8 -#define AUX_WINDOW_VERT_CNTL 0x02DC -#define DDA_CONFIG 0x02e0 -#define DDA_ON_OFF 0x02e4 - -#define GRPH_BUFFER_CNTL 0x02F0 -#define VGA_BUFFER_CNTL 0x02F4 - -/* first overlay unit (there is only one) */ - -#define OV0_Y_X_START 0x0400 -#define OV0_Y_X_END 0x0404 -#define OV0_PIPELINE_CNTL 0x0408 -#define OV0_EXCLUSIVE_HORZ 0x0408 -# define EXCL_HORZ_START_MASK 0x000000ff -# define EXCL_HORZ_END_MASK 0x0000ff00 -# define EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 -# define EXCL_HORZ_EXCLUSIVE_EN 0x80000000 -#define OV0_EXCLUSIVE_VERT 0x040C -# define EXCL_VERT_START_MASK 0x000003ff -# define EXCL_VERT_END_MASK 0x03ff0000 -#define OV0_REG_LOAD_CNTL 0x0410 -# define REG_LD_CTL_LOCK 0x00000001L -# define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L -# define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L -# define REG_LD_CTL_LOCK_READBACK 0x00000008L -#define OV0_SCALE_CNTL 0x0420 -# define SCALER_PIX_EXPAND 0x00000001L -# define SCALER_Y2R_TEMP 0x00000002L -#ifdef RAGE128 -# define SCALER_HORZ_PICK_NEAREST 0x00000003L -# define SCALER_VERT_PICK_NEAREST 0x00000004L -#else -# define SCALER_HORZ_PICK_NEAREST 0x00000004L -# define SCALER_VERT_PICK_NEAREST 0x00000008L -#endif -# define SCALER_SIGNED_UV 0x00000010L -# define SCALER_GAMMA_SEL_MASK 0x00000060L -# define SCALER_GAMMA_SEL_BRIGHT 0x00000000L -# define SCALER_GAMMA_SEL_G22 0x00000020L -# define SCALER_GAMMA_SEL_G18 0x00000040L -# define SCALER_GAMMA_SEL_G14 0x00000060L -# define SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L -# define SCALER_SURFAC_FORMAT 0x00000f00L -# define SCALER_SOURCE_UNK0 0x00000000L /* 2 bpp ??? */ -# define SCALER_SOURCE_UNK1 0x00000100L /* 4 bpp ??? */ -# define SCALER_SOURCE_UNK2 0x00000200L /* 8 bpp ??? */ -# define SCALER_SOURCE_15BPP 0x00000300L -# define SCALER_SOURCE_16BPP 0x00000400L -# define SCALER_SOURCE_24BPP 0x00000500L -# define SCALER_SOURCE_32BPP 0x00000600L -# define SCALER_SOURCE_UNK3 0x00000700L /* 8BPP_RGB332 ??? */ -# define SCALER_SOURCE_UNK4 0x00000800L /* 8BPP_Y8 ??? */ -# define SCALER_SOURCE_YUV9 0x00000900L /* 8BPP_RGB8 */ -# define SCALER_SOURCE_YUV12 0x00000A00L -# define SCALER_SOURCE_VYUY422 0x00000B00L -# define SCALER_SOURCE_YVYU422 0x00000C00L -# define SCALER_SOURCE_UNK5 0x00000D00L /* ??? */ -# define SCALER_SOURCE_UNK6 0x00000E00L /* 32BPP_AYUV444 */ -# define SCALER_SOURCE_UNK7 0x00000F00L /* 16BPP_ARGB4444 */ -# define SCALER_ADAPTIVE_DEINT 0x00001000L -# define R200_SCALER_TEMPORAL_DEINT 0x00002000L -# define SCALER_UNKNOWN_FLAG1 0x00004000L /* ??? */ -# define SCALER_SMART_SWITCH 0x00008000L -#ifdef RAGE128 -# define SCALER_BURST_PER_PLANE 0x00ff0000L -#else -# define SCALER_BURST_PER_PLANE 0x007f0000L -#endif -# define SCALER_DOUBLE_BUFFER 0x01000000L -# define SCALER_UNKNOWN_FLAG3 0x02000000L /* ??? */ -# define SCALER_UNKNOWN_FLAG4 0x04000000L /* ??? */ -# define SCALER_DIS_LIMIT 0x08000000L -# define SCALER_PRG_LOAD_START 0x10000000L -# define SCALER_INT_EMU 0x20000000L -# define SCALER_ENABLE 0x40000000L -# define SCALER_SOFT_RESET 0x80000000L -#define OV0_V_INC 0x0424 -#define OV0_P1_V_ACCUM_INIT 0x0428 -# define OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L -# define OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L -#define OV0_P23_V_ACCUM_INIT 0x042C -# define OV0_P23_MAX_LN_IN_PER_LN_OUT 0x00000003L -# define OV0_P23_V_ACCUM_INIT_MASK 0x01ff8000L -#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 -# define P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL -# define P1_ACTIVE_LINES_M1 0x0fff0000L -#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 -# define P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL -# define P23_ACTIVE_LINES_M1 0x07ff0000L -#ifndef RAGE128 -#define OV0_BASE_ADDR 0x043C -#endif -#define OV0_VID_BUF0_BASE_ADRS 0x0440 -# define VIF_BUF0_PITCH_SEL 0x00000001L -# define VIF_BUF0_TILE_ADRS 0x00000002L -# define VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L -# define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L -#define OV0_VID_BUF1_BASE_ADRS 0x0444 -# define VIF_BUF1_PITCH_SEL 0x00000001L -# define VIF_BUF1_TILE_ADRS 0x00000002L -# define VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L -# define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L -#define OV0_VID_BUF2_BASE_ADRS 0x0448 -# define VIF_BUF2_PITCH_SEL 0x00000001L -# define VIF_BUF2_TILE_ADRS 0x00000002L -# define VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L -# define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L -#define OV0_VID_BUF3_BASE_ADRS 0x044C -# define VIF_BUF3_PITCH_SEL 0x00000001L -# define VIF_BUF3_TILE_ADRS 0x00000002L -# define VIF_BUF3_BASE_ADRS_MASK 0x03fffff0L -# define VIF_BUF3_1ST_LINE_LSBS_MASK 0x48000000L -#define OV0_VID_BUF4_BASE_ADRS 0x0450 -# define VIF_BUF4_PITCH_SEL 0x00000001L -# define VIF_BUF4_TILE_ADRS 0x00000002L -# define VIF_BUF4_BASE_ADRS_MASK 0x03fffff0L -# define VIF_BUF4_1ST_LINE_LSBS_MASK 0x48000000L -#define OV0_VID_BUF5_BASE_ADRS 0x0454 -# define VIF_BUF5_PITCH_SEL 0x00000001L -# define VIF_BUF5_TILE_ADRS 0x00000002L -# define VIF_BUF5_BASE_ADRS_MASK 0x03fffff0L -# define VIF_BUF5_1ST_LINE_LSBS_MASK 0x48000000L -#define OV0_VID_BUF_PITCH0_VALUE 0x0460 -#define OV0_VID_BUF_PITCH1_VALUE 0x0464 -#define OV0_AUTO_FLIP_CNTL 0x0470 -# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 -# define OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 -# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 -# define OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 -# define OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 -# define OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 -# define OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 -# define OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 -# define OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 -# define OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 -#define OV0_DEINTERLACE_PATTERN 0x0474 -#define OV0_SUBMIT_HISTORY 0x0478 -#define OV0_H_INC 0x0480 -#define OV0_STEP_BY 0x0484 -#define OV0_P1_H_ACCUM_INIT 0x0488 -#define OV0_P23_H_ACCUM_INIT 0x048C -#define OV0_P1_X_START_END 0x0494 -#define OV0_P2_X_START_END 0x0498 -#define OV0_P3_X_START_END 0x049C -#define OV0_FILTER_CNTL 0x04A0 -# define FILTER_PROGRAMMABLE_COEF 0x00000000 -# define FILTER_HARDCODED_COEF 0x0000000F -# define FILTER_COEF_MASK 0x0000000F -/* other values allow us use hardcoded coefs for Y and - programmable for UV that's nosense. */ -/* - Top quality 4x4-tap filtered vertical and horizontal scaler. - It allows up to 64:1 upscaling and downscaling without - performance or quality degradation. -*/ -#define OV0_FOUR_TAP_COEF_0 0x04B0 -#define OV0_FOUR_TAP_COEF_1 0x04B4 -#define OV0_FOUR_TAP_COEF_2 0x04B8 -#define OV0_FOUR_TAP_COEF_3 0x04BC -#define OV0_FOUR_TAP_COEF_4 0x04C0 - -#define OV0_FLAG_CNTL 0x04DC -#ifdef RAGE128 -#define OV0_COLOUR_CNTL 0x04E0 -# define COLOUR_CNTL_BRIGHTNESS 0x0000007F -# define COLOUR_CNTL_SATURATION 0x001F1F00 -#else -/* NB: radeons have no COLOUR_CNTL register */ -#define OV0_SLICE_CNTL 0x04E0 -# define SLICE_CNTL_DISABLE 0x40000000 -#endif -/* Video and graphics keys allow alpha blending, color correction - and many other video effects */ -#define OV0_VID_KEY_CLR 0x04E4 -#define OV0_VID_KEY_MSK 0x04E8 -#define OV0_GRAPHICS_KEY_CLR 0x04EC -#define OV0_GRAPHICS_KEY_MSK 0x04F0 -#define OV0_KEY_CNTL 0x04F4 -# define VIDEO_KEY_FN_MASK 0x00000007L -# define VIDEO_KEY_FN_FALSE 0x00000000L -# define VIDEO_KEY_FN_TRUE 0x00000001L -# define VIDEO_KEY_FN_EQ 0x00000004L -# define VIDEO_KEY_FN_NE 0x00000005L -# define GRAPHIC_KEY_FN_MASK 0x00000070L -# define GRAPHIC_KEY_FN_FALSE 0x00000000L -# define GRAPHIC_KEY_FN_TRUE 0x00000010L -# define GRAPHIC_KEY_FN_EQ 0x00000040L -# define GRAPHIC_KEY_FN_NE 0x00000050L -# define CMP_MIX_MASK 0x00000100L -# define CMP_MIX_OR 0x00000000L -# define CMP_MIX_AND 0x00000100L -#define OV0_TEST 0x04F8 -#define OV0_LIN_TRANS_A 0x0D20 -#define OV0_LIN_TRANS_B 0x0D24 -#define OV0_LIN_TRANS_C 0x0D28 -#define OV0_LIN_TRANS_D 0x0D2C -#define OV0_LIN_TRANS_E 0x0D30 -#define OV0_LIN_TRANS_F 0x0D34 -#define OV0_GAMMA_0_F 0x0D40 -#define OV0_GAMMA_10_1F 0x0D44 -#define OV0_GAMMA_20_3F 0x0D48 -#define OV0_GAMMA_40_7F 0x0D4C -/* These registers exist on R200 only */ -#define OV0_GAMMA_80_BF 0x0E00 -#define OV0_GAMMA_C0_FF 0x0E04 -#define OV0_GAMMA_100_13F 0x0E08 -#define OV0_GAMMA_140_17F 0x0E0C -#define OV0_GAMMA_180_1BF 0x0E10 -#define OV0_GAMMA_1C0_1FF 0x0E14 -#define OV0_GAMMA_200_23F 0x0E18 -#define OV0_GAMMA_240_27F 0x0E1C -#define OV0_GAMMA_280_2BF 0x0E20 -#define OV0_GAMMA_2C0_2FF 0x0E24 -#define OV0_GAMMA_300_33F 0x0E28 -#define OV0_GAMMA_340_37F 0x0E2C -/* End of R200 specific definitions */ -#define OV0_GAMMA_380_3BF 0x0D50 -#define OV0_GAMMA_3C0_3FF 0x0D54 - -/* - IDCT ENGINE: - It's MPEG-2 hardware decoder which incorporates run-level decode, de-zigzag - and IDCT into an IDCT engine to complement the motion compensation engine. -*/ -#define IDCT_RUNS 0x1F80 -#define IDCT_LEVELS 0x1F84 -#define IDCT_AUTH_CONTROL 0x1F88 -#define IDCT_AUTH 0x1F8C -#define IDCT_CONTROL 0x1FBC - -#define SE_MC_SRC2_CNTL 0x19D4 -#define SE_MC_SRC1_CNTL 0x19D8 -#define SE_MC_DST_CNTL 0x19DC -#define SE_MC_CNTL_START 0x19E0 -#ifndef RAGE128 -#define SE_MC_BUF_BASE 0x19E4 -#define PP_MC_CONTEXT 0x19E8 -#define PP_MISC 0x1C14 -#endif -/* - SUBPICTURE UNIT: - Decompressing, scaling and alpha blending the compressed bitmap on the fly. - Provide optimal DVD subpicture qualtity. -*/ -#define SUBPIC_CNTL 0x0540 -#define SUBPIC_DEFCOLCON 0x0544 -#define SUBPIC_Y_X_START 0x054C -#define SUBPIC_Y_X_END 0x0550 -#define SUBPIC_V_INC 0x0554 -#define SUBPIC_H_INC 0x0558 -#define SUBPIC_BUF0_OFFSET 0x055C -#define SUBPIC_BUF1_OFFSET 0x0560 -#define SUBPIC_LC0_OFFSET 0x0564 -#define SUBPIC_LC1_OFFSET 0x0568 -#define SUBPIC_PITCH 0x056C -#define SUBPIC_BTN_HLI_COLCON 0x0570 -#define SUBPIC_BTN_HLI_Y_X_START 0x0574 -#define SUBPIC_BTN_HLI_Y_X_END 0x0578 -#define SUBPIC_PALETTE_INDEX 0x057C -#define SUBPIC_PALETTE_DATA 0x0580 -#define SUBPIC_H_ACCUM_INIT 0x0584 -#define SUBPIC_V_ACCUM_INIT 0x0588 - -#define CP_RB_BASE 0x0700 -#define CP_RB_CNTL 0x0704 -#define CP_RB_RPTR_ADDR 0x070C -#define CP_RB_RPTR 0x0710 -#define CP_RB_WPTR 0x0714 -#define CP_RB_WPTR_DELAY 0x0718 -#define CP_IB_BASE 0x0738 -#define CP_IB_BUFSZ 0x073C -#define CP_CSQ_CNTL 0x0740 -#define SCRATCH_UMSK 0x0770 -#define SCRATCH_ADDR 0x0774 -#define DMA_GUI_TABLE_ADDR 0x0780 -#define DMA_GUI_SRC_ADDR 0x0784 -#define DMA_GUI_DST_ADDR 0x0788 -#define DMA_GUI_COMMAND 0x078C -#define DMA_GUI_STATUS 0x0790 -#define DMA_GUI_ACT_DSCRPTR 0x0794 -#define DMA_VID_TABLE_ADDR 0x07A0 -#define DMA_VID_SRC_ADDR 0x07A4 -#define DMA_VID_DST_ADDR 0x07A8 -#define DMA_VID_COMMAND 0x07AC -#define DMA_VID_STATUS 0x07B0 -#define DMA_VID_ACT_DSCRPTR 0x07B4 -#define CP_ME_CNTL 0x07D0 -#define CP_ME_RAM_ADDR 0x07D4 -#define CP_ME_RAM_RADDR 0x07D8 -#define CP_ME_RAM_DATAH 0x07DC -#define CP_ME_RAM_DATAL 0x07E0 -#define CP_CSQ_ADDR 0x07F0 -#define CP_CSQ_DATA 0x07F4 -#define CP_CSQ_STAT 0x07F8 - -#define DISP_MISC_CNTL 0x0D00 -# define SOFT_RESET_GRPH_PP (1 << 0) -#define DAC_MACRO_CNTL 0x0D04 -#define DISP_PWR_MAN 0x0D08 -#define DISP_TEST_DEBUG_CNTL 0x0D10 -#define DISP_HW_DEBUG 0x0D14 -#define DAC_CRC_SIG1 0x0D18 -#define DAC_CRC_SIG2 0x0D1C - -/* first capture unit */ - -#define VID_BUFFER_CONTROL 0x0900 -#define CAP_INT_CNTL 0x0908 -#define CAP_INT_STATUS 0x090C -#define FCP_CNTL 0x0910 -#define CAP0_BUF0_OFFSET 0x0920 -#define CAP0_BUF1_OFFSET 0x0924 -#define CAP0_BUF0_EVEN_OFFSET 0x0928 -#define CAP0_BUF1_EVEN_OFFSET 0x092C -#define CAP0_BUF_PITCH 0x0930 -#define CAP0_V_WINDOW 0x0934 -#define CAP0_H_WINDOW 0x0938 -#define CAP0_VBI0_OFFSET 0x093C -#define CAP0_VBI1_OFFSET 0x0940 -#define CAP0_VBI_V_WINDOW 0x0944 -#define CAP0_VBI_H_WINDOW 0x0948 -#define CAP0_PORT_MODE_CNTL 0x094C -#define CAP0_TRIG_CNTL 0x0950 -#define CAP0_DEBUG 0x0954 -#define CAP0_CONFIG 0x0958 -# define CAP0_CONFIG_CONTINUOS 0x00000001 -# define CAP0_CONFIG_START_FIELD_EVEN 0x00000002 -# define CAP0_CONFIG_START_BUF_GET 0x00000004 -# define CAP0_CONFIG_START_BUF_SET 0x00000008 -# define CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 -# define CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 -# define CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 -# define CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 -# define CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 -# define CAP0_CONFIG_MIRROR_EN 0x00000200 -# define CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 -# define CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 -# define CAP0_CONFIG_ANC_DECODE_EN 0x00001000 -# define CAP0_CONFIG_VBI_EN 0x00002000 -# define CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 -# define CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 -# define CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 -# define CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 -# define CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 -# define CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 -# define CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 -# define CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 -# define CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 -# define CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 -# define CAP0_CONFIG_FORMAT_CCIR656 0x00800000 -# define CAP0_CONFIG_FORMAT_ZV 0x01000000 -# define CAP0_CONFIG_FORMAT_VIP 0x01800000 -# define CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 -# define CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 -# define CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 -# define CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 -# define CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 -# define CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 -#define CAP0_ANC_ODD_OFFSET 0x095C -#define CAP0_ANC_EVEN_OFFSET 0x0960 -#define CAP0_ANC_H_WINDOW 0x0964 -#define CAP0_VIDEO_SYNC_TEST 0x0968 -#define CAP0_ONESHOT_BUF_OFFSET 0x096C -#define CAP0_BUF_STATUS 0x0970 -#ifdef RAGE128 -#define CAP0_DWNSC_XRATIO 0x0978 -#define CAP0_XSHARPNESS 0x097C -#else -/* #define CAP0_DWNSC_XRATIO 0x0978 */ -/* #define CAP0_XSHARPNESS 0x097C */ -#endif -#define CAP0_VBI2_OFFSET 0x0980 -#define CAP0_VBI3_OFFSET 0x0984 -#define CAP0_ANC2_OFFSET 0x0988 -#define CAP0_ANC3_OFFSET 0x098C - -/* second capture unit */ - -#define CAP1_BUF0_OFFSET 0x0990 -#define CAP1_BUF1_OFFSET 0x0994 -#define CAP1_BUF0_EVEN_OFFSET 0x0998 -#define CAP1_BUF1_EVEN_OFFSET 0x099C - -#define CAP1_BUF_PITCH 0x09A0 -#define CAP1_V_WINDOW 0x09A4 -#define CAP1_H_WINDOW 0x09A8 -#define CAP1_VBI_ODD_OFFSET 0x09AC -#define CAP1_VBI_EVEN_OFFSET 0x09B0 -#define CAP1_VBI_V_WINDOW 0x09B4 -#define CAP1_VBI_H_WINDOW 0x09B8 -#define CAP1_PORT_MODE_CNTL 0x09BC -#define CAP1_TRIG_CNTL 0x09C0 -#define CAP1_DEBUG 0x09C4 -#define CAP1_CONFIG 0x09C8 -#define CAP1_ANC_ODD_OFFSET 0x09CC -#define CAP1_ANC_EVEN_OFFSET 0x09D0 -#define CAP1_ANC_H_WINDOW 0x09D4 -#define CAP1_VIDEO_SYNC_TEST 0x09D8 -#define CAP1_ONESHOT_BUF_OFFSET 0x09DC -#define CAP1_BUF_STATUS 0x09E0 -#define CAP1_DWNSC_XRATIO 0x09E8 -#define CAP1_XSHARPNESS 0x09EC - -#define DISP_MERGE_CNTL 0x0D60 -#define DISP_OUTPUT_CNTL 0x0D64 -# define DISP_DAC_SOURCE_MASK 0x03 -# define DISP_DAC_SOURCE_CRTC2 0x01 -#define DISP_LIN_TRANS_GRPH_A 0x0D80 -#define DISP_LIN_TRANS_GRPH_B 0x0D84 -#define DISP_LIN_TRANS_GRPH_C 0x0D88 -#define DISP_LIN_TRANS_GRPH_D 0x0D8C -#define DISP_LIN_TRANS_GRPH_E 0x0D90 -#define DISP_LIN_TRANS_GRPH_F 0x0D94 -#define DISP_LIN_TRANS_VID_A 0x0D98 -#define DISP_LIN_TRANS_VID_B 0x0D9C -#define DISP_LIN_TRANS_VID_C 0x0DA0 -#define DISP_LIN_TRANS_VID_D 0x0DA4 -#define DISP_LIN_TRANS_VID_E 0x0DA8 -#define DISP_LIN_TRANS_VID_F 0x0DAC -#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 -#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 -#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 -#define RMX_HORZ_PHASE 0x0DBC -#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 -#define DAC_BROAD_PULSE 0x0DC4 -#define DAC_SKEW_CLKS 0x0DC8 -#define DAC_INCR 0x0DCC -#define DAC_NEG_SYNC_LEVEL 0x0DD0 -#define DAC_POS_SYNC_LEVEL 0x0DD4 -#define DAC_BLANK_LEVEL 0x0DD8 -#define CLOCK_CNTL_INDEX 0x0008 -/* CLOCK_CNTL_INDEX bit constants */ -# define PLL_WR_EN 0x00000080 -# define PLL_DIV_SEL (3 << 8) -# define PLL2_DIV_SEL_MASK ~(3 << 8) -#define CLOCK_CNTL_DATA 0x000C -#define CP_RB_CNTL 0x0704 -#define CP_RB_BASE 0x0700 -#define CP_RB_RPTR_ADDR 0x070C -#define CP_RB_RPTR 0x0710 -#define CP_RB_WPTR 0x0714 -#define CP_RB_WPTR_DELAY 0x0718 -#define CP_IB_BASE 0x0738 -#define CP_IB_BUFSZ 0x073C -#define SCRATCH_REG0 0x15E0 -#define GUI_SCRATCH_REG0 0x15E0 -#define SCRATCH_REG1 0x15E4 -#define GUI_SCRATCH_REG1 0x15E4 -#define SCRATCH_REG2 0x15E8 -#define GUI_SCRATCH_REG2 0x15E8 -#define SCRATCH_REG3 0x15EC -#define GUI_SCRATCH_REG3 0x15EC -#define SCRATCH_REG4 0x15F0 -#define GUI_SCRATCH_REG4 0x15F0 -#define SCRATCH_REG5 0x15F4 -#define GUI_SCRATCH_REG5 0x15F4 -#define SCRATCH_UMSK 0x0770 -#define SCRATCH_ADDR 0x0774 -#define DP_BRUSH_FRGD_CLR 0x147C -#define DP_BRUSH_BKGD_CLR 0x1478 -#define DST_LINE_START 0x1600 -#define DST_LINE_END 0x1604 -#define SRC_OFFSET 0x15AC -#define SRC_PITCH 0x15B0 -#define SRC_TILE 0x1704 -#define SRC_PITCH_OFFSET 0x1428 -#define SRC_X 0x1414 -#define SRC_Y 0x1418 -#define DST_WIDTH_X 0x1588 -#define DST_HEIGHT_WIDTH_8 0x158C -#define SRC_X_Y 0x1590 -#define SRC_Y_X 0x1434 -#define DST_Y_X 0x1438 -#define DST_WIDTH_HEIGHT 0x1598 -#define DST_HEIGHT_WIDTH 0x143c -#define SRC_CLUT_ADDRESS 0x1780 -#define SRC_CLUT_DATA 0x1784 -#define SRC_CLUT_DATA_RD 0x1788 -#define HOST_DATA0 0x17C0 -#define HOST_DATA1 0x17C4 -#define HOST_DATA2 0x17C8 -#define HOST_DATA3 0x17CC -#define HOST_DATA4 0x17D0 -#define HOST_DATA5 0x17D4 -#define HOST_DATA6 0x17D8 -#define HOST_DATA7 0x17DC -#define HOST_DATA_LAST 0x17E0 -#define DP_SRC_ENDIAN 0x15D4 -#define DP_SRC_FRGD_CLR 0x15D8 -#define DP_SRC_BKGD_CLR 0x15DC -#define DP_WRITE_MASK 0x16cc -#define SC_LEFT 0x1640 -#define SC_RIGHT 0x1644 -#define SC_TOP 0x1648 -#define SC_BOTTOM 0x164C -#define SRC_SC_RIGHT 0x1654 -#define SRC_SC_BOTTOM 0x165C -#define DP_CNTL 0x16C0 -/* DP_CNTL bit constants */ -# define DST_X_RIGHT_TO_LEFT 0x00000000 -# define DST_X_LEFT_TO_RIGHT 0x00000001 -# define DST_Y_BOTTOM_TO_TOP 0x00000000 -# define DST_Y_TOP_TO_BOTTOM 0x00000002 -# define DST_X_MAJOR 0x00000000 -# define DST_Y_MAJOR 0x00000004 -# define DST_X_TILE 0x00000008 -# define DST_Y_TILE 0x00000010 -# define DST_LAST_PEL 0x00000020 -# define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 -# define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 -# define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 -# define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 -# define DST_BRES_SIGN 0x00000100 -# define DST_HOST_BIG_ENDIAN_EN 0x00000200 -# define DST_POLYLINE_NONLAST 0x00008000 -# define DST_RASTER_STALL 0x00010000 -# define DST_POLY_EDGE 0x00040000 -#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 -/* DP_CNTL_XDIR_YDIR_YMAJOR bit constants (short version of DP_CNTL) */ -# define DST_X_MAJOR_S 0x00000000 -# define DST_Y_MAJOR_S 0x00000001 -# define DST_Y_BOTTOM_TO_TOP_S 0x00000000 -# define DST_Y_TOP_TO_BOTTOM_S 0x00008000 -# define DST_X_RIGHT_TO_LEFT_S 0x00000000 -# define DST_X_LEFT_TO_RIGHT_S 0x80000000 -#define DP_DATATYPE 0x16C4 -/* DP_DATATYPE bit constants */ -# define DST_8BPP 0x00000002 -# define DST_15BPP 0x00000003 -# define DST_16BPP 0x00000004 -# define DST_24BPP 0x00000005 -# define DST_32BPP 0x00000006 -# define DST_8BPP_RGB332 0x00000007 -# define DST_8BPP_Y8 0x00000008 -# define DST_8BPP_RGB8 0x00000009 -# define DST_16BPP_VYUY422 0x0000000b -# define DST_16BPP_YVYU422 0x0000000c -# define DST_32BPP_AYUV444 0x0000000e -# define DST_16BPP_ARGB4444 0x0000000f -# define BRUSH_SOLIDCOLOR 0x00000d00 -# define SRC_MONO 0x00000000 -# define SRC_MONO_LBKGD 0x00010000 -# define SRC_DSTCOLOR 0x00030000 -# define BYTE_ORDER_MSB_TO_LSB 0x00000000 -# define BYTE_ORDER_LSB_TO_MSB 0x40000000 -# define DP_CONVERSION_TEMP 0x80000000 -# define HOST_BIG_ENDIAN_EN (1 << 29) -#define DP_MIX 0x16C8 -/* DP_MIX bit constants */ -# define DP_SRC_RECT 0x00000200 -# define DP_SRC_HOST 0x00000300 -# define DP_SRC_HOST_BYTEALIGN 0x00000400 -#define DP_WRITE_MSK 0x16CC -#define DP_XOP 0x17F8 -#define CLR_CMP_CLR_SRC 0x15C4 -#define CLR_CMP_CLR_DST 0x15C8 -#define CLR_CMP_CNTL 0x15C0 -/* CLR_CMP_CNTL bit constants */ -# define COMPARE_SRC_FALSE 0x00000000 -# define COMPARE_SRC_TRUE 0x00000001 -# define COMPARE_SRC_NOT_EQUAL 0x00000004 -# define COMPARE_SRC_EQUAL 0x00000005 -# define COMPARE_SRC_EQUAL_FLIP 0x00000007 -# define COMPARE_DST_FALSE 0x00000000 -# define COMPARE_DST_TRUE 0x00000100 -# define COMPARE_DST_NOT_EQUAL 0x00000400 -# define COMPARE_DST_EQUAL 0x00000500 -# define COMPARE_DESTINATION 0x00000000 -# define COMPARE_SOURCE 0x01000000 -# define COMPARE_SRC_AND_DST 0x02000000 -#define CLR_CMP_MSK 0x15CC -#define DSTCACHE_MODE 0x1710 -#define DSTCACHE_CTLSTAT 0x1714 -/* DSTCACHE_CTLSTAT bit constants */ -# define RB2D_DC_FLUSH (3 << 0) -# define RB2D_DC_FLUSH_ALL 0xf -# define RB2D_DC_BUSY (1 << 31) -#define DEFAULT_OFFSET 0x16e0 -#define DEFAULT_PITCH_OFFSET 0x16E0 -#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 -/* DEFAULT_SC_BOTTOM_RIGHT bit constants */ -# define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) -# define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) -#define DP_GUI_MASTER_CNTL 0x146C -/* DP_GUI_MASTER_CNTL bit constants */ -# define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 -# define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 -# define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 -# define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 -# define GMC_SRC_CLIP_DEFAULT 0x00000000 -# define GMC_SRC_CLIP_LEAVE 0x00000004 -# define GMC_DST_CLIP_DEFAULT 0x00000000 -# define GMC_DST_CLIP_LEAVE 0x00000008 -# define GMC_BRUSH_8x8MONO 0x00000000 -# define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 -# define GMC_BRUSH_8x1MONO 0x00000020 -# define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 -# define GMC_BRUSH_1x8MONO 0x00000040 -# define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 -# define GMC_BRUSH_32x1MONO 0x00000060 -# define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 -# define GMC_BRUSH_32x32MONO 0x00000080 -# define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 -# define GMC_BRUSH_8x8COLOR 0x000000a0 -# define GMC_BRUSH_8x1COLOR 0x000000b0 -# define GMC_BRUSH_1x8COLOR 0x000000c0 -# define GMC_BRUSH_SOLID_COLOR 0x000000d0 -# define GMC_DST_8BPP 0x00000200 -# define GMC_DST_15BPP 0x00000300 -# define GMC_DST_16BPP 0x00000400 -# define GMC_DST_24BPP 0x00000500 -# define GMC_DST_32BPP 0x00000600 -# define GMC_DST_8BPP_RGB332 0x00000700 -# define GMC_DST_8BPP_Y8 0x00000800 -# define GMC_DST_8BPP_RGB8 0x00000900 -# define GMC_DST_16BPP_VYUY422 0x00000b00 -# define GMC_DST_16BPP_YVYU422 0x00000c00 -# define GMC_DST_32BPP_AYUV444 0x00000e00 -# define GMC_DST_16BPP_ARGB4444 0x00000f00 -# define GMC_SRC_MONO 0x00000000 -# define GMC_SRC_MONO_LBKGD 0x00001000 -# define GMC_SRC_DSTCOLOR 0x00003000 -# define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 -# define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 -# define GMC_DP_CONVERSION_TEMP_9300 0x00008000 -# define GMC_DP_CONVERSION_TEMP_6500 0x00000000 -# define GMC_DP_SRC_RECT 0x02000000 -# define GMC_DP_SRC_HOST 0x03000000 -# define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 -# define GMC_3D_FCN_EN_CLR 0x00000000 -# define GMC_3D_FCN_EN_SET 0x08000000 -# define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 -# define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 -# define GMC_AUX_CLIP_LEAVE 0x00000000 -# define GMC_AUX_CLIP_CLEAR 0x20000000 -# define GMC_WRITE_MASK_LEAVE 0x00000000 -# define GMC_WRITE_MASK_SET 0x40000000 -# define GMC_CLR_CMP_CNTL_DIS (1 << 28) -# define GMC_SRC_DATATYPE_COLOR (3 << 12) -# define ROP3_S 0x00cc0000 -# define ROP3_SRCCOPY 0x00cc0000 -# define ROP3_P 0x00f00000 -# define ROP3_PATCOPY 0x00f00000 -# define DP_SRC_SOURCE_MASK (7 << 24) -# define GMC_BRUSH_NONE (15 << 4) -# define DP_SRC_SOURCE_MEMORY (2 << 24) -# define GMC_BRUSH_SOLIDCOLOR 0x000000d0 -#define SC_TOP_LEFT 0x16EC -#define SC_BOTTOM_RIGHT 0x16F0 -#define SRC_SC_BOTTOM_RIGHT 0x16F4 -#define RB2D_DSTCACHE_CTLSTAT 0x342C -#define RB2D_DSTCACHE_MODE 0x3428 - -#define BASE_CODE 0x0f0b -#define RADEON_BIOS_0_SCRATCH 0x0010 -#define RADEON_BIOS_1_SCRATCH 0x0014 -#define RADEON_BIOS_2_SCRATCH 0x0018 -#define RADEON_BIOS_3_SCRATCH 0x001c -#define RADEON_BIOS_4_SCRATCH 0x0020 -#define RADEON_BIOS_5_SCRATCH 0x0024 -#define RADEON_BIOS_6_SCRATCH 0x0028 -#define RADEON_BIOS_7_SCRATCH 0x002c - - -#define CLK_PIN_CNTL 0x0001 -#define PPLL_CNTL 0x0002 -# define PPLL_RESET (1 << 0) -# define PPLL_SLEEP (1 << 1) -# define PPLL_ATOMIC_UPDATE_EN (1 << 16) -# define PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) -# define PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) -#define PPLL_REF_DIV 0x0003 -# define PPLL_REF_DIV_MASK 0x03ff -# define PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ -# define PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ -#define PPLL_DIV_0 0x0004 -#define PPLL_DIV_1 0x0005 -#define PPLL_DIV_2 0x0006 -#define PPLL_DIV_3 0x0007 -#define VCLK_ECP_CNTL 0x0008 -#define HTOTAL_CNTL 0x0009 -#define HTOTAL2_CNTL 0x002e /* PLL */ -#define M_SPLL_REF_FB_DIV 0x000a -#define AGP_PLL_CNTL 0x000b -#define SPLL_CNTL 0x000c -#define SCLK_CNTL 0x000d -#define MPLL_CNTL 0x000e -#define MCLK_CNTL 0x0012 -/* MCLK_CNTL bit constants */ -# define FORCEON_MCLKA (1 << 16) -# define FORCEON_MCLKB (1 << 17) -# define FORCEON_YCLKA (1 << 18) -# define FORCEON_YCLKB (1 << 19) -# define FORCEON_MC (1 << 20) -# define FORCEON_AIC (1 << 21) -#define PLL_TEST_CNTL 0x0013 -#define P2PLL_CNTL 0x002a /* P2PLL */ -# define P2PLL_RESET (1 << 0) -# define P2PLL_SLEEP (1 << 1) -# define P2PLL_ATOMIC_UPDATE_EN (1 << 16) -# define P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) -# define P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) -#define P2PLL_DIV_0 0x002c -# define P2PLL_FB0_DIV_MASK 0x07ff -# define P2PLL_POST0_DIV_MASK 0x00070000 -#define P2PLL_REF_DIV 0x002B /* PLL */ -# define P2PLL_REF_DIV_MASK 0x03ff -# define P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ -# define P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ - -/* masks */ - -#define CONFIG_MEMSIZE_MASK 0x1f000000 -#define MEM_CFG_TYPE 0x40000000 -#define DST_OFFSET_MASK 0x003fffff -#define DST_PITCH_MASK 0x3fc00000 -#define DEFAULT_TILE_MASK 0xc0000000 -#define PPLL_DIV_SEL_MASK 0x00000300 -#define PPLL_FB3_DIV_MASK 0x000007ff -#define PPLL_POST3_DIV_MASK 0x00070000 - -#define GUI_ACTIVE 0x80000000 - -/* GEN_RESET_CNTL bit constants */ -#define SOFT_RESET_GUI 0x00000001 -#define SOFT_RESET_VCLK 0x00000100 -#define SOFT_RESET_PCLK 0x00000200 -#define SOFT_RESET_ECP 0x00000400 -#define SOFT_RESET_DISPENG_XCLK 0x00000800 - -/* RAGE THEATER REGISTERS */ - -#define DMA_VIPH0_COMMAND 0x0A00 -#define DMA_VIPH1_COMMAND 0x0A04 -#define DMA_VIPH2_COMMAND 0x0A08 -#define DMA_VIPH3_COMMAND 0x0A0C -#define DMA_VIPH_STATUS 0x0A10 -#define DMA_VIPH_CHUNK_0 0x0A18 -#define DMA_VIPH_CHUNK_1_VAL 0x0A1C -#define DMA_VIP0_TABLE_ADDR 0x0A20 -#define DMA_VIPH0_ACTIVE 0x0A24 -#define DMA_VIP1_TABLE_ADDR 0x0A30 -#define DMA_VIPH1_ACTIVE 0x0A34 -#define DMA_VIP2_TABLE_ADDR 0x0A40 -#define DMA_VIPH2_ACTIVE 0x0A44 -#define DMA_VIP3_TABLE_ADDR 0x0A50 -#define DMA_VIPH3_ACTIVE 0x0A54 -#define DMA_VIPH_ABORT 0x0A88 - -#define VIPH_CH0_DATA 0x0c00 -#define VIPH_CH1_DATA 0x0c04 -#define VIPH_CH2_DATA 0x0c08 -#define VIPH_CH3_DATA 0x0c0c -#define VIPH_CH0_ADDR 0x0c10 -#define VIPH_CH1_ADDR 0x0c14 -#define VIPH_CH2_ADDR 0x0c18 -#define VIPH_CH3_ADDR 0x0c1c -#define VIPH_CH0_SBCNT 0x0c20 -#define VIPH_CH1_SBCNT 0x0c24 -#define VIPH_CH2_SBCNT 0x0c28 -#define VIPH_CH3_SBCNT 0x0c2c -#define VIPH_CH0_ABCNT 0x0c30 -#define VIPH_CH1_ABCNT 0x0c34 -#define VIPH_CH2_ABCNT 0x0c38 -#define VIPH_CH3_ABCNT 0x0c3c -#define VIPH_CONTROL 0x0c40 -#define VIPH_DV_LAT 0x0c44 -#define VIPH_BM_CHUNK 0x0c48 -#define VIPH_DV_INT 0x0c4c -#define VIPH_TIMEOUT_STAT 0x0c50 - -#define VIPH_REG_DATA 0x0084 -#define VIPH_REG_ADDR 0x0080 - -/* Address Space Rage Theatre Registers (VIP Access) */ -#define VIP_VIP_VENDOR_DEVICE_ID 0x0000 -#define VIP_VIP_SUB_VENDOR_DEVICE_ID 0x0004 -#define VIP_VIP_COMMAND_STATUS 0x0008 -#define VIP_VIP_REVISION_ID 0x000c -#define VIP_HW_DEBUG 0x0010 -#define VIP_SW_SCRATCH 0x0014 -#define VIP_I2C_CNTL_0 0x0020 -#define VIP_I2C_CNTL_1 0x0024 -#define VIP_I2C_DATA 0x0028 -#define VIP_INT_CNTL 0x002c -#define VIP_GPIO_INOUT 0x0030 -#define VIP_GPIO_CNTL 0x0034 -#define VIP_CLKOUT_GPIO_CNTL 0x0038 -#define VIP_RIPINTF_PORT_CNTL 0x003c -#define VIP_ADC_CNTL 0x0400 -#define VIP_ADC_DEBUG 0x0404 -#define VIP_STANDARD_SELECT 0x0408 -#define VIP_THERMO2BIN_STATUS 0x040c -#define VIP_COMB_CNTL0 0x0440 -#define VIP_COMB_CNTL1 0x0444 -#define VIP_COMB_CNTL2 0x0448 -#define VIP_COMB_LINE_LENGTH 0x044c -#define VIP_NOISE_CNTL0 0x0450 -#define VIP_HS_PLINE 0x0480 -#define VIP_HS_DTOINC 0x0484 -#define VIP_HS_PLLGAIN 0x0488 -#define VIP_HS_MINMAXWIDTH 0x048c -#define VIP_HS_GENLOCKDELAY 0x0490 -#define VIP_HS_WINDOW_LIMIT 0x0494 -#define VIP_HS_WINDOW_OC_SPEED 0x0498 -#define VIP_HS_PULSE_WIDTH 0x049c -#define VIP_HS_PLL_ERROR 0x04a0 -#define VIP_HS_PLL_FS_PATH 0x04a4 -#define VIP_SG_BLACK_GATE 0x04c0 -#define VIP_SG_SYNCTIP_GATE 0x04c4 -#define VIP_SG_UVGATE_GATE 0x04c8 -#define VIP_LP_AGC_CLAMP_CNTL0 0x0500 -#define VIP_LP_AGC_CLAMP_CNTL1 0x0504 -#define VIP_LP_BRIGHTNESS 0x0508 -#define VIP_LP_CONTRAST 0x050c -#define VIP_LP_SLICE_LIMIT 0x0510 -#define VIP_LP_WPA_CNTL0 0x0514 -#define VIP_LP_WPA_CNTL1 0x0518 -#define VIP_LP_BLACK_LEVEL 0x051c -#define VIP_LP_SLICE_LEVEL 0x0520 -#define VIP_LP_SYNCTIP_LEVEL 0x0524 -#define VIP_LP_VERT_LOCKOUT 0x0528 -#define VIP_VS_DETECTOR_CNTL 0x0540 -#define VIP_VS_BLANKING_CNTL 0x0544 -#define VIP_VS_FIELD_ID_CNTL 0x0548 -#define VIP_VS_COUNTER_CNTL 0x054c -#define VIP_VS_FRAME_TOTAL 0x0550 -#define VIP_VS_LINE_COUNT 0x0554 -#define VIP_CP_PLL_CNTL0 0x0580 -#define VIP_CP_PLL_CNTL1 0x0584 -#define VIP_CP_HUE_CNTL 0x0588 -#define VIP_CP_BURST_GAIN 0x058c -#define VIP_CP_AGC_CNTL 0x0590 -#define VIP_CP_ACTIVE_GAIN 0x0594 -#define VIP_CP_PLL_STATUS0 0x0598 -#define VIP_CP_PLL_STATUS1 0x059c -#define VIP_CP_PLL_STATUS2 0x05a0 -#define VIP_CP_PLL_STATUS3 0x05a4 -#define VIP_CP_PLL_STATUS4 0x05a8 -#define VIP_CP_PLL_STATUS5 0x05ac -#define VIP_CP_PLL_STATUS6 0x05b0 -#define VIP_CP_PLL_STATUS7 0x05b4 -#define VIP_CP_DEBUG_FORCE 0x05b8 -#define VIP_CP_VERT_LOCKOUT 0x05bc -#define VIP_H_ACTIVE_WINDOW 0x05c0 -#define VIP_V_ACTIVE_WINDOW 0x05c4 -#define VIP_H_VBI_WINDOW 0x05c8 -#define VIP_V_VBI_WINDOW 0x05cc -#define VIP_VBI_CONTROL 0x05d0 -#define VIP_DECODER_DEBUG_CNTL 0x05d4 -#define VIP_SINGLE_STEP_DATA 0x05d8 -#define VIP_MASTER_CNTL 0x0040 -#define VIP_RGB_CNTL 0x0048 -#define VIP_CLKOUT_CNTL 0x004c -#define VIP_SYNC_CNTL 0x0050 -#define VIP_I2C_CNTL 0x0054 -#define VIP_HTOTAL 0x0080 -#define VIP_HDISP 0x0084 -#define VIP_HSIZE 0x0088 -#define VIP_HSTART 0x008c -#define VIP_HCOUNT 0x0090 -#define VIP_VTOTAL 0x0094 -#define VIP_VDISP 0x0098 -#define VIP_VCOUNT 0x009c -#define VIP_VFTOTAL 0x00a0 -#define VIP_DFCOUNT 0x00a4 -#define VIP_DFRESTART 0x00a8 -#define VIP_DHRESTART 0x00ac -#define VIP_DVRESTART 0x00b0 -#define VIP_SYNC_SIZE 0x00b4 -#define VIP_TV_PLL_FINE_CNTL 0x00b8 -#define VIP_CRT_PLL_FINE_CNTL 0x00bc -#define VIP_TV_PLL_CNTL 0x00c0 -#define VIP_CRT_PLL_CNTL 0x00c4 -#define VIP_PLL_CNTL0 0x00c8 -#define VIP_PLL_TEST_CNTL 0x00cc -#define VIP_CLOCK_SEL_CNTL 0x00d0 -#define VIP_VIN_PLL_CNTL 0x00d4 -#define VIP_VIN_PLL_FINE_CNTL 0x00d8 -#define VIP_AUD_PLL_CNTL 0x00e0 -#define VIP_AUD_PLL_FINE_CNTL 0x00e4 -#define VIP_AUD_CLK_DIVIDERS 0x00e8 -#define VIP_AUD_DTO_INCREMENTS 0x00ec -#define VIP_L54_PLL_CNTL 0x00f0 -#define VIP_L54_PLL_FINE_CNTL 0x00f4 -#define VIP_L54_DTO_INCREMENTS 0x00f8 -#define VIP_PLL_CNTL1 0x00fc -#define VIP_FRAME_LOCK_CNTL 0x0100 -#define VIP_SYNC_LOCK_CNTL 0x0104 -#define VIP_TVO_SYNC_PAT_ACCUM 0x0108 -#define VIP_TVO_SYNC_THRESHOLD 0x010c -#define VIP_TVO_SYNC_PAT_EXPECT 0x0110 -#define VIP_DELAY_ONE_MAP_A 0x0114 -#define VIP_DELAY_ONE_MAP_B 0x0118 -#define VIP_DELAY_ZERO_MAP_A 0x011c -#define VIP_DELAY_ZERO_MAP_B 0x0120 -#define VIP_TVO_DATA_DELAY_A 0x0140 -#define VIP_TVO_DATA_DELAY_B 0x0144 -#define VIP_HOST_READ_DATA 0x0180 -#define VIP_HOST_WRITE_DATA 0x0184 -#define VIP_HOST_RD_WT_CNTL 0x0188 -#define VIP_VSCALER_CNTL1 0x01c0 -#define VIP_TIMING_CNTL 0x01c4 -#define VIP_VSCALER_CNTL2 0x01c8 -#define VIP_Y_FALL_CNTL 0x01cc -#define VIP_Y_RISE_CNTL 0x01d0 -#define VIP_Y_SAW_TOOTH_CNTL 0x01d4 -#define VIP_UPSAMP_AND_GAIN_CNTL 0x01e0 -#define VIP_GAIN_LIMIT_SETTINGS 0x01e4 -#define VIP_LINEAR_GAIN_SETTINGS 0x01e8 -#define VIP_MODULATOR_CNTL1 0x0200 -#define VIP_MODULATOR_CNTL2 0x0204 -#define VIP_MV_MODE_CNTL 0x0208 -#define VIP_MV_STRIPE_CNTL 0x020c -#define VIP_MV_LEVEL_CNTL1 0x0210 -#define VIP_MV_LEVEL_CNTL2 0x0214 -#define VIP_PRE_DAC_MUX_CNTL 0x0240 -#define VIP_TV_DAC_CNTL 0x0280 -#define VIP_CRC_CNTL 0x02c0 -#define VIP_VIDEO_PORT_SIG 0x02c4 -#define VIP_VBI_CC_CNTL 0x02c8 -#define VIP_VBI_EDS_CNTL 0x02cc -#define VIP_VBI_20BIT_CNTL 0x02d0 -#define VIP_VBI_DTO_CNTL 0x02d4 -#define VIP_VBI_LEVEL_CNTL 0x02d8 -#define VIP_UV_ADR 0x0300 -#define VIP_MV_STATUS 0x0330 -#define VIP_UPSAMP_COEFF0_0 0x0340 -#define VIP_UPSAMP_COEFF0_1 0x0344 -#define VIP_UPSAMP_COEFF0_2 0x0348 -#define VIP_UPSAMP_COEFF1_0 0x034c -#define VIP_UPSAMP_COEFF1_1 0x0350 -#define VIP_UPSAMP_COEFF1_2 0x0354 -#define VIP_UPSAMP_COEFF2_0 0x0358 -#define VIP_UPSAMP_COEFF2_1 0x035c -#define VIP_UPSAMP_COEFF2_2 0x0360 -#define VIP_UPSAMP_COEFF3_0 0x0364 -#define VIP_UPSAMP_COEFF3_1 0x0368 -#define VIP_UPSAMP_COEFF3_2 0x036c -#define VIP_UPSAMP_COEFF4_0 0x0370 -#define VIP_UPSAMP_COEFF4_1 0x0374 -#define VIP_UPSAMP_COEFF4_2 0x0378 -#define VIP_TV_DTO_INCREMENTS 0x0390 -#define VIP_CRT_DTO_INCREMENTS 0x0394 -#define VIP_VSYNC_DIFF_CNTL 0x03a0 -#define VIP_VSYNC_DIFF_LIMITS 0x03a4 -#define VIP_VSYNC_DIFF_RD_DATA 0x03a8 -#define VIP_SCALER_IN_WINDOW 0x0618 -#define VIP_SCALER_OUT_WINDOW 0x061c -#define VIP_H_SCALER_CONTROL 0x0600 -#define VIP_V_SCALER_CONTROL 0x0604 -#define VIP_V_DEINTERLACE_CONTROL 0x0608 -#define VIP_VBI_SCALER_CONTROL 0x060c -#define VIP_DVS_PORT_CTRL 0x0610 -#define VIP_DVS_PORT_READBACK 0x0614 -#define VIP_FIFOA_CONFIG 0x0800 -#define VIP_FIFOB_CONFIG 0x0804 -#define VIP_FIFOC_CONFIG 0x0808 -#define VIP_SPDIF_PORT_CNTL 0x080c -#define VIP_SPDIF_CHANNEL_STAT 0x0810 -#define VIP_SPDIF_AC3_PREAMBLE 0x0814 -#define VIP_I2S_TRANSMIT_CNTL 0x0818 -#define VIP_I2S_RECEIVE_CNTL 0x081c -#define VIP_SPDIF_TX_CNT_REG 0x0820 -#define VIP_IIS_TX_CNT_REG 0x0824 - -/* Status defines */ -#define VIP_BUSY 0 -#define VIP_IDLE 1 -#define VIP_RESET 2 - -#define VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 -#define VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 -#define VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 -#define TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 - -#define RT_ATI_ID 0x4D541002 - -/* Register/Field values: */ -#define RT_COMP0 0x0 -#define RT_COMP1 0x1 -#define RT_COMP2 0x2 -#define RT_YF_COMP3 0x3 -#define RT_YR_COMP3 0x4 -#define RT_YCF_COMP4 0x5 -#define RT_YCR_COMP4 0x6 - -/* Video standard defines */ -#define RT_NTSC 0x0 -#define RT_PAL 0x1 -#define RT_SECAM 0x2 -#define extNONE 0x0000 -#define extNTSC 0x0100 -#define extRsvd 0x0200 -#define extPAL 0x0300 -#define extPAL_M 0x0400 -#define extPAL_N 0x0500 -#define extSECAM 0x0600 -#define extPAL_NCOMB 0x0700 -#define extNTSC_J 0x0800 -#define extNTSC_443 0x0900 -#define extPAL_BGHI 0x0A00 -#define extPAL_60 0x0B00 - /* these are used in MSP3430 */ -#define extPAL_DK1 0x0C00 -#define extPAL_AUTO 0x0D00 - -#define RT_FREF_2700 6 -#define RT_FREF_2950 5 - -#define RT_COMPOSITE 0x0 -#define RT_SVIDEO 0x1 - -#define RT_NORM_SHARPNESS 0x03 -#define RT_HIGH_SHARPNESS 0x0F - -#define RT_HUE_PAL_DEF 0x00 - -#define RT_DECINTERLACED 0x1 -#define RT_DECNONINTERLACED 0x0 - -#define NTSC_LINES 525 -#define PAL_SECAM_LINES 625 - -#define RT_ASYNC_ENABLE 0x0 -#define RT_ASYNC_DISABLE 0x1 -#define RT_ASYNC_RESET 0x1 - -#define RT_VINRST_ACTIVE 0x0 -#define RT_VINRST_RESET 0x1 -#define RT_L54RST_RESET 0x1 - -#define RT_REF_CLK 0x0 -#define RT_PLL_VIN_CLK 0x1 - -#define RT_VIN_ASYNC_RST 0x20 -#define RT_DVS_ASYNC_RST 0x80 - -#define RT_ADC_ENABLE 0x0 -#define RT_ADC_DISABLE 0x1 - -#define RT_DVSDIR_IN 0x0 -#define RT_DVSDIR_OUT 0x1 - -#define RT_DVSCLK_HIGH 0x0 -#define RT_DVSCLK_LOW 0x1 - -#define RT_DVSCLK_SEL_8FS 0x0 -#define RT_DVSCLK_SEL_27MHZ 0x1 - -#define RT_DVS_CONTSTREAM 0x1 -#define RT_DVS_NONCONTSTREAM 0x0 - -#define RT_DVSDAT_HIGH 0x0 -#define RT_DVSDAT_LOW 0x1 - -#define RT_ADC_CNTL_DEFAULT 0x03252338 - -/* COMB_CNTL0 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ -#define RT_NTSCM_COMB_CNTL0_COMPOSITE 0x09438090 -#define RT_NTSCM_COMB_CNTL0_SVIDEO 0x48540000 - -#define RT_PAL_COMB_CNTL0_COMPOSITE 0x09438090 -#define RT_PAL_COMB_CNTL0_SVIDEO 0x40348090 - -#define RT_SECAM_COMB_CNTL0_COMPOSITE 0xD0108090 /* instead of orig 0xD0088090 - eric*/ -#define RT_SECAM_COMB_CNTL0_SVIDEO 0x50148090 - -#define RT_PALN_COMB_CNTL0_COMPOSITE 0x09438090 -#define RT_PALN_COMB_CNTL0_SVIDEO 0x40348090 - -#define RT_PALM_COMB_CNTL0_COMPOSITE 0x09438090 -#define RT_PALM_COMB_CNTL0_SVIDEO 0x40348090 -/* End of filter settings. */ - -/* COMB_CNTL1 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ -#define RT_NTSCM_COMB_CNTL1_COMPOSITE 0x00000010 -#define RT_NTSCM_COMB_CNTL1_SVIDEO 0x00000081 - -#define RT_PAL_COMB_CNTL1_COMPOSITE 0x00000010 -#define RT_PAL_COMB_CNTL1_SVIDEO 0x000000A1 - -#define RT_SECAM_COMB_CNTL1_COMPOSITE 0x00000091 -#define RT_SECAM_COMB_CNTL1_SVIDEO 0x00000081 - -#define RT_PALN_COMB_CNTL1_COMPOSITE 0x00000010 -#define RT_PALN_COMB_CNTL1_SVIDEO 0x000000A1 - -#define RT_PALM_COMB_CNTL1_COMPOSITE 0x00000010 -#define RT_PALM_COMB_CNTL1_SVIDEO 0x000000A1 -/* End of filter settings. */ - -/* COMB_CNTL2 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ -#define RT_NTSCM_COMB_CNTL2_COMPOSITE 0x16161010 -#define RT_NTSCM_COMB_CNTL2_SVIDEO 0xFFFFFFFF - -#define RT_PAL_COMB_CNTL2_COMPOSITE 0x06080102 /* instead of 0x16161010 - Ivo */ -#define RT_PAL_COMB_CNTL2_SVIDEO 0x06080102 - -#define RT_SECAM_COMB_CNTL2_COMPOSITE 0xffffffff /* instead of 0x06080102 - eric */ -#define RT_SECAM_COMB_CNTL2_SVIDEO 0x06080102 - -#define RT_PALN_COMB_CNTL2_COMPOSITE 0x06080102 -#define RT_PALN_COMB_CNTL2_SVIDEO 0x06080102 - -#define RT_PALM_COMB_CNTL2_COMPOSITE 0x06080102 -#define RT_PALM_COMB_CNTL2_SVIDEO 0x06080102 -/* End of filter settings. */ - -/* COMB_LINE_LENGTH FILTER SETTINGS FOR DIFFERENT STANDARDS: */ -#define RT_NTSCM_COMB_LENGTH_COMPOSITE 0x0718038A -#define RT_NTSCM_COMB_LENGTH_SVIDEO 0x0718038A - -#define RT_PAL_COMB_LENGTH_COMPOSITE 0x08DA046B -#define RT_PAL_COMB_LENGTH_SVIDEO 0x08DA046B - -#define RT_SECAM_COMB_LENGTH_COMPOSITE 0x08DA046A -#define RT_SECAM_COMB_LENGTH_SVIDEO 0x08DA046A - -#define RT_PALN_COMB_LENGTH_COMPOSITE 0x07260391 -#define RT_PALN_COMB_LENGTH_SVIDEO 0x07260391 - -#define RT_PALM_COMB_LENGTH_COMPOSITE 0x07160389 -#define RT_PALM_COMB_LENGTH_SVIDEO 0x07160389 -/* End of filter settings. */ - -/* LP_AGC_CLAMP_CNTL0 */ -#define RT_NTSCM_SYNCTIP_REF0 0x00000037 -#define RT_NTSCM_SYNCTIP_REF1 0x00000029 -#define RT_NTSCM_CLAMP_REF 0x0000003B -#define RT_NTSCM_PEAKWHITE 0x000000FF -#define RT_NTSCM_VBI_PEAKWHITE 0x000000C2 - -#define RT_NTSCM_WPA_THRESHOLD 0x00000406 -#define RT_NTSCM_WPA_TRIGGER_LO 0x000000B3 - -#define RT_NTSCM_WPA_TRIGGER_HIGH 0x0000021B - -#define RT_NTSCM_LP_LOCKOUT_START 0x00000206 -#define RT_NTSCM_LP_LOCKOUT_END 0x00000021 -#define RT_NTSCM_CH_DTO_INC 0x00400000 -#define RT_NTSCM_CH_PLL_SGAIN 0x00000001 -#define RT_NTSCM_CH_PLL_FGAIN 0x00000002 - -#define RT_NTSCM_CR_BURST_GAIN 0x0000007A -#define RT_NTSCM_CB_BURST_GAIN 0x000000AC - -#define RT_NTSCM_CH_HEIGHT 0x000000CD -#define RT_NTSCM_CH_KILL_LEVEL 0x000000C0 -#define RT_NTSCM_CH_AGC_ERROR_LIM 0x00000002 -#define RT_NTSCM_CH_AGC_FILTER_EN 0x00000000 -#define RT_NTSCM_CH_AGC_LOOP_SPEED 0x00000000 - -#define RT_NTSCM_CRDR_ACTIVE_GAIN 0x0000007A -#define RT_NTSCM_CBDB_ACTIVE_GAIN 0x000000AC - -#define RT_NTSCM_VERT_LOCKOUT_START 0x00000207 -#define RT_NTSCM_VERT_LOCKOUT_END 0x0000000E - -#define RT_NTSCJ_SYNCTIP_REF0 0x00000004 -#define RT_NTSCJ_SYNCTIP_REF1 0x00000012 -#define RT_NTSCJ_CLAMP_REF 0x0000003B -#define RT_NTSCJ_PEAKWHITE 0x000000CB -#define RT_NTSCJ_VBI_PEAKWHITE 0x000000C2 -#define RT_NTSCJ_WPA_THRESHOLD 0x000004B0 -#define RT_NTSCJ_WPA_TRIGGER_LO 0x000000B4 -#define RT_NTSCJ_WPA_TRIGGER_HIGH 0x0000021C -#define RT_NTSCJ_LP_LOCKOUT_START 0x00000206 -#define RT_NTSCJ_LP_LOCKOUT_END 0x00000021 - -#define RT_NTSCJ_CR_BURST_GAIN 0x00000071 -#define RT_NTSCJ_CB_BURST_GAIN 0x0000009F -#define RT_NTSCJ_CH_HEIGHT 0x000000CD -#define RT_NTSCJ_CH_KILL_LEVEL 0x000000C0 -#define RT_NTSCJ_CH_AGC_ERROR_LIM 0x00000002 -#define RT_NTSCJ_CH_AGC_FILTER_EN 0x00000000 -#define RT_NTSCJ_CH_AGC_LOOP_SPEED 0x00000000 - -#define RT_NTSCJ_CRDR_ACTIVE_GAIN 0x00000071 -#define RT_NTSCJ_CBDB_ACTIVE_GAIN 0x0000009F -#define RT_NTSCJ_VERT_LOCKOUT_START 0x00000207 -#define RT_NTSCJ_VERT_LOCKOUT_END 0x0000000E - -#define RT_PAL_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ -#define RT_PAL_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ -#define RT_PAL_CLAMP_REF 0x0000003B -#define RT_PAL_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ -#define RT_PAL_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ -#define RT_PAL_WPA_THRESHOLD 0x59C /* instead of 0x000006A4 - Ivo */ - -#define RT_PAL_WPA_TRIGGER_LO 0x00000096 -#define RT_PAL_WPA_TRIGGER_HIGH 0x000001C2 -#define RT_PAL_LP_LOCKOUT_START 0x00000263 -#define RT_PAL_LP_LOCKOUT_END 0x0000002C - -#define RT_PAL_CH_DTO_INC 0x00400000 -#define RT_PAL_CH_PLL_SGAIN 1 /* instead of 0x00000002 - Ivo */ -#define RT_PAL_CH_PLL_FGAIN 2 /* instead of 0x00000001 - Ivo */ -#define RT_PAL_CR_BURST_GAIN 0x0000007A -#define RT_PAL_CB_BURST_GAIN 0x000000AB -#define RT_PAL_CH_HEIGHT 0x0000009C -#define RT_PAL_CH_KILL_LEVEL 4 /* instead of 0x00000090 - Ivo */ -#define RT_PAL_CH_AGC_ERROR_LIM 1 /* instead of 0x00000002 - Ivo */ -#define RT_PAL_CH_AGC_FILTER_EN 1 /* instead of 0x00000000 - Ivo */ -#define RT_PAL_CH_AGC_LOOP_SPEED 0x00000000 - -#define RT_PAL_CRDR_ACTIVE_GAIN 0x9E /* instead of 0x0000007A - Ivo */ -#define RT_PAL_CBDB_ACTIVE_GAIN 0xDF /* instead of 0x000000AB - Ivo */ -#define RT_PAL_VERT_LOCKOUT_START 0x00000269 -#define RT_PAL_VERT_LOCKOUT_END 0x00000012 - -#define RT_SECAM_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ -#define RT_SECAM_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ -#define RT_SECAM_CLAMP_REF 0x0000003B -#define RT_SECAM_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ -#define RT_SECAM_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ -#define RT_SECAM_WPA_THRESHOLD 0x57A /* instead of 0x6A4, instead of 0x0000059C is Ivo's value , -eric*/ - -#define RT_SECAM_WPA_TRIGGER_LO 0x96 /* instead of 0x0000026B - eric */ -#define RT_SECAM_WPA_TRIGGER_HIGH 0x000001C2 -#define RT_SECAM_LP_LOCKOUT_START 0x263 /* instead of 0x0000026B - eric */ -#define RT_SECAM_LP_LOCKOUT_END 0x2b /* instead of 0x0000002C -eric */ - -#define RT_SECAM_CH_DTO_INC 0x003E7A28 -#define RT_SECAM_CH_PLL_SGAIN 0x4 /* instead of 0x00000006 -Volodya */ -#define RT_SECAM_CH_PLL_FGAIN 0x7 /* instead of 0x00000006 -Volodya */ - -#define RT_SECAM_CR_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ -#define RT_SECAM_CB_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ -#define RT_SECAM_CH_HEIGHT 0x00000066 -#define RT_SECAM_CH_KILL_LEVEL 0x00000060 -#define RT_SECAM_CH_AGC_ERROR_LIM 0x00000003 -#define RT_SECAM_CH_AGC_FILTER_EN 0x00000000 -#define RT_SECAM_CH_AGC_LOOP_SPEED 0x00000000 - -#define RT_SECAM_CRDR_ACTIVE_GAIN 0x11B /* instead of 0x00000200 - eric */ -#define RT_SECAM_CBDB_ACTIVE_GAIN 0x15A /* instead of 0x00000200 - eric */ -#define RT_SECAM_VERT_LOCKOUT_START 0x00000269 -#define RT_SECAM_VERT_LOCKOUT_END 0x00000012 - -#define RT_PAL_VS_FIELD_BLANK_END 0x2A /* instead of 0x0000002C - Ivo*/ -#define RT_NTSCM_VS_FIELD_BLANK_END 0x0000000A - -#define RT_NTSCM_FIELD_IDLOCATION 0x00000105 -#define RT_PAL_FIELD_IDLOCATION 0x00000137 - -#define RT_NTSCM_H_ACTIVE_START 0x00000070 -#define RT_NTSCM_H_ACTIVE_END 0x00000363 - -#define RT_PAL_H_ACTIVE_START 0x0000009A -#define RT_PAL_H_ACTIVE_END 0x00000439 - -#define RT_NTSCM_V_ACTIVE_START ((22-4)*2+1) -#define RT_NTSCM_V_ACTIVE_END ((22+240-4)*2+1) - -#define RT_PAL_V_ACTIVE_START 0x2E /* instead of 0x00000023 (Same as SECAM) - Ivo */ -#define RT_PAL_V_ACTIVE_END 0x269 /* instead of 0x00000262 - Ivo */ - -/* VBI */ -#define RT_NTSCM_H_VBI_WIND_START 0x00000049 -#define RT_NTSCM_H_VBI_WIND_END 0x00000366 - -#define RT_PAL_H_VBI_WIND_START 0x00000084 -#define RT_PAL_H_VBI_WIND_END 0x0000041F - -#define RT_NTSCM_V_VBI_WIND_START fld_V_VBI_WIND_START_def -#define RT_NTSCM_V_VBI_WIND_END fld_V_VBI_WIND_END_def - -#define RT_PAL_V_VBI_WIND_START 0x8 /* instead of 0x0000000B - Ivo */ -#define RT_PAL_V_VBI_WIND_END 0x2D /* instead of 0x00000022 - Ivo */ - -#define RT_VBI_CAPTURE_EN 0x00000001 /* Enable */ -#define RT_VBI_CAPTURE_DIS 0x00000000 /* Disable */ -#define RT_RAW_CAPTURE 0x00000002 /* Use raw Video Capture. */ - -#define RT_NTSCM_VSYNC_INT_TRIGGER 0x2AA -#define RT_PALSEM_VSYNC_INT_TRIGGER 0x353 - -#define RT_NTSCM_VSYNC_INT_HOLD 0x17 -#define RT_PALSEM_VSYNC_INT_HOLD 0x1C - -#define RT_NTSCM_VS_FIELD_BLANK_START 0x206 -#define RT_PALSEM_VS_FIELD_BLANK_START 0x26D /* instead of 0x26C - Ivo */ - -#define RT_FIELD_FLIP_EN 0x4 -#define RT_V_FIELD_FLIP_INVERTED 0x2000 - -#define RT_NTSCM_H_IN_START 0x70 -#define RT_PAL_H_IN_START 154 /* instead of 144 - Ivo */ -#define RT_SECAM_H_IN_START 0x91 /* instead of 0x9A, Ivo value is 154, instead of 144 - Volodya, - eric */ -#define RT_NTSC_H_ACTIVE_SIZE 744 -#define RT_PAL_H_ACTIVE_SIZE 928 /* instead of 927 - Ivo */ -#define RT_SECAM_H_ACTIVE_SIZE 932 /* instead of 928, instead of 927 - Ivo, - eric */ -#define RT_NTSCM_V_IN_START (0x23) -#define RT_PAL_V_IN_START 44 /* instead of (45-6) - Ivo */ -#define RT_SECAM_V_IN_START 0x2C /* instead of (45-6) - Volodya */ -#define RT_NTSCM_V_ACTIVE_SIZE 480 -#define RT_PAL_V_ACTIVE_SIZE 572 /* instead of 575 - Ivo */ -#define RT_SECAM_V_ACTIVE_SIZE 570 /* instead of 572, instead of 575 - Ivo, - eric */ - -#define RT_NTSCM_WIN_CLOSE_LIMIT 0x4D -#define RT_NTSCJ_WIN_CLOSE_LIMIT 0x4D -#define RT_NTSC443_WIN_CLOSE_LIMIT 0x5F -#define RT_PALM_WIN_CLOSE_LIMIT 0x4D -#define RT_PALN_WIN_CLOSE_LIMIT 0x5F -#define RT_SECAM_WIN_CLOSE_LIMIT 0xC7 /* instead of 0x5F - eric */ - -#define RT_NTSCM_VS_FIELD_BLANK_START 0x206 - -#define RT_NTSCM_HS_PLL_SGAIN 0x5 -#define RT_NTSCM_HS_PLL_FGAIN 0x7 - -#define RT_NTSCM_H_OUT_WIND_WIDTH 0x2F4 -#define RT_NTSCM_V_OUT_WIND_HEIGHT 0xF0 - -#define TV 0x1 -#define LINEIN 0x2 -#define MUTE 0x3 - -#define DEC_COMPOSITE 0 -#define DEC_SVIDEO 1 -#define DEC_TUNER 2 - -#define DEC_NTSC 0 -#define DEC_PAL 1 -#define DEC_SECAM 2 -#define DEC_NTSC_J 8 - -#define DEC_SMOOTH 0 -#define DEC_SHARP 1 - -/* RT Register Field Defaults: */ -#define fld_tmpReg1_def 0x00000000 -#define fld_tmpReg2_def 0x00000001 -#define fld_tmpReg3_def 0x00000002 - -#define fld_LP_CONTRAST_def 0x0000006e -#define fld_LP_BRIGHTNESS_def 0x00003ff0 -#define fld_CP_HUE_CNTL_def 0x00000000 -#define fld_LUMA_FILTER_def 0x00000001 -#define fld_H_SCALE_RATIO_def 0x00010000 -#define fld_H_SHARPNESS_def 0x00000000 - -#define fld_V_SCALE_RATIO_def 0x00000800 -#define fld_V_DEINTERLACE_ON_def 0x00000001 -#define fld_V_BYPSS_def 0x00000000 -#define fld_V_DITHER_ON_def 0x00000001 -#define fld_EVENF_OFFSET_def 0x00000000 -#define fld_ODDF_OFFSET_def 0x00000000 - -#define fld_INTERLACE_DETECTED_def 0x00000000 - -#define fld_VS_LINE_COUNT_def 0x00000000 -#define fld_VS_DETECTED_LINES_def 0x00000000 -#define fld_VS_ITU656_VB_def 0x00000000 - -#define fld_VBI_CC_DATA_def 0x00000000 -#define fld_VBI_CC_WT_def 0x00000000 -#define fld_VBI_CC_WT_ACK_def 0x00000000 -#define fld_VBI_CC_HOLD_def 0x00000000 -#define fld_VBI_DECODE_EN_def 0x00000000 - -#define fld_VBI_CC_DTO_P_def 0x00001802 -#define fld_VBI_20BIT_DTO_P_def 0x0000155c - -#define fld_VBI_CC_LEVEL_def 0x0000003f -#define fld_VBI_20BIT_LEVEL_def 0x00000059 -#define fld_VBI_CLK_RUNIN_GAIN_def 0x0000010f - -#define fld_H_VBI_WIND_START_def 0x00000041 -#define fld_H_VBI_WIND_END_def 0x00000366 - -#define fld_V_VBI_WIND_START_def 0x0D -#define fld_V_VBI_WIND_END_def 0x24 - -#define fld_VBI_20BIT_DATA0_def 0x00000000 -#define fld_VBI_20BIT_DATA1_def 0x00000000 -#define fld_VBI_20BIT_WT_def 0x00000000 -#define fld_VBI_20BIT_WT_ACK_def 0x00000000 -#define fld_VBI_20BIT_HOLD_def 0x00000000 - -#define fld_VBI_CAPTURE_ENABLE_def 0x00000000 - -#define fld_VBI_EDS_DATA_def 0x00000000 -#define fld_VBI_EDS_WT_def 0x00000000 -#define fld_VBI_EDS_WT_ACK_def 0x00000000 -#define fld_VBI_EDS_HOLD_def 0x00000000 - -#define fld_VBI_SCALING_RATIO_def 0x00010000 -#define fld_VBI_ALIGNER_ENABLE_def 0x00000000 - -#define fld_H_ACTIVE_START_def 0x00000070 -#define fld_H_ACTIVE_END_def 0x000002f0 - -#define fld_V_ACTIVE_START_def ((22-4)*2+1) -#define fld_V_ACTIVE_END_def ((22+240-4)*2+2) - -#define fld_CH_HEIGHT_def 0x000000CD -#define fld_CH_KILL_LEVEL_def 0x000000C0 -#define fld_CH_AGC_ERROR_LIM_def 0x00000002 -#define fld_CH_AGC_FILTER_EN_def 0x00000000 -#define fld_CH_AGC_LOOP_SPEED_def 0x00000000 - -#define fld_HUE_ADJ_def 0x00000000 - -#define fld_STANDARD_SEL_def 0x00000000 -#define fld_STANDARD_YC_def 0x00000000 - -#define fld_ADC_PDWN_def 0x00000001 -#define fld_INPUT_SELECT_def 0x00000000 - -#define fld_ADC_PREFLO_def 0x00000003 -#define fld_H_SYNC_PULSE_WIDTH_def 0x00000000 -#define fld_HS_GENLOCKED_def 0x00000000 -#define fld_HS_SYNC_IN_WIN_def 0x00000000 - -#define fld_VIN_ASYNC_RST_def 0x00000001 -#define fld_DVS_ASYNC_RST_def 0x00000001 - -/* Vendor IDs: */ -#define fld_VIP_VENDOR_ID_def 0x00001002 -#define fld_VIP_DEVICE_ID_def 0x00004d54 -#define fld_VIP_REVISION_ID_def 0x00000001 - -/* AGC Delay Register */ -#define fld_BLACK_INT_START_def 0x00000031 -#define fld_BLACK_INT_LENGTH_def 0x0000000f - -#define fld_UV_INT_START_def 0x0000003b -#define fld_U_INT_LENGTH_def 0x0000000f -#define fld_V_INT_LENGTH_def 0x0000000f -#define fld_CRDR_ACTIVE_GAIN_def 0x0000007a -#define fld_CBDB_ACTIVE_GAIN_def 0x000000ac - -#define fld_DVS_DIRECTION_def 0x00000000 -#define fld_DVS_VBI_CARD8_SWAP_def 0x00000000 -#define fld_DVS_CLK_SELECT_def 0x00000000 -#define fld_CONTINUOUS_STREAM_def 0x00000000 -#define fld_DVSOUT_CLK_DRV_def 0x00000001 -#define fld_DVSOUT_DATA_DRV_def 0x00000001 - -#define fld_COMB_CNTL0_def 0x09438090 -#define fld_COMB_CNTL1_def 0x00000010 - -#define fld_COMB_CNTL2_def 0x16161010 -#define fld_COMB_LENGTH_def 0x0718038A - -#define fld_SYNCTIP_REF0_def 0x00000037 -#define fld_SYNCTIP_REF1_def 0x00000029 -#define fld_CLAMP_REF_def 0x0000003B -#define fld_AGC_PEAKWHITE_def 0x000000FF -#define fld_VBI_PEAKWHITE_def 0x000000D2 - -#define fld_WPA_THRESHOLD_def 0x000003B0 - -#define fld_WPA_TRIGGER_LO_def 0x000000B4 -#define fld_WPA_TRIGGER_HIGH_def 0x0000021C - -#define fld_LOCKOUT_START_def 0x00000206 -#define fld_LOCKOUT_END_def 0x00000021 - -#define fld_CH_DTO_INC_def 0x00400000 -#define fld_PLL_SGAIN_def 0x00000001 -#define fld_PLL_FGAIN_def 0x00000002 - -#define fld_CR_BURST_GAIN_def 0x0000007a -#define fld_CB_BURST_GAIN_def 0x000000ac - -#define fld_VERT_LOCKOUT_START_def 0x00000207 -#define fld_VERT_LOCKOUT_END_def 0x0000000E - -#define fld_H_IN_WIND_START_def 0x00000070 -#define fld_V_IN_WIND_START_def 0x00000027 - -#define fld_H_OUT_WIND_WIDTH_def 0x000002f4 - -#define fld_V_OUT_WIND_WIDTH_def 0x000000f0 - -#define fld_HS_LINE_TOTAL_def 0x0000038E - -#define fld_MIN_PULSE_WIDTH_def 0x0000002F -#define fld_MAX_PULSE_WIDTH_def 0x00000046 - -#define fld_WIN_CLOSE_LIMIT_def 0x0000004D -#define fld_WIN_OPEN_LIMIT_def 0x000001B7 - -#define fld_VSYNC_INT_TRIGGER_def 0x000002AA - -#define fld_VSYNC_INT_HOLD_def 0x0000001D - -#define fld_VIN_M0_def 0x00000039 -#define fld_VIN_N0_def 0x0000014c -#define fld_MNFLIP_EN_def 0x00000000 -#define fld_VIN_P_def 0x00000006 -#define fld_REG_CLK_SEL_def 0x00000000 - -#define fld_VIN_M1_def 0x00000000 -#define fld_VIN_N1_def 0x00000000 -#define fld_VIN_DRIVER_SEL_def 0x00000000 -#define fld_VIN_MNFLIP_REQ_def 0x00000000 -#define fld_VIN_MNFLIP_DONE_def 0x00000000 -#define fld_TV_LOCK_TO_VIN_def 0x00000000 -#define fld_TV_P_FOR_WINCLK_def 0x00000004 - -#define fld_VINRST_def 0x00000001 -#define fld_VIN_CLK_SEL_def 0x00000000 - -#define fld_VS_FIELD_BLANK_START_def 0x00000206 - -#define fld_VS_FIELD_BLANK_END_def 0x0000000A - -/*#define fld_VS_FIELD_IDLOCATION_def 0x00000105 */ -#define fld_VS_FIELD_IDLOCATION_def 0x00000001 -#define fld_VS_FRAME_TOTAL_def 0x00000217 - -#define fld_SYNC_TIP_START_def 0x00000372 -#define fld_SYNC_TIP_LENGTH_def 0x0000000F - -#define fld_GAIN_FORCE_DATA_def 0x00000000 -#define fld_GAIN_FORCE_EN_def 0x00000000 -#define fld_I_CLAMP_SEL_def 0x00000003 -#define fld_I_AGC_SEL_def 0x00000001 -#define fld_EXT_CLAMP_CAP_def 0x00000001 -#define fld_EXT_AGC_CAP_def 0x00000001 -#define fld_DECI_DITHER_EN_def 0x00000001 -#define fld_ADC_PREFHI_def 0x00000000 -#define fld_ADC_CH_GAIN_SEL_def 0x00000001 - -#define fld_HS_PLL_SGAIN_def 0x00000003 - -#define fld_NREn_def 0x00000000 -#define fld_NRGainCntl_def 0x00000000 -#define fld_NRBWTresh_def 0x00000000 -#define fld_NRGCTresh_def 0x00000000 -#define fld_NRCoefDespeclMode_def 0x00000000 - -#define fld_GPIO_5_OE_def 0x00000000 -#define fld_GPIO_6_OE_def 0x00000000 - -#define fld_GPIO_5_OUT_def 0x00000000 -#define fld_GPIO_6_OUT_def 0x00000000 - -/* End of field default values. */ - -#endif /* RADEON_H */
--- a/drivers/radeon/radeon_vid.c Sat Mar 17 21:21:04 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1544 +0,0 @@ -/* - * - * radeon_vid.c - * - * Copyright (C) 2001 Nick Kurshev - * - * BES YUV video overlay driver for Radeon/Rage128Pro/Rage128 cards - * - * This software has been released under the terms of the GNU Public - * license. See http://www.gnu.org/copyleft/gpl.html for details. - * - * This file is partly based on mga_vid and sis_vid stuff from - * mplayer's package. - * Also here was used code from CVS of GATOS project and X11 trees. - * - * SPECIAL THANKS TO: Hans-Peter Raschke for active testing and hacking - * Rage128(pro) stuff of this driver. - */ - -#define RADEON_VID_VERSION "1.2.1" - -/* - It's entirely possible this major conflicts with something else - mknod /dev/radeon_vid c 178 0 - or - mknod /dev/rage128_vid c 178 0 - for Rage128/Rage128Pro chips (although it doesn't matter) - +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - TESTED and WORKING formats: YUY2, UYVY, IYUV, I420, YV12 - ----------------------------------------------------------- - TODO: - Highest priority: fbvid.h compatibility - High priority: Fixing BUGS - Middle priority: RGB/BGR 2-32, YVU9, IF09 support - Low priority: CLPL, IYU1, IYU2, UYNV, CYUV, YUNV, YVYU, Y41P, Y211, Y41T, - ^^^^ - Y42T, V422, V655, CLJR, YUVP, UYVP, Mpeg PES (mpeg-1,2) support - ........................................................... - BUGS and LACKS: - Color and video keys don't work -*/ - -#include <linux/config.h> -#include <linux/version.h> -#include <linux/module.h> -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/mm.h> -#include <linux/string.h> -#include <linux/errno.h> -#include <linux/slab.h> -#include <linux/pci.h> -#include <linux/ioport.h> -#include <linux/init.h> -#include <linux/byteorder/swab.h> - -#include "radeon_vid.h" -#include "radeon.h" - -#ifdef CONFIG_MTRR -#include <asm/mtrr.h> -#endif - -#include <asm/uaccess.h> -#include <asm/system.h> -#include <asm/io.h> - -#define TRUE 1 -#define FALSE 0 - -#define RADEON_VID_MAJOR 178 - - -MODULE_AUTHOR("Nick Kurshev <nickols_k@mail.ru>"); -#ifdef RAGE128 -MODULE_DESCRIPTION("Accelerated YUV BES driver for Rage128. Version: "RADEON_VID_VERSION); -#else -MODULE_DESCRIPTION("Accelerated YUV BES driver for Radeons. Version: "RADEON_VID_VERSION); -#endif -#ifdef MODULE_LICENSE -MODULE_LICENSE("GPL"); -#endif -#ifdef CONFIG_MTRR -MODULE_PARM(mtrr, "i"); -MODULE_PARM_DESC(mtrr, "Tune MTRR (touch=1(default))"); -static int mtrr __initdata = 1; -static struct { int vram; int vram_valid; } smtrr; -#endif -MODULE_PARM(swap_fourcc, "i"); -MODULE_PARM_DESC(swap_fourcc, "Swap fourcc (don't swap=0(default))"); -static int swap_fourcc __initdata = 0; - -#ifdef RAGE128 -#define RVID_MSG "rage128_vid: " -#define X_ADJUST 0 -#else -#define RVID_MSG "radeon_vid: " -#define X_ADJUST 8 -#ifndef RADEON -#define RADEON -#endif -#endif - -#undef DEBUG -#if DEBUG -#define RTRACE printk -#else -#define RTRACE(...) ((void)0) -#endif - -#ifndef min -#define min(a,b) (a < b ? a : b) -#endif - -#ifndef RAGE128 -#if defined(__i386__) -/* Ugly but only way */ -#undef AVOID_FPU -static double inline __FastSin(double x) -{ - register double res; - __asm __volatile("fsin":"=t"(res):"0"(x)); - return res; -} -#undef sin -#define sin(x) __FastSin(x) - -static double inline __FastCos(double x) -{ - register double res; - __asm __volatile("fcos":"=t"(res):"0"(x)); - return res; -} -#undef cos -#define cos(x) __FastCos(x) -#else -#include "generic_math.h" -#endif /*__386__*/ -#endif /*RAGE128*/ - -#if !defined( RAGE128 ) && !defined( AVOID_FPU ) -#define RADEON_FPU 1 -#endif - -typedef struct bes_registers_s -{ - /* base address of yuv framebuffer */ - uint32_t yuv_base; - uint32_t fourcc; - uint32_t dest_bpp; - /* YUV BES registers */ - uint32_t reg_load_cntl; - uint32_t h_inc; - uint32_t step_by; - uint32_t y_x_start; - uint32_t y_x_end; - uint32_t v_inc; - uint32_t p1_blank_lines_at_top; - uint32_t p23_blank_lines_at_top; - uint32_t vid_buf_pitch0_value; - uint32_t vid_buf_pitch1_value; - uint32_t p1_x_start_end; - uint32_t p2_x_start_end; - uint32_t p3_x_start_end; - uint32_t base_addr; - uint32_t vid_buf0_base_adrs; - /* These ones are for auto flip: maybe in the future */ - uint32_t vid_buf1_base_adrs; - uint32_t vid_buf2_base_adrs; - uint32_t vid_buf3_base_adrs; - uint32_t vid_buf4_base_adrs; - uint32_t vid_buf5_base_adrs; - - uint32_t p1_v_accum_init; - uint32_t p1_h_accum_init; - uint32_t p23_v_accum_init; - uint32_t p23_h_accum_init; - uint32_t scale_cntl; - uint32_t exclusive_horz; - uint32_t auto_flip_cntl; - uint32_t filter_cntl; - uint32_t key_cntl; - uint32_t test; - /* Configurable stuff */ - int double_buff; - - int brightness; - int saturation; - - int ckey_on; - uint32_t graphics_key_clr; - uint32_t graphics_key_msk; - - int deinterlace_on; - uint32_t deinterlace_pattern; - -} bes_registers_t; - -typedef struct video_registers_s -{ -#ifdef DEBUG - const char * sname; -#endif - uint32_t name; - uint32_t value; -}video_registers_t; - -static bes_registers_t besr; -#ifndef RAGE128 -static int IsR200=0; -#endif -#ifdef DEBUG -#define DECLARE_VREG(name) { #name, name, 0 } -#else -#define DECLARE_VREG(name) { name, 0 } -#endif -#ifdef DEBUG -static video_registers_t vregs[] = -{ - DECLARE_VREG(VIDEOMUX_CNTL), - DECLARE_VREG(VIPPAD_MASK), - DECLARE_VREG(VIPPAD1_A), - DECLARE_VREG(VIPPAD1_EN), - DECLARE_VREG(VIPPAD1_Y), - DECLARE_VREG(OV0_Y_X_START), - DECLARE_VREG(OV0_Y_X_END), - DECLARE_VREG(OV0_PIPELINE_CNTL), - DECLARE_VREG(OV0_EXCLUSIVE_HORZ), - DECLARE_VREG(OV0_EXCLUSIVE_VERT), - DECLARE_VREG(OV0_REG_LOAD_CNTL), - DECLARE_VREG(OV0_SCALE_CNTL), - DECLARE_VREG(OV0_V_INC), - DECLARE_VREG(OV0_P1_V_ACCUM_INIT), - DECLARE_VREG(OV0_P23_V_ACCUM_INIT), - DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), - DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), -#ifdef RADEON - DECLARE_VREG(OV0_BASE_ADDR), -#endif - DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), - DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), - DECLARE_VREG(OV0_AUTO_FLIP_CNTL), - DECLARE_VREG(OV0_DEINTERLACE_PATTERN), - DECLARE_VREG(OV0_SUBMIT_HISTORY), - DECLARE_VREG(OV0_H_INC), - DECLARE_VREG(OV0_STEP_BY), - DECLARE_VREG(OV0_P1_H_ACCUM_INIT), - DECLARE_VREG(OV0_P23_H_ACCUM_INIT), - DECLARE_VREG(OV0_P1_X_START_END), - DECLARE_VREG(OV0_P2_X_START_END), - DECLARE_VREG(OV0_P3_X_START_END), - DECLARE_VREG(OV0_FILTER_CNTL), - DECLARE_VREG(OV0_FOUR_TAP_COEF_0), - DECLARE_VREG(OV0_FOUR_TAP_COEF_1), - DECLARE_VREG(OV0_FOUR_TAP_COEF_2), - DECLARE_VREG(OV0_FOUR_TAP_COEF_3), - DECLARE_VREG(OV0_FOUR_TAP_COEF_4), - DECLARE_VREG(OV0_FLAG_CNTL), -#ifdef RAGE128 - DECLARE_VREG(OV0_COLOUR_CNTL), -#else - DECLARE_VREG(OV0_SLICE_CNTL), -#endif - DECLARE_VREG(OV0_VID_KEY_CLR), - DECLARE_VREG(OV0_VID_KEY_MSK), - DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), - DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), - DECLARE_VREG(OV0_KEY_CNTL), - DECLARE_VREG(OV0_TEST), - DECLARE_VREG(OV0_LIN_TRANS_A), - DECLARE_VREG(OV0_LIN_TRANS_B), - DECLARE_VREG(OV0_LIN_TRANS_C), - DECLARE_VREG(OV0_LIN_TRANS_D), - DECLARE_VREG(OV0_LIN_TRANS_E), - DECLARE_VREG(OV0_LIN_TRANS_F), - DECLARE_VREG(OV0_GAMMA_0_F), - DECLARE_VREG(OV0_GAMMA_10_1F), - DECLARE_VREG(OV0_GAMMA_20_3F), - DECLARE_VREG(OV0_GAMMA_40_7F), - DECLARE_VREG(OV0_GAMMA_380_3BF), - DECLARE_VREG(OV0_GAMMA_3C0_3FF), - DECLARE_VREG(SUBPIC_CNTL), - DECLARE_VREG(SUBPIC_DEFCOLCON), - DECLARE_VREG(SUBPIC_Y_X_START), - DECLARE_VREG(SUBPIC_Y_X_END), - DECLARE_VREG(SUBPIC_V_INC), - DECLARE_VREG(SUBPIC_H_INC), - DECLARE_VREG(SUBPIC_BUF0_OFFSET), - DECLARE_VREG(SUBPIC_BUF1_OFFSET), - DECLARE_VREG(SUBPIC_LC0_OFFSET), - DECLARE_VREG(SUBPIC_LC1_OFFSET), - DECLARE_VREG(SUBPIC_PITCH), - DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), - DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), - DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), - DECLARE_VREG(SUBPIC_PALETTE_INDEX), - DECLARE_VREG(SUBPIC_PALETTE_DATA), - DECLARE_VREG(SUBPIC_H_ACCUM_INIT), - DECLARE_VREG(SUBPIC_V_ACCUM_INIT), - DECLARE_VREG(IDCT_RUNS), - DECLARE_VREG(IDCT_LEVELS), - DECLARE_VREG(IDCT_AUTH_CONTROL), - DECLARE_VREG(IDCT_AUTH), - DECLARE_VREG(IDCT_CONTROL) -}; -#endif -static uint32_t radeon_vid_in_use = 0; - -static uint8_t *radeon_mmio_base = 0; -static uint32_t radeon_mem_base = 0; -static int32_t radeon_overlay_off = 0; -static uint32_t radeon_ram_size = 0; -#define PARAM_BUFF_SIZE 4096 -static uint8_t *radeon_param_buff = NULL; -static uint32_t radeon_param_buff_size=0; -static uint32_t radeon_param_buff_len=0; /* real length of buffer */ -static mga_vid_config_t radeon_config; - -static char *fourcc_format_name(int format) -{ - switch(format) - { - case IMGFMT_RGB8: return("RGB 8-bit"); - case IMGFMT_RGB15: return("RGB 15-bit"); - case IMGFMT_RGB16: return("RGB 16-bit"); - case IMGFMT_RGB24: return("RGB 24-bit"); - case IMGFMT_RGB32: return("RGB 32-bit"); - case IMGFMT_BGR8: return("BGR 8-bit"); - case IMGFMT_BGR15: return("BGR 15-bit"); - case IMGFMT_BGR16: return("BGR 16-bit"); - case IMGFMT_BGR24: return("BGR 24-bit"); - case IMGFMT_BGR32: return("BGR 32-bit"); - case IMGFMT_YVU9: return("Planar YVU9"); - case IMGFMT_IF09: return("Planar IF09"); - case IMGFMT_YV12: return("Planar YV12"); - case IMGFMT_I420: return("Planar I420"); - case IMGFMT_IYUV: return("Planar IYUV"); - case IMGFMT_CLPL: return("Planar CLPL"); - case IMGFMT_Y800: return("Planar Y800"); - case IMGFMT_Y8: return("Planar Y8"); - case IMGFMT_IUYV: return("Packed IUYV"); - case IMGFMT_IY41: return("Packed IY41"); - case IMGFMT_IYU1: return("Packed IYU1"); - case IMGFMT_IYU2: return("Packed IYU2"); - case IMGFMT_UYNV: return("Packed UYNV"); - case IMGFMT_cyuv: return("Packed CYUV"); - case IMGFMT_Y422: return("Packed Y422"); - case IMGFMT_YUY2: return("Packed YUY2"); - case IMGFMT_YUNV: return("Packed YUNV"); - case IMGFMT_UYVY: return("Packed UYVY"); -// case IMGFMT_YVYU: return("Packed YVYU"); - case IMGFMT_Y41P: return("Packed Y41P"); - case IMGFMT_Y211: return("Packed Y211"); - case IMGFMT_Y41T: return("Packed Y41T"); - case IMGFMT_Y42T: return("Packed Y42T"); - case IMGFMT_V422: return("Packed V422"); - case IMGFMT_V655: return("Packed V655"); - case IMGFMT_CLJR: return("Packed CLJR"); - case IMGFMT_YUVP: return("Packed YUVP"); - case IMGFMT_UYVP: return("Packed UYVP"); - case IMGFMT_MPEGPES: return("Mpeg PES"); - } - return("Unknown"); -} - - -/* - * IO macros - */ - -#define INREG8(addr) readb((radeon_mmio_base)+addr) -#define OUTREG8(addr,val) writeb(val, (radeon_mmio_base)+addr) -#define INREG(addr) readl((radeon_mmio_base)+addr) -#define OUTREG(addr,val) writel(val, (radeon_mmio_base)+addr) -#define OUTREGP(addr,val,mask) \ - do { \ - unsigned int _tmp = INREG(addr); \ - _tmp &= (mask); \ - _tmp |= (val); \ - OUTREG(addr, _tmp); \ - } while (0) - -static uint32_t radeon_vid_get_dbpp( void ) -{ - uint32_t dbpp,retval; - dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; - switch(dbpp) - { - case DST_8BPP: retval = 8; break; - case DST_15BPP: retval = 15; break; - case DST_16BPP: retval = 16; break; - case DST_24BPP: retval = 24; break; - default: retval=32; break; - } - return retval; -} - -static int radeon_is_dbl_scan( void ) -{ - return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; -} - -static int radeon_is_interlace( void ) -{ - return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; -} - -static __inline__ void radeon_engine_flush ( void ) -{ - int i; - - /* initiate flush */ - OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, - ~RB2D_DC_FLUSH_ALL); - - for (i=0; i < 2000000; i++) { - if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) - break; - } -} - - -static __inline__ void _radeon_fifo_wait (int entries) -{ - int i; - - for (i=0; i<2000000; i++) - if ((INREG(RBBM_STATUS) & 0x7f) >= entries) - return; -} - - -static __inline__ void _radeon_engine_idle ( void ) -{ - int i; - - /* ensure FIFO is empty before waiting for idle */ - _radeon_fifo_wait (64); - - for (i=0; i<2000000; i++) { - if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { - radeon_engine_flush (); - return; - } - } -} - -#define radeon_engine_idle() _radeon_engine_idle() -#define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) - -#if 0 -static void __init radeon_vid_save_state( void ) -{ - size_t i; - for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) - vregs[i].value = INREG(vregs[i].name); -} - -static void __exit radeon_vid_restore_state( void ) -{ - size_t i; - radeon_fifo_wait(2); - OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); - radeon_engine_idle(); - while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); - radeon_fifo_wait(15); - for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) - { - radeon_fifo_wait(1); - OUTREG(vregs[i].name,vregs[i].value); - } - OUTREG(OV0_REG_LOAD_CNTL, 0); -} -#endif -#ifdef DEBUG -static void radeon_vid_dump_regs( void ) -{ - size_t i; - printk(RVID_MSG"*** Begin of OV0 registers dump ***\n"); - for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) - printk(RVID_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); - printk(RVID_MSG"*** End of OV0 registers dump ***\n"); -} -#endif - -#ifdef RADEON_FPU -/* Reference color space transform data */ -typedef struct tagREF_TRANSFORM -{ - float RefLuma; - float RefRCb; - float RefRCr; - float RefGCb; - float RefGCr; - float RefBCb; - float RefBCr; -} REF_TRANSFORM; - -/* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ -REF_TRANSFORM trans[2] = -{ - {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ - {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ -}; -/**************************************************************************** - * SetTransform * - * Function: Calculates and sets color space transform from supplied * - * reference transform, gamma, brightness, contrast, hue and * - * saturation. * - * Inputs: bright - brightness * - * cont - contrast * - * sat - saturation * - * hue - hue * - * ref - index to the table of refernce transforms * - * Outputs: NONE * - ****************************************************************************/ - -static void radeon_set_transform(float bright, float cont, float sat, - float hue, unsigned ref) -{ - float OvHueSin, OvHueCos; - float CAdjLuma, CAdjOff; - float CAdjRCb, CAdjRCr; - float CAdjGCb, CAdjGCr; - float CAdjBCb, CAdjBCr; - float OvLuma, OvROff, OvGOff, OvBOff; - float OvRCb, OvRCr; - float OvGCb, OvGCr; - float OvBCb, OvBCr; - float Loff = 64.0; - float Coff = 512.0f; - - u32 dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; - u32 dwOvRCb, dwOvRCr; - u32 dwOvGCb, dwOvGCr; - u32 dwOvBCb, dwOvBCr; - - if (ref >= 2) return; - - OvHueSin = sin((double)hue); - OvHueCos = cos((double)hue); - - CAdjLuma = cont * trans[ref].RefLuma; - CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; - - CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; - CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; - CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); - CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); - CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; - CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; - -#if 0 /* default constants */ - CAdjLuma = 1.16455078125; - - CAdjRCb = 0.0; - CAdjRCr = 1.59619140625; - CAdjGCb = -0.39111328125; - CAdjGCr = -0.8125; - CAdjBCb = 2.01708984375; - CAdjBCr = 0; -#endif - OvLuma = CAdjLuma; - OvRCb = CAdjRCb; - OvRCr = CAdjRCr; - OvGCb = CAdjGCb; - OvGCr = CAdjGCr; - OvBCb = CAdjBCb; - OvBCr = CAdjBCr; - OvROff = CAdjOff - - OvLuma * Loff - (OvRCb + OvRCr) * Coff; - OvGOff = CAdjOff - - OvLuma * Loff - (OvGCb + OvGCr) * Coff; - OvBOff = CAdjOff - - OvLuma * Loff - (OvBCb + OvBCr) * Coff; -#if 0 /* default constants */ - OvROff = -888.5; - OvGOff = 545; - OvBOff = -1104; -#endif - - dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; - dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; - dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; - if(!IsR200) - { - dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; - dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; - dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; - dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; - dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; - dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; - dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; - } - else - { - dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; - dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; - dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; - dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; - dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; - dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; - dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; - } - - OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); - OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); - OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); - OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); - OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); - OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); -} -#endif - -#ifndef RAGE128 -/* Gamma curve definition */ -typedef struct -{ - unsigned int gammaReg; - unsigned int gammaSlope; - unsigned int gammaOffset; -}GAMMA_SETTINGS; - -/* Recommended gamma curve parameters */ -GAMMA_SETTINGS r200_def_gamma[18] = -{ - {OV0_GAMMA_0_F, 0x100, 0x0000}, - {OV0_GAMMA_10_1F, 0x100, 0x0020}, - {OV0_GAMMA_20_3F, 0x100, 0x0040}, - {OV0_GAMMA_40_7F, 0x100, 0x0080}, - {OV0_GAMMA_80_BF, 0x100, 0x0100}, - {OV0_GAMMA_C0_FF, 0x100, 0x0100}, - {OV0_GAMMA_100_13F, 0x100, 0x0200}, - {OV0_GAMMA_140_17F, 0x100, 0x0200}, - {OV0_GAMMA_180_1BF, 0x100, 0x0300}, - {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, - {OV0_GAMMA_200_23F, 0x100, 0x0400}, - {OV0_GAMMA_240_27F, 0x100, 0x0400}, - {OV0_GAMMA_280_2BF, 0x100, 0x0500}, - {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, - {OV0_GAMMA_300_33F, 0x100, 0x0600}, - {OV0_GAMMA_340_37F, 0x100, 0x0600}, - {OV0_GAMMA_380_3BF, 0x100, 0x0700}, - {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} -}; - -GAMMA_SETTINGS r100_def_gamma[6] = -{ - {OV0_GAMMA_0_F, 0x100, 0x0000}, - {OV0_GAMMA_10_1F, 0x100, 0x0020}, - {OV0_GAMMA_20_3F, 0x100, 0x0040}, - {OV0_GAMMA_40_7F, 0x100, 0x0080}, - {OV0_GAMMA_380_3BF, 0x100, 0x0100}, - {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} -}; - -static void make_default_gamma_correction( void ) -{ - size_t i; - if(!IsR200){ - OUTREG(OV0_LIN_TRANS_A, 0x12A00000); - OUTREG(OV0_LIN_TRANS_B, 0x199018FE); - OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); - OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); - OUTREG(OV0_LIN_TRANS_E, 0x12A02050); - OUTREG(OV0_LIN_TRANS_F, 0x0000174E); - for(i=0; i<6; i++){ - OUTREG(r100_def_gamma[i].gammaReg, - (r100_def_gamma[i].gammaSlope<<16) | - r100_def_gamma[i].gammaOffset); - } - } - else{ - OUTREG(OV0_LIN_TRANS_A, 0x12a00000); - OUTREG(OV0_LIN_TRANS_B, 0x1990190e); - OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); - OUTREG(OV0_LIN_TRANS_D, 0xf3000442); - OUTREG(OV0_LIN_TRANS_E, 0x12a02040); - OUTREG(OV0_LIN_TRANS_F, 0x175f); - - /* Default Gamma, - Of 18 segments for gamma cure, all segments in R200 are programmable, - while only lower 4 and upper 2 segments are programmable in Radeon*/ - for(i=0; i<18; i++){ - OUTREG(r200_def_gamma[i].gammaReg, - (r200_def_gamma[i].gammaSlope<<16) | - r200_def_gamma[i].gammaOffset); - } - } -} -#endif - -static void radeon_vid_stop_video( void ) -{ - radeon_engine_idle(); - OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); - OUTREG(OV0_EXCLUSIVE_HORZ, 0); - OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ - OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); - OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); - OUTREG(OV0_TEST, 0); -} - -static void radeon_vid_display_video( void ) -{ - int bes_flags; - radeon_fifo_wait(2); - OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); - radeon_engine_idle(); - while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); - radeon_fifo_wait(15); - OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); - OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); - OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); - - OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); -#ifdef RAGE128 - OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | - (besr.saturation << 8) | - (besr.saturation << 16)); -#endif - radeon_fifo_wait(2); - if(besr.ckey_on) - { - OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); - OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); - OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_EQ|VIDEO_KEY_FN_FALSE|CMP_MIX_OR); - } - else - { - OUTREG(OV0_GRAPHICS_KEY_MSK, 0ULL); - OUTREG(OV0_GRAPHICS_KEY_CLR, 0ULL); - OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_NE); - } - - OUTREG(OV0_H_INC, besr.h_inc); - OUTREG(OV0_STEP_BY, besr.step_by); - OUTREG(OV0_Y_X_START, besr.y_x_start); - OUTREG(OV0_Y_X_END, besr.y_x_end); - OUTREG(OV0_V_INC, besr.v_inc); - OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); - OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); - OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); - OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); - OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); - OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); - OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); -#ifdef RADEON - OUTREG(OV0_BASE_ADDR, besr.base_addr); -#endif - OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs); - OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs); - OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs); - radeon_fifo_wait(9); - OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs); - OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs); - OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf5_base_adrs); - OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); - OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); - OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); - OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); - -#ifdef RADEON - bes_flags = SCALER_ENABLE | - SCALER_SMART_SWITCH; -// SCALER_HORZ_PICK_NEAREST; -#else - bes_flags = SCALER_ENABLE | - SCALER_SMART_SWITCH | - SCALER_Y2R_TEMP | - SCALER_PIX_EXPAND; -#endif - if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; - if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; -#ifdef RAGE128 - bes_flags |= SCALER_BURST_PER_PLANE; -#endif - switch(besr.fourcc) - { - case IMGFMT_RGB15: - case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; - case IMGFMT_RGB16: - case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; - case IMGFMT_RGB24: - case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; - case IMGFMT_RGB32: - case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; - /* 4:1:0*/ - case IMGFMT_IF09: - case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; - /* 4:2:0 */ - case IMGFMT_IYUV: - case IMGFMT_I420: - case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; - break; - /* 4:2:2 */ - case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; - case IMGFMT_YUY2: - default: bes_flags |= SCALER_SOURCE_VYUY422; break; - } - OUTREG(OV0_SCALE_CNTL, bes_flags); - OUTREG(OV0_REG_LOAD_CNTL, 0); -#ifdef DEBUG - radeon_vid_dump_regs(); -#endif -} - -void radeon_vid_set_color_key(int ckey_on, uint8_t R, uint8_t G, uint8_t B) -{ - besr.ckey_on = ckey_on; - besr.graphics_key_msk=(1ULL<<radeon_vid_get_dbpp()) - 1; - besr.graphics_key_clr=(R<<16)|(G<<8)|(B)|(0x00 << 24); -} - - -#define XXX_SRC_X 0 -#define XXX_SRC_Y 0 - -static int radeon_vid_init_video( mga_vid_config_t *config ) -{ - uint32_t tmp,src_w,src_h,pitch,h_inc,step_by,left,leftUV,top; - int is_420; -RTRACE(RVID_MSG"usr_config: version = %x format=%x card=%x ram=%u src(%ux%u) dest(%u:%ux%u:%u) frame_size=%u num_frames=%u\n" - ,(uint32_t)config->version - ,(uint32_t)config->format - ,(uint32_t)config->card_type - ,(uint32_t)config->ram_size - ,(uint32_t)config->src_width - ,(uint32_t)config->src_height - ,(uint32_t)config->x_org - ,(uint32_t)config->y_org - ,(uint32_t)config->dest_width - ,(uint32_t)config->dest_height - ,(uint32_t)config->frame_size - ,(uint32_t)config->num_frames); - radeon_vid_stop_video(); - left = XXX_SRC_X << 16; - top = XXX_SRC_Y << 16; - src_h = config->src_height; - src_w = config->src_width; - switch(config->format) - { - case IMGFMT_RGB15: - case IMGFMT_BGR15: - case IMGFMT_RGB16: - case IMGFMT_BGR16: - case IMGFMT_RGB24: - case IMGFMT_BGR24: - case IMGFMT_RGB32: - case IMGFMT_BGR32: - /* 4:1:0 */ - case IMGFMT_IF09: - case IMGFMT_YVU9: - /* 4:2:0 */ - case IMGFMT_IYUV: - case IMGFMT_YV12: - case IMGFMT_I420: - /* 4:2:2 */ - case IMGFMT_UYVY: - case IMGFMT_YUY2: - break; - default: - printk(RVID_MSG"Unsupported pixel format: 0x%X\n",config->format); - return -1; - } - is_420 = 0; - if(config->format == IMGFMT_YV12 || - config->format == IMGFMT_I420 || - config->format == IMGFMT_IYUV) is_420 = 1; - switch(config->format) - { - /* 4:1:0 */ - case IMGFMT_YVU9: - case IMGFMT_IF09: - /* 4:2:0 */ - case IMGFMT_IYUV: - case IMGFMT_YV12: - case IMGFMT_I420: pitch = (src_w + 31) & ~31; break; - /* 4:2:2 */ - default: - case IMGFMT_UYVY: - case IMGFMT_YUY2: - case IMGFMT_RGB15: - case IMGFMT_BGR15: - case IMGFMT_RGB16: - case IMGFMT_BGR16: pitch = ((src_w*2) + 15) & ~15; break; - case IMGFMT_RGB24: - case IMGFMT_BGR24: pitch = ((src_w*3) + 15) & ~15; break; - case IMGFMT_RGB32: - case IMGFMT_BGR32: pitch = ((src_w*4) + 15) & ~15; break; - } - if(radeon_is_dbl_scan()) config->dest_height *= 2; - else - if(radeon_is_interlace()) config->dest_height /= 2; - besr.dest_bpp = radeon_vid_get_dbpp(); - besr.fourcc = config->format; - besr.v_inc = (src_h << 20) / config->dest_height; - h_inc = (src_w << 12) / config->dest_width; - step_by = 1; - - while(h_inc >= (2 << 12)) { - step_by++; - h_inc >>= 1; - } - - /* keep everything in 16.16 */ - besr.base_addr = radeon_mem_base; - if(is_420) - { - uint32_t d1line,d2line,d3line; - d1line = top*pitch; - d2line = src_h*pitch+(d1line>>1); - d3line = d2line+((src_h*pitch)>>2); - d1line += (left >> 16) & ~15; - d2line += (left >> 17) & ~15; - d3line += (left >> 17) & ~15; - besr.vid_buf0_base_adrs=((radeon_overlay_off+d1line)&VIF_BUF0_BASE_ADRS_MASK); - besr.vid_buf1_base_adrs=((radeon_overlay_off+d2line)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; - besr.vid_buf2_base_adrs=((radeon_overlay_off+d3line)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; - if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) - { - uint32_t tmp; - tmp = besr.vid_buf1_base_adrs; - besr.vid_buf1_base_adrs = besr.vid_buf2_base_adrs; - besr.vid_buf2_base_adrs = tmp; - } - } - else - { - besr.vid_buf0_base_adrs = radeon_overlay_off; - besr.vid_buf0_base_adrs += ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; - besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs; - besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs; - } - besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; - besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs+config->frame_size; - besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs+config->frame_size; - - tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); - besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | - ((tmp << 12) & 0xf0000000); - - tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); - besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | - ((tmp << 12) & 0x70000000); - tmp = (top & 0x0000ffff) + 0x00018000; - besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) - |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); - - tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; - besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) - |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; - - leftUV = (left >> 17) & 15; - left = (left >> 16) & 15; - besr.h_inc = h_inc | ((h_inc >> 1) << 16); - besr.step_by = step_by | (step_by << 8); - besr.y_x_start = (config->x_org+X_ADJUST) | (config->y_org << 16); - besr.y_x_end = (config->x_org + config->dest_width+X_ADJUST) | ((config->y_org + config->dest_height) << 16); - besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); - if(is_420) - { - src_h = (src_h + 1) >> 1; - besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); - } - else besr.p23_blank_lines_at_top = 0; - besr.vid_buf_pitch0_value = pitch; - besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch; - besr.p1_x_start_end = (src_w+left-1)|(left<<16); - src_w>>=1; - besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); - besr.p3_x_start_end = besr.p2_x_start_end; - return 0; -} - -static void radeon_vid_frame_sel(int frame) -{ - uint32_t off0,off1,off2; - if(!besr.double_buff) return; - if(frame%2) - { - off0 = besr.vid_buf3_base_adrs; - off1 = besr.vid_buf4_base_adrs; - off2 = besr.vid_buf5_base_adrs; - } - else - { - off0 = besr.vid_buf0_base_adrs; - off1 = besr.vid_buf1_base_adrs; - off2 = besr.vid_buf2_base_adrs; - } - OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); - while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); - OUTREG(OV0_VID_BUF0_BASE_ADRS, off0); - OUTREG(OV0_VID_BUF1_BASE_ADRS, off1); - OUTREG(OV0_VID_BUF2_BASE_ADRS, off2); - OUTREG(OV0_REG_LOAD_CNTL, 0); -} - -static void radeon_vid_make_default(void) -{ -#ifdef RAGE128 - OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brihgtness and saturation for Rage128 */ -#else - make_default_gamma_correction(); -#endif - besr.deinterlace_pattern = 0x900AAAAA; - OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); - besr.deinterlace_on=1; - besr.double_buff=1; -} - - -static void radeon_vid_preset(void) -{ -#ifdef RAGE128 - unsigned tmp; - tmp = INREG(OV0_COLOUR_CNTL); - besr.saturation = (tmp>>8)&0x1f; - besr.brightness = tmp & 0x7f; -#endif - besr.graphics_key_clr = INREG(OV0_GRAPHICS_KEY_CLR); - besr.deinterlace_pattern = INREG(OV0_DEINTERLACE_PATTERN); -} - -static int video_on = 0; - -static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) -{ - int frame; - - switch(cmd) - { - case MGA_VID_CONFIG: - RTRACE(RVID_MSG"radeon_mmio_base = %p\n",radeon_mmio_base); - RTRACE(RVID_MSG"radeon_mem_base = %08x\n",radeon_mem_base); - RTRACE(RVID_MSG"Received configuration\n"); - - if(copy_from_user(&radeon_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t))) - { - printk(RVID_MSG"failed copy from userspace\n"); - return -EFAULT; - } - if(radeon_config.version != MGA_VID_VERSION){ - printk(RVID_MSG"incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,radeon_config.version); - return -EFAULT; - } - - if(radeon_config.frame_size==0 || radeon_config.frame_size>1024*768*2){ - printk(RVID_MSG"illegal frame_size: %d\n",radeon_config.frame_size); - return -EFAULT; - } - - if(radeon_config.num_frames<1){ - printk(RVID_MSG"illegal num_frames: %d\n",radeon_config.num_frames); - return -EFAULT; - } - if(radeon_config.num_frames==1) besr.double_buff=0; - if(!besr.double_buff) radeon_config.num_frames=1; - else radeon_config.num_frames=2; - radeon_config.card_type = 0; - radeon_config.ram_size = radeon_ram_size; - radeon_overlay_off = radeon_ram_size*0x100000 - radeon_config.frame_size*radeon_config.num_frames; - radeon_overlay_off &= 0xffff0000; - if(radeon_overlay_off < 0){ - printk(RVID_MSG"not enough video memory. Need: %u has: %u\n",radeon_config.frame_size*radeon_config.num_frames,radeon_ram_size*0x100000); - return -EFAULT; - } - RTRACE(RVID_MSG"using video overlay at offset %08X\n",radeon_overlay_off); - if (copy_to_user((mga_vid_config_t *) arg, &radeon_config, sizeof(mga_vid_config_t))) - { - printk(RVID_MSG"failed copy to userspace\n"); - return -EFAULT; - } - radeon_vid_set_color_key(radeon_config.colkey_on, - radeon_config.colkey_red, - radeon_config.colkey_green, - radeon_config.colkey_blue); - if(swap_fourcc) radeon_config.format = swab32(radeon_config.format); - printk(RVID_MSG"configuring for '%s' fourcc\n",fourcc_format_name(radeon_config.format)); - return radeon_vid_init_video(&radeon_config); - break; - - case MGA_VID_ON: - RTRACE(RVID_MSG"Video ON (ioctl)\n"); - radeon_vid_display_video(); - video_on = 1; - break; - - case MGA_VID_OFF: - RTRACE(RVID_MSG"Video OFF (ioctl)\n"); - if(video_on) radeon_vid_stop_video(); - video_on = 0; - break; - - case MGA_VID_FSEL: - if(copy_from_user(&frame,(int *) arg,sizeof(int))) - { - printk(RVID_MSG"FSEL failed copy from userspace\n"); - return(-EFAULT); - } - radeon_vid_frame_sel(frame); - break; - - default: - printk(RVID_MSG"Invalid ioctl\n"); - return (-EINVAL); - } - - return 0; -} - -struct ati_card_id_s -{ - const int id; - const char name[17]; -}; - -const struct ati_card_id_s ati_card_ids[]= -{ -#ifdef RAGE128 - /* - This driver should be compatible with Rage128 (pro) chips. - (include adaptive deinterlacing!!!). - Moreover: the same logic can be used with Mach64 chips. - (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). - but they are incompatible by i/o ports. So if enthusiasts will want - then they can redefine OUTREG and INREG macros and redefine OV0_* - constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY - fourccs (422 and 420 formats only). - */ -/* Rage128 Pro GL */ - { PCI_DEVICE_ID_ATI_Rage128_PA, "R128Pro PA" }, - { PCI_DEVICE_ID_ATI_Rage128_PB, "R128Pro PB" }, - { PCI_DEVICE_ID_ATI_Rage128_PC, "R128Pro PC" }, - { PCI_DEVICE_ID_ATI_Rage128_PD, "R128Pro PD" }, - { PCI_DEVICE_ID_ATI_Rage128_PE, "R128Pro PE" }, - { PCI_DEVICE_ID_ATI_RAGE128_PF, "R128Pro PF" }, -/* Rage128 Pro VR */ - { PCI_DEVICE_ID_ATI_RAGE128_PG, "R128Pro PG" }, - { PCI_DEVICE_ID_ATI_RAGE128_PH, "R128Pro PH" }, - { PCI_DEVICE_ID_ATI_RAGE128_PI, "R128Pro PI" }, - { PCI_DEVICE_ID_ATI_RAGE128_PJ, "R128Pro PJ" }, - { PCI_DEVICE_ID_ATI_RAGE128_PK, "R128Pro PK" }, - { PCI_DEVICE_ID_ATI_RAGE128_PL, "R128Pro PL" }, - { PCI_DEVICE_ID_ATI_RAGE128_PM, "R128Pro PM" }, - { PCI_DEVICE_ID_ATI_RAGE128_PN, "R128Pro PN" }, - { PCI_DEVICE_ID_ATI_RAGE128_PO, "R128Pro PO" }, - { PCI_DEVICE_ID_ATI_RAGE128_PP, "R128Pro PP" }, - { PCI_DEVICE_ID_ATI_RAGE128_PQ, "R128Pro PQ" }, - { PCI_DEVICE_ID_ATI_RAGE128_PR, "R128Pro PR" }, - { PCI_DEVICE_ID_ATI_RAGE128_TR, "R128Pro TR" }, - { PCI_DEVICE_ID_ATI_RAGE128_PS, "R128Pro PS" }, - { PCI_DEVICE_ID_ATI_RAGE128_PT, "R128Pro PT" }, - { PCI_DEVICE_ID_ATI_RAGE128_PU, "R128Pro PU" }, - { PCI_DEVICE_ID_ATI_RAGE128_PV, "R128Pro PV" }, - { PCI_DEVICE_ID_ATI_RAGE128_PW, "R128Pro PW" }, - { PCI_DEVICE_ID_ATI_RAGE128_PX, "R128Pro PX" }, -/* Rage128 GL */ - { PCI_DEVICE_ID_ATI_RAGE128_RE, "R128 RE" }, - { PCI_DEVICE_ID_ATI_RAGE128_RF, "R128 RF" }, - { PCI_DEVICE_ID_ATI_RAGE128_RG, "R128 RG" }, - { PCI_DEVICE_ID_ATI_RAGE128_RH, "R128 RH" }, - { PCI_DEVICE_ID_ATI_RAGE128_RI, "R128 RI" }, -/* Rage128 VR */ - { PCI_DEVICE_ID_ATI_RAGE128_RK, "R128 RK" }, - { PCI_DEVICE_ID_ATI_RAGE128_RL, "R128 RL" }, - { PCI_DEVICE_ID_ATI_RAGE128_RM, "R128 RM" }, - { PCI_DEVICE_ID_ATI_RAGE128_RN, "R128 RN" }, - { PCI_DEVICE_ID_ATI_RAGE128_RO, "R128 RO" }, -/* Rage128 M3 */ - { PCI_DEVICE_ID_ATI_RAGE128_LE, "R128 M3 LE" }, - { PCI_DEVICE_ID_ATI_RAGE128_LF, "R128 M3 LF" }, -/* Rage128 Pro Ultra */ - { PCI_DEVICE_ID_ATI_RAGE128_U1, "R128Pro U1" }, - { PCI_DEVICE_ID_ATI_RAGE128_U2, "R128Pro U2" }, - { PCI_DEVICE_ID_ATI_RAGE128_U3, "R128Pro U3" } -#else -/* Radeons (indeed: Rage 256 Pro ;) */ - { PCI_DEVICE_ID_RADEON_QD, "Radeon QD " }, - { PCI_DEVICE_ID_RADEON_QE, "Radeon QE " }, - { PCI_DEVICE_ID_RADEON_QF, "Radeon QF " }, - { PCI_DEVICE_ID_RADEON_QG, "Radeon QG " }, - { PCI_DEVICE_ID_RADEON_QY, "Radeon VE QY " }, - { PCI_DEVICE_ID_RADEON_QZ, "Radeon VE QZ " }, - { PCI_DEVICE_ID_RADEON_LY, "Radeon M6 LY " }, - { PCI_DEVICE_ID_RADEON_LZ, "Radeon M6 LZ " }, - { PCI_DEVICE_ID_RADEON_LW, "Radeon M7 LW " }, - { PCI_DEVICE_ID_R200_QL, "Radeon2 8500 QL " }, - { PCI_DEVICE_ID_R200_BB, "Radeon2 8500 AIW" }, - { PCI_DEVICE_ID_RV200_QW, "Radeon2 7500 QW " } -#endif -}; - -static int detected_chip; - -static int __init radeon_vid_config_card(void) -{ - struct pci_dev *dev = NULL; - size_t i; - - for(i=0;i<sizeof(ati_card_ids)/sizeof(struct ati_card_id_s);i++) - if((dev=pci_find_device(PCI_VENDOR_ID_ATI, ati_card_ids[i].id, NULL))) - break; - if(!dev) - { - printk(RVID_MSG"No supported cards found\n"); - return FALSE; - } - - radeon_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RADEON_REGSIZE); - radeon_mem_base = dev->resource[0].start; - - RTRACE(RVID_MSG"MMIO at 0x%p\n", radeon_mmio_base); - RTRACE(RVID_MSG"Frame Buffer at 0x%08x\n", radeon_mem_base); - - /* video memory size */ - radeon_ram_size = INREG(CONFIG_MEMSIZE); - - /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ - radeon_ram_size &= CONFIG_MEMSIZE_MASK; - radeon_ram_size /= 0x100000; - detected_chip = i; - printk(RVID_MSG"Found %s (%uMb memory)\n",ati_card_ids[i].name,radeon_ram_size); -#ifndef RAGE128 - if(ati_card_ids[i].id == PCI_DEVICE_ID_R200_QL || - ati_card_ids[i].id == PCI_DEVICE_ID_R200_BB || - ati_card_ids[i].id == PCI_DEVICE_ID_RV200_QW) IsR200 = 1; -#endif - return TRUE; -} - -#define PARAM_BRIGHTNESS "brightness=" -#define PARAM_SATURATION "saturation=" -#define PARAM_CONTRAST "contrast=" -#define PARAM_HUE "hue=" -#define PARAM_DOUBLE_BUFF "double_buff=" -#define PARAM_DEINTERLACE "deinterlace=" -#define PARAM_DEINTERLACE_PATTERN "deinterlace_pattern=" -#ifdef RADEON_FPU -static int ovBrightness=0, ovSaturation=0, ovContrast=0, ovHue=0, ov_trans_idx=0; -#endif - -static void radeon_param_buff_fill( void ) -{ - unsigned len,saturation; - int8_t brightness; - brightness = besr.brightness & 0x7f; - /* FIXME: It's probably x86 specific convertion. But it doesn't matter - for general logic - only for printing value */ - if(brightness > 63) brightness = (((~besr.brightness) & 0x3f)+1) * (-1); - saturation = besr.saturation; - len = 0; - len += sprintf(&radeon_param_buff[len],"Interface version: %04X\nDriver version: %s\n",MGA_VID_VERSION,RADEON_VID_VERSION); - len += sprintf(&radeon_param_buff[len],"Chip: %s\n",ati_card_ids[detected_chip].name); - len += sprintf(&radeon_param_buff[len],"Memory: %x:%x\n",radeon_mem_base,radeon_ram_size*0x100000); - len += sprintf(&radeon_param_buff[len],"MMIO: %p\n",radeon_mmio_base); - len += sprintf(&radeon_param_buff[len],"Overlay offset: %x\n",radeon_overlay_off); -#ifdef CONFIG_MTRR - len += sprintf(&radeon_param_buff[len],"Tune MTRR: %s\n",mtrr?"on":"off"); -#endif - if(besr.ckey_on) len += sprintf(&radeon_param_buff[len],"Last used color_key=%X (mask=%X)\n",besr.graphics_key_clr,besr.graphics_key_msk); - len += sprintf(&radeon_param_buff[len],"Swapped fourcc: %s\n",swap_fourcc?"on":"off"); - len += sprintf(&radeon_param_buff[len],"Last BPP: %u\n",besr.dest_bpp); - len += sprintf(&radeon_param_buff[len],"Last fourcc: %s\n\n",fourcc_format_name(besr.fourcc)); - len += sprintf(&radeon_param_buff[len],"Configurable stuff:\n"); - len += sprintf(&radeon_param_buff[len],"~~~~~~~~~~~~~~~~~~~\n"); - len += sprintf(&radeon_param_buff[len],PARAM_DOUBLE_BUFF"%s\n",besr.double_buff?"on":"off"); -#ifdef RAGE128 - len += sprintf(&radeon_param_buff[len],PARAM_BRIGHTNESS"%i\n",(int)brightness); - len += sprintf(&radeon_param_buff[len],PARAM_SATURATION"%u\n",saturation); -#else -#ifdef RADEON_FPU - len += sprintf(&radeon_param_buff[len],PARAM_BRIGHTNESS"%i\n",ovBrightness); - len += sprintf(&radeon_param_buff[len],PARAM_SATURATION"%i\n",ovSaturation); - len += sprintf(&radeon_param_buff[len],PARAM_CONTRAST"%i\n",ovContrast); - len += sprintf(&radeon_param_buff[len],PARAM_HUE"%i\n",ovHue); -#endif -#endif - len += sprintf(&radeon_param_buff[len],PARAM_DEINTERLACE"%s\n",besr.deinterlace_on?"on":"off"); - len += sprintf(&radeon_param_buff[len],PARAM_DEINTERLACE_PATTERN"%X\n",besr.deinterlace_pattern); - radeon_param_buff_len = len; -} - -static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) -{ - uint32_t size; - if(!radeon_param_buff) return -ESPIPE; - if(!(*ppos)) radeon_param_buff_fill(); - if(*ppos >= radeon_param_buff_len) return 0; - size = min(count,radeon_param_buff_len-(uint32_t)(*ppos)); - memcpy(buf,radeon_param_buff,size); - *ppos += size; - return size; -} - -#define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) -#define RTFBrightness(a) (((a)*1.0)/2000.0) -#define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) -#define RTFHue(a) (((a)*3.1416)/1000.0) -#define RadeonSetParm(a,b,c,d) if((b)>=(c)&&(b)<=(d)) { (a)=(b);\ - radeon_set_transform(RTFBrightness(ovBrightness),RTFContrast(ovContrast)\ - ,RTFSaturation(ovSaturation),RTFHue(ovHue),ov_trans_idx); } - - -static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) -{ -#ifdef RAGE128 - if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0) - { - long brightness; - brightness=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10); - if(brightness >= -64 && brightness <= 63) - { - besr.brightness = brightness; - OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) | - (besr.saturation << 8) | - (besr.saturation << 16)); - } - } - else - if(memcmp(buf,PARAM_SATURATION,min(count,strlen(PARAM_SATURATION))) == 0) - { - long saturation; - saturation=simple_strtol(&buf[strlen(PARAM_SATURATION)],NULL,10); - if(saturation >= 0 && saturation <= 31) - OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | - (saturation << 8) | - (saturation << 16)); - } - else -#else -#ifdef RADEON_FPU - if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0) - { - int tmp; - tmp=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10); - RadeonSetParm(ovBrightness,tmp,-1000,1000); - } - else - if(memcmp(buf,PARAM_SATURATION,min(count,strlen(PARAM_SATURATION))) == 0) - { - int tmp; - tmp=simple_strtol(&buf[strlen(PARAM_SATURATION)],NULL,10); - RadeonSetParm(ovSaturation,tmp,-1000,1000); - } - else - if(memcmp(buf,PARAM_CONTRAST,min(count,strlen(PARAM_CONTRAST))) == 0) - { - int tmp; - tmp=simple_strtol(&buf[strlen(PARAM_CONTRAST)],NULL,10); - RadeonSetParm(ovContrast,tmp,-1000,1000); - } - else - if(memcmp(buf,PARAM_HUE,min(count,strlen(PARAM_HUE))) == 0) - { - int tmp; - tmp=simple_strtol(&buf[strlen(PARAM_HUE)],NULL,10); - RadeonSetParm(ovHue,tmp,-1000,1000); - } - else -#endif -#endif - if(memcmp(buf,PARAM_DOUBLE_BUFF,min(count,strlen(PARAM_DOUBLE_BUFF))) == 0) - { - if(memcmp(&buf[strlen(PARAM_DOUBLE_BUFF)],"on",2) == 0) besr.double_buff = 1; - else besr.double_buff = 0; - } - else - if(memcmp(buf,PARAM_DEINTERLACE,min(count,strlen(PARAM_DEINTERLACE))) == 0) - { - if(memcmp(&buf[strlen(PARAM_DEINTERLACE)],"on",2) == 0) besr.deinterlace_on = 1; - else besr.deinterlace_on = 0; - } - else - if(memcmp(buf,PARAM_DEINTERLACE_PATTERN,min(count,strlen(PARAM_DEINTERLACE_PATTERN))) == 0) - { - long dpat; - dpat=simple_strtol(&buf[strlen(PARAM_DEINTERLACE_PATTERN)],NULL,16); - OUTREG(OV0_DEINTERLACE_PATTERN, dpat); - } - else count = -EIO; - radeon_vid_preset(); - return count; -} - -static int radeon_vid_mmap(struct file *file, struct vm_area_struct *vma) -{ - - RTRACE(RVID_MSG"mapping video memory into userspace\n"); - if(remap_page_range(vma->vm_start, radeon_mem_base + radeon_overlay_off, - vma->vm_end - vma->vm_start, vma->vm_page_prot)) - { - printk(RVID_MSG"error mapping video memory\n"); - return(-EAGAIN); - } - - return(0); -} - -static int radeon_vid_release(struct inode *inode, struct file *file) -{ - radeon_vid_in_use = 0; - radeon_vid_stop_video(); - - MOD_DEC_USE_COUNT; - return 0; -} - -static long long radeon_vid_lseek(struct file *file, long long offset, int origin) -{ - return -ESPIPE; -} - -static int radeon_vid_open(struct inode *inode, struct file *file) -{ - int minor = MINOR(inode->i_rdev); - - if(minor != 0) - return(-ENXIO); - - if(radeon_vid_in_use == 1) - return(-EBUSY); - - radeon_vid_in_use = 1; - MOD_INC_USE_COUNT; - return(0); -} - -#if LINUX_VERSION_CODE >= 0x020400 -static struct file_operations radeon_vid_fops = -{ - llseek: radeon_vid_lseek, - read: radeon_vid_read, - write: radeon_vid_write, -/* - readdir: - poll: -*/ - ioctl: radeon_vid_ioctl, - mmap: radeon_vid_mmap, - open: radeon_vid_open, -/* - flush: -*/ - release: radeon_vid_release -/* - fsync: - fasync: - lock: - readv: - writev: - sendpage: - get_unmapped_area: -*/ -}; -#else -static struct file_operations radeon_vid_fops = -{ - radeon_vid_lseek, - radeon_vid_read, - radeon_vid_write, - NULL, - NULL, - radeon_vid_ioctl, - radeon_vid_mmap, - radeon_vid_open, - NULL, - radeon_vid_release -}; -#endif - -/* - * Main Initialization Function - */ - -static int __init radeon_vid_initialize(void) -{ - radeon_vid_in_use = 0; -#ifdef RAGE128 - printk(RVID_MSG"Rage128/Rage128Pro video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); -#else - printk(RVID_MSG"Radeon video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); -#endif - if(register_chrdev(RADEON_VID_MAJOR, "radeon_vid", &radeon_vid_fops)) - { - printk(RVID_MSG"unable to get major: %d\n", RADEON_VID_MAJOR); - return -EIO; - } - - if (!radeon_vid_config_card()) - { - printk(RVID_MSG"can't configure this card\n"); - unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); - return -EINVAL; - } - radeon_param_buff = kmalloc(PARAM_BUFF_SIZE,GFP_KERNEL); - if(radeon_param_buff) radeon_param_buff_size = PARAM_BUFF_SIZE; -#if 0 - radeon_vid_save_state(); -#endif - radeon_vid_make_default(); - radeon_vid_preset(); -#ifdef CONFIG_MTRR - if (mtrr) { - smtrr.vram = mtrr_add(radeon_mem_base, - radeon_ram_size*0x100000, MTRR_TYPE_WRCOMB, 1); - smtrr.vram_valid = 1; - /* let there be speed */ - printk(RVID_MSG"MTRR set to ON\n"); - } -#endif /* CONFIG_MTRR */ - return(0); -} - -int __init init_module(void) -{ - return radeon_vid_initialize(); -} - -void __exit cleanup_module(void) -{ -#if 0 - radeon_vid_restore_state(); -#endif - if(radeon_mmio_base) - iounmap(radeon_mmio_base); - kfree(radeon_param_buff); - RTRACE(RVID_MSG"Cleaning up module\n"); - unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); -#ifdef CONFIG_MTRR - if (smtrr.vram_valid) - mtrr_del(smtrr.vram, radeon_mem_base, - radeon_ram_size*0x100000); -#endif /* CONFIG_MTRR */ -} -
--- a/drivers/radeon/radeon_vid.h Sat Mar 17 21:21:04 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,117 +0,0 @@ -/* - * - * radeon_vid.h - * - * Copyright (C) 2001 Nick Kurshev - * - * BES YUV Framebuffer driver for Radeon cards - * - * This software has been released under the terms of the GNU Public - * license. See http://www.gnu.org/copyleft/gpl.html for details. - * - * This file is partly based on mga_vid and sis_vid stuff from - * mplayer's package. - */ - -#ifndef __RADEON_VID_INCLUDED -#define __RADEON_VID_INCLUDED - -typedef struct mga_vid_config_s -{ -uint16_t version; -uint16_t card_type; -uint32_t ram_size; -uint32_t src_width; -uint32_t src_height; -uint32_t dest_width; -uint32_t dest_height; -uint32_t x_org; /* dest x */ -uint32_t y_org; /* dest y */ -uint8_t colkey_on; -uint8_t colkey_red; -uint8_t colkey_green; -uint8_t colkey_blue; -uint32_t format; -uint32_t frame_size; -uint32_t num_frames; -} mga_vid_config_t; - -#define IMGFMT_RGB_MASK 0xFFFFFF00 -#define IMGFMT_RGB (('R'<<24)|('G'<<16)|('B'<<8)) -#define IMGFMT_RGB8 (IMGFMT_RGB|8) -#define IMGFMT_RGB15 (IMGFMT_RGB|15) -#define IMGFMT_RGB16 (IMGFMT_RGB|16) -#define IMGFMT_RGB24 (IMGFMT_RGB|24) -#define IMGFMT_RGB32 (IMGFMT_RGB|32) - -#define IMGFMT_BGR_MASK 0xFFFFFF00 -#define IMGFMT_BGR (('B'<<24)|('G'<<16)|('R'<<8)) -#define IMGFMT_BGR8 (IMGFMT_BGR|8) -#define IMGFMT_BGR15 (IMGFMT_BGR|15) -#define IMGFMT_BGR16 (IMGFMT_BGR|16) -#define IMGFMT_BGR24 (IMGFMT_BGR|24) -#define IMGFMT_BGR32 (IMGFMT_BGR|32) - -#define IMGFMT_IS_RGB(fmt) (((fmt)&IMGFMT_RGB_MASK)==IMGFMT_RGB) -#define IMGFMT_IS_BGR(fmt) (((fmt)&IMGFMT_BGR_MASK)==IMGFMT_BGR) - -#define IMGFMT_RGB_DEPTH(fmt) ((fmt)&~IMGFMT_RGB) -#define IMGFMT_BGR_DEPTH(fmt) ((fmt)&~IMGFMT_BGR) - - -/* Planar YUV Formats */ - -#define IMGFMT_YVU9 0x39555659 -#define IMGFMT_IF09 0x39304649 -#define IMGFMT_YV12 0x32315659 -#if 0 -#define IMGFMT_I420 0x30323449 -#define IMGFMT_IYUV 0x56555949 -#else -#define IMGFMT_I420 (('I'<<24)|('4'<<16)|('2'<<8)|'0') -#define IMGFMT_IYUV (('I'<<24)|('Y'<<16)|('U'<<8)|'V') -#endif -#define IMGFMT_CLPL 0x4C504C43 -#define IMGFMT_Y800 0x30303859 -#define IMGFMT_Y8 0x20203859 - -/* Packed YUV Formats */ - -#define IMGFMT_IUYV 0x56595549 -#define IMGFMT_IY41 0x31435949 -#define IMGFMT_IYU1 0x31555949 -#define IMGFMT_IYU2 0x32555949 -#define IMGFMT_UYNV 0x564E5955 -#define IMGFMT_cyuv 0x76757963 -#define IMGFMT_Y422 0x32323459 -#if 0 -#define IMGFMT_YUY2 0x32595559 -#define IMGFMT_UYVY 0x59565955 -#else -#define IMGFMT_YUY2 (('Y'<<24)|('U'<<16)|('Y'<<8)|'2') -#define IMGFMT_UYVY (('U'<<24)|('Y'<<16)|('V'<<8)|'Y') -#endif -#define IMGFMT_YUNV 0x564E5559 -#define IMGFMT_YVYU 0x55595659 -#define IMGFMT_Y41P 0x50313459 -#define IMGFMT_Y211 0x31313259 -#define IMGFMT_Y41T 0x54313459 -#define IMGFMT_Y42T 0x54323459 -#define IMGFMT_V422 0x32323456 -#define IMGFMT_V655 0x35353656 -#define IMGFMT_CLJR 0x524A4C43 -#define IMGFMT_YUVP 0x50565559 -#define IMGFMT_UYVP 0x50565955 - -/* Compressed Formats. MPlayer's extensions!!! */ -#define IMGFMT_MPEGPES (('M'<<24)|('P'<<16)|('E'<<8)|('S')) - - -#define MGA_VID_CONFIG _IOR('J', 1, mga_vid_config_t) -#define MGA_VID_ON _IO ('J', 2) -#define MGA_VID_OFF _IO ('J', 3) -#define MGA_VID_FSEL _IOR('J', 4, int) - -#define MGA_VID_VERSION 0x0201 - -#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/drivers/radeon_vid.c Sat Mar 17 21:27:42 2007 +0000 @@ -0,0 +1,1544 @@ +/* + * + * radeon_vid.c + * + * Copyright (C) 2001 Nick Kurshev + * + * BES YUV video overlay driver for Radeon/Rage128Pro/Rage128 cards + * + * This software has been released under the terms of the GNU Public + * license. See http://www.gnu.org/copyleft/gpl.html for details. + * + * This file is partly based on mga_vid and sis_vid stuff from + * mplayer's package. + * Also here was used code from CVS of GATOS project and X11 trees. + * + * SPECIAL THANKS TO: Hans-Peter Raschke for active testing and hacking + * Rage128(pro) stuff of this driver. + */ + +#define RADEON_VID_VERSION "1.2.1" + +/* + It's entirely possible this major conflicts with something else + mknod /dev/radeon_vid c 178 0 + or + mknod /dev/rage128_vid c 178 0 + for Rage128/Rage128Pro chips (although it doesn't matter) + +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + TESTED and WORKING formats: YUY2, UYVY, IYUV, I420, YV12 + ----------------------------------------------------------- + TODO: + Highest priority: fbvid.h compatibility + High priority: Fixing BUGS + Middle priority: RGB/BGR 2-32, YVU9, IF09 support + Low priority: CLPL, IYU1, IYU2, UYNV, CYUV, YUNV, YVYU, Y41P, Y211, Y41T, + ^^^^ + Y42T, V422, V655, CLJR, YUVP, UYVP, Mpeg PES (mpeg-1,2) support + ........................................................... + BUGS and LACKS: + Color and video keys don't work +*/ + +#include <linux/config.h> +#include <linux/version.h> +#include <linux/module.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/mm.h> +#include <linux/string.h> +#include <linux/errno.h> +#include <linux/slab.h> +#include <linux/pci.h> +#include <linux/ioport.h> +#include <linux/init.h> +#include <linux/byteorder/swab.h> + +#include "radeon_vid.h" +#include "radeon.h" + +#ifdef CONFIG_MTRR +#include <asm/mtrr.h> +#endif + +#include <asm/uaccess.h> +#include <asm/system.h> +#include <asm/io.h> + +#define TRUE 1 +#define FALSE 0 + +#define RADEON_VID_MAJOR 178 + + +MODULE_AUTHOR("Nick Kurshev <nickols_k@mail.ru>"); +#ifdef RAGE128 +MODULE_DESCRIPTION("Accelerated YUV BES driver for Rage128. Version: "RADEON_VID_VERSION); +#else +MODULE_DESCRIPTION("Accelerated YUV BES driver for Radeons. Version: "RADEON_VID_VERSION); +#endif +#ifdef MODULE_LICENSE +MODULE_LICENSE("GPL"); +#endif +#ifdef CONFIG_MTRR +MODULE_PARM(mtrr, "i"); +MODULE_PARM_DESC(mtrr, "Tune MTRR (touch=1(default))"); +static int mtrr __initdata = 1; +static struct { int vram; int vram_valid; } smtrr; +#endif +MODULE_PARM(swap_fourcc, "i"); +MODULE_PARM_DESC(swap_fourcc, "Swap fourcc (don't swap=0(default))"); +static int swap_fourcc __initdata = 0; + +#ifdef RAGE128 +#define RVID_MSG "rage128_vid: " +#define X_ADJUST 0 +#else +#define RVID_MSG "radeon_vid: " +#define X_ADJUST 8 +#ifndef RADEON +#define RADEON +#endif +#endif + +#undef DEBUG +#if DEBUG +#define RTRACE printk +#else +#define RTRACE(...) ((void)0) +#endif + +#ifndef min +#define min(a,b) (a < b ? a : b) +#endif + +#ifndef RAGE128 +#if defined(__i386__) +/* Ugly but only way */ +#undef AVOID_FPU +static double inline __FastSin(double x) +{ + register double res; + __asm __volatile("fsin":"=t"(res):"0"(x)); + return res; +} +#undef sin +#define sin(x) __FastSin(x) + +static double inline __FastCos(double x) +{ + register double res; + __asm __volatile("fcos":"=t"(res):"0"(x)); + return res; +} +#undef cos +#define cos(x) __FastCos(x) +#else +#include "generic_math.h" +#endif /*__386__*/ +#endif /*RAGE128*/ + +#if !defined( RAGE128 ) && !defined( AVOID_FPU ) +#define RADEON_FPU 1 +#endif + +typedef struct bes_registers_s +{ + /* base address of yuv framebuffer */ + uint32_t yuv_base; + uint32_t fourcc; + uint32_t dest_bpp; + /* YUV BES registers */ + uint32_t reg_load_cntl; + uint32_t h_inc; + uint32_t step_by; + uint32_t y_x_start; + uint32_t y_x_end; + uint32_t v_inc; + uint32_t p1_blank_lines_at_top; + uint32_t p23_blank_lines_at_top; + uint32_t vid_buf_pitch0_value; + uint32_t vid_buf_pitch1_value; + uint32_t p1_x_start_end; + uint32_t p2_x_start_end; + uint32_t p3_x_start_end; + uint32_t base_addr; + uint32_t vid_buf0_base_adrs; + /* These ones are for auto flip: maybe in the future */ + uint32_t vid_buf1_base_adrs; + uint32_t vid_buf2_base_adrs; + uint32_t vid_buf3_base_adrs; + uint32_t vid_buf4_base_adrs; + uint32_t vid_buf5_base_adrs; + + uint32_t p1_v_accum_init; + uint32_t p1_h_accum_init; + uint32_t p23_v_accum_init; + uint32_t p23_h_accum_init; + uint32_t scale_cntl; + uint32_t exclusive_horz; + uint32_t auto_flip_cntl; + uint32_t filter_cntl; + uint32_t key_cntl; + uint32_t test; + /* Configurable stuff */ + int double_buff; + + int brightness; + int saturation; + + int ckey_on; + uint32_t graphics_key_clr; + uint32_t graphics_key_msk; + + int deinterlace_on; + uint32_t deinterlace_pattern; + +} bes_registers_t; + +typedef struct video_registers_s +{ +#ifdef DEBUG + const char * sname; +#endif + uint32_t name; + uint32_t value; +}video_registers_t; + +static bes_registers_t besr; +#ifndef RAGE128 +static int IsR200=0; +#endif +#ifdef DEBUG +#define DECLARE_VREG(name) { #name, name, 0 } +#else +#define DECLARE_VREG(name) { name, 0 } +#endif +#ifdef DEBUG +static video_registers_t vregs[] = +{ + DECLARE_VREG(VIDEOMUX_CNTL), + DECLARE_VREG(VIPPAD_MASK), + DECLARE_VREG(VIPPAD1_A), + DECLARE_VREG(VIPPAD1_EN), + DECLARE_VREG(VIPPAD1_Y), + DECLARE_VREG(OV0_Y_X_START), + DECLARE_VREG(OV0_Y_X_END), + DECLARE_VREG(OV0_PIPELINE_CNTL), + DECLARE_VREG(OV0_EXCLUSIVE_HORZ), + DECLARE_VREG(OV0_EXCLUSIVE_VERT), + DECLARE_VREG(OV0_REG_LOAD_CNTL), + DECLARE_VREG(OV0_SCALE_CNTL), + DECLARE_VREG(OV0_V_INC), + DECLARE_VREG(OV0_P1_V_ACCUM_INIT), + DECLARE_VREG(OV0_P23_V_ACCUM_INIT), + DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), + DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), +#ifdef RADEON + DECLARE_VREG(OV0_BASE_ADDR), +#endif + DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), + DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), + DECLARE_VREG(OV0_AUTO_FLIP_CNTL), + DECLARE_VREG(OV0_DEINTERLACE_PATTERN), + DECLARE_VREG(OV0_SUBMIT_HISTORY), + DECLARE_VREG(OV0_H_INC), + DECLARE_VREG(OV0_STEP_BY), + DECLARE_VREG(OV0_P1_H_ACCUM_INIT), + DECLARE_VREG(OV0_P23_H_ACCUM_INIT), + DECLARE_VREG(OV0_P1_X_START_END), + DECLARE_VREG(OV0_P2_X_START_END), + DECLARE_VREG(OV0_P3_X_START_END), + DECLARE_VREG(OV0_FILTER_CNTL), + DECLARE_VREG(OV0_FOUR_TAP_COEF_0), + DECLARE_VREG(OV0_FOUR_TAP_COEF_1), + DECLARE_VREG(OV0_FOUR_TAP_COEF_2), + DECLARE_VREG(OV0_FOUR_TAP_COEF_3), + DECLARE_VREG(OV0_FOUR_TAP_COEF_4), + DECLARE_VREG(OV0_FLAG_CNTL), +#ifdef RAGE128 + DECLARE_VREG(OV0_COLOUR_CNTL), +#else + DECLARE_VREG(OV0_SLICE_CNTL), +#endif + DECLARE_VREG(OV0_VID_KEY_CLR), + DECLARE_VREG(OV0_VID_KEY_MSK), + DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), + DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), + DECLARE_VREG(OV0_KEY_CNTL), + DECLARE_VREG(OV0_TEST), + DECLARE_VREG(OV0_LIN_TRANS_A), + DECLARE_VREG(OV0_LIN_TRANS_B), + DECLARE_VREG(OV0_LIN_TRANS_C), + DECLARE_VREG(OV0_LIN_TRANS_D), + DECLARE_VREG(OV0_LIN_TRANS_E), + DECLARE_VREG(OV0_LIN_TRANS_F), + DECLARE_VREG(OV0_GAMMA_0_F), + DECLARE_VREG(OV0_GAMMA_10_1F), + DECLARE_VREG(OV0_GAMMA_20_3F), + DECLARE_VREG(OV0_GAMMA_40_7F), + DECLARE_VREG(OV0_GAMMA_380_3BF), + DECLARE_VREG(OV0_GAMMA_3C0_3FF), + DECLARE_VREG(SUBPIC_CNTL), + DECLARE_VREG(SUBPIC_DEFCOLCON), + DECLARE_VREG(SUBPIC_Y_X_START), + DECLARE_VREG(SUBPIC_Y_X_END), + DECLARE_VREG(SUBPIC_V_INC), + DECLARE_VREG(SUBPIC_H_INC), + DECLARE_VREG(SUBPIC_BUF0_OFFSET), + DECLARE_VREG(SUBPIC_BUF1_OFFSET), + DECLARE_VREG(SUBPIC_LC0_OFFSET), + DECLARE_VREG(SUBPIC_LC1_OFFSET), + DECLARE_VREG(SUBPIC_PITCH), + DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), + DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), + DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), + DECLARE_VREG(SUBPIC_PALETTE_INDEX), + DECLARE_VREG(SUBPIC_PALETTE_DATA), + DECLARE_VREG(SUBPIC_H_ACCUM_INIT), + DECLARE_VREG(SUBPIC_V_ACCUM_INIT), + DECLARE_VREG(IDCT_RUNS), + DECLARE_VREG(IDCT_LEVELS), + DECLARE_VREG(IDCT_AUTH_CONTROL), + DECLARE_VREG(IDCT_AUTH), + DECLARE_VREG(IDCT_CONTROL) +}; +#endif +static uint32_t radeon_vid_in_use = 0; + +static uint8_t *radeon_mmio_base = 0; +static uint32_t radeon_mem_base = 0; +static int32_t radeon_overlay_off = 0; +static uint32_t radeon_ram_size = 0; +#define PARAM_BUFF_SIZE 4096 +static uint8_t *radeon_param_buff = NULL; +static uint32_t radeon_param_buff_size=0; +static uint32_t radeon_param_buff_len=0; /* real length of buffer */ +static mga_vid_config_t radeon_config; + +static char *fourcc_format_name(int format) +{ + switch(format) + { + case IMGFMT_RGB8: return("RGB 8-bit"); + case IMGFMT_RGB15: return("RGB 15-bit"); + case IMGFMT_RGB16: return("RGB 16-bit"); + case IMGFMT_RGB24: return("RGB 24-bit"); + case IMGFMT_RGB32: return("RGB 32-bit"); + case IMGFMT_BGR8: return("BGR 8-bit"); + case IMGFMT_BGR15: return("BGR 15-bit"); + case IMGFMT_BGR16: return("BGR 16-bit"); + case IMGFMT_BGR24: return("BGR 24-bit"); + case IMGFMT_BGR32: return("BGR 32-bit"); + case IMGFMT_YVU9: return("Planar YVU9"); + case IMGFMT_IF09: return("Planar IF09"); + case IMGFMT_YV12: return("Planar YV12"); + case IMGFMT_I420: return("Planar I420"); + case IMGFMT_IYUV: return("Planar IYUV"); + case IMGFMT_CLPL: return("Planar CLPL"); + case IMGFMT_Y800: return("Planar Y800"); + case IMGFMT_Y8: return("Planar Y8"); + case IMGFMT_IUYV: return("Packed IUYV"); + case IMGFMT_IY41: return("Packed IY41"); + case IMGFMT_IYU1: return("Packed IYU1"); + case IMGFMT_IYU2: return("Packed IYU2"); + case IMGFMT_UYNV: return("Packed UYNV"); + case IMGFMT_cyuv: return("Packed CYUV"); + case IMGFMT_Y422: return("Packed Y422"); + case IMGFMT_YUY2: return("Packed YUY2"); + case IMGFMT_YUNV: return("Packed YUNV"); + case IMGFMT_UYVY: return("Packed UYVY"); +// case IMGFMT_YVYU: return("Packed YVYU"); + case IMGFMT_Y41P: return("Packed Y41P"); + case IMGFMT_Y211: return("Packed Y211"); + case IMGFMT_Y41T: return("Packed Y41T"); + case IMGFMT_Y42T: return("Packed Y42T"); + case IMGFMT_V422: return("Packed V422"); + case IMGFMT_V655: return("Packed V655"); + case IMGFMT_CLJR: return("Packed CLJR"); + case IMGFMT_YUVP: return("Packed YUVP"); + case IMGFMT_UYVP: return("Packed UYVP"); + case IMGFMT_MPEGPES: return("Mpeg PES"); + } + return("Unknown"); +} + + +/* + * IO macros + */ + +#define INREG8(addr) readb((radeon_mmio_base)+addr) +#define OUTREG8(addr,val) writeb(val, (radeon_mmio_base)+addr) +#define INREG(addr) readl((radeon_mmio_base)+addr) +#define OUTREG(addr,val) writel(val, (radeon_mmio_base)+addr) +#define OUTREGP(addr,val,mask) \ + do { \ + unsigned int _tmp = INREG(addr); \ + _tmp &= (mask); \ + _tmp |= (val); \ + OUTREG(addr, _tmp); \ + } while (0) + +static uint32_t radeon_vid_get_dbpp( void ) +{ + uint32_t dbpp,retval; + dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; + switch(dbpp) + { + case DST_8BPP: retval = 8; break; + case DST_15BPP: retval = 15; break; + case DST_16BPP: retval = 16; break; + case DST_24BPP: retval = 24; break; + default: retval=32; break; + } + return retval; +} + +static int radeon_is_dbl_scan( void ) +{ + return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; +} + +static int radeon_is_interlace( void ) +{ + return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; +} + +static __inline__ void radeon_engine_flush ( void ) +{ + int i; + + /* initiate flush */ + OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, + ~RB2D_DC_FLUSH_ALL); + + for (i=0; i < 2000000; i++) { + if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) + break; + } +} + + +static __inline__ void _radeon_fifo_wait (int entries) +{ + int i; + + for (i=0; i<2000000; i++) + if ((INREG(RBBM_STATUS) & 0x7f) >= entries) + return; +} + + +static __inline__ void _radeon_engine_idle ( void ) +{ + int i; + + /* ensure FIFO is empty before waiting for idle */ + _radeon_fifo_wait (64); + + for (i=0; i<2000000; i++) { + if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { + radeon_engine_flush (); + return; + } + } +} + +#define radeon_engine_idle() _radeon_engine_idle() +#define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) + +#if 0 +static void __init radeon_vid_save_state( void ) +{ + size_t i; + for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) + vregs[i].value = INREG(vregs[i].name); +} + +static void __exit radeon_vid_restore_state( void ) +{ + size_t i; + radeon_fifo_wait(2); + OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); + radeon_engine_idle(); + while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); + radeon_fifo_wait(15); + for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) + { + radeon_fifo_wait(1); + OUTREG(vregs[i].name,vregs[i].value); + } + OUTREG(OV0_REG_LOAD_CNTL, 0); +} +#endif +#ifdef DEBUG +static void radeon_vid_dump_regs( void ) +{ + size_t i; + printk(RVID_MSG"*** Begin of OV0 registers dump ***\n"); + for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) + printk(RVID_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); + printk(RVID_MSG"*** End of OV0 registers dump ***\n"); +} +#endif + +#ifdef RADEON_FPU +/* Reference color space transform data */ +typedef struct tagREF_TRANSFORM +{ + float RefLuma; + float RefRCb; + float RefRCr; + float RefGCb; + float RefGCr; + float RefBCb; + float RefBCr; +} REF_TRANSFORM; + +/* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ +REF_TRANSFORM trans[2] = +{ + {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ + {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ +}; +/**************************************************************************** + * SetTransform * + * Function: Calculates and sets color space transform from supplied * + * reference transform, gamma, brightness, contrast, hue and * + * saturation. * + * Inputs: bright - brightness * + * cont - contrast * + * sat - saturation * + * hue - hue * + * ref - index to the table of refernce transforms * + * Outputs: NONE * + ****************************************************************************/ + +static void radeon_set_transform(float bright, float cont, float sat, + float hue, unsigned ref) +{ + float OvHueSin, OvHueCos; + float CAdjLuma, CAdjOff; + float CAdjRCb, CAdjRCr; + float CAdjGCb, CAdjGCr; + float CAdjBCb, CAdjBCr; + float OvLuma, OvROff, OvGOff, OvBOff; + float OvRCb, OvRCr; + float OvGCb, OvGCr; + float OvBCb, OvBCr; + float Loff = 64.0; + float Coff = 512.0f; + + u32 dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; + u32 dwOvRCb, dwOvRCr; + u32 dwOvGCb, dwOvGCr; + u32 dwOvBCb, dwOvBCr; + + if (ref >= 2) return; + + OvHueSin = sin((double)hue); + OvHueCos = cos((double)hue); + + CAdjLuma = cont * trans[ref].RefLuma; + CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; + + CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; + CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; + CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); + CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); + CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; + CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; + +#if 0 /* default constants */ + CAdjLuma = 1.16455078125; + + CAdjRCb = 0.0; + CAdjRCr = 1.59619140625; + CAdjGCb = -0.39111328125; + CAdjGCr = -0.8125; + CAdjBCb = 2.01708984375; + CAdjBCr = 0; +#endif + OvLuma = CAdjLuma; + OvRCb = CAdjRCb; + OvRCr = CAdjRCr; + OvGCb = CAdjGCb; + OvGCr = CAdjGCr; + OvBCb = CAdjBCb; + OvBCr = CAdjBCr; + OvROff = CAdjOff - + OvLuma * Loff - (OvRCb + OvRCr) * Coff; + OvGOff = CAdjOff - + OvLuma * Loff - (OvGCb + OvGCr) * Coff; + OvBOff = CAdjOff - + OvLuma * Loff - (OvBCb + OvBCr) * Coff; +#if 0 /* default constants */ + OvROff = -888.5; + OvGOff = 545; + OvBOff = -1104; +#endif + + dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; + dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; + dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; + if(!IsR200) + { + dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; + dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; + dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; + dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; + dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; + dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; + dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; + } + else + { + dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; + dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; + dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; + dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; + dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; + dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; + dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; + } + + OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); + OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); + OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); + OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); + OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); + OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); +} +#endif + +#ifndef RAGE128 +/* Gamma curve definition */ +typedef struct +{ + unsigned int gammaReg; + unsigned int gammaSlope; + unsigned int gammaOffset; +}GAMMA_SETTINGS; + +/* Recommended gamma curve parameters */ +GAMMA_SETTINGS r200_def_gamma[18] = +{ + {OV0_GAMMA_0_F, 0x100, 0x0000}, + {OV0_GAMMA_10_1F, 0x100, 0x0020}, + {OV0_GAMMA_20_3F, 0x100, 0x0040}, + {OV0_GAMMA_40_7F, 0x100, 0x0080}, + {OV0_GAMMA_80_BF, 0x100, 0x0100}, + {OV0_GAMMA_C0_FF, 0x100, 0x0100}, + {OV0_GAMMA_100_13F, 0x100, 0x0200}, + {OV0_GAMMA_140_17F, 0x100, 0x0200}, + {OV0_GAMMA_180_1BF, 0x100, 0x0300}, + {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, + {OV0_GAMMA_200_23F, 0x100, 0x0400}, + {OV0_GAMMA_240_27F, 0x100, 0x0400}, + {OV0_GAMMA_280_2BF, 0x100, 0x0500}, + {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, + {OV0_GAMMA_300_33F, 0x100, 0x0600}, + {OV0_GAMMA_340_37F, 0x100, 0x0600}, + {OV0_GAMMA_380_3BF, 0x100, 0x0700}, + {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} +}; + +GAMMA_SETTINGS r100_def_gamma[6] = +{ + {OV0_GAMMA_0_F, 0x100, 0x0000}, + {OV0_GAMMA_10_1F, 0x100, 0x0020}, + {OV0_GAMMA_20_3F, 0x100, 0x0040}, + {OV0_GAMMA_40_7F, 0x100, 0x0080}, + {OV0_GAMMA_380_3BF, 0x100, 0x0100}, + {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} +}; + +static void make_default_gamma_correction( void ) +{ + size_t i; + if(!IsR200){ + OUTREG(OV0_LIN_TRANS_A, 0x12A00000); + OUTREG(OV0_LIN_TRANS_B, 0x199018FE); + OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); + OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); + OUTREG(OV0_LIN_TRANS_E, 0x12A02050); + OUTREG(OV0_LIN_TRANS_F, 0x0000174E); + for(i=0; i<6; i++){ + OUTREG(r100_def_gamma[i].gammaReg, + (r100_def_gamma[i].gammaSlope<<16) | + r100_def_gamma[i].gammaOffset); + } + } + else{ + OUTREG(OV0_LIN_TRANS_A, 0x12a00000); + OUTREG(OV0_LIN_TRANS_B, 0x1990190e); + OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); + OUTREG(OV0_LIN_TRANS_D, 0xf3000442); + OUTREG(OV0_LIN_TRANS_E, 0x12a02040); + OUTREG(OV0_LIN_TRANS_F, 0x175f); + + /* Default Gamma, + Of 18 segments for gamma cure, all segments in R200 are programmable, + while only lower 4 and upper 2 segments are programmable in Radeon*/ + for(i=0; i<18; i++){ + OUTREG(r200_def_gamma[i].gammaReg, + (r200_def_gamma[i].gammaSlope<<16) | + r200_def_gamma[i].gammaOffset); + } + } +} +#endif + +static void radeon_vid_stop_video( void ) +{ + radeon_engine_idle(); + OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); + OUTREG(OV0_EXCLUSIVE_HORZ, 0); + OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ + OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); + OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); + OUTREG(OV0_TEST, 0); +} + +static void radeon_vid_display_video( void ) +{ + int bes_flags; + radeon_fifo_wait(2); + OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); + radeon_engine_idle(); + while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); + radeon_fifo_wait(15); + OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); + OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); + OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); + + OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); +#ifdef RAGE128 + OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | + (besr.saturation << 8) | + (besr.saturation << 16)); +#endif + radeon_fifo_wait(2); + if(besr.ckey_on) + { + OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); + OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); + OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_EQ|VIDEO_KEY_FN_FALSE|CMP_MIX_OR); + } + else + { + OUTREG(OV0_GRAPHICS_KEY_MSK, 0ULL); + OUTREG(OV0_GRAPHICS_KEY_CLR, 0ULL); + OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_NE); + } + + OUTREG(OV0_H_INC, besr.h_inc); + OUTREG(OV0_STEP_BY, besr.step_by); + OUTREG(OV0_Y_X_START, besr.y_x_start); + OUTREG(OV0_Y_X_END, besr.y_x_end); + OUTREG(OV0_V_INC, besr.v_inc); + OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); + OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); + OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); + OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); + OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); + OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); + OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); +#ifdef RADEON + OUTREG(OV0_BASE_ADDR, besr.base_addr); +#endif + OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs); + OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs); + OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs); + radeon_fifo_wait(9); + OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs); + OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs); + OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf5_base_adrs); + OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); + OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); + OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); + OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); + +#ifdef RADEON + bes_flags = SCALER_ENABLE | + SCALER_SMART_SWITCH; +// SCALER_HORZ_PICK_NEAREST; +#else + bes_flags = SCALER_ENABLE | + SCALER_SMART_SWITCH | + SCALER_Y2R_TEMP | + SCALER_PIX_EXPAND; +#endif + if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; + if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; +#ifdef RAGE128 + bes_flags |= SCALER_BURST_PER_PLANE; +#endif + switch(besr.fourcc) + { + case IMGFMT_RGB15: + case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; + case IMGFMT_RGB16: + case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; + case IMGFMT_RGB24: + case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; + case IMGFMT_RGB32: + case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; + /* 4:1:0*/ + case IMGFMT_IF09: + case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_I420: + case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; + break; + /* 4:2:2 */ + case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; + case IMGFMT_YUY2: + default: bes_flags |= SCALER_SOURCE_VYUY422; break; + } + OUTREG(OV0_SCALE_CNTL, bes_flags); + OUTREG(OV0_REG_LOAD_CNTL, 0); +#ifdef DEBUG + radeon_vid_dump_regs(); +#endif +} + +void radeon_vid_set_color_key(int ckey_on, uint8_t R, uint8_t G, uint8_t B) +{ + besr.ckey_on = ckey_on; + besr.graphics_key_msk=(1ULL<<radeon_vid_get_dbpp()) - 1; + besr.graphics_key_clr=(R<<16)|(G<<8)|(B)|(0x00 << 24); +} + + +#define XXX_SRC_X 0 +#define XXX_SRC_Y 0 + +static int radeon_vid_init_video( mga_vid_config_t *config ) +{ + uint32_t tmp,src_w,src_h,pitch,h_inc,step_by,left,leftUV,top; + int is_420; +RTRACE(RVID_MSG"usr_config: version = %x format=%x card=%x ram=%u src(%ux%u) dest(%u:%ux%u:%u) frame_size=%u num_frames=%u\n" + ,(uint32_t)config->version + ,(uint32_t)config->format + ,(uint32_t)config->card_type + ,(uint32_t)config->ram_size + ,(uint32_t)config->src_width + ,(uint32_t)config->src_height + ,(uint32_t)config->x_org + ,(uint32_t)config->y_org + ,(uint32_t)config->dest_width + ,(uint32_t)config->dest_height + ,(uint32_t)config->frame_size + ,(uint32_t)config->num_frames); + radeon_vid_stop_video(); + left = XXX_SRC_X << 16; + top = XXX_SRC_Y << 16; + src_h = config->src_height; + src_w = config->src_width; + switch(config->format) + { + case IMGFMT_RGB15: + case IMGFMT_BGR15: + case IMGFMT_RGB16: + case IMGFMT_BGR16: + case IMGFMT_RGB24: + case IMGFMT_BGR24: + case IMGFMT_RGB32: + case IMGFMT_BGR32: + /* 4:1:0 */ + case IMGFMT_IF09: + case IMGFMT_YVU9: + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_YV12: + case IMGFMT_I420: + /* 4:2:2 */ + case IMGFMT_UYVY: + case IMGFMT_YUY2: + break; + default: + printk(RVID_MSG"Unsupported pixel format: 0x%X\n",config->format); + return -1; + } + is_420 = 0; + if(config->format == IMGFMT_YV12 || + config->format == IMGFMT_I420 || + config->format == IMGFMT_IYUV) is_420 = 1; + switch(config->format) + { + /* 4:1:0 */ + case IMGFMT_YVU9: + case IMGFMT_IF09: + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_YV12: + case IMGFMT_I420: pitch = (src_w + 31) & ~31; break; + /* 4:2:2 */ + default: + case IMGFMT_UYVY: + case IMGFMT_YUY2: + case IMGFMT_RGB15: + case IMGFMT_BGR15: + case IMGFMT_RGB16: + case IMGFMT_BGR16: pitch = ((src_w*2) + 15) & ~15; break; + case IMGFMT_RGB24: + case IMGFMT_BGR24: pitch = ((src_w*3) + 15) & ~15; break; + case IMGFMT_RGB32: + case IMGFMT_BGR32: pitch = ((src_w*4) + 15) & ~15; break; + } + if(radeon_is_dbl_scan()) config->dest_height *= 2; + else + if(radeon_is_interlace()) config->dest_height /= 2; + besr.dest_bpp = radeon_vid_get_dbpp(); + besr.fourcc = config->format; + besr.v_inc = (src_h << 20) / config->dest_height; + h_inc = (src_w << 12) / config->dest_width; + step_by = 1; + + while(h_inc >= (2 << 12)) { + step_by++; + h_inc >>= 1; + } + + /* keep everything in 16.16 */ + besr.base_addr = radeon_mem_base; + if(is_420) + { + uint32_t d1line,d2line,d3line; + d1line = top*pitch; + d2line = src_h*pitch+(d1line>>1); + d3line = d2line+((src_h*pitch)>>2); + d1line += (left >> 16) & ~15; + d2line += (left >> 17) & ~15; + d3line += (left >> 17) & ~15; + besr.vid_buf0_base_adrs=((radeon_overlay_off+d1line)&VIF_BUF0_BASE_ADRS_MASK); + besr.vid_buf1_base_adrs=((radeon_overlay_off+d2line)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; + besr.vid_buf2_base_adrs=((radeon_overlay_off+d3line)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; + if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) + { + uint32_t tmp; + tmp = besr.vid_buf1_base_adrs; + besr.vid_buf1_base_adrs = besr.vid_buf2_base_adrs; + besr.vid_buf2_base_adrs = tmp; + } + } + else + { + besr.vid_buf0_base_adrs = radeon_overlay_off; + besr.vid_buf0_base_adrs += ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; + besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs; + besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs; + } + besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; + besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs+config->frame_size; + besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs+config->frame_size; + + tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); + besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | + ((tmp << 12) & 0xf0000000); + + tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); + besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | + ((tmp << 12) & 0x70000000); + tmp = (top & 0x0000ffff) + 0x00018000; + besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) + |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); + + tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; + besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) + |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; + + leftUV = (left >> 17) & 15; + left = (left >> 16) & 15; + besr.h_inc = h_inc | ((h_inc >> 1) << 16); + besr.step_by = step_by | (step_by << 8); + besr.y_x_start = (config->x_org+X_ADJUST) | (config->y_org << 16); + besr.y_x_end = (config->x_org + config->dest_width+X_ADJUST) | ((config->y_org + config->dest_height) << 16); + besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); + if(is_420) + { + src_h = (src_h + 1) >> 1; + besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); + } + else besr.p23_blank_lines_at_top = 0; + besr.vid_buf_pitch0_value = pitch; + besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch; + besr.p1_x_start_end = (src_w+left-1)|(left<<16); + src_w>>=1; + besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); + besr.p3_x_start_end = besr.p2_x_start_end; + return 0; +} + +static void radeon_vid_frame_sel(int frame) +{ + uint32_t off0,off1,off2; + if(!besr.double_buff) return; + if(frame%2) + { + off0 = besr.vid_buf3_base_adrs; + off1 = besr.vid_buf4_base_adrs; + off2 = besr.vid_buf5_base_adrs; + } + else + { + off0 = besr.vid_buf0_base_adrs; + off1 = besr.vid_buf1_base_adrs; + off2 = besr.vid_buf2_base_adrs; + } + OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); + while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); + OUTREG(OV0_VID_BUF0_BASE_ADRS, off0); + OUTREG(OV0_VID_BUF1_BASE_ADRS, off1); + OUTREG(OV0_VID_BUF2_BASE_ADRS, off2); + OUTREG(OV0_REG_LOAD_CNTL, 0); +} + +static void radeon_vid_make_default(void) +{ +#ifdef RAGE128 + OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brihgtness and saturation for Rage128 */ +#else + make_default_gamma_correction(); +#endif + besr.deinterlace_pattern = 0x900AAAAA; + OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); + besr.deinterlace_on=1; + besr.double_buff=1; +} + + +static void radeon_vid_preset(void) +{ +#ifdef RAGE128 + unsigned tmp; + tmp = INREG(OV0_COLOUR_CNTL); + besr.saturation = (tmp>>8)&0x1f; + besr.brightness = tmp & 0x7f; +#endif + besr.graphics_key_clr = INREG(OV0_GRAPHICS_KEY_CLR); + besr.deinterlace_pattern = INREG(OV0_DEINTERLACE_PATTERN); +} + +static int video_on = 0; + +static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) +{ + int frame; + + switch(cmd) + { + case MGA_VID_CONFIG: + RTRACE(RVID_MSG"radeon_mmio_base = %p\n",radeon_mmio_base); + RTRACE(RVID_MSG"radeon_mem_base = %08x\n",radeon_mem_base); + RTRACE(RVID_MSG"Received configuration\n"); + + if(copy_from_user(&radeon_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t))) + { + printk(RVID_MSG"failed copy from userspace\n"); + return -EFAULT; + } + if(radeon_config.version != MGA_VID_VERSION){ + printk(RVID_MSG"incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,radeon_config.version); + return -EFAULT; + } + + if(radeon_config.frame_size==0 || radeon_config.frame_size>1024*768*2){ + printk(RVID_MSG"illegal frame_size: %d\n",radeon_config.frame_size); + return -EFAULT; + } + + if(radeon_config.num_frames<1){ + printk(RVID_MSG"illegal num_frames: %d\n",radeon_config.num_frames); + return -EFAULT; + } + if(radeon_config.num_frames==1) besr.double_buff=0; + if(!besr.double_buff) radeon_config.num_frames=1; + else radeon_config.num_frames=2; + radeon_config.card_type = 0; + radeon_config.ram_size = radeon_ram_size; + radeon_overlay_off = radeon_ram_size*0x100000 - radeon_config.frame_size*radeon_config.num_frames; + radeon_overlay_off &= 0xffff0000; + if(radeon_overlay_off < 0){ + printk(RVID_MSG"not enough video memory. Need: %u has: %u\n",radeon_config.frame_size*radeon_config.num_frames,radeon_ram_size*0x100000); + return -EFAULT; + } + RTRACE(RVID_MSG"using video overlay at offset %08X\n",radeon_overlay_off); + if (copy_to_user((mga_vid_config_t *) arg, &radeon_config, sizeof(mga_vid_config_t))) + { + printk(RVID_MSG"failed copy to userspace\n"); + return -EFAULT; + } + radeon_vid_set_color_key(radeon_config.colkey_on, + radeon_config.colkey_red, + radeon_config.colkey_green, + radeon_config.colkey_blue); + if(swap_fourcc) radeon_config.format = swab32(radeon_config.format); + printk(RVID_MSG"configuring for '%s' fourcc\n",fourcc_format_name(radeon_config.format)); + return radeon_vid_init_video(&radeon_config); + break; + + case MGA_VID_ON: + RTRACE(RVID_MSG"Video ON (ioctl)\n"); + radeon_vid_display_video(); + video_on = 1; + break; + + case MGA_VID_OFF: + RTRACE(RVID_MSG"Video OFF (ioctl)\n"); + if(video_on) radeon_vid_stop_video(); + video_on = 0; + break; + + case MGA_VID_FSEL: + if(copy_from_user(&frame,(int *) arg,sizeof(int))) + { + printk(RVID_MSG"FSEL failed copy from userspace\n"); + return(-EFAULT); + } + radeon_vid_frame_sel(frame); + break; + + default: + printk(RVID_MSG"Invalid ioctl\n"); + return (-EINVAL); + } + + return 0; +} + +struct ati_card_id_s +{ + const int id; + const char name[17]; +}; + +const struct ati_card_id_s ati_card_ids[]= +{ +#ifdef RAGE128 + /* + This driver should be compatible with Rage128 (pro) chips. + (include adaptive deinterlacing!!!). + Moreover: the same logic can be used with Mach64 chips. + (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). + but they are incompatible by i/o ports. So if enthusiasts will want + then they can redefine OUTREG and INREG macros and redefine OV0_* + constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY + fourccs (422 and 420 formats only). + */ +/* Rage128 Pro GL */ + { PCI_DEVICE_ID_ATI_Rage128_PA, "R128Pro PA" }, + { PCI_DEVICE_ID_ATI_Rage128_PB, "R128Pro PB" }, + { PCI_DEVICE_ID_ATI_Rage128_PC, "R128Pro PC" }, + { PCI_DEVICE_ID_ATI_Rage128_PD, "R128Pro PD" }, + { PCI_DEVICE_ID_ATI_Rage128_PE, "R128Pro PE" }, + { PCI_DEVICE_ID_ATI_RAGE128_PF, "R128Pro PF" }, +/* Rage128 Pro VR */ + { PCI_DEVICE_ID_ATI_RAGE128_PG, "R128Pro PG" }, + { PCI_DEVICE_ID_ATI_RAGE128_PH, "R128Pro PH" }, + { PCI_DEVICE_ID_ATI_RAGE128_PI, "R128Pro PI" }, + { PCI_DEVICE_ID_ATI_RAGE128_PJ, "R128Pro PJ" }, + { PCI_DEVICE_ID_ATI_RAGE128_PK, "R128Pro PK" }, + { PCI_DEVICE_ID_ATI_RAGE128_PL, "R128Pro PL" }, + { PCI_DEVICE_ID_ATI_RAGE128_PM, "R128Pro PM" }, + { PCI_DEVICE_ID_ATI_RAGE128_PN, "R128Pro PN" }, + { PCI_DEVICE_ID_ATI_RAGE128_PO, "R128Pro PO" }, + { PCI_DEVICE_ID_ATI_RAGE128_PP, "R128Pro PP" }, + { PCI_DEVICE_ID_ATI_RAGE128_PQ, "R128Pro PQ" }, + { PCI_DEVICE_ID_ATI_RAGE128_PR, "R128Pro PR" }, + { PCI_DEVICE_ID_ATI_RAGE128_TR, "R128Pro TR" }, + { PCI_DEVICE_ID_ATI_RAGE128_PS, "R128Pro PS" }, + { PCI_DEVICE_ID_ATI_RAGE128_PT, "R128Pro PT" }, + { PCI_DEVICE_ID_ATI_RAGE128_PU, "R128Pro PU" }, + { PCI_DEVICE_ID_ATI_RAGE128_PV, "R128Pro PV" }, + { PCI_DEVICE_ID_ATI_RAGE128_PW, "R128Pro PW" }, + { PCI_DEVICE_ID_ATI_RAGE128_PX, "R128Pro PX" }, +/* Rage128 GL */ + { PCI_DEVICE_ID_ATI_RAGE128_RE, "R128 RE" }, + { PCI_DEVICE_ID_ATI_RAGE128_RF, "R128 RF" }, + { PCI_DEVICE_ID_ATI_RAGE128_RG, "R128 RG" }, + { PCI_DEVICE_ID_ATI_RAGE128_RH, "R128 RH" }, + { PCI_DEVICE_ID_ATI_RAGE128_RI, "R128 RI" }, +/* Rage128 VR */ + { PCI_DEVICE_ID_ATI_RAGE128_RK, "R128 RK" }, + { PCI_DEVICE_ID_ATI_RAGE128_RL, "R128 RL" }, + { PCI_DEVICE_ID_ATI_RAGE128_RM, "R128 RM" }, + { PCI_DEVICE_ID_ATI_RAGE128_RN, "R128 RN" }, + { PCI_DEVICE_ID_ATI_RAGE128_RO, "R128 RO" }, +/* Rage128 M3 */ + { PCI_DEVICE_ID_ATI_RAGE128_LE, "R128 M3 LE" }, + { PCI_DEVICE_ID_ATI_RAGE128_LF, "R128 M3 LF" }, +/* Rage128 Pro Ultra */ + { PCI_DEVICE_ID_ATI_RAGE128_U1, "R128Pro U1" }, + { PCI_DEVICE_ID_ATI_RAGE128_U2, "R128Pro U2" }, + { PCI_DEVICE_ID_ATI_RAGE128_U3, "R128Pro U3" } +#else +/* Radeons (indeed: Rage 256 Pro ;) */ + { PCI_DEVICE_ID_RADEON_QD, "Radeon QD " }, + { PCI_DEVICE_ID_RADEON_QE, "Radeon QE " }, + { PCI_DEVICE_ID_RADEON_QF, "Radeon QF " }, + { PCI_DEVICE_ID_RADEON_QG, "Radeon QG " }, + { PCI_DEVICE_ID_RADEON_QY, "Radeon VE QY " }, + { PCI_DEVICE_ID_RADEON_QZ, "Radeon VE QZ " }, + { PCI_DEVICE_ID_RADEON_LY, "Radeon M6 LY " }, + { PCI_DEVICE_ID_RADEON_LZ, "Radeon M6 LZ " }, + { PCI_DEVICE_ID_RADEON_LW, "Radeon M7 LW " }, + { PCI_DEVICE_ID_R200_QL, "Radeon2 8500 QL " }, + { PCI_DEVICE_ID_R200_BB, "Radeon2 8500 AIW" }, + { PCI_DEVICE_ID_RV200_QW, "Radeon2 7500 QW " } +#endif +}; + +static int detected_chip; + +static int __init radeon_vid_config_card(void) +{ + struct pci_dev *dev = NULL; + size_t i; + + for(i=0;i<sizeof(ati_card_ids)/sizeof(struct ati_card_id_s);i++) + if((dev=pci_find_device(PCI_VENDOR_ID_ATI, ati_card_ids[i].id, NULL))) + break; + if(!dev) + { + printk(RVID_MSG"No supported cards found\n"); + return FALSE; + } + + radeon_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RADEON_REGSIZE); + radeon_mem_base = dev->resource[0].start; + + RTRACE(RVID_MSG"MMIO at 0x%p\n", radeon_mmio_base); + RTRACE(RVID_MSG"Frame Buffer at 0x%08x\n", radeon_mem_base); + + /* video memory size */ + radeon_ram_size = INREG(CONFIG_MEMSIZE); + + /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ + radeon_ram_size &= CONFIG_MEMSIZE_MASK; + radeon_ram_size /= 0x100000; + detected_chip = i; + printk(RVID_MSG"Found %s (%uMb memory)\n",ati_card_ids[i].name,radeon_ram_size); +#ifndef RAGE128 + if(ati_card_ids[i].id == PCI_DEVICE_ID_R200_QL || + ati_card_ids[i].id == PCI_DEVICE_ID_R200_BB || + ati_card_ids[i].id == PCI_DEVICE_ID_RV200_QW) IsR200 = 1; +#endif + return TRUE; +} + +#define PARAM_BRIGHTNESS "brightness=" +#define PARAM_SATURATION "saturation=" +#define PARAM_CONTRAST "contrast=" +#define PARAM_HUE "hue=" +#define PARAM_DOUBLE_BUFF "double_buff=" +#define PARAM_DEINTERLACE "deinterlace=" +#define PARAM_DEINTERLACE_PATTERN "deinterlace_pattern=" +#ifdef RADEON_FPU +static int ovBrightness=0, ovSaturation=0, ovContrast=0, ovHue=0, ov_trans_idx=0; +#endif + +static void radeon_param_buff_fill( void ) +{ + unsigned len,saturation; + int8_t brightness; + brightness = besr.brightness & 0x7f; + /* FIXME: It's probably x86 specific convertion. But it doesn't matter + for general logic - only for printing value */ + if(brightness > 63) brightness = (((~besr.brightness) & 0x3f)+1) * (-1); + saturation = besr.saturation; + len = 0; + len += sprintf(&radeon_param_buff[len],"Interface version: %04X\nDriver version: %s\n",MGA_VID_VERSION,RADEON_VID_VERSION); + len += sprintf(&radeon_param_buff[len],"Chip: %s\n",ati_card_ids[detected_chip].name); + len += sprintf(&radeon_param_buff[len],"Memory: %x:%x\n",radeon_mem_base,radeon_ram_size*0x100000); + len += sprintf(&radeon_param_buff[len],"MMIO: %p\n",radeon_mmio_base); + len += sprintf(&radeon_param_buff[len],"Overlay offset: %x\n",radeon_overlay_off); +#ifdef CONFIG_MTRR + len += sprintf(&radeon_param_buff[len],"Tune MTRR: %s\n",mtrr?"on":"off"); +#endif + if(besr.ckey_on) len += sprintf(&radeon_param_buff[len],"Last used color_key=%X (mask=%X)\n",besr.graphics_key_clr,besr.graphics_key_msk); + len += sprintf(&radeon_param_buff[len],"Swapped fourcc: %s\n",swap_fourcc?"on":"off"); + len += sprintf(&radeon_param_buff[len],"Last BPP: %u\n",besr.dest_bpp); + len += sprintf(&radeon_param_buff[len],"Last fourcc: %s\n\n",fourcc_format_name(besr.fourcc)); + len += sprintf(&radeon_param_buff[len],"Configurable stuff:\n"); + len += sprintf(&radeon_param_buff[len],"~~~~~~~~~~~~~~~~~~~\n"); + len += sprintf(&radeon_param_buff[len],PARAM_DOUBLE_BUFF"%s\n",besr.double_buff?"on":"off"); +#ifdef RAGE128 + len += sprintf(&radeon_param_buff[len],PARAM_BRIGHTNESS"%i\n",(int)brightness); + len += sprintf(&radeon_param_buff[len],PARAM_SATURATION"%u\n",saturation); +#else +#ifdef RADEON_FPU + len += sprintf(&radeon_param_buff[len],PARAM_BRIGHTNESS"%i\n",ovBrightness); + len += sprintf(&radeon_param_buff[len],PARAM_SATURATION"%i\n",ovSaturation); + len += sprintf(&radeon_param_buff[len],PARAM_CONTRAST"%i\n",ovContrast); + len += sprintf(&radeon_param_buff[len],PARAM_HUE"%i\n",ovHue); +#endif +#endif + len += sprintf(&radeon_param_buff[len],PARAM_DEINTERLACE"%s\n",besr.deinterlace_on?"on":"off"); + len += sprintf(&radeon_param_buff[len],PARAM_DEINTERLACE_PATTERN"%X\n",besr.deinterlace_pattern); + radeon_param_buff_len = len; +} + +static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) +{ + uint32_t size; + if(!radeon_param_buff) return -ESPIPE; + if(!(*ppos)) radeon_param_buff_fill(); + if(*ppos >= radeon_param_buff_len) return 0; + size = min(count,radeon_param_buff_len-(uint32_t)(*ppos)); + memcpy(buf,radeon_param_buff,size); + *ppos += size; + return size; +} + +#define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) +#define RTFBrightness(a) (((a)*1.0)/2000.0) +#define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) +#define RTFHue(a) (((a)*3.1416)/1000.0) +#define RadeonSetParm(a,b,c,d) if((b)>=(c)&&(b)<=(d)) { (a)=(b);\ + radeon_set_transform(RTFBrightness(ovBrightness),RTFContrast(ovContrast)\ + ,RTFSaturation(ovSaturation),RTFHue(ovHue),ov_trans_idx); } + + +static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) +{ +#ifdef RAGE128 + if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0) + { + long brightness; + brightness=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10); + if(brightness >= -64 && brightness <= 63) + { + besr.brightness = brightness; + OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) | + (besr.saturation << 8) | + (besr.saturation << 16)); + } + } + else + if(memcmp(buf,PARAM_SATURATION,min(count,strlen(PARAM_SATURATION))) == 0) + { + long saturation; + saturation=simple_strtol(&buf[strlen(PARAM_SATURATION)],NULL,10); + if(saturation >= 0 && saturation <= 31) + OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | + (saturation << 8) | + (saturation << 16)); + } + else +#else +#ifdef RADEON_FPU + if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0) + { + int tmp; + tmp=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10); + RadeonSetParm(ovBrightness,tmp,-1000,1000); + } + else + if(memcmp(buf,PARAM_SATURATION,min(count,strlen(PARAM_SATURATION))) == 0) + { + int tmp; + tmp=simple_strtol(&buf[strlen(PARAM_SATURATION)],NULL,10); + RadeonSetParm(ovSaturation,tmp,-1000,1000); + } + else + if(memcmp(buf,PARAM_CONTRAST,min(count,strlen(PARAM_CONTRAST))) == 0) + { + int tmp; + tmp=simple_strtol(&buf[strlen(PARAM_CONTRAST)],NULL,10); + RadeonSetParm(ovContrast,tmp,-1000,1000); + } + else + if(memcmp(buf,PARAM_HUE,min(count,strlen(PARAM_HUE))) == 0) + { + int tmp; + tmp=simple_strtol(&buf[strlen(PARAM_HUE)],NULL,10); + RadeonSetParm(ovHue,tmp,-1000,1000); + } + else +#endif +#endif + if(memcmp(buf,PARAM_DOUBLE_BUFF,min(count,strlen(PARAM_DOUBLE_BUFF))) == 0) + { + if(memcmp(&buf[strlen(PARAM_DOUBLE_BUFF)],"on",2) == 0) besr.double_buff = 1; + else besr.double_buff = 0; + } + else + if(memcmp(buf,PARAM_DEINTERLACE,min(count,strlen(PARAM_DEINTERLACE))) == 0) + { + if(memcmp(&buf[strlen(PARAM_DEINTERLACE)],"on",2) == 0) besr.deinterlace_on = 1; + else besr.deinterlace_on = 0; + } + else + if(memcmp(buf,PARAM_DEINTERLACE_PATTERN,min(count,strlen(PARAM_DEINTERLACE_PATTERN))) == 0) + { + long dpat; + dpat=simple_strtol(&buf[strlen(PARAM_DEINTERLACE_PATTERN)],NULL,16); + OUTREG(OV0_DEINTERLACE_PATTERN, dpat); + } + else count = -EIO; + radeon_vid_preset(); + return count; +} + +static int radeon_vid_mmap(struct file *file, struct vm_area_struct *vma) +{ + + RTRACE(RVID_MSG"mapping video memory into userspace\n"); + if(remap_page_range(vma->vm_start, radeon_mem_base + radeon_overlay_off, + vma->vm_end - vma->vm_start, vma->vm_page_prot)) + { + printk(RVID_MSG"error mapping video memory\n"); + return(-EAGAIN); + } + + return(0); +} + +static int radeon_vid_release(struct inode *inode, struct file *file) +{ + radeon_vid_in_use = 0; + radeon_vid_stop_video(); + + MOD_DEC_USE_COUNT; + return 0; +} + +static long long radeon_vid_lseek(struct file *file, long long offset, int origin) +{ + return -ESPIPE; +} + +static int radeon_vid_open(struct inode *inode, struct file *file) +{ + int minor = MINOR(inode->i_rdev); + + if(minor != 0) + return(-ENXIO); + + if(radeon_vid_in_use == 1) + return(-EBUSY); + + radeon_vid_in_use = 1; + MOD_INC_USE_COUNT; + return(0); +} + +#if LINUX_VERSION_CODE >= 0x020400 +static struct file_operations radeon_vid_fops = +{ + llseek: radeon_vid_lseek, + read: radeon_vid_read, + write: radeon_vid_write, +/* + readdir: + poll: +*/ + ioctl: radeon_vid_ioctl, + mmap: radeon_vid_mmap, + open: radeon_vid_open, +/* + flush: +*/ + release: radeon_vid_release +/* + fsync: + fasync: + lock: + readv: + writev: + sendpage: + get_unmapped_area: +*/ +}; +#else +static struct file_operations radeon_vid_fops = +{ + radeon_vid_lseek, + radeon_vid_read, + radeon_vid_write, + NULL, + NULL, + radeon_vid_ioctl, + radeon_vid_mmap, + radeon_vid_open, + NULL, + radeon_vid_release +}; +#endif + +/* + * Main Initialization Function + */ + +static int __init radeon_vid_initialize(void) +{ + radeon_vid_in_use = 0; +#ifdef RAGE128 + printk(RVID_MSG"Rage128/Rage128Pro video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); +#else + printk(RVID_MSG"Radeon video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); +#endif + if(register_chrdev(RADEON_VID_MAJOR, "radeon_vid", &radeon_vid_fops)) + { + printk(RVID_MSG"unable to get major: %d\n", RADEON_VID_MAJOR); + return -EIO; + } + + if (!radeon_vid_config_card()) + { + printk(RVID_MSG"can't configure this card\n"); + unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); + return -EINVAL; + } + radeon_param_buff = kmalloc(PARAM_BUFF_SIZE,GFP_KERNEL); + if(radeon_param_buff) radeon_param_buff_size = PARAM_BUFF_SIZE; +#if 0 + radeon_vid_save_state(); +#endif + radeon_vid_make_default(); + radeon_vid_preset(); +#ifdef CONFIG_MTRR + if (mtrr) { + smtrr.vram = mtrr_add(radeon_mem_base, + radeon_ram_size*0x100000, MTRR_TYPE_WRCOMB, 1); + smtrr.vram_valid = 1; + /* let there be speed */ + printk(RVID_MSG"MTRR set to ON\n"); + } +#endif /* CONFIG_MTRR */ + return(0); +} + +int __init init_module(void) +{ + return radeon_vid_initialize(); +} + +void __exit cleanup_module(void) +{ +#if 0 + radeon_vid_restore_state(); +#endif + if(radeon_mmio_base) + iounmap(radeon_mmio_base); + kfree(radeon_param_buff); + RTRACE(RVID_MSG"Cleaning up module\n"); + unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); +#ifdef CONFIG_MTRR + if (smtrr.vram_valid) + mtrr_del(smtrr.vram, radeon_mem_base, + radeon_ram_size*0x100000); +#endif /* CONFIG_MTRR */ +} +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/drivers/radeon_vid.h Sat Mar 17 21:27:42 2007 +0000 @@ -0,0 +1,117 @@ +/* + * + * radeon_vid.h + * + * Copyright (C) 2001 Nick Kurshev + * + * BES YUV Framebuffer driver for Radeon cards + * + * This software has been released under the terms of the GNU Public + * license. See http://www.gnu.org/copyleft/gpl.html for details. + * + * This file is partly based on mga_vid and sis_vid stuff from + * mplayer's package. + */ + +#ifndef __RADEON_VID_INCLUDED +#define __RADEON_VID_INCLUDED + +typedef struct mga_vid_config_s +{ +uint16_t version; +uint16_t card_type; +uint32_t ram_size; +uint32_t src_width; +uint32_t src_height; +uint32_t dest_width; +uint32_t dest_height; +uint32_t x_org; /* dest x */ +uint32_t y_org; /* dest y */ +uint8_t colkey_on; +uint8_t colkey_red; +uint8_t colkey_green; +uint8_t colkey_blue; +uint32_t format; +uint32_t frame_size; +uint32_t num_frames; +} mga_vid_config_t; + +#define IMGFMT_RGB_MASK 0xFFFFFF00 +#define IMGFMT_RGB (('R'<<24)|('G'<<16)|('B'<<8)) +#define IMGFMT_RGB8 (IMGFMT_RGB|8) +#define IMGFMT_RGB15 (IMGFMT_RGB|15) +#define IMGFMT_RGB16 (IMGFMT_RGB|16) +#define IMGFMT_RGB24 (IMGFMT_RGB|24) +#define IMGFMT_RGB32 (IMGFMT_RGB|32) + +#define IMGFMT_BGR_MASK 0xFFFFFF00 +#define IMGFMT_BGR (('B'<<24)|('G'<<16)|('R'<<8)) +#define IMGFMT_BGR8 (IMGFMT_BGR|8) +#define IMGFMT_BGR15 (IMGFMT_BGR|15) +#define IMGFMT_BGR16 (IMGFMT_BGR|16) +#define IMGFMT_BGR24 (IMGFMT_BGR|24) +#define IMGFMT_BGR32 (IMGFMT_BGR|32) + +#define IMGFMT_IS_RGB(fmt) (((fmt)&IMGFMT_RGB_MASK)==IMGFMT_RGB) +#define IMGFMT_IS_BGR(fmt) (((fmt)&IMGFMT_BGR_MASK)==IMGFMT_BGR) + +#define IMGFMT_RGB_DEPTH(fmt) ((fmt)&~IMGFMT_RGB) +#define IMGFMT_BGR_DEPTH(fmt) ((fmt)&~IMGFMT_BGR) + + +/* Planar YUV Formats */ + +#define IMGFMT_YVU9 0x39555659 +#define IMGFMT_IF09 0x39304649 +#define IMGFMT_YV12 0x32315659 +#if 0 +#define IMGFMT_I420 0x30323449 +#define IMGFMT_IYUV 0x56555949 +#else +#define IMGFMT_I420 (('I'<<24)|('4'<<16)|('2'<<8)|'0') +#define IMGFMT_IYUV (('I'<<24)|('Y'<<16)|('U'<<8)|'V') +#endif +#define IMGFMT_CLPL 0x4C504C43 +#define IMGFMT_Y800 0x30303859 +#define IMGFMT_Y8 0x20203859 + +/* Packed YUV Formats */ + +#define IMGFMT_IUYV 0x56595549 +#define IMGFMT_IY41 0x31435949 +#define IMGFMT_IYU1 0x31555949 +#define IMGFMT_IYU2 0x32555949 +#define IMGFMT_UYNV 0x564E5955 +#define IMGFMT_cyuv 0x76757963 +#define IMGFMT_Y422 0x32323459 +#if 0 +#define IMGFMT_YUY2 0x32595559 +#define IMGFMT_UYVY 0x59565955 +#else +#define IMGFMT_YUY2 (('Y'<<24)|('U'<<16)|('Y'<<8)|'2') +#define IMGFMT_UYVY (('U'<<24)|('Y'<<16)|('V'<<8)|'Y') +#endif +#define IMGFMT_YUNV 0x564E5559 +#define IMGFMT_YVYU 0x55595659 +#define IMGFMT_Y41P 0x50313459 +#define IMGFMT_Y211 0x31313259 +#define IMGFMT_Y41T 0x54313459 +#define IMGFMT_Y42T 0x54323459 +#define IMGFMT_V422 0x32323456 +#define IMGFMT_V655 0x35353656 +#define IMGFMT_CLJR 0x524A4C43 +#define IMGFMT_YUVP 0x50565559 +#define IMGFMT_UYVP 0x50565955 + +/* Compressed Formats. MPlayer's extensions!!! */ +#define IMGFMT_MPEGPES (('M'<<24)|('P'<<16)|('E'<<8)|('S')) + + +#define MGA_VID_CONFIG _IOR('J', 1, mga_vid_config_t) +#define MGA_VID_ON _IO ('J', 2) +#define MGA_VID_OFF _IO ('J', 3) +#define MGA_VID_FSEL _IOR('J', 4, int) + +#define MGA_VID_VERSION 0x0201 + +#endif