Mercurial > mplayer.hg
annotate drivers/radeon_vid.c @ 25899:9d4121fa508a
Split osd related stuff from mp_core.h into new header file mp_osd.h.
author | ulion |
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date | Wed, 30 Jan 2008 07:21:05 +0000 |
parents | 4be9faee0360 |
children | a506a6ab14e1 |
rev | line source |
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22691 | 1 /* |
2 * | |
3 * radeon_vid.c | |
4 * | |
5 * Copyright (C) 2001 Nick Kurshev | |
6 * | |
7 * BES YUV video overlay driver for Radeon/Rage128Pro/Rage128 cards | |
8 * | |
9 * This software has been released under the terms of the GNU Public | |
10 * license. See http://www.gnu.org/copyleft/gpl.html for details. | |
11 * | |
12 * This file is partly based on mga_vid and sis_vid stuff from | |
13 * mplayer's package. | |
14 * Also here was used code from CVS of GATOS project and X11 trees. | |
15 * | |
16 * SPECIAL THANKS TO: Hans-Peter Raschke for active testing and hacking | |
17 * Rage128(pro) stuff of this driver. | |
18 */ | |
19 | |
20 #define RADEON_VID_VERSION "1.2.1" | |
21 | |
22 /* | |
23 It's entirely possible this major conflicts with something else | |
24 mknod /dev/radeon_vid c 178 0 | |
25 or | |
26 mknod /dev/rage128_vid c 178 0 | |
27 for Rage128/Rage128Pro chips (although it doesn't matter) | |
28 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | |
29 TESTED and WORKING formats: YUY2, UYVY, IYUV, I420, YV12 | |
30 ----------------------------------------------------------- | |
31 TODO: | |
32 Highest priority: fbvid.h compatibility | |
33 High priority: Fixing BUGS | |
34 Middle priority: RGB/BGR 2-32, YVU9, IF09 support | |
35 Low priority: CLPL, IYU1, IYU2, UYNV, CYUV, YUNV, YVYU, Y41P, Y211, Y41T, | |
36 ^^^^ | |
37 Y42T, V422, V655, CLJR, YUVP, UYVP, Mpeg PES (mpeg-1,2) support | |
38 ........................................................... | |
39 BUGS and LACKS: | |
40 Color and video keys don't work | |
41 */ | |
42 | |
43 #include <linux/config.h> | |
44 #include <linux/version.h> | |
45 #include <linux/module.h> | |
46 #include <linux/types.h> | |
47 #include <linux/kernel.h> | |
48 #include <linux/sched.h> | |
49 #include <linux/mm.h> | |
50 #include <linux/string.h> | |
51 #include <linux/errno.h> | |
52 #include <linux/slab.h> | |
53 #include <linux/pci.h> | |
54 #include <linux/ioport.h> | |
55 #include <linux/init.h> | |
56 #include <linux/byteorder/swab.h> | |
57 | |
58 #include "radeon_vid.h" | |
59 #include "radeon.h" | |
60 | |
61 #ifdef CONFIG_MTRR | |
62 #include <asm/mtrr.h> | |
63 #endif | |
64 | |
65 #include <asm/uaccess.h> | |
66 #include <asm/system.h> | |
67 #include <asm/io.h> | |
68 | |
69 #define TRUE 1 | |
70 #define FALSE 0 | |
71 | |
72 #define RADEON_VID_MAJOR 178 | |
73 | |
74 | |
75 MODULE_AUTHOR("Nick Kurshev <nickols_k@mail.ru>"); | |
76 #ifdef RAGE128 | |
77 MODULE_DESCRIPTION("Accelerated YUV BES driver for Rage128. Version: "RADEON_VID_VERSION); | |
78 #else | |
79 MODULE_DESCRIPTION("Accelerated YUV BES driver for Radeons. Version: "RADEON_VID_VERSION); | |
80 #endif | |
81 #ifdef MODULE_LICENSE | |
82 MODULE_LICENSE("GPL"); | |
83 #endif | |
84 #ifdef CONFIG_MTRR | |
85 MODULE_PARM(mtrr, "i"); | |
86 MODULE_PARM_DESC(mtrr, "Tune MTRR (touch=1(default))"); | |
87 static int mtrr __initdata = 1; | |
88 static struct { int vram; int vram_valid; } smtrr; | |
89 #endif | |
90 MODULE_PARM(swap_fourcc, "i"); | |
91 MODULE_PARM_DESC(swap_fourcc, "Swap fourcc (don't swap=0(default))"); | |
92 static int swap_fourcc __initdata = 0; | |
93 | |
94 #ifdef RAGE128 | |
95 #define RVID_MSG "rage128_vid: " | |
96 #define X_ADJUST 0 | |
97 #else | |
98 #define RVID_MSG "radeon_vid: " | |
99 #define X_ADJUST 8 | |
100 #ifndef RADEON | |
101 #define RADEON | |
102 #endif | |
103 #endif | |
104 | |
105 #undef DEBUG | |
106 #if DEBUG | |
107 #define RTRACE printk | |
108 #else | |
109 #define RTRACE(...) ((void)0) | |
110 #endif | |
111 | |
112 #ifndef min | |
113 #define min(a,b) (a < b ? a : b) | |
114 #endif | |
115 | |
116 #ifndef RAGE128 | |
117 #if defined(__i386__) | |
118 /* Ugly but only way */ | |
119 #undef AVOID_FPU | |
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120 static inline double FastSin(double x) |
22691 | 121 { |
122 register double res; | |
123 __asm __volatile("fsin":"=t"(res):"0"(x)); | |
124 return res; | |
125 } | |
126 #undef sin | |
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127 #define sin(x) FastSin(x) |
22691 | 128 |
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129 static inline double FastCos(double x) |
22691 | 130 { |
131 register double res; | |
132 __asm __volatile("fcos":"=t"(res):"0"(x)); | |
133 return res; | |
134 } | |
135 #undef cos | |
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136 #define cos(x) FastCos(x) |
22691 | 137 #else |
138 #include "generic_math.h" | |
139 #endif /*__386__*/ | |
140 #endif /*RAGE128*/ | |
141 | |
142 #if !defined( RAGE128 ) && !defined( AVOID_FPU ) | |
143 #define RADEON_FPU 1 | |
144 #endif | |
145 | |
146 typedef struct bes_registers_s | |
147 { | |
148 /* base address of yuv framebuffer */ | |
149 uint32_t yuv_base; | |
150 uint32_t fourcc; | |
151 uint32_t dest_bpp; | |
152 /* YUV BES registers */ | |
153 uint32_t reg_load_cntl; | |
154 uint32_t h_inc; | |
155 uint32_t step_by; | |
156 uint32_t y_x_start; | |
157 uint32_t y_x_end; | |
158 uint32_t v_inc; | |
159 uint32_t p1_blank_lines_at_top; | |
160 uint32_t p23_blank_lines_at_top; | |
161 uint32_t vid_buf_pitch0_value; | |
162 uint32_t vid_buf_pitch1_value; | |
163 uint32_t p1_x_start_end; | |
164 uint32_t p2_x_start_end; | |
165 uint32_t p3_x_start_end; | |
166 uint32_t base_addr; | |
167 uint32_t vid_buf0_base_adrs; | |
168 /* These ones are for auto flip: maybe in the future */ | |
169 uint32_t vid_buf1_base_adrs; | |
170 uint32_t vid_buf2_base_adrs; | |
171 uint32_t vid_buf3_base_adrs; | |
172 uint32_t vid_buf4_base_adrs; | |
173 uint32_t vid_buf5_base_adrs; | |
174 | |
175 uint32_t p1_v_accum_init; | |
176 uint32_t p1_h_accum_init; | |
177 uint32_t p23_v_accum_init; | |
178 uint32_t p23_h_accum_init; | |
179 uint32_t scale_cntl; | |
180 uint32_t exclusive_horz; | |
181 uint32_t auto_flip_cntl; | |
182 uint32_t filter_cntl; | |
183 uint32_t key_cntl; | |
184 uint32_t test; | |
185 /* Configurable stuff */ | |
186 int double_buff; | |
187 | |
188 int brightness; | |
189 int saturation; | |
190 | |
191 int ckey_on; | |
192 uint32_t graphics_key_clr; | |
193 uint32_t graphics_key_msk; | |
194 | |
195 int deinterlace_on; | |
196 uint32_t deinterlace_pattern; | |
197 | |
198 } bes_registers_t; | |
199 | |
200 typedef struct video_registers_s | |
201 { | |
202 #ifdef DEBUG | |
203 const char * sname; | |
204 #endif | |
205 uint32_t name; | |
206 uint32_t value; | |
207 }video_registers_t; | |
208 | |
209 static bes_registers_t besr; | |
210 #ifndef RAGE128 | |
211 static int IsR200=0; | |
212 #endif | |
213 #ifdef DEBUG | |
214 #define DECLARE_VREG(name) { #name, name, 0 } | |
215 #else | |
216 #define DECLARE_VREG(name) { name, 0 } | |
217 #endif | |
218 #ifdef DEBUG | |
219 static video_registers_t vregs[] = | |
220 { | |
221 DECLARE_VREG(VIDEOMUX_CNTL), | |
222 DECLARE_VREG(VIPPAD_MASK), | |
223 DECLARE_VREG(VIPPAD1_A), | |
224 DECLARE_VREG(VIPPAD1_EN), | |
225 DECLARE_VREG(VIPPAD1_Y), | |
226 DECLARE_VREG(OV0_Y_X_START), | |
227 DECLARE_VREG(OV0_Y_X_END), | |
228 DECLARE_VREG(OV0_PIPELINE_CNTL), | |
229 DECLARE_VREG(OV0_EXCLUSIVE_HORZ), | |
230 DECLARE_VREG(OV0_EXCLUSIVE_VERT), | |
231 DECLARE_VREG(OV0_REG_LOAD_CNTL), | |
232 DECLARE_VREG(OV0_SCALE_CNTL), | |
233 DECLARE_VREG(OV0_V_INC), | |
234 DECLARE_VREG(OV0_P1_V_ACCUM_INIT), | |
235 DECLARE_VREG(OV0_P23_V_ACCUM_INIT), | |
236 DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), | |
237 DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), | |
238 #ifdef RADEON | |
239 DECLARE_VREG(OV0_BASE_ADDR), | |
240 #endif | |
241 DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), | |
242 DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), | |
243 DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), | |
244 DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), | |
245 DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), | |
246 DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), | |
247 DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), | |
248 DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), | |
249 DECLARE_VREG(OV0_AUTO_FLIP_CNTL), | |
250 DECLARE_VREG(OV0_DEINTERLACE_PATTERN), | |
251 DECLARE_VREG(OV0_SUBMIT_HISTORY), | |
252 DECLARE_VREG(OV0_H_INC), | |
253 DECLARE_VREG(OV0_STEP_BY), | |
254 DECLARE_VREG(OV0_P1_H_ACCUM_INIT), | |
255 DECLARE_VREG(OV0_P23_H_ACCUM_INIT), | |
256 DECLARE_VREG(OV0_P1_X_START_END), | |
257 DECLARE_VREG(OV0_P2_X_START_END), | |
258 DECLARE_VREG(OV0_P3_X_START_END), | |
259 DECLARE_VREG(OV0_FILTER_CNTL), | |
260 DECLARE_VREG(OV0_FOUR_TAP_COEF_0), | |
261 DECLARE_VREG(OV0_FOUR_TAP_COEF_1), | |
262 DECLARE_VREG(OV0_FOUR_TAP_COEF_2), | |
263 DECLARE_VREG(OV0_FOUR_TAP_COEF_3), | |
264 DECLARE_VREG(OV0_FOUR_TAP_COEF_4), | |
265 DECLARE_VREG(OV0_FLAG_CNTL), | |
266 #ifdef RAGE128 | |
267 DECLARE_VREG(OV0_COLOUR_CNTL), | |
268 #else | |
269 DECLARE_VREG(OV0_SLICE_CNTL), | |
270 #endif | |
271 DECLARE_VREG(OV0_VID_KEY_CLR), | |
272 DECLARE_VREG(OV0_VID_KEY_MSK), | |
273 DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), | |
274 DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), | |
275 DECLARE_VREG(OV0_KEY_CNTL), | |
276 DECLARE_VREG(OV0_TEST), | |
277 DECLARE_VREG(OV0_LIN_TRANS_A), | |
278 DECLARE_VREG(OV0_LIN_TRANS_B), | |
279 DECLARE_VREG(OV0_LIN_TRANS_C), | |
280 DECLARE_VREG(OV0_LIN_TRANS_D), | |
281 DECLARE_VREG(OV0_LIN_TRANS_E), | |
282 DECLARE_VREG(OV0_LIN_TRANS_F), | |
283 DECLARE_VREG(OV0_GAMMA_0_F), | |
284 DECLARE_VREG(OV0_GAMMA_10_1F), | |
285 DECLARE_VREG(OV0_GAMMA_20_3F), | |
286 DECLARE_VREG(OV0_GAMMA_40_7F), | |
287 DECLARE_VREG(OV0_GAMMA_380_3BF), | |
288 DECLARE_VREG(OV0_GAMMA_3C0_3FF), | |
289 DECLARE_VREG(SUBPIC_CNTL), | |
290 DECLARE_VREG(SUBPIC_DEFCOLCON), | |
291 DECLARE_VREG(SUBPIC_Y_X_START), | |
292 DECLARE_VREG(SUBPIC_Y_X_END), | |
293 DECLARE_VREG(SUBPIC_V_INC), | |
294 DECLARE_VREG(SUBPIC_H_INC), | |
295 DECLARE_VREG(SUBPIC_BUF0_OFFSET), | |
296 DECLARE_VREG(SUBPIC_BUF1_OFFSET), | |
297 DECLARE_VREG(SUBPIC_LC0_OFFSET), | |
298 DECLARE_VREG(SUBPIC_LC1_OFFSET), | |
299 DECLARE_VREG(SUBPIC_PITCH), | |
300 DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), | |
301 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), | |
302 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), | |
303 DECLARE_VREG(SUBPIC_PALETTE_INDEX), | |
304 DECLARE_VREG(SUBPIC_PALETTE_DATA), | |
305 DECLARE_VREG(SUBPIC_H_ACCUM_INIT), | |
306 DECLARE_VREG(SUBPIC_V_ACCUM_INIT), | |
307 DECLARE_VREG(IDCT_RUNS), | |
308 DECLARE_VREG(IDCT_LEVELS), | |
309 DECLARE_VREG(IDCT_AUTH_CONTROL), | |
310 DECLARE_VREG(IDCT_AUTH), | |
311 DECLARE_VREG(IDCT_CONTROL) | |
312 }; | |
313 #endif | |
314 static uint32_t radeon_vid_in_use = 0; | |
315 | |
316 static uint8_t *radeon_mmio_base = 0; | |
317 static uint32_t radeon_mem_base = 0; | |
318 static int32_t radeon_overlay_off = 0; | |
319 static uint32_t radeon_ram_size = 0; | |
320 #define PARAM_BUFF_SIZE 4096 | |
321 static uint8_t *radeon_param_buff = NULL; | |
322 static uint32_t radeon_param_buff_size=0; | |
323 static uint32_t radeon_param_buff_len=0; /* real length of buffer */ | |
324 static mga_vid_config_t radeon_config; | |
325 | |
326 static char *fourcc_format_name(int format) | |
327 { | |
328 switch(format) | |
329 { | |
330 case IMGFMT_RGB8: return("RGB 8-bit"); | |
331 case IMGFMT_RGB15: return("RGB 15-bit"); | |
332 case IMGFMT_RGB16: return("RGB 16-bit"); | |
333 case IMGFMT_RGB24: return("RGB 24-bit"); | |
334 case IMGFMT_RGB32: return("RGB 32-bit"); | |
335 case IMGFMT_BGR8: return("BGR 8-bit"); | |
336 case IMGFMT_BGR15: return("BGR 15-bit"); | |
337 case IMGFMT_BGR16: return("BGR 16-bit"); | |
338 case IMGFMT_BGR24: return("BGR 24-bit"); | |
339 case IMGFMT_BGR32: return("BGR 32-bit"); | |
340 case IMGFMT_YVU9: return("Planar YVU9"); | |
341 case IMGFMT_IF09: return("Planar IF09"); | |
342 case IMGFMT_YV12: return("Planar YV12"); | |
343 case IMGFMT_I420: return("Planar I420"); | |
344 case IMGFMT_IYUV: return("Planar IYUV"); | |
345 case IMGFMT_CLPL: return("Planar CLPL"); | |
346 case IMGFMT_Y800: return("Planar Y800"); | |
347 case IMGFMT_Y8: return("Planar Y8"); | |
348 case IMGFMT_IUYV: return("Packed IUYV"); | |
349 case IMGFMT_IY41: return("Packed IY41"); | |
350 case IMGFMT_IYU1: return("Packed IYU1"); | |
351 case IMGFMT_IYU2: return("Packed IYU2"); | |
352 case IMGFMT_UYNV: return("Packed UYNV"); | |
353 case IMGFMT_cyuv: return("Packed CYUV"); | |
354 case IMGFMT_Y422: return("Packed Y422"); | |
355 case IMGFMT_YUY2: return("Packed YUY2"); | |
356 case IMGFMT_YUNV: return("Packed YUNV"); | |
357 case IMGFMT_UYVY: return("Packed UYVY"); | |
358 // case IMGFMT_YVYU: return("Packed YVYU"); | |
359 case IMGFMT_Y41P: return("Packed Y41P"); | |
360 case IMGFMT_Y211: return("Packed Y211"); | |
361 case IMGFMT_Y41T: return("Packed Y41T"); | |
362 case IMGFMT_Y42T: return("Packed Y42T"); | |
363 case IMGFMT_V422: return("Packed V422"); | |
364 case IMGFMT_V655: return("Packed V655"); | |
365 case IMGFMT_CLJR: return("Packed CLJR"); | |
366 case IMGFMT_YUVP: return("Packed YUVP"); | |
367 case IMGFMT_UYVP: return("Packed UYVP"); | |
368 case IMGFMT_MPEGPES: return("Mpeg PES"); | |
369 } | |
370 return("Unknown"); | |
371 } | |
372 | |
373 | |
374 /* | |
375 * IO macros | |
376 */ | |
377 | |
378 #define INREG8(addr) readb((radeon_mmio_base)+addr) | |
379 #define OUTREG8(addr,val) writeb(val, (radeon_mmio_base)+addr) | |
380 #define INREG(addr) readl((radeon_mmio_base)+addr) | |
381 #define OUTREG(addr,val) writel(val, (radeon_mmio_base)+addr) | |
382 #define OUTREGP(addr,val,mask) \ | |
383 do { \ | |
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384 unsigned int tmp = INREG(addr); \ |
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385 tmp &= (mask); \ |
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386 tmp |= (val); \ |
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387 OUTREG(addr, tmp); \ |
22691 | 388 } while (0) |
389 | |
390 static uint32_t radeon_vid_get_dbpp( void ) | |
391 { | |
392 uint32_t dbpp,retval; | |
393 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; | |
394 switch(dbpp) | |
395 { | |
396 case DST_8BPP: retval = 8; break; | |
397 case DST_15BPP: retval = 15; break; | |
398 case DST_16BPP: retval = 16; break; | |
399 case DST_24BPP: retval = 24; break; | |
400 default: retval=32; break; | |
401 } | |
402 return retval; | |
403 } | |
404 | |
405 static int radeon_is_dbl_scan( void ) | |
406 { | |
407 return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; | |
408 } | |
409 | |
410 static int radeon_is_interlace( void ) | |
411 { | |
412 return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; | |
413 } | |
414 | |
415 static __inline__ void radeon_engine_flush ( void ) | |
416 { | |
417 int i; | |
418 | |
419 /* initiate flush */ | |
420 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, | |
421 ~RB2D_DC_FLUSH_ALL); | |
422 | |
423 for (i=0; i < 2000000; i++) { | |
424 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) | |
425 break; | |
426 } | |
427 } | |
428 | |
429 | |
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430 static __inline__ void radeon_fifo_wait (int entries) |
22691 | 431 { |
432 int i; | |
433 | |
434 for (i=0; i<2000000; i++) | |
435 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) | |
436 return; | |
437 } | |
438 | |
439 | |
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440 static __inline__ void radeon_engine_idle ( void ) |
22691 | 441 { |
442 int i; | |
443 | |
444 /* ensure FIFO is empty before waiting for idle */ | |
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445 radeon_fifo_wait (64); |
22691 | 446 |
447 for (i=0; i<2000000; i++) { | |
448 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { | |
449 radeon_engine_flush (); | |
450 return; | |
451 } | |
452 } | |
453 } | |
454 | |
455 #if 0 | |
456 static void __init radeon_vid_save_state( void ) | |
457 { | |
458 size_t i; | |
459 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
460 vregs[i].value = INREG(vregs[i].name); | |
461 } | |
462 | |
463 static void __exit radeon_vid_restore_state( void ) | |
464 { | |
465 size_t i; | |
466 radeon_fifo_wait(2); | |
467 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
468 radeon_engine_idle(); | |
469 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
470 radeon_fifo_wait(15); | |
471 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
472 { | |
473 radeon_fifo_wait(1); | |
474 OUTREG(vregs[i].name,vregs[i].value); | |
475 } | |
476 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
477 } | |
478 #endif | |
479 #ifdef DEBUG | |
480 static void radeon_vid_dump_regs( void ) | |
481 { | |
482 size_t i; | |
483 printk(RVID_MSG"*** Begin of OV0 registers dump ***\n"); | |
484 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
485 printk(RVID_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); | |
486 printk(RVID_MSG"*** End of OV0 registers dump ***\n"); | |
487 } | |
488 #endif | |
489 | |
490 #ifdef RADEON_FPU | |
491 /* Reference color space transform data */ | |
492 typedef struct tagREF_TRANSFORM | |
493 { | |
494 float RefLuma; | |
495 float RefRCb; | |
496 float RefRCr; | |
497 float RefGCb; | |
498 float RefGCr; | |
499 float RefBCb; | |
500 float RefBCr; | |
501 } REF_TRANSFORM; | |
502 | |
503 /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ | |
504 REF_TRANSFORM trans[2] = | |
505 { | |
506 {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ | |
507 {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ | |
508 }; | |
509 /**************************************************************************** | |
510 * SetTransform * | |
511 * Function: Calculates and sets color space transform from supplied * | |
512 * reference transform, gamma, brightness, contrast, hue and * | |
513 * saturation. * | |
514 * Inputs: bright - brightness * | |
515 * cont - contrast * | |
516 * sat - saturation * | |
517 * hue - hue * | |
518 * ref - index to the table of refernce transforms * | |
519 * Outputs: NONE * | |
520 ****************************************************************************/ | |
521 | |
522 static void radeon_set_transform(float bright, float cont, float sat, | |
523 float hue, unsigned ref) | |
524 { | |
525 float OvHueSin, OvHueCos; | |
526 float CAdjLuma, CAdjOff; | |
527 float CAdjRCb, CAdjRCr; | |
528 float CAdjGCb, CAdjGCr; | |
529 float CAdjBCb, CAdjBCr; | |
530 float OvLuma, OvROff, OvGOff, OvBOff; | |
531 float OvRCb, OvRCr; | |
532 float OvGCb, OvGCr; | |
533 float OvBCb, OvBCr; | |
534 float Loff = 64.0; | |
535 float Coff = 512.0f; | |
536 | |
537 u32 dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; | |
538 u32 dwOvRCb, dwOvRCr; | |
539 u32 dwOvGCb, dwOvGCr; | |
540 u32 dwOvBCb, dwOvBCr; | |
541 | |
542 if (ref >= 2) return; | |
543 | |
544 OvHueSin = sin((double)hue); | |
545 OvHueCos = cos((double)hue); | |
546 | |
547 CAdjLuma = cont * trans[ref].RefLuma; | |
548 CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; | |
549 | |
550 CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; | |
551 CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; | |
552 CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); | |
553 CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); | |
554 CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; | |
555 CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; | |
556 | |
557 #if 0 /* default constants */ | |
558 CAdjLuma = 1.16455078125; | |
559 | |
560 CAdjRCb = 0.0; | |
561 CAdjRCr = 1.59619140625; | |
562 CAdjGCb = -0.39111328125; | |
563 CAdjGCr = -0.8125; | |
564 CAdjBCb = 2.01708984375; | |
565 CAdjBCr = 0; | |
566 #endif | |
567 OvLuma = CAdjLuma; | |
568 OvRCb = CAdjRCb; | |
569 OvRCr = CAdjRCr; | |
570 OvGCb = CAdjGCb; | |
571 OvGCr = CAdjGCr; | |
572 OvBCb = CAdjBCb; | |
573 OvBCr = CAdjBCr; | |
574 OvROff = CAdjOff - | |
575 OvLuma * Loff - (OvRCb + OvRCr) * Coff; | |
576 OvGOff = CAdjOff - | |
577 OvLuma * Loff - (OvGCb + OvGCr) * Coff; | |
578 OvBOff = CAdjOff - | |
579 OvLuma * Loff - (OvBCb + OvBCr) * Coff; | |
580 #if 0 /* default constants */ | |
581 OvROff = -888.5; | |
582 OvGOff = 545; | |
583 OvBOff = -1104; | |
584 #endif | |
585 | |
586 dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; | |
587 dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; | |
588 dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; | |
589 if(!IsR200) | |
590 { | |
591 dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; | |
592 dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; | |
593 dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; | |
594 dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; | |
595 dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; | |
596 dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; | |
597 dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; | |
598 } | |
599 else | |
600 { | |
601 dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; | |
602 dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; | |
603 dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; | |
604 dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; | |
605 dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; | |
606 dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; | |
607 dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; | |
608 } | |
609 | |
610 OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); | |
611 OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); | |
612 OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); | |
613 OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); | |
614 OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); | |
615 OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); | |
616 } | |
617 #endif | |
618 | |
619 #ifndef RAGE128 | |
620 /* Gamma curve definition */ | |
621 typedef struct | |
622 { | |
623 unsigned int gammaReg; | |
624 unsigned int gammaSlope; | |
625 unsigned int gammaOffset; | |
626 }GAMMA_SETTINGS; | |
627 | |
628 /* Recommended gamma curve parameters */ | |
629 GAMMA_SETTINGS r200_def_gamma[18] = | |
630 { | |
631 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
632 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
633 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
634 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
635 {OV0_GAMMA_80_BF, 0x100, 0x0100}, | |
636 {OV0_GAMMA_C0_FF, 0x100, 0x0100}, | |
637 {OV0_GAMMA_100_13F, 0x100, 0x0200}, | |
638 {OV0_GAMMA_140_17F, 0x100, 0x0200}, | |
639 {OV0_GAMMA_180_1BF, 0x100, 0x0300}, | |
640 {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, | |
641 {OV0_GAMMA_200_23F, 0x100, 0x0400}, | |
642 {OV0_GAMMA_240_27F, 0x100, 0x0400}, | |
643 {OV0_GAMMA_280_2BF, 0x100, 0x0500}, | |
644 {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, | |
645 {OV0_GAMMA_300_33F, 0x100, 0x0600}, | |
646 {OV0_GAMMA_340_37F, 0x100, 0x0600}, | |
647 {OV0_GAMMA_380_3BF, 0x100, 0x0700}, | |
648 {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} | |
649 }; | |
650 | |
651 GAMMA_SETTINGS r100_def_gamma[6] = | |
652 { | |
653 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
654 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
655 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
656 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
657 {OV0_GAMMA_380_3BF, 0x100, 0x0100}, | |
658 {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} | |
659 }; | |
660 | |
661 static void make_default_gamma_correction( void ) | |
662 { | |
663 size_t i; | |
664 if(!IsR200){ | |
665 OUTREG(OV0_LIN_TRANS_A, 0x12A00000); | |
666 OUTREG(OV0_LIN_TRANS_B, 0x199018FE); | |
667 OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); | |
668 OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); | |
669 OUTREG(OV0_LIN_TRANS_E, 0x12A02050); | |
670 OUTREG(OV0_LIN_TRANS_F, 0x0000174E); | |
671 for(i=0; i<6; i++){ | |
672 OUTREG(r100_def_gamma[i].gammaReg, | |
673 (r100_def_gamma[i].gammaSlope<<16) | | |
674 r100_def_gamma[i].gammaOffset); | |
675 } | |
676 } | |
677 else{ | |
678 OUTREG(OV0_LIN_TRANS_A, 0x12a00000); | |
679 OUTREG(OV0_LIN_TRANS_B, 0x1990190e); | |
680 OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); | |
681 OUTREG(OV0_LIN_TRANS_D, 0xf3000442); | |
682 OUTREG(OV0_LIN_TRANS_E, 0x12a02040); | |
683 OUTREG(OV0_LIN_TRANS_F, 0x175f); | |
684 | |
685 /* Default Gamma, | |
686 Of 18 segments for gamma cure, all segments in R200 are programmable, | |
687 while only lower 4 and upper 2 segments are programmable in Radeon*/ | |
688 for(i=0; i<18; i++){ | |
689 OUTREG(r200_def_gamma[i].gammaReg, | |
690 (r200_def_gamma[i].gammaSlope<<16) | | |
691 r200_def_gamma[i].gammaOffset); | |
692 } | |
693 } | |
694 } | |
695 #endif | |
696 | |
697 static void radeon_vid_stop_video( void ) | |
698 { | |
699 radeon_engine_idle(); | |
700 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
701 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
702 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
703 OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); | |
704 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); | |
705 OUTREG(OV0_TEST, 0); | |
706 } | |
707 | |
708 static void radeon_vid_display_video( void ) | |
709 { | |
710 int bes_flags; | |
711 radeon_fifo_wait(2); | |
712 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
713 radeon_engine_idle(); | |
714 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
715 radeon_fifo_wait(15); | |
716 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); | |
717 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
718 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
719 | |
720 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
721 #ifdef RAGE128 | |
722 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | | |
723 (besr.saturation << 8) | | |
724 (besr.saturation << 16)); | |
725 #endif | |
726 radeon_fifo_wait(2); | |
727 if(besr.ckey_on) | |
728 { | |
729 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); | |
730 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
731 OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_EQ|VIDEO_KEY_FN_FALSE|CMP_MIX_OR); | |
732 } | |
733 else | |
734 { | |
735 OUTREG(OV0_GRAPHICS_KEY_MSK, 0ULL); | |
736 OUTREG(OV0_GRAPHICS_KEY_CLR, 0ULL); | |
737 OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_NE); | |
738 } | |
739 | |
740 OUTREG(OV0_H_INC, besr.h_inc); | |
741 OUTREG(OV0_STEP_BY, besr.step_by); | |
742 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
743 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
744 OUTREG(OV0_V_INC, besr.v_inc); | |
745 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
746 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); | |
747 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); | |
748 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); | |
749 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); | |
750 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
751 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
752 #ifdef RADEON | |
753 OUTREG(OV0_BASE_ADDR, besr.base_addr); | |
754 #endif | |
755 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs); | |
756 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs); | |
757 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs); | |
758 radeon_fifo_wait(9); | |
759 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs); | |
760 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs); | |
761 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf5_base_adrs); | |
762 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); | |
763 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
764 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
765 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); | |
766 | |
767 #ifdef RADEON | |
768 bes_flags = SCALER_ENABLE | | |
769 SCALER_SMART_SWITCH; | |
770 // SCALER_HORZ_PICK_NEAREST; | |
771 #else | |
772 bes_flags = SCALER_ENABLE | | |
773 SCALER_SMART_SWITCH | | |
774 SCALER_Y2R_TEMP | | |
775 SCALER_PIX_EXPAND; | |
776 #endif | |
777 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; | |
778 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
779 #ifdef RAGE128 | |
780 bes_flags |= SCALER_BURST_PER_PLANE; | |
781 #endif | |
782 switch(besr.fourcc) | |
783 { | |
784 case IMGFMT_RGB15: | |
785 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
786 case IMGFMT_RGB16: | |
787 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; | |
788 case IMGFMT_RGB24: | |
789 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
790 case IMGFMT_RGB32: | |
791 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
792 /* 4:1:0*/ | |
793 case IMGFMT_IF09: | |
794 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; | |
795 /* 4:2:0 */ | |
796 case IMGFMT_IYUV: | |
797 case IMGFMT_I420: | |
798 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; | |
799 break; | |
800 /* 4:2:2 */ | |
801 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; | |
802 case IMGFMT_YUY2: | |
803 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
804 } | |
805 OUTREG(OV0_SCALE_CNTL, bes_flags); | |
806 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
807 #ifdef DEBUG | |
808 radeon_vid_dump_regs(); | |
809 #endif | |
810 } | |
811 | |
812 void radeon_vid_set_color_key(int ckey_on, uint8_t R, uint8_t G, uint8_t B) | |
813 { | |
814 besr.ckey_on = ckey_on; | |
815 besr.graphics_key_msk=(1ULL<<radeon_vid_get_dbpp()) - 1; | |
816 besr.graphics_key_clr=(R<<16)|(G<<8)|(B)|(0x00 << 24); | |
817 } | |
818 | |
819 | |
820 #define XXX_SRC_X 0 | |
821 #define XXX_SRC_Y 0 | |
822 | |
823 static int radeon_vid_init_video( mga_vid_config_t *config ) | |
824 { | |
825 uint32_t tmp,src_w,src_h,pitch,h_inc,step_by,left,leftUV,top; | |
826 int is_420; | |
827 RTRACE(RVID_MSG"usr_config: version = %x format=%x card=%x ram=%u src(%ux%u) dest(%u:%ux%u:%u) frame_size=%u num_frames=%u\n" | |
828 ,(uint32_t)config->version | |
829 ,(uint32_t)config->format | |
830 ,(uint32_t)config->card_type | |
831 ,(uint32_t)config->ram_size | |
832 ,(uint32_t)config->src_width | |
833 ,(uint32_t)config->src_height | |
834 ,(uint32_t)config->x_org | |
835 ,(uint32_t)config->y_org | |
836 ,(uint32_t)config->dest_width | |
837 ,(uint32_t)config->dest_height | |
838 ,(uint32_t)config->frame_size | |
839 ,(uint32_t)config->num_frames); | |
840 radeon_vid_stop_video(); | |
841 left = XXX_SRC_X << 16; | |
842 top = XXX_SRC_Y << 16; | |
843 src_h = config->src_height; | |
844 src_w = config->src_width; | |
845 switch(config->format) | |
846 { | |
847 case IMGFMT_RGB15: | |
848 case IMGFMT_BGR15: | |
849 case IMGFMT_RGB16: | |
850 case IMGFMT_BGR16: | |
851 case IMGFMT_RGB24: | |
852 case IMGFMT_BGR24: | |
853 case IMGFMT_RGB32: | |
854 case IMGFMT_BGR32: | |
855 /* 4:1:0 */ | |
856 case IMGFMT_IF09: | |
857 case IMGFMT_YVU9: | |
858 /* 4:2:0 */ | |
859 case IMGFMT_IYUV: | |
860 case IMGFMT_YV12: | |
861 case IMGFMT_I420: | |
862 /* 4:2:2 */ | |
863 case IMGFMT_UYVY: | |
864 case IMGFMT_YUY2: | |
865 break; | |
866 default: | |
867 printk(RVID_MSG"Unsupported pixel format: 0x%X\n",config->format); | |
868 return -1; | |
869 } | |
870 is_420 = 0; | |
871 if(config->format == IMGFMT_YV12 || | |
872 config->format == IMGFMT_I420 || | |
873 config->format == IMGFMT_IYUV) is_420 = 1; | |
874 switch(config->format) | |
875 { | |
876 /* 4:1:0 */ | |
877 case IMGFMT_YVU9: | |
878 case IMGFMT_IF09: | |
879 /* 4:2:0 */ | |
880 case IMGFMT_IYUV: | |
881 case IMGFMT_YV12: | |
882 case IMGFMT_I420: pitch = (src_w + 31) & ~31; break; | |
883 /* 4:2:2 */ | |
884 default: | |
885 case IMGFMT_UYVY: | |
886 case IMGFMT_YUY2: | |
887 case IMGFMT_RGB15: | |
888 case IMGFMT_BGR15: | |
889 case IMGFMT_RGB16: | |
890 case IMGFMT_BGR16: pitch = ((src_w*2) + 15) & ~15; break; | |
891 case IMGFMT_RGB24: | |
892 case IMGFMT_BGR24: pitch = ((src_w*3) + 15) & ~15; break; | |
893 case IMGFMT_RGB32: | |
894 case IMGFMT_BGR32: pitch = ((src_w*4) + 15) & ~15; break; | |
895 } | |
896 if(radeon_is_dbl_scan()) config->dest_height *= 2; | |
897 else | |
898 if(radeon_is_interlace()) config->dest_height /= 2; | |
899 besr.dest_bpp = radeon_vid_get_dbpp(); | |
900 besr.fourcc = config->format; | |
901 besr.v_inc = (src_h << 20) / config->dest_height; | |
902 h_inc = (src_w << 12) / config->dest_width; | |
903 step_by = 1; | |
904 | |
905 while(h_inc >= (2 << 12)) { | |
906 step_by++; | |
907 h_inc >>= 1; | |
908 } | |
909 | |
910 /* keep everything in 16.16 */ | |
911 besr.base_addr = radeon_mem_base; | |
912 if(is_420) | |
913 { | |
914 uint32_t d1line,d2line,d3line; | |
915 d1line = top*pitch; | |
916 d2line = src_h*pitch+(d1line>>1); | |
917 d3line = d2line+((src_h*pitch)>>2); | |
918 d1line += (left >> 16) & ~15; | |
919 d2line += (left >> 17) & ~15; | |
920 d3line += (left >> 17) & ~15; | |
921 besr.vid_buf0_base_adrs=((radeon_overlay_off+d1line)&VIF_BUF0_BASE_ADRS_MASK); | |
922 besr.vid_buf1_base_adrs=((radeon_overlay_off+d2line)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
923 besr.vid_buf2_base_adrs=((radeon_overlay_off+d3line)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
924 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) | |
925 { | |
926 uint32_t tmp; | |
927 tmp = besr.vid_buf1_base_adrs; | |
928 besr.vid_buf1_base_adrs = besr.vid_buf2_base_adrs; | |
929 besr.vid_buf2_base_adrs = tmp; | |
930 } | |
931 } | |
932 else | |
933 { | |
934 besr.vid_buf0_base_adrs = radeon_overlay_off; | |
935 besr.vid_buf0_base_adrs += ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; | |
936 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs; | |
937 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs; | |
938 } | |
939 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; | |
940 besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs+config->frame_size; | |
941 besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs+config->frame_size; | |
942 | |
943 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); | |
944 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
945 ((tmp << 12) & 0xf0000000); | |
946 | |
947 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); | |
948 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
949 ((tmp << 12) & 0x70000000); | |
950 tmp = (top & 0x0000ffff) + 0x00018000; | |
951 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) | |
952 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
953 | |
954 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
955 besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) | |
956 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; | |
957 | |
958 leftUV = (left >> 17) & 15; | |
959 left = (left >> 16) & 15; | |
960 besr.h_inc = h_inc | ((h_inc >> 1) << 16); | |
961 besr.step_by = step_by | (step_by << 8); | |
962 besr.y_x_start = (config->x_org+X_ADJUST) | (config->y_org << 16); | |
963 besr.y_x_end = (config->x_org + config->dest_width+X_ADJUST) | ((config->y_org + config->dest_height) << 16); | |
964 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
965 if(is_420) | |
966 { | |
967 src_h = (src_h + 1) >> 1; | |
968 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
969 } | |
970 else besr.p23_blank_lines_at_top = 0; | |
971 besr.vid_buf_pitch0_value = pitch; | |
972 besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch; | |
973 besr.p1_x_start_end = (src_w+left-1)|(left<<16); | |
974 src_w>>=1; | |
975 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
976 besr.p3_x_start_end = besr.p2_x_start_end; | |
977 return 0; | |
978 } | |
979 | |
980 static void radeon_vid_frame_sel(int frame) | |
981 { | |
982 uint32_t off0,off1,off2; | |
983 if(!besr.double_buff) return; | |
984 if(frame%2) | |
985 { | |
986 off0 = besr.vid_buf3_base_adrs; | |
987 off1 = besr.vid_buf4_base_adrs; | |
988 off2 = besr.vid_buf5_base_adrs; | |
989 } | |
990 else | |
991 { | |
992 off0 = besr.vid_buf0_base_adrs; | |
993 off1 = besr.vid_buf1_base_adrs; | |
994 off2 = besr.vid_buf2_base_adrs; | |
995 } | |
996 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
997 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
998 OUTREG(OV0_VID_BUF0_BASE_ADRS, off0); | |
999 OUTREG(OV0_VID_BUF1_BASE_ADRS, off1); | |
1000 OUTREG(OV0_VID_BUF2_BASE_ADRS, off2); | |
1001 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
1002 } | |
1003 | |
1004 static void radeon_vid_make_default(void) | |
1005 { | |
1006 #ifdef RAGE128 | |
1007 OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brihgtness and saturation for Rage128 */ | |
1008 #else | |
1009 make_default_gamma_correction(); | |
1010 #endif | |
1011 besr.deinterlace_pattern = 0x900AAAAA; | |
1012 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
1013 besr.deinterlace_on=1; | |
1014 besr.double_buff=1; | |
1015 } | |
1016 | |
1017 | |
1018 static void radeon_vid_preset(void) | |
1019 { | |
1020 #ifdef RAGE128 | |
1021 unsigned tmp; | |
1022 tmp = INREG(OV0_COLOUR_CNTL); | |
1023 besr.saturation = (tmp>>8)&0x1f; | |
1024 besr.brightness = tmp & 0x7f; | |
1025 #endif | |
1026 besr.graphics_key_clr = INREG(OV0_GRAPHICS_KEY_CLR); | |
1027 besr.deinterlace_pattern = INREG(OV0_DEINTERLACE_PATTERN); | |
1028 } | |
1029 | |
1030 static int video_on = 0; | |
1031 | |
1032 static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) | |
1033 { | |
1034 int frame; | |
1035 | |
1036 switch(cmd) | |
1037 { | |
1038 case MGA_VID_CONFIG: | |
1039 RTRACE(RVID_MSG"radeon_mmio_base = %p\n",radeon_mmio_base); | |
1040 RTRACE(RVID_MSG"radeon_mem_base = %08x\n",radeon_mem_base); | |
1041 RTRACE(RVID_MSG"Received configuration\n"); | |
1042 | |
1043 if(copy_from_user(&radeon_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t))) | |
1044 { | |
1045 printk(RVID_MSG"failed copy from userspace\n"); | |
1046 return -EFAULT; | |
1047 } | |
1048 if(radeon_config.version != MGA_VID_VERSION){ | |
1049 printk(RVID_MSG"incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,radeon_config.version); | |
1050 return -EFAULT; | |
1051 } | |
1052 | |
1053 if(radeon_config.frame_size==0 || radeon_config.frame_size>1024*768*2){ | |
1054 printk(RVID_MSG"illegal frame_size: %d\n",radeon_config.frame_size); | |
1055 return -EFAULT; | |
1056 } | |
1057 | |
1058 if(radeon_config.num_frames<1){ | |
1059 printk(RVID_MSG"illegal num_frames: %d\n",radeon_config.num_frames); | |
1060 return -EFAULT; | |
1061 } | |
1062 if(radeon_config.num_frames==1) besr.double_buff=0; | |
1063 if(!besr.double_buff) radeon_config.num_frames=1; | |
1064 else radeon_config.num_frames=2; | |
1065 radeon_config.card_type = 0; | |
1066 radeon_config.ram_size = radeon_ram_size; | |
1067 radeon_overlay_off = radeon_ram_size*0x100000 - radeon_config.frame_size*radeon_config.num_frames; | |
1068 radeon_overlay_off &= 0xffff0000; | |
1069 if(radeon_overlay_off < 0){ | |
1070 printk(RVID_MSG"not enough video memory. Need: %u has: %u\n",radeon_config.frame_size*radeon_config.num_frames,radeon_ram_size*0x100000); | |
1071 return -EFAULT; | |
1072 } | |
1073 RTRACE(RVID_MSG"using video overlay at offset %08X\n",radeon_overlay_off); | |
1074 if (copy_to_user((mga_vid_config_t *) arg, &radeon_config, sizeof(mga_vid_config_t))) | |
1075 { | |
1076 printk(RVID_MSG"failed copy to userspace\n"); | |
1077 return -EFAULT; | |
1078 } | |
1079 radeon_vid_set_color_key(radeon_config.colkey_on, | |
1080 radeon_config.colkey_red, | |
1081 radeon_config.colkey_green, | |
1082 radeon_config.colkey_blue); | |
1083 if(swap_fourcc) radeon_config.format = swab32(radeon_config.format); | |
1084 printk(RVID_MSG"configuring for '%s' fourcc\n",fourcc_format_name(radeon_config.format)); | |
1085 return radeon_vid_init_video(&radeon_config); | |
1086 break; | |
1087 | |
1088 case MGA_VID_ON: | |
1089 RTRACE(RVID_MSG"Video ON (ioctl)\n"); | |
1090 radeon_vid_display_video(); | |
1091 video_on = 1; | |
1092 break; | |
1093 | |
1094 case MGA_VID_OFF: | |
1095 RTRACE(RVID_MSG"Video OFF (ioctl)\n"); | |
1096 if(video_on) radeon_vid_stop_video(); | |
1097 video_on = 0; | |
1098 break; | |
1099 | |
1100 case MGA_VID_FSEL: | |
1101 if(copy_from_user(&frame,(int *) arg,sizeof(int))) | |
1102 { | |
1103 printk(RVID_MSG"FSEL failed copy from userspace\n"); | |
1104 return(-EFAULT); | |
1105 } | |
1106 radeon_vid_frame_sel(frame); | |
1107 break; | |
1108 | |
1109 default: | |
1110 printk(RVID_MSG"Invalid ioctl\n"); | |
1111 return (-EINVAL); | |
1112 } | |
1113 | |
1114 return 0; | |
1115 } | |
1116 | |
1117 struct ati_card_id_s | |
1118 { | |
1119 const int id; | |
1120 const char name[17]; | |
1121 }; | |
1122 | |
1123 const struct ati_card_id_s ati_card_ids[]= | |
1124 { | |
1125 #ifdef RAGE128 | |
1126 /* | |
1127 This driver should be compatible with Rage128 (pro) chips. | |
1128 (include adaptive deinterlacing!!!). | |
1129 Moreover: the same logic can be used with Mach64 chips. | |
1130 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
1131 but they are incompatible by i/o ports. So if enthusiasts will want | |
1132 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
1133 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
1134 fourccs (422 and 420 formats only). | |
1135 */ | |
1136 /* Rage128 Pro GL */ | |
1137 { PCI_DEVICE_ID_ATI_Rage128_PA, "R128Pro PA" }, | |
1138 { PCI_DEVICE_ID_ATI_Rage128_PB, "R128Pro PB" }, | |
1139 { PCI_DEVICE_ID_ATI_Rage128_PC, "R128Pro PC" }, | |
1140 { PCI_DEVICE_ID_ATI_Rage128_PD, "R128Pro PD" }, | |
1141 { PCI_DEVICE_ID_ATI_Rage128_PE, "R128Pro PE" }, | |
1142 { PCI_DEVICE_ID_ATI_RAGE128_PF, "R128Pro PF" }, | |
1143 /* Rage128 Pro VR */ | |
1144 { PCI_DEVICE_ID_ATI_RAGE128_PG, "R128Pro PG" }, | |
1145 { PCI_DEVICE_ID_ATI_RAGE128_PH, "R128Pro PH" }, | |
1146 { PCI_DEVICE_ID_ATI_RAGE128_PI, "R128Pro PI" }, | |
1147 { PCI_DEVICE_ID_ATI_RAGE128_PJ, "R128Pro PJ" }, | |
1148 { PCI_DEVICE_ID_ATI_RAGE128_PK, "R128Pro PK" }, | |
1149 { PCI_DEVICE_ID_ATI_RAGE128_PL, "R128Pro PL" }, | |
1150 { PCI_DEVICE_ID_ATI_RAGE128_PM, "R128Pro PM" }, | |
1151 { PCI_DEVICE_ID_ATI_RAGE128_PN, "R128Pro PN" }, | |
1152 { PCI_DEVICE_ID_ATI_RAGE128_PO, "R128Pro PO" }, | |
1153 { PCI_DEVICE_ID_ATI_RAGE128_PP, "R128Pro PP" }, | |
1154 { PCI_DEVICE_ID_ATI_RAGE128_PQ, "R128Pro PQ" }, | |
1155 { PCI_DEVICE_ID_ATI_RAGE128_PR, "R128Pro PR" }, | |
1156 { PCI_DEVICE_ID_ATI_RAGE128_TR, "R128Pro TR" }, | |
1157 { PCI_DEVICE_ID_ATI_RAGE128_PS, "R128Pro PS" }, | |
1158 { PCI_DEVICE_ID_ATI_RAGE128_PT, "R128Pro PT" }, | |
1159 { PCI_DEVICE_ID_ATI_RAGE128_PU, "R128Pro PU" }, | |
1160 { PCI_DEVICE_ID_ATI_RAGE128_PV, "R128Pro PV" }, | |
1161 { PCI_DEVICE_ID_ATI_RAGE128_PW, "R128Pro PW" }, | |
1162 { PCI_DEVICE_ID_ATI_RAGE128_PX, "R128Pro PX" }, | |
1163 /* Rage128 GL */ | |
1164 { PCI_DEVICE_ID_ATI_RAGE128_RE, "R128 RE" }, | |
1165 { PCI_DEVICE_ID_ATI_RAGE128_RF, "R128 RF" }, | |
1166 { PCI_DEVICE_ID_ATI_RAGE128_RG, "R128 RG" }, | |
1167 { PCI_DEVICE_ID_ATI_RAGE128_RH, "R128 RH" }, | |
1168 { PCI_DEVICE_ID_ATI_RAGE128_RI, "R128 RI" }, | |
1169 /* Rage128 VR */ | |
1170 { PCI_DEVICE_ID_ATI_RAGE128_RK, "R128 RK" }, | |
1171 { PCI_DEVICE_ID_ATI_RAGE128_RL, "R128 RL" }, | |
1172 { PCI_DEVICE_ID_ATI_RAGE128_RM, "R128 RM" }, | |
1173 { PCI_DEVICE_ID_ATI_RAGE128_RN, "R128 RN" }, | |
1174 { PCI_DEVICE_ID_ATI_RAGE128_RO, "R128 RO" }, | |
1175 /* Rage128 M3 */ | |
1176 { PCI_DEVICE_ID_ATI_RAGE128_LE, "R128 M3 LE" }, | |
1177 { PCI_DEVICE_ID_ATI_RAGE128_LF, "R128 M3 LF" }, | |
1178 /* Rage128 Pro Ultra */ | |
1179 { PCI_DEVICE_ID_ATI_RAGE128_U1, "R128Pro U1" }, | |
1180 { PCI_DEVICE_ID_ATI_RAGE128_U2, "R128Pro U2" }, | |
1181 { PCI_DEVICE_ID_ATI_RAGE128_U3, "R128Pro U3" } | |
1182 #else | |
1183 /* Radeons (indeed: Rage 256 Pro ;) */ | |
1184 { PCI_DEVICE_ID_RADEON_QD, "Radeon QD " }, | |
1185 { PCI_DEVICE_ID_RADEON_QE, "Radeon QE " }, | |
1186 { PCI_DEVICE_ID_RADEON_QF, "Radeon QF " }, | |
1187 { PCI_DEVICE_ID_RADEON_QG, "Radeon QG " }, | |
1188 { PCI_DEVICE_ID_RADEON_QY, "Radeon VE QY " }, | |
1189 { PCI_DEVICE_ID_RADEON_QZ, "Radeon VE QZ " }, | |
1190 { PCI_DEVICE_ID_RADEON_LY, "Radeon M6 LY " }, | |
1191 { PCI_DEVICE_ID_RADEON_LZ, "Radeon M6 LZ " }, | |
1192 { PCI_DEVICE_ID_RADEON_LW, "Radeon M7 LW " }, | |
1193 { PCI_DEVICE_ID_R200_QL, "Radeon2 8500 QL " }, | |
1194 { PCI_DEVICE_ID_R200_BB, "Radeon2 8500 AIW" }, | |
1195 { PCI_DEVICE_ID_RV200_QW, "Radeon2 7500 QW " } | |
1196 #endif | |
1197 }; | |
1198 | |
1199 static int detected_chip; | |
1200 | |
1201 static int __init radeon_vid_config_card(void) | |
1202 { | |
1203 struct pci_dev *dev = NULL; | |
1204 size_t i; | |
1205 | |
1206 for(i=0;i<sizeof(ati_card_ids)/sizeof(struct ati_card_id_s);i++) | |
1207 if((dev=pci_find_device(PCI_VENDOR_ID_ATI, ati_card_ids[i].id, NULL))) | |
1208 break; | |
1209 if(!dev) | |
1210 { | |
1211 printk(RVID_MSG"No supported cards found\n"); | |
1212 return FALSE; | |
1213 } | |
1214 | |
1215 radeon_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RADEON_REGSIZE); | |
1216 radeon_mem_base = dev->resource[0].start; | |
1217 | |
1218 RTRACE(RVID_MSG"MMIO at 0x%p\n", radeon_mmio_base); | |
1219 RTRACE(RVID_MSG"Frame Buffer at 0x%08x\n", radeon_mem_base); | |
1220 | |
1221 /* video memory size */ | |
1222 radeon_ram_size = INREG(CONFIG_MEMSIZE); | |
1223 | |
1224 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ | |
1225 radeon_ram_size &= CONFIG_MEMSIZE_MASK; | |
1226 radeon_ram_size /= 0x100000; | |
1227 detected_chip = i; | |
1228 printk(RVID_MSG"Found %s (%uMb memory)\n",ati_card_ids[i].name,radeon_ram_size); | |
1229 #ifndef RAGE128 | |
1230 if(ati_card_ids[i].id == PCI_DEVICE_ID_R200_QL || | |
1231 ati_card_ids[i].id == PCI_DEVICE_ID_R200_BB || | |
1232 ati_card_ids[i].id == PCI_DEVICE_ID_RV200_QW) IsR200 = 1; | |
1233 #endif | |
1234 return TRUE; | |
1235 } | |
1236 | |
1237 #define PARAM_BRIGHTNESS "brightness=" | |
1238 #define PARAM_SATURATION "saturation=" | |
1239 #define PARAM_CONTRAST "contrast=" | |
1240 #define PARAM_HUE "hue=" | |
1241 #define PARAM_DOUBLE_BUFF "double_buff=" | |
1242 #define PARAM_DEINTERLACE "deinterlace=" | |
1243 #define PARAM_DEINTERLACE_PATTERN "deinterlace_pattern=" | |
1244 #ifdef RADEON_FPU | |
1245 static int ovBrightness=0, ovSaturation=0, ovContrast=0, ovHue=0, ov_trans_idx=0; | |
1246 #endif | |
1247 | |
1248 static void radeon_param_buff_fill( void ) | |
1249 { | |
1250 unsigned len,saturation; | |
1251 int8_t brightness; | |
1252 brightness = besr.brightness & 0x7f; | |
1253 /* FIXME: It's probably x86 specific convertion. But it doesn't matter | |
1254 for general logic - only for printing value */ | |
1255 if(brightness > 63) brightness = (((~besr.brightness) & 0x3f)+1) * (-1); | |
1256 saturation = besr.saturation; | |
1257 len = 0; | |
1258 len += sprintf(&radeon_param_buff[len],"Interface version: %04X\nDriver version: %s\n",MGA_VID_VERSION,RADEON_VID_VERSION); | |
1259 len += sprintf(&radeon_param_buff[len],"Chip: %s\n",ati_card_ids[detected_chip].name); | |
1260 len += sprintf(&radeon_param_buff[len],"Memory: %x:%x\n",radeon_mem_base,radeon_ram_size*0x100000); | |
1261 len += sprintf(&radeon_param_buff[len],"MMIO: %p\n",radeon_mmio_base); | |
1262 len += sprintf(&radeon_param_buff[len],"Overlay offset: %x\n",radeon_overlay_off); | |
1263 #ifdef CONFIG_MTRR | |
1264 len += sprintf(&radeon_param_buff[len],"Tune MTRR: %s\n",mtrr?"on":"off"); | |
1265 #endif | |
1266 if(besr.ckey_on) len += sprintf(&radeon_param_buff[len],"Last used color_key=%X (mask=%X)\n",besr.graphics_key_clr,besr.graphics_key_msk); | |
1267 len += sprintf(&radeon_param_buff[len],"Swapped fourcc: %s\n",swap_fourcc?"on":"off"); | |
1268 len += sprintf(&radeon_param_buff[len],"Last BPP: %u\n",besr.dest_bpp); | |
1269 len += sprintf(&radeon_param_buff[len],"Last fourcc: %s\n\n",fourcc_format_name(besr.fourcc)); | |
1270 len += sprintf(&radeon_param_buff[len],"Configurable stuff:\n"); | |
1271 len += sprintf(&radeon_param_buff[len],"~~~~~~~~~~~~~~~~~~~\n"); | |
1272 len += sprintf(&radeon_param_buff[len],PARAM_DOUBLE_BUFF"%s\n",besr.double_buff?"on":"off"); | |
1273 #ifdef RAGE128 | |
1274 len += sprintf(&radeon_param_buff[len],PARAM_BRIGHTNESS"%i\n",(int)brightness); | |
1275 len += sprintf(&radeon_param_buff[len],PARAM_SATURATION"%u\n",saturation); | |
1276 #else | |
1277 #ifdef RADEON_FPU | |
1278 len += sprintf(&radeon_param_buff[len],PARAM_BRIGHTNESS"%i\n",ovBrightness); | |
1279 len += sprintf(&radeon_param_buff[len],PARAM_SATURATION"%i\n",ovSaturation); | |
1280 len += sprintf(&radeon_param_buff[len],PARAM_CONTRAST"%i\n",ovContrast); | |
1281 len += sprintf(&radeon_param_buff[len],PARAM_HUE"%i\n",ovHue); | |
1282 #endif | |
1283 #endif | |
1284 len += sprintf(&radeon_param_buff[len],PARAM_DEINTERLACE"%s\n",besr.deinterlace_on?"on":"off"); | |
1285 len += sprintf(&radeon_param_buff[len],PARAM_DEINTERLACE_PATTERN"%X\n",besr.deinterlace_pattern); | |
1286 radeon_param_buff_len = len; | |
1287 } | |
1288 | |
1289 static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) | |
1290 { | |
1291 uint32_t size; | |
1292 if(!radeon_param_buff) return -ESPIPE; | |
1293 if(!(*ppos)) radeon_param_buff_fill(); | |
1294 if(*ppos >= radeon_param_buff_len) return 0; | |
1295 size = min(count,radeon_param_buff_len-(uint32_t)(*ppos)); | |
1296 memcpy(buf,radeon_param_buff,size); | |
1297 *ppos += size; | |
1298 return size; | |
1299 } | |
1300 | |
1301 #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) | |
1302 #define RTFBrightness(a) (((a)*1.0)/2000.0) | |
1303 #define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) | |
1304 #define RTFHue(a) (((a)*3.1416)/1000.0) | |
1305 #define RadeonSetParm(a,b,c,d) if((b)>=(c)&&(b)<=(d)) { (a)=(b);\ | |
1306 radeon_set_transform(RTFBrightness(ovBrightness),RTFContrast(ovContrast)\ | |
1307 ,RTFSaturation(ovSaturation),RTFHue(ovHue),ov_trans_idx); } | |
1308 | |
1309 | |
1310 static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) | |
1311 { | |
1312 #ifdef RAGE128 | |
1313 if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0) | |
1314 { | |
1315 long brightness; | |
1316 brightness=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10); | |
1317 if(brightness >= -64 && brightness <= 63) | |
1318 { | |
1319 besr.brightness = brightness; | |
1320 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) | | |
1321 (besr.saturation << 8) | | |
1322 (besr.saturation << 16)); | |
1323 } | |
1324 } | |
1325 else | |
1326 if(memcmp(buf,PARAM_SATURATION,min(count,strlen(PARAM_SATURATION))) == 0) | |
1327 { | |
1328 long saturation; | |
1329 saturation=simple_strtol(&buf[strlen(PARAM_SATURATION)],NULL,10); | |
1330 if(saturation >= 0 && saturation <= 31) | |
1331 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | | |
1332 (saturation << 8) | | |
1333 (saturation << 16)); | |
1334 } | |
1335 else | |
1336 #else | |
1337 #ifdef RADEON_FPU | |
1338 if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0) | |
1339 { | |
1340 int tmp; | |
1341 tmp=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10); | |
1342 RadeonSetParm(ovBrightness,tmp,-1000,1000); | |
1343 } | |
1344 else | |
1345 if(memcmp(buf,PARAM_SATURATION,min(count,strlen(PARAM_SATURATION))) == 0) | |
1346 { | |
1347 int tmp; | |
1348 tmp=simple_strtol(&buf[strlen(PARAM_SATURATION)],NULL,10); | |
1349 RadeonSetParm(ovSaturation,tmp,-1000,1000); | |
1350 } | |
1351 else | |
1352 if(memcmp(buf,PARAM_CONTRAST,min(count,strlen(PARAM_CONTRAST))) == 0) | |
1353 { | |
1354 int tmp; | |
1355 tmp=simple_strtol(&buf[strlen(PARAM_CONTRAST)],NULL,10); | |
1356 RadeonSetParm(ovContrast,tmp,-1000,1000); | |
1357 } | |
1358 else | |
1359 if(memcmp(buf,PARAM_HUE,min(count,strlen(PARAM_HUE))) == 0) | |
1360 { | |
1361 int tmp; | |
1362 tmp=simple_strtol(&buf[strlen(PARAM_HUE)],NULL,10); | |
1363 RadeonSetParm(ovHue,tmp,-1000,1000); | |
1364 } | |
1365 else | |
1366 #endif | |
1367 #endif | |
1368 if(memcmp(buf,PARAM_DOUBLE_BUFF,min(count,strlen(PARAM_DOUBLE_BUFF))) == 0) | |
1369 { | |
1370 if(memcmp(&buf[strlen(PARAM_DOUBLE_BUFF)],"on",2) == 0) besr.double_buff = 1; | |
1371 else besr.double_buff = 0; | |
1372 } | |
1373 else | |
1374 if(memcmp(buf,PARAM_DEINTERLACE,min(count,strlen(PARAM_DEINTERLACE))) == 0) | |
1375 { | |
1376 if(memcmp(&buf[strlen(PARAM_DEINTERLACE)],"on",2) == 0) besr.deinterlace_on = 1; | |
1377 else besr.deinterlace_on = 0; | |
1378 } | |
1379 else | |
1380 if(memcmp(buf,PARAM_DEINTERLACE_PATTERN,min(count,strlen(PARAM_DEINTERLACE_PATTERN))) == 0) | |
1381 { | |
1382 long dpat; | |
1383 dpat=simple_strtol(&buf[strlen(PARAM_DEINTERLACE_PATTERN)],NULL,16); | |
1384 OUTREG(OV0_DEINTERLACE_PATTERN, dpat); | |
1385 } | |
1386 else count = -EIO; | |
1387 radeon_vid_preset(); | |
1388 return count; | |
1389 } | |
1390 | |
1391 static int radeon_vid_mmap(struct file *file, struct vm_area_struct *vma) | |
1392 { | |
1393 | |
1394 RTRACE(RVID_MSG"mapping video memory into userspace\n"); | |
1395 if(remap_page_range(vma->vm_start, radeon_mem_base + radeon_overlay_off, | |
1396 vma->vm_end - vma->vm_start, vma->vm_page_prot)) | |
1397 { | |
1398 printk(RVID_MSG"error mapping video memory\n"); | |
1399 return(-EAGAIN); | |
1400 } | |
1401 | |
1402 return(0); | |
1403 } | |
1404 | |
1405 static int radeon_vid_release(struct inode *inode, struct file *file) | |
1406 { | |
1407 radeon_vid_in_use = 0; | |
1408 radeon_vid_stop_video(); | |
1409 | |
1410 MOD_DEC_USE_COUNT; | |
1411 return 0; | |
1412 } | |
1413 | |
1414 static long long radeon_vid_lseek(struct file *file, long long offset, int origin) | |
1415 { | |
1416 return -ESPIPE; | |
1417 } | |
1418 | |
1419 static int radeon_vid_open(struct inode *inode, struct file *file) | |
1420 { | |
1421 int minor = MINOR(inode->i_rdev); | |
1422 | |
1423 if(minor != 0) | |
1424 return(-ENXIO); | |
1425 | |
1426 if(radeon_vid_in_use == 1) | |
1427 return(-EBUSY); | |
1428 | |
1429 radeon_vid_in_use = 1; | |
1430 MOD_INC_USE_COUNT; | |
1431 return(0); | |
1432 } | |
1433 | |
1434 #if LINUX_VERSION_CODE >= 0x020400 | |
1435 static struct file_operations radeon_vid_fops = | |
1436 { | |
1437 llseek: radeon_vid_lseek, | |
1438 read: radeon_vid_read, | |
1439 write: radeon_vid_write, | |
1440 /* | |
1441 readdir: | |
1442 poll: | |
1443 */ | |
1444 ioctl: radeon_vid_ioctl, | |
1445 mmap: radeon_vid_mmap, | |
1446 open: radeon_vid_open, | |
1447 /* | |
1448 flush: | |
1449 */ | |
1450 release: radeon_vid_release | |
1451 /* | |
1452 fsync: | |
1453 fasync: | |
1454 lock: | |
1455 readv: | |
1456 writev: | |
1457 sendpage: | |
1458 get_unmapped_area: | |
1459 */ | |
1460 }; | |
1461 #else | |
1462 static struct file_operations radeon_vid_fops = | |
1463 { | |
1464 radeon_vid_lseek, | |
1465 radeon_vid_read, | |
1466 radeon_vid_write, | |
1467 NULL, | |
1468 NULL, | |
1469 radeon_vid_ioctl, | |
1470 radeon_vid_mmap, | |
1471 radeon_vid_open, | |
1472 NULL, | |
1473 radeon_vid_release | |
1474 }; | |
1475 #endif | |
1476 | |
1477 /* | |
1478 * Main Initialization Function | |
1479 */ | |
1480 | |
1481 static int __init radeon_vid_initialize(void) | |
1482 { | |
1483 radeon_vid_in_use = 0; | |
1484 #ifdef RAGE128 | |
1485 printk(RVID_MSG"Rage128/Rage128Pro video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); | |
1486 #else | |
1487 printk(RVID_MSG"Radeon video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); | |
1488 #endif | |
1489 if(register_chrdev(RADEON_VID_MAJOR, "radeon_vid", &radeon_vid_fops)) | |
1490 { | |
1491 printk(RVID_MSG"unable to get major: %d\n", RADEON_VID_MAJOR); | |
1492 return -EIO; | |
1493 } | |
1494 | |
1495 if (!radeon_vid_config_card()) | |
1496 { | |
1497 printk(RVID_MSG"can't configure this card\n"); | |
1498 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); | |
1499 return -EINVAL; | |
1500 } | |
1501 radeon_param_buff = kmalloc(PARAM_BUFF_SIZE,GFP_KERNEL); | |
1502 if(radeon_param_buff) radeon_param_buff_size = PARAM_BUFF_SIZE; | |
1503 #if 0 | |
1504 radeon_vid_save_state(); | |
1505 #endif | |
1506 radeon_vid_make_default(); | |
1507 radeon_vid_preset(); | |
1508 #ifdef CONFIG_MTRR | |
1509 if (mtrr) { | |
1510 smtrr.vram = mtrr_add(radeon_mem_base, | |
1511 radeon_ram_size*0x100000, MTRR_TYPE_WRCOMB, 1); | |
1512 smtrr.vram_valid = 1; | |
1513 /* let there be speed */ | |
1514 printk(RVID_MSG"MTRR set to ON\n"); | |
1515 } | |
1516 #endif /* CONFIG_MTRR */ | |
1517 return(0); | |
1518 } | |
1519 | |
1520 int __init init_module(void) | |
1521 { | |
1522 return radeon_vid_initialize(); | |
1523 } | |
1524 | |
1525 void __exit cleanup_module(void) | |
1526 { | |
1527 #if 0 | |
1528 radeon_vid_restore_state(); | |
1529 #endif | |
1530 if(radeon_mmio_base) | |
1531 iounmap(radeon_mmio_base); | |
1532 kfree(radeon_param_buff); | |
1533 RTRACE(RVID_MSG"Cleaning up module\n"); | |
1534 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); | |
1535 #ifdef CONFIG_MTRR | |
1536 if (smtrr.vram_valid) | |
1537 mtrr_del(smtrr.vram, radeon_mem_base, | |
1538 radeon_ram_size*0x100000); | |
1539 #endif /* CONFIG_MTRR */ | |
1540 } | |
1541 |