Mercurial > mplayer.hg
annotate vidix/unichrome_regs.h @ 25899:9d4121fa508a
Split osd related stuff from mp_core.h into new header file mp_osd.h.
author | ulion |
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date | Wed, 30 Jan 2008 07:21:05 +0000 |
parents | 88bed2131f19 |
children | a93e46adb54c |
rev | line source |
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22850 | 1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/via/via.h,v 1.5 2004/01/05 00:34:17 dawes Exp $ */ |
2 /* | |
3 * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. | |
4 * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. | |
5 * | |
6 * Permission is hereby granted, free of charge, to any person obtaining a | |
7 * copy of this software and associated documentation files (the "Software"), | |
8 * to deal in the Software without restriction, including without limitation | |
9 * the rights to use, copy, modify, merge, publish, distribute, sub license, | |
10 * and/or sell copies of the Software, and to permit persons to whom the | |
11 * Software is furnished to do so, subject to the following conditions: | |
12 * | |
13 * The above copyright notice and this permission notice (including the | |
14 * next paragraph) shall be included in all copies or substantial portions | |
15 * of the Software. | |
16 * | |
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
20 * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 * DEALINGS IN THE SOFTWARE. | |
24 */ | |
25 | |
23934
88bed2131f19
Identifiers starting with underscores are reserved.
diego
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26 #ifndef UNICHROME_REGS_H |
88bed2131f19
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27 #define UNICHROME_REGS_H |
22850 | 28 |
29 /* Video status flag */ | |
30 | |
31 #define VIDEO_SHOW 0x80000000 /*Video on*/ | |
32 #define VIDEO_HIDE 0x00000000 /*Video off*/ | |
33 #define VIDEO_MPEG_INUSE 0x08000000 /*Video is used with MPEG */ | |
34 #define VIDEO_HQV_INUSE 0x04000000 /*Video is used with HQV*/ | |
35 #define VIDEO_CAPTURE0_INUSE 0x02000000 /*Video is used with CAPTURE 0*/ | |
36 #define VIDEO_CAPTURE1_INUSE 0x00000000 /*Video is used with CAPTURE 1*/ | |
37 #define VIDEO_1_INUSE 0x01000000 /*Video 1 is used with software flip*/ | |
38 #define VIDEO_3_INUSE 0x00000000 /*Video 3 is used with software flip*/ | |
39 #define MPEG_USE_V1 0x00010000 /*[16] : 1:MPEG use V1, 0:MPEG use V3*/ | |
40 #define MPEG_USE_V3 0x00000000 /*[16] : 1:MPEG use V1, 0:MPEG use V3*/ | |
41 #define MPEG_USE_HQV 0x00020000 /*[17] : 1:MPEG use HQV,0:MPEG not use HQV*/ | |
42 #define MPEG_USE_HW_FLIP 0x00040000 /*[18] : 1:MPEG use H/W flip,0:MPEG use S/W flip*/ | |
43 #define MPEG_USE_SW_FLIP 0x00000000 /*[18] : 1:MPEG use H/W flip,0:MPEG use S/W flip*/ | |
44 #define CAP0_USE_V1 0x00001000 /*[12] : 1:Capture 0 use V1, 0:Capture 0 use V3*/ | |
45 #define CAP0_USE_V3 0x00000000 /*[12] : 1:Capture 0 use V1, 0:Capture 0 use V3*/ | |
46 #define CAP0_USE_HQV 0x00002000 /*[13] : 1:Capture 0 use HQV,0:Capture 0 not use HQV*/ | |
47 #define CAP0_USE_HW_FLIP 0x00004000 /*[14] : 1:Capture 0 use H/W flip,0:Capture 0 use S/W flip*/ | |
48 #define CAP0_USE_CCIR656 0x00008000 /*[15] : 1:Capture 0 use CCIR656,0:Capture 0 CCIR601*/ | |
49 #define CAP1_USE_V1 0x00000100 /*[ 8] : 1:Capture 1 use V1, 0:Capture 1 use V3*/ | |
50 #define CAP1_USE_V3 0x00000000 /*[ 8] : 1:Capture 1 use V1, 0:Capture 1 use V3*/ | |
51 #define CAP1_USE_HQV 0x00000200 /*[ 9] : 1:Capture 1 use HQV,0:Capture 1 not use HQV*/ | |
52 #define CAP1_USE_HW_FLIP 0x00000400 /*[10] : 1:Capture 1 use H/W flip,0:Capture 1 use S/W flip */ | |
53 #define SW_USE_V1 0x00000010 /*[ 4] : 1:Capture 1 use V1, 0:Capture 1 use V3 */ | |
54 #define SW_USE_V3 0x00000000 /*[ 4] : 1:Capture 1 use V1, 0:Capture 1 use V3 */ | |
55 #define SW_USE_HQV 0x00000020 /*[ 5] : 1:Capture 1 use HQV,0:Capture 1 not use HQV */ | |
56 | |
57 /* | |
58 #define VIDEO1_INUSE 0x00000010 //[ 4] : 1:Video 1 is used with S/W flip | |
59 #define VIDEO1_USE_HQV 0x00000020 //[ 5] : 1:Video 1 use HQV with S/W flip | |
60 #define VIDEO3_INUSE 0x00000001 //[ 0] : 1:Video 3 is used with S/W flip | |
61 #define VIDEO3_USE_HQV 0x00000002 //[ 1] : 1:Video 3 use HQV with S/W flip | |
62 */ | |
63 | |
64 /* H/W registers for Video Engine */ | |
65 | |
66 /* | |
67 * bus master | |
68 */ | |
69 #define PCI_MASTER_ENABLE 0x01 | |
70 #define PCI_MASTER_SCATTER 0x00 | |
71 #define PCI_MASTER_SINGLE 0x02 | |
72 #define PCI_MASTER_GUI 0x00 | |
73 #define PCI_MASTER_VIDEO 0x04 | |
74 #define PCI_MASTER_INPUT 0x00 | |
75 #define PCI_MASTER_OUTPUT 0x08 | |
76 | |
77 /* | |
78 * video registers | |
79 */ | |
80 #define V_FLAGS 0x00 | |
81 #define V_CAP_STATUS 0x04 | |
82 #define V_FLIP_STATUS 0x04 | |
83 #define V_ALPHA_WIN_START 0x08 | |
84 #define V_ALPHA_WIN_END 0x0C | |
85 #define V_ALPHA_CONTROL 0x10 | |
86 #define V_CRT_STARTADDR 0x14 | |
87 #define V_CRT_STARTADDR_2 0x18 | |
88 #define V_ALPHA_STRIDE 0x1C | |
89 #define V_COLOR_KEY 0x20 | |
90 #define V_ALPHA_STARTADDR 0x24 | |
91 #define V_CHROMAKEY_LOW 0x28 | |
92 #define V_CHROMAKEY_HIGH 0x2C | |
93 #define V1_CONTROL 0x30 | |
94 #define V12_QWORD_PER_LINE 0x34 | |
95 #define V1_STARTADDR_1 0x38 | |
96 #define V1_STARTADDR_Y1 V1_STARTADDR_1 | |
97 #define V1_STRIDE 0x3C | |
98 #define V1_WIN_START_Y 0x40 | |
99 #define V1_WIN_START_X 0x42 | |
100 #define V1_WIN_END_Y 0x44 | |
101 #define V1_WIN_END_X 0x46 | |
102 #define V1_STARTADDR_2 0x48 | |
103 #define V1_STARTADDR_Y2 V1_STARTADDR_2 | |
104 #define V1_ZOOM_CONTROL 0x4C | |
105 #define V1_MINI_CONTROL 0x50 | |
106 #define V1_STARTADDR_0 0x54 | |
107 #define V1_STARTADDR_Y0 V1_STARTADDR_0 | |
108 #define V_FIFO_CONTROL 0x58 | |
109 #define V1_STARTADDR_3 0x5C | |
110 #define V1_STARTADDR_Y3 V1_STARTADDR_3 | |
111 #define HI_CONTROL 0x60 | |
112 #define SND_COLOR_KEY 0x64 | |
113 #define ALPHA_V3_PREFIFO_CONTROL 0x68 | |
114 #define V1_SOURCE_HEIGHT 0x6C | |
115 #define HI_TRANSPARENT_COLOR 0x70 | |
116 #define V_DISPLAY_TEMP 0x74 /* No use */ | |
117 #define ALPHA_V3_FIFO_CONTROL 0x78 | |
118 #define V3_SOURCE_WIDTH 0x7C | |
119 #define V3_COLOR_KEY 0x80 | |
120 #define V1_ColorSpaceReg_1 0x84 | |
121 #define V1_ColorSpaceReg_2 0x88 | |
122 #define V1_STARTADDR_CB0 0x8C | |
123 #define V1_OPAQUE_CONTROL 0x90 /* To be deleted */ | |
124 #define V3_OPAQUE_CONTROL 0x94 /* To be deleted */ | |
125 #define V_COMPOSE_MODE 0x98 | |
126 #define V3_STARTADDR_2 0x9C | |
127 #define V3_CONTROL 0xA0 | |
128 #define V3_STARTADDR_0 0xA4 | |
129 #define V3_STARTADDR_1 0xA8 | |
130 #define V3_STRIDE 0xAC | |
131 #define V3_WIN_START_Y 0xB0 | |
132 #define V3_WIN_START_X 0xB2 | |
133 #define V3_WIN_END_Y 0xB4 | |
134 #define V3_WIN_END_X 0xB6 | |
135 #define V3_ALPHA_QWORD_PER_LINE 0xB8 | |
136 #define V3_ZOOM_CONTROL 0xBC | |
137 #define V3_MINI_CONTROL 0xC0 | |
138 #define V3_ColorSpaceReg_1 0xC4 | |
139 #define V3_ColorSpaceReg_2 0xC8 | |
140 #define V3_DISPLAY_TEMP 0xCC /* No use */ | |
141 #define V1_STARTADDR_CB1 0xE4 | |
142 #define V1_STARTADDR_CB2 0xE8 | |
143 #define V1_STARTADDR_CB3 0xEC | |
144 #define V1_STARTADDR_CR0 0xF0 | |
145 #define V1_STARTADDR_CR1 0xF4 | |
146 #define V1_STARTADDR_CR2 0xF8 | |
147 #define V1_STARTADDR_CR3 0xFC | |
148 | |
149 /* Video Capture Engine Registers | |
150 * Capture Port 1 | |
151 */ | |
152 #define CAP0_MASKS 0x100 | |
153 #define CAP1_MASKS 0x104 | |
154 #define CAP0_CONTROL 0x110 | |
155 #define CAP0_H_RANGE 0x114 | |
156 #define CAP0_V_RANGE 0x118 | |
157 #define CAP0_SCAL_CONTROL 0x11C | |
158 #define CAP0_VBI_H_RANGE 0x120 | |
159 #define CAP0_VBI_V_RANGE 0x124 | |
160 #define CAP0_VBI_STARTADDR 0x128 | |
161 #define CAP0_VBI_STRIDE 0x12C | |
162 #define CAP0_ANCIL_COUNT 0x130 | |
163 #define CAP0_MAXCOUNT 0x134 | |
164 #define CAP0_VBIMAX_COUNT 0x138 | |
165 #define CAP0_DATA_COUNT 0x13C | |
166 #define CAP0_FB_STARTADDR0 0x140 | |
167 #define CAP0_FB_STARTADDR1 0x144 | |
168 #define CAP0_FB_STARTADDR2 0x148 | |
169 #define CAP0_STRIDE 0x150 | |
170 /* Capture Port 2 */ | |
171 #define CAP1_CONTROL 0x154 | |
172 #define CAP1_SCAL_CONTROL 0x160 | |
173 #define CAP1_VBI_H_RANGE 0x164 /*To be deleted*/ | |
174 #define CAP1_VBI_V_RANGE 0x168 /*To be deleted*/ | |
175 #define CAP1_VBI_STARTADDR 0x16C /*To be deleted*/ | |
176 #define CAP1_VBI_STRIDE 0x170 /*To be deleted*/ | |
177 #define CAP1_ANCIL_COUNT 0x174 /*To be deleted*/ | |
178 #define CAP1_MAXCOUNT 0x178 | |
179 #define CAP1_VBIMAX_COUNT 0x17C /*To be deleted*/ | |
180 #define CAP1_DATA_COUNT 0x180 | |
181 #define CAP1_FB_STARTADDR0 0x184 | |
182 #define CAP1_FB_STARTADDR1 0x188 | |
183 #define CAP1_STRIDE 0x18C | |
184 | |
185 /* SUBPICTURE Registers */ | |
186 #define SUBP_CONTROL_STRIDE 0x1C0 | |
187 #define SUBP_STARTADDR 0x1C4 | |
188 #define RAM_TABLE_CONTROL 0x1C8 | |
189 #define RAM_TABLE_READ 0x1CC | |
190 | |
191 /* HQV Registers */ | |
192 #define HQV_CONTROL 0x1D0 | |
193 #define HQV_SRC_STARTADDR_Y 0x1D4 | |
194 #define HQV_SRC_STARTADDR_U 0x1D8 | |
195 #define HQV_SRC_STARTADDR_V 0x1DC | |
196 #define HQV_SRC_FETCH_LINE 0x1E0 | |
197 #define HQV_FILTER_CONTROL 0x1E4 | |
198 #define HQV_MINIFY_CONTROL 0x1E8 | |
199 #define HQV_DST_STARTADDR0 0x1EC | |
200 #define HQV_DST_STARTADDR1 0x1F0 | |
201 #define HQV_DST_STARTADDR2 0x1FC | |
202 #define HQV_DST_STRIDE 0x1F4 | |
203 #define HQV_SRC_STRIDE 0x1F8 | |
204 | |
205 | |
206 /* | |
207 * Video command definition | |
208 */ | |
209 /* #define V_ALPHA_CONTROL 0x210 */ | |
210 #define ALPHA_WIN_EXPIRENUMBER_4 0x00040000 | |
211 #define ALPHA_WIN_CONSTANT_FACTOR_4 0x00004000 | |
212 #define ALPHA_WIN_CONSTANT_FACTOR_12 0x0000c000 | |
213 #define ALPHA_WIN_BLENDING_CONSTANT 0x00000000 | |
214 #define ALPHA_WIN_BLENDING_ALPHA 0x00000001 | |
215 #define ALPHA_WIN_BLENDING_GRAPHIC 0x00000002 | |
216 #define ALPHA_WIN_PREFIFO_THRESHOLD_12 0x000c0000 | |
217 #define ALPHA_WIN_FIFO_THRESHOLD_8 0x000c0000 | |
218 #define ALPHA_WIN_FIFO_DEPTH_16 0x00100000 | |
219 | |
220 /* V_CHROMAKEY_LOW 0x228 */ | |
221 #define V_CHROMAKEY_V3 0x80000000 | |
222 | |
223 /* V1_CONTROL 0x230 */ | |
224 #define V1_ENABLE 0x00000001 | |
225 #define V1_FULL_SCREEN 0x00000002 | |
226 #define V1_YUV422 0x00000000 | |
227 #define V1_RGB32 0x00000004 | |
228 #define V1_RGB15 0x00000008 | |
229 #define V1_RGB16 0x0000000C | |
230 #define V1_YCbCr420 0x00000010 | |
231 #define V1_COLORSPACE_SIGN 0x00000080 | |
232 #define V1_SRC_IS_FIELD_PIC 0x00000200 | |
233 #define V1_SRC_IS_FRAME_PIC 0x00000000 | |
234 #define V1_BOB_ENABLE 0x00400000 | |
235 #define V1_FIELD_BASE 0x00000000 | |
236 #define V1_FRAME_BASE 0x01000000 | |
237 #define V1_SWAP_SW 0x00000000 | |
238 #define V1_SWAP_HW_HQV 0x02000000 | |
239 #define V1_SWAP_HW_CAPTURE 0x04000000 | |
240 #define V1_SWAP_HW_MC 0x06000000 | |
241 /* #define V1_DOUBLE_BUFFERS 0x00000000 */ | |
242 /* #define V1_QUADRUPLE_BUFFERS 0x18000000 */ | |
243 #define V1_EXPIRE_NUM 0x00050000 | |
244 #define V1_EXPIRE_NUM_A 0x000a0000 | |
245 #define V1_EXPIRE_NUM_F 0x000f0000 /* jason */ | |
246 #define V1_FIFO_EXTENDED 0x00200000 | |
247 #define V1_ON_CRT 0x00000000 | |
248 #define V1_ON_SND_DISPLAY 0x80000000 | |
249 #define V1_FIFO_32V1_32V2 0x00000000 | |
250 #define V1_FIFO_48V1_32V2 0x00200000 | |
251 | |
252 /* V12_QWORD_PER_LINE 0x234 */ | |
253 #define V1_FETCH_COUNT 0x3ff00000 | |
254 #define V1_FETCHCOUNT_ALIGNMENT 0x0000000f | |
255 #define V1_FETCHCOUNT_UNIT 0x00000004 /* Doubld QWORD */ | |
256 | |
257 /* V1_STRIDE */ | |
258 #define V1_STRIDE_YMASK 0x00001fff | |
259 #define V1_STRIDE_UVMASK 0x1ff00000 | |
260 | |
261 /* V1_ZOOM_CONTROL 0x24C */ | |
262 #define V1_X_ZOOM_ENABLE 0x80000000 | |
263 #define V1_Y_ZOOM_ENABLE 0x00008000 | |
264 | |
265 /* V1_MINI_CONTROL 0x250 */ | |
266 #define V1_X_INTERPOLY 0x00000002 /* X interpolation */ | |
267 #define V1_Y_INTERPOLY 0x00000001 /* Y interpolation */ | |
268 #define V1_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ | |
269 #define V1_X_DIV_2 0x01000000 | |
270 #define V1_X_DIV_4 0x03000000 | |
271 #define V1_X_DIV_8 0x05000000 | |
272 #define V1_X_DIV_16 0x07000000 | |
273 #define V1_Y_DIV_2 0x00010000 | |
274 #define V1_Y_DIV_4 0x00030000 | |
275 #define V1_Y_DIV_8 0x00050000 | |
276 #define V1_Y_DIV_16 0x00070000 | |
277 | |
278 /* V1_STARTADDR0 0x254 */ | |
279 #define SW_FLIP_ODD 0x08000000 | |
280 | |
281 /* V_FIFO_CONTROL 0x258 | |
282 * IA2 has 32 level FIFO for packet mode video format | |
283 * 32 level FIFO for planar mode video YV12. with extension reg 230 bit 21 enable | |
284 * 16 level FIFO for planar mode video YV12. with extension reg 230 bit 21 disable | |
285 * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 | |
286 */ | |
287 #define V1_FIFO_DEPTH12 0x0000000B | |
288 #define V1_FIFO_DEPTH16 0x0000000F | |
289 #define V1_FIFO_DEPTH32 0x0000001F | |
290 #define V1_FIFO_DEPTH48 0x0000002F | |
291 #define V1_FIFO_DEPTH64 0x0000003F | |
292 #define V1_FIFO_THRESHOLD6 0x00000600 | |
293 #define V1_FIFO_THRESHOLD8 0x00000800 | |
294 #define V1_FIFO_THRESHOLD12 0x00000C00 | |
295 #define V1_FIFO_THRESHOLD16 0x00001000 | |
296 #define V1_FIFO_THRESHOLD24 0x00001800 | |
297 #define V1_FIFO_THRESHOLD32 0x00002000 | |
298 #define V1_FIFO_THRESHOLD40 0x00002800 | |
299 #define V1_FIFO_THRESHOLD48 0x00003000 | |
300 #define V1_FIFO_THRESHOLD56 0x00003800 | |
301 #define V1_FIFO_THRESHOLD61 0x00003D00 | |
302 #define V1_FIFO_PRETHRESHOLD10 0x0A000000 | |
303 #define V1_FIFO_PRETHRESHOLD12 0x0C000000 | |
304 #define V1_FIFO_PRETHRESHOLD29 0x1d000000 | |
305 #define V1_FIFO_PRETHRESHOLD40 0x28000000 | |
306 #define V1_FIFO_PRETHRESHOLD44 0x2c000000 | |
307 #define V1_FIFO_PRETHRESHOLD56 0x38000000 | |
308 #define V1_FIFO_PRETHRESHOLD61 0x3D000000 | |
309 | |
310 /* ALPHA_V3_FIFO_CONTROL 0x278 | |
311 * IA2 has 32 level FIFO for packet mode video format | |
312 * 32 level FIFO for planar mode video YV12. with extension reg 230 bit 21 enable | |
313 * 16 level FIFO for planar mode video YV12. with extension reg 230 bit 21 disable | |
314 * 8 level FIFO for ALPHA | |
315 * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 | |
316 */ | |
317 #define V3_FIFO_DEPTH16 0x0000000F | |
318 #define V3_FIFO_DEPTH24 0x00000017 | |
319 #define V3_FIFO_DEPTH32 0x0000001F | |
320 #define V3_FIFO_DEPTH48 0x0000002F | |
321 #define V3_FIFO_DEPTH64 0x0000003F | |
322 #define V3_FIFO_THRESHOLD8 0x00000800 | |
323 #define V3_FIFO_THRESHOLD12 0x00000C00 | |
324 #define V3_FIFO_THRESHOLD16 0x00001000 | |
325 #define V3_FIFO_THRESHOLD24 0x00001800 | |
326 #define V3_FIFO_THRESHOLD32 0x00002000 | |
327 #define V3_FIFO_THRESHOLD40 0x00002800 | |
328 #define V3_FIFO_THRESHOLD48 0x00003000 | |
329 #define V3_FIFO_THRESHOLD56 0x00003800 | |
330 #define V3_FIFO_THRESHOLD61 0x00003D00 | |
331 #define V3_FIFO_PRETHRESHOLD10 0x0000000A | |
332 #define V3_FIFO_PRETHRESHOLD12 0x0000000C | |
333 #define V3_FIFO_PRETHRESHOLD29 0x0000001d | |
334 #define V3_FIFO_PRETHRESHOLD40 0x00000028 | |
335 #define V3_FIFO_PRETHRESHOLD44 0x0000002c | |
336 #define V3_FIFO_PRETHRESHOLD56 0x00000038 | |
337 #define V3_FIFO_PRETHRESHOLD61 0x0000003D | |
338 #define V3_FIFO_MASK 0x0000007F | |
339 #define ALPHA_FIFO_DEPTH8 0x00070000 | |
340 #define ALPHA_FIFO_THRESHOLD4 0x04000000 | |
341 #define ALPHA_FIFO_MASK 0xffff0000 | |
342 #define ALPHA_FIFO_PRETHRESHOLD4 0x00040000 | |
343 | |
344 /* IA2 */ | |
345 #define ColorSpaceValue_1 0x140020f2 | |
346 #define ColorSpaceValue_2 0x0a0a2c00 | |
347 | |
348 #define ColorSpaceValue_1_3123C0 0x13000DED | |
349 #define ColorSpaceValue_2_3123C0 0x13171000 | |
350 | |
351 /* For TV setting */ | |
352 #define ColorSpaceValue_1TV 0x140020f2 | |
353 #define ColorSpaceValue_2TV 0x0a0a2c00 | |
354 | |
355 /* V_COMPOSE_MODE 0x298 */ | |
356 #define SELECT_VIDEO_IF_COLOR_KEY 0x00000001 /* select video if (color key),otherwise select graphics */ | |
357 #define SELECT_VIDEO3_IF_COLOR_KEY 0x00000020 /* For 3123C0, select video3 if (color key),otherwise select graphics */ | |
358 #define SELECT_VIDEO_IF_CHROMA_KEY 0x00000002 /* 0x0000000a //select video if (chroma key ),otherwise select graphics */ | |
359 #define ALWAYS_SELECT_VIDEO 0x00000000 /* always select video,Chroma key and Color key disable */ | |
360 #define COMPOSE_V1_V3 0x00000000 /* V1 on top of V3 */ | |
361 #define COMPOSE_V3_V1 0x00100000 /* V3 on top of V1 */ | |
362 #define COMPOSE_V1_TOP 0x00000000 | |
363 #define COMPOSE_V3_TOP 0x00100000 | |
364 #define V1_COMMAND_FIRE 0x80000000 /* V1 commands fire */ | |
365 #define V3_COMMAND_FIRE 0x40000000 /* V3 commands fire */ | |
366 #define V_COMMAND_LOAD 0x20000000 /* Video register always loaded */ | |
367 #define V_COMMAND_LOAD_VBI 0x10000000 /* Video register always loaded at vbi without waiting source flip */ | |
368 #define V3_COMMAND_LOAD 0x08000000 /* CLE_C0 Video3 register always loaded */ | |
369 #define V3_COMMAND_LOAD_VBI 0x00000100 /* CLE_C0 Video3 register always loaded at vbi without waiting source flip */ | |
370 #define SECOND_DISPLAY_COLOR_KEY_ENABLE 0x00010000 | |
371 | |
372 /* V3_ZOOM_CONTROL 0x2bc */ | |
373 #define V3_X_ZOOM_ENABLE 0x80000000 | |
374 #define V3_Y_ZOOM_ENABLE 0x00008000 | |
375 | |
376 /* V3_MINI_CONTROL 0x2c0 */ | |
377 #define V3_X_INTERPOLY 0x00000002 /* X interpolation */ | |
378 #define V3_Y_INTERPOLY 0x00000001 /* Y interpolation */ | |
379 #define V3_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ | |
380 #define V3_X_DIV_2 0x01000000 | |
381 #define V3_X_DIV_4 0x03000000 | |
382 #define V3_X_DIV_8 0x05000000 | |
383 #define V3_X_DIV_16 0x07000000 | |
384 #define V3_Y_DIV_2 0x00010000 | |
385 #define V3_Y_DIV_4 0x00030000 | |
386 #define V3_Y_DIV_8 0x00050000 | |
387 #define V3_Y_DIV_16 0x00070000 | |
388 | |
389 /* SUBP_CONTROL_STRIDE 0x3c0 */ | |
390 #define SUBP_HQV_ENABLE 0x00010000 | |
391 #define SUBP_IA44 0x00020000 | |
392 #define SUBP_AI44 0x00000000 | |
393 #define SUBP_STRIDE_MASK 0x00001fff | |
394 #define SUBP_CONTROL_MASK 0x00070000 | |
395 | |
396 /* RAM_TABLE_CONTROL 0x3c8 */ | |
397 #define RAM_TABLE_RGB_ENABLE 0x00000007 | |
398 | |
399 /* CAPTURE0_CONTROL 0x310 */ | |
400 #define C0_ENABLE 0x00000001 | |
401 #define BUFFER_2_MODE 0x00000000 | |
402 #define BUFFER_3_MODE 0x00000004 | |
403 #define BUFFER_4_MODE 0x00000006 | |
404 #define SWAP_YUYV 0x00000000 | |
405 #define SWAP_UYVY 0x00000100 | |
406 #define SWAP_YVYU 0x00000200 | |
407 #define SWAP_VYUY 0x00000300 | |
408 #define IN_601_8 0x00000000 | |
409 #define IN_656_8 0x00000010 | |
410 #define IN_601_16 0x00000020 | |
411 #define IN_656_16 0x00000030 | |
412 #define DEINTER_ODD 0x00000000 | |
413 #define DEINTER_EVEN 0x00001000 | |
414 #define DEINTER_ODD_EVEN 0x00002000 | |
415 #define DEINTER_FRAME 0x00003000 | |
416 #define VIP_1 0x00000000 | |
417 #define VIP_2 0x00000400 | |
418 #define H_FILTER_2 0x00010000 | |
419 #define H_FILTER_4 0x00020000 | |
420 #define H_FILTER_8_1331 0x00030000 | |
421 #define H_FILTER_8_12221 0x00040000 | |
422 #define VIP_ENABLE 0x00000008 | |
423 #define EN_FIELD_SIG 0x00000800 | |
424 #define VREF_INVERT 0x00100000 | |
425 #define FIELD_INPUT_INVERSE 0x00400000 | |
426 #define FIELD_INVERSE 0x40000000 | |
427 | |
428 #define C1_H_MINI_EN 0x00000800 | |
429 #define C0_H_MINI_EN 0x00000800 | |
430 #define C1_V_MINI_EN 0x04000000 | |
431 #define C0_V_MINI_EN 0x04000000 | |
432 #define C1_H_MINI_2 0x00000400 | |
433 | |
434 /* CAPTURE1_CONTROL 0x354 */ | |
435 #define C1_ENABLE 0x00000001 | |
436 | |
437 /* V3_CONTROL 0x2A0 */ | |
438 #define V3_ENABLE 0x00000001 | |
439 #define V3_FULL_SCREEN 0x00000002 | |
440 #define V3_YUV422 0x00000000 | |
441 #define V3_RGB32 0x00000004 | |
442 #define V3_RGB15 0x00000008 | |
443 #define V3_RGB16 0x0000000C | |
444 #define V3_COLORSPACE_SIGN 0x00000080 | |
445 #define V3_EXPIRE_NUM 0x00040000 | |
446 #define V3_EXPIRE_NUM_F 0x000f0000 | |
447 #define V3_BOB_ENABLE 0x00400000 | |
448 #define V3_FIELD_BASE 0x00000000 | |
449 #define V3_FRAME_BASE 0x01000000 | |
450 #define V3_SWAP_SW 0x00000000 | |
451 #define V3_SWAP_HW_HQV 0x02000000 | |
452 #define V3_FLIP_HW_CAPTURE0 0x04000000 | |
453 #define V3_FLIP_HW_CAPTURE1 0x06000000 | |
454 | |
455 /* V3_ALPHA_FETCH_COUNT 0x2B8 */ | |
456 #define V3_FETCH_COUNT 0x3ff00000 | |
457 #define ALPHA_FETCH_COUNT 0x000003ff | |
458 | |
459 /* HQV_CONTROL 0x3D0 */ | |
460 #define HQV_RGB32 0x00000000 | |
461 #define HQV_RGB16 0x20000000 | |
462 #define HQV_RGB15 0x30000000 | |
463 #define HQV_YUV422 0x80000000 | |
464 #define HQV_YUV420 0xC0000000 | |
465 #define HQV_ENABLE 0x08000000 | |
466 #define HQV_SRC_SW 0x00000000 | |
467 #define HQV_SRC_MC 0x01000000 | |
468 #define HQV_SRC_CAPTURE0 0x02000000 | |
469 #define HQV_SRC_CAPTURE1 0x03000000 | |
470 #define HQV_FLIP_EVEN 0x00000000 | |
471 #define HQV_FLIP_ODD 0x00000020 | |
472 #define HQV_SW_FLIP 0x00000010 /* Write 1 to flip HQV buffer */ | |
473 #define HQV_DEINTERLACE 0x00010000 /* First line of odd field will be repeated 3 times */ | |
474 #define HQV_FIELD_2_FRAME 0x00020000 /* Src is field. Display each line 2 times */ | |
475 #define HQV_FRAME_2_FIELD 0x00040000 /* Src is field. Display field */ | |
476 #define HQV_FRAME_UV 0x00000000 /* Src is Non-interleaved */ | |
477 #define HQV_FIELD_UV 0x00100000 /* Src is interleaved */ | |
478 #define HQV_IDLE 0x00000008 | |
479 #define HQV_FLIP_STATUS 0x00000001 | |
480 #define HQV_DOUBLE_BUFF 0x00000000 | |
481 #define HQV_TRIPLE_BUFF 0x04000000 | |
482 #define HQV_SUBPIC_FLIP 0x00008000 | |
483 #define HQV_FIFO_STATUS 0x00001000 | |
484 | |
485 /* HQV_FILTER_CONTROL 0x3E4 */ | |
486 #define HQV_H_LOWPASS_2TAP 0x00000001 | |
487 #define HQV_H_LOWPASS_4TAP 0x00000002 | |
488 #define HQV_H_LOWPASS_8TAP1 0x00000003 /* To be deleted */ | |
489 #define HQV_H_LOWPASS_8TAP2 0x00000004 /* To be deleted */ | |
490 #define HQV_H_HIGH_PASS 0x00000008 | |
491 #define HQV_H_LOW_PASS 0x00000000 | |
492 #define HQV_V_LOWPASS_2TAP 0x00010000 | |
493 #define HQV_V_LOWPASS_4TAP 0x00020000 | |
494 #define HQV_V_LOWPASS_8TAP1 0x00030000 | |
495 #define HQV_V_LOWPASS_8TAP2 0x00040000 | |
496 #define HQV_V_HIGH_PASS 0x00080000 | |
497 #define HQV_V_LOW_PASS 0x00000000 | |
498 #define HQV_H_HIPASS_F1_DEFAULT 0x00000040 | |
499 #define HQV_H_HIPASS_F2_DEFAULT 0x00000000 | |
500 #define HQV_V_HIPASS_F1_DEFAULT 0x00400000 | |
501 #define HQV_V_HIPASS_F2_DEFAULT 0x00000000 | |
502 #define HQV_H_HIPASS_F1_2TAP 0x00000050 | |
503 #define HQV_H_HIPASS_F2_2TAP 0x00000100 | |
504 #define HQV_V_HIPASS_F1_2TAP 0x00500000 | |
505 #define HQV_V_HIPASS_F2_2TAP 0x01000000 | |
506 #define HQV_H_HIPASS_F1_4TAP 0x00000060 | |
507 #define HQV_H_HIPASS_F2_4TAP 0x00000200 | |
508 #define HQV_V_HIPASS_F1_4TAP 0x00600000 | |
509 #define HQV_V_HIPASS_F2_4TAP 0x02000000 | |
510 #define HQV_H_HIPASS_F1_8TAP 0x00000080 | |
511 #define HQV_H_HIPASS_F2_8TAP 0x00000400 | |
512 #define HQV_V_HIPASS_F1_8TAP 0x00800000 | |
513 #define HQV_V_HIPASS_F2_8TAP 0x04000000 | |
514 /* IA2 NEW */ | |
515 #define HQV_V_FILTER2 0x00080000 | |
516 #define HQV_H_FILTER2 0x00000008 | |
517 #define HQV_H_TAP2_11 0x00000041 | |
518 #define HQV_H_TAP4_121 0x00000042 | |
519 #define HQV_H_TAP4_1111 0x00000401 | |
520 #define HQV_H_TAP8_1331 0x00000221 | |
521 #define HQV_H_TAP8_12221 0x00000402 | |
522 #define HQV_H_TAP16_1991 0x00000159 | |
523 #define HQV_H_TAP16_141041 0x0000026A | |
524 #define HQV_H_TAP32 0x0000015A | |
525 #define HQV_V_TAP2_11 0x00410000 | |
526 #define HQV_V_TAP4_121 0x00420000 | |
527 #define HQV_V_TAP4_1111 0x04010000 | |
528 #define HQV_V_TAP8_1331 0x02210000 | |
529 #define HQV_V_TAP8_12221 0x04020000 | |
530 #define HQV_V_TAP16_1991 0x01590000 | |
531 #define HQV_V_TAP16_141041 0x026A0000 | |
532 #define HQV_V_TAP32 0x015A0000 | |
533 #define HQV_V_FILTER_DEFAULT 0x00420000 | |
534 #define HQV_H_FILTER_DEFAULT 0x00000040 | |
535 | |
536 | |
537 | |
538 | |
539 /* HQV_MINI_CONTROL 0x3E8 */ | |
540 #define HQV_H_MINIFY_ENABLE 0x00000800 | |
541 #define HQV_V_MINIFY_ENABLE 0x08000000 | |
542 #define HQV_VDEBLOCK_FILTER 0x80000000 | |
543 #define HQV_HDEBLOCK_FILTER 0x00008000 | |
544 | |
545 | |
546 #define CHROMA_KEY_LOW 0x00FFFFFF | |
547 #define CHROMA_KEY_HIGH 0x00FFFFFF | |
548 | |
549 /* V_CAP_STATUS */ | |
550 #define V_ST_UPDATE_NOT_YET 0x00000003 | |
551 #define V1_ST_UPDATE_NOT_YET 0x00000001 | |
552 #define V3_ST_UPDATE_NOT_YET 0x00000008 | |
553 | |
554 #define VBI_STATUS 0x00000002 | |
555 | |
556 /* | |
557 * Macros for Video MMIO | |
558 */ | |
559 #ifndef V4L2 | |
560 #define VIDInB(port) *((volatile CARD8 *)(pVia->VidMapBase + (port))) | |
561 #define VIDInW(port) *((volatile CARD16 *)(pVia->VidMapBase + (port))) | |
562 #define VIDInD(port) *((volatile CARD32 *)(pVia->VidMapBase + (port))) | |
563 #define VIDOutB(port, data) *((volatile CARD8 *)(pVia->VidMapBase + (port))) = (data) | |
564 #define VIDOutW(port, data) *((volatile CARD16 *)(pVia->VidMapBase + (port))) = (data) | |
565 #define VIDOutD(port, data) *((volatile CARD32 *)(pVia->VidMapBase + (port))) = (data) | |
566 #define MPGOutD(port, data) *((volatile CARD32 *)(lpMPEGMMIO +(port))) = (data) | |
567 #define MPGInD(port) *((volatile CARD32 *)(lpMPEGMMIO +(port))) | |
568 #endif | |
569 | |
570 /* | |
571 * Macros for GE MMIO | |
572 */ | |
573 #define GEInW(port) *((volatile CARD16 *)(lpGEMMIO + (port))) | |
574 #define GEInD(port) *((volatile CARD32 *)(lpGEMMIO + (port))) | |
575 #define GEOutW(port, data) *((volatile CARD16 *)(lpGEMMIO + (port))) = (data) | |
576 #define GEOutD(port, data) *((volatile CARD32 *)(lpGEMMIO + (port))) = (data) | |
577 | |
578 /* | |
579 * MPEG 1/2 Slice Engine (at 0xC00 relative to base) | |
580 */ | |
581 | |
582 #define MPG_CONTROL 0x00 | |
583 #define MPG_CONTROL_STRUCT 0x03 | |
584 #define MPG_CONTROL_STRUCT_TOP 0x01 | |
585 #define MPG_CONTROL_STRUCT_BOTTOM 0x02 | |
586 #define MPG_CONTROL_STRUCT_FRAME 0x03 | |
587 /* Use TOP if interlaced */ | |
588 #define MPG_CONTROL_TYPE 0x3C | |
589 #define MPG_CONTROL_TYPE_I (0x01 << 2) | |
590 #define MPG_CONTROL_TYPE_B (0x02 << 2) | |
591 #define MPG_CONTROL_TYPE_P (0x03 << 3) | |
592 #define MPG_CONTROL_ALTSCAN 0x40 | |
593 #define MPG_BLOCK 0x08 /* Unsure */ | |
594 #define MPG_COMMAND 0x0C | |
595 #define MPG_DATA1 0x10 | |
596 #define MPG_DATA2 0x14 | |
597 #define MPG_DATA3 0x18 | |
598 #define MPG_DATA4 0x1C | |
599 | |
600 #define MPG_YPHYSICAL(x) (0x20 + 12*(x)) | |
601 #define MPG_CbPHYSICAL(x) (0x24 + 12*(x)) | |
602 #define MPG_CrPHYSICAL(x) (0x28 + 12*(x)) | |
603 | |
604 #define MPG_PITCH 0x50 | |
605 #define MPG_STATUS 0x54 | |
606 | |
607 #define MPG_MATRIX_IDX 0x5C | |
608 #define MPG_MATRIX_IDX_INTRA 0x00 | |
609 #define MPG_MATRIX_IDX_NON 0x01 | |
610 #define MPG_MATRIX_DATA 0x60 | |
611 | |
612 #define MPG_SLICE_CTRL_1 0x90 | |
613 #define MPG_SLICE_MBAMAX 0x2FFF | |
614 #define MPG_SLICE_PREDICTIVE_DCT 0x4000 | |
615 #define MPG_SLICE_TOP_FIRST 0x8000 | |
616 #define MPG_SLICE_MACROBLOCK_WIDTH(x) ((x)<<18) /* in 64's */ | |
617 #define MPG_SLICE_CTRL_2 0x94 | |
618 #define MPG_SLICE_CONCEAL_MVEC 0x0000001 | |
619 #define MPG_SLICE_QSCALE_TYPE 0x0000002 | |
620 #define MPG_SLICE_DCPRECISION 0x000000C | |
621 #define MPG_SLICE_MACROBQUOT 0x0FFFFF0 | |
622 #define MPG_SLICE_INTRAVLC 0x1000000 | |
623 #define MPG_SLICE_CTRL_3 0x98 | |
624 #define MPG_SLICE_FHMVR 0x0000003 | |
625 #define MPG_SLICE_FVMVR 0x000000C | |
626 #define MPG_SLICE_BHMVR 0x0000030 | |
627 #define MPG_SLICE_BVMVR 0x00000C0 | |
628 #define MPG_SLICE_SECOND_FIELD 0x0100000 | |
629 #define MPG_SLICE_RESET 0x0400000 | |
630 #define MPG_SLICE_LENGTH 0x9C | |
631 #define MPG_SLICE_DATA 0xA0 | |
632 | |
633 | |
634 | |
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635 #endif /* UNICHROME_REGS_H */ |