annotate vidix/sis_regs.h @ 34692:a3c178a46634

Remove pointless check that used internals would fail always after the switch to encode2.
author reimar
date Tue, 28 Feb 2012 19:31:56 +0000
parents 3abd1629658b
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 /*
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2 * SiS register definitions and access macros
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3 * From SiS X11 driver
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4 *
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5 * Copyright (C) 2001-2003 by Thomas Winischhofer, Vienna, Austria
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6 *
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7 * This file is part of MPlayer.
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8 *
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9 * MPlayer is free software; you can redistribute it and/or modify
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10 * it under the terms of the GNU General Public License as published by
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11 * the Free Software Foundation; either version 2 of the License, or
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12 * (at your option) any later version.
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13 *
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14 * MPlayer is distributed in the hope that it will be useful,
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15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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17 * GNU General Public License for more details.
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18 *
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19 * You should have received a copy of the GNU General Public License along
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20 * with MPlayer; if not, write to the Free Software Foundation, Inc.,
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21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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22 */
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23
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24 #ifndef MPLAYER_SIS_REGS_H
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25 #define MPLAYER_SIS_REGS_H
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26
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27 #define inSISREG(base) INPORT8(base)
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28 #define outSISREG(base,val) OUTPORT8(base, val)
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29 #define orSISREG(base,val) do { \
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30 unsigned char tmp = INPORT8(base); \
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31 outSISREG(base, tmp | (val)); \
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32 } while (0)
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33 #define andSISREG(base,val) do { \
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34 unsigned char tmp = INPORT8(base); \
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35 outSISREG(base, tmp & (val)); \
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36 } while (0)
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37
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38 #define inSISIDXREG(base,idx,var) do { \
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39 OUTPORT8(base, idx); var=INPORT8((base)+1); \
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40 } while (0)
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41 #define outSISIDXREG(base,idx,val) do { \
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42 OUTPORT8(base, idx); OUTPORT8((base)+1, val); \
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43 } while (0)
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44 #define orSISIDXREG(base,idx,val) do { \
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45 unsigned char tmp; \
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46 OUTPORT8(base, idx); \
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47 tmp = INPORT8((base)+1)|(val); \
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48 outSISIDXREG(base,idx,tmp); \
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49 } while (0)
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50 #define andSISIDXREG(base,idx,and) do { \
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51 unsigned char tmp; \
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52 OUTPORT8(base, idx); \
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53 tmp = INPORT8((base)+1)&(and); \
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54 outSISIDXREG(base,idx,tmp); \
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55 } while (0)
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56 #define setSISIDXREG(base,idx,and,or) do { \
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57 unsigned char tmp; \
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58 OUTPORT8(base, idx); \
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59 tmp = (INPORT8((base)+1)&(and))|(or); \
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60 outSISIDXREG(base,idx,tmp); \
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61 } while (0)
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62
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63 #define BITMASK(h,l) (((unsigned)(1U << ((h)-(l)+1))-1)<<(l))
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64 #define GENMASK(mask) BITMASK(1?mask,0?mask)
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65
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66 #define GETBITS(var,mask) (((var) & GENMASK(mask)) >> (0?mask))
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67 #define SETBITS(val,mask) ((val) << (0?mask))
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68 #define SETBIT(n) (1<<(n))
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69
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70 #define GETBITSTR(val,from,to) ((GETBITS(val,from)) << (0?to))
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71 #define SETVARBITS(var,val,from,to) (((var)&(~(GENMASK(to)))) | \
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72 GETBITSTR(val,from,to))
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73 #define GETVAR8(var) ((var)&0xFF)
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74 #define SETVAR8(var,val) (var) = GETVAR8(val)
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75
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76 /* #define VGA_RELIO_BASE 0x380 */
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77
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78 #define AROFFSET 0x40 /* VGA_ATTR_INDEX - VGA_RELIO_BASE */
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79 #define ARROFFSET 0x41 /* VGA_ATTR_DATA_R - VGA_RELIO_BASE */
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80 #define GROFFSET 0x4e /* VGA_GRAPH_INDEX - VGA_RELIO_BASE */
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81 #define SROFFSET 0x44 /* VGA_SEQ_INDEX - VGA_RELIO_BASE */
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82 #define CROFFSET 0x54 /* VGA_CRTC_INDEX_OFFSET + VGA_IOBASE_COLOR - VGA_RELIO_BASE */
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83 #define MISCROFFSET 0x4c /* VGA_MISC_OUT_R - VGA_RELIO_BASE */
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84 #define MISCWOFFSET 0x42 /* VGA_MISC_OUT_W - VGA_RELIO_BASE */
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85 #define INPUTSTATOFFSET 0x5A
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86 #define PART1OFFSET 0x04
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87 #define PART2OFFSET 0x10
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88 #define PART3OFFSET 0x12
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89 #define PART4OFFSET 0x14
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90 #define PART5OFFSET 0x16
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91 #define VIDEOOFFSET 0x02
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92 #define COLREGOFFSET 0x48
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93
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94 #define SIS_IOBASE sis_iobase /* var defined in sis_vid.c */
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95 #define SISAR SIS_IOBASE + AROFFSET
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96 #define SISARR SIS_IOBASE + ARROFFSET
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97 #define SISGR SIS_IOBASE + GROFFSET
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98 #define SISSR SIS_IOBASE + SROFFSET
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99 #define SISCR SIS_IOBASE + CROFFSET
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100 #define SISMISCR SIS_IOBASE + MISCROFFSET
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101 #define SISMISCW SIS_IOBASE + MISCWOFFSET
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102 #define SISINPSTAT SIS_IOBASE + INPUTSTATOFFSET
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103 #define SISPART1 SIS_IOBASE + PART1OFFSET
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104 #define SISPART2 SIS_IOBASE + PART2OFFSET
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105 #define SISPART3 SIS_IOBASE + PART3OFFSET
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106 #define SISPART4 SIS_IOBASE + PART4OFFSET
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107 #define SISPART5 SIS_IOBASE + PART5OFFSET
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108 #define SISVID SIS_IOBASE + VIDEOOFFSET
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109 #define SISCOLIDX SIS_IOBASE + COLREGOFFSET
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110 #define SISCOLDATA SIS_IOBASE + COLREGOFFSET + 1
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111 #define SISCOL2IDX SISPART5
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112 #define SISCOL2DATA SISPART5 + 1
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113
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114
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115 #define vc_index_offset 0x00 /* Video capture - unused */
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116 #define vc_data_offset 0x01
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117 #define vi_index_offset VIDEOOFFSET
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118 #define vi_data_offset (VIDEOOFFSET + 1)
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119 #define crt2_index_offset PART1OFFSET
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120 #define crt2_port_offset (PART1OFFSET + 1)
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121 #define sr_index_offset SROFFSET
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122 #define sr_data_offset (SROFFSET + 1)
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123 #define cr_index_offset CROFFSET
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124 #define cr_data_offset (CROFFSET + 1)
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125 #define input_stat INPUTSTATOFFSET
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126
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127 /* For old chipsets (5597/5598, 6326, 530/620) ------------ */
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128 /* SR (3C4) */
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129 #define BankReg 0x06
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130 #define ClockReg 0x07
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131 #define CPUThreshold 0x08
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132 #define CRTThreshold 0x09
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133 #define CRTCOff 0x0A
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134 #define DualBanks 0x0B
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135 #define MMIOEnable 0x0B
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136 #define RAMSize 0x0C
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137 #define Mode64 0x0C
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138 #define ExtConfStatus1 0x0E
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139 #define ClockBase 0x13
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140 #define LinearAdd0 0x20
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141 #define LinearAdd1 0x21
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142 #define GraphEng 0x27
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143 #define MemClock0 0x28
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144 #define MemClock1 0x29
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145 #define XR2A 0x2A
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146 #define XR2B 0x2B
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147 #define TurboQueueBase 0x2C
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148 #define FBSize 0x2F
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149 #define ExtMiscCont5 0x34
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150 #define ExtMiscCont9 0x3C
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151
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152 /* 3x4 */
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153 #define Offset 0x13
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154
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155 /* SiS Registers for 300, 540, 630, 730, 315, 550, 650, 740 */
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156
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157 /* VGA standard register */
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158 #define Index_SR_Graphic_Mode 0x06
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159 #define Index_SR_RAMDAC_Ctrl 0x07
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160 #define Index_SR_Threshold_Ctrl1 0x08
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161 #define Index_SR_Threshold_Ctrl2 0x09
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162 #define Index_SR_Misc_Ctrl 0x0F
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163 #define Index_SR_DDC 0x11
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164 #define Index_SR_Feature_Connector_Ctrl 0x12
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165 #define Index_SR_DRAM_Sizing 0x14
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166 #define Index_SR_DRAM_State_Machine_Ctrl 0x15
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167 #define Index_SR_AGP_PCI_State_Machine 0x21
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168 #define Index_SR_Internal_MCLK0 0x28
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169 #define Index_SR_Internal_MCLK1 0x29
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170 #define Index_SR_Internal_DCLK1 0x2B
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171 #define Index_SR_Internal_DCLK2 0x2C
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172 #define Index_SR_Internal_DCLK3 0x2D
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173 #define Index_SR_Ext_Clock_Sel 0x32
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174 #define Index_SR_Int_Status 0x34
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175 #define Index_SR_Int_Enable 0x35
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176 #define Index_SR_Int_Reset 0x36
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177 #define Index_SR_Power_On_Trap 0x38
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178 #define Index_SR_Power_On_Trap2 0x39
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179 #define Index_SR_Power_On_Trap3 0x3A
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180
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181 /* video registers (300/630/730/315/550/650/740 only) */
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182 #define Index_VI_Passwd 0x00
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183
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184 /* Video overlay horizontal start/end, unit=screen pixels */
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185 #define Index_VI_Win_Hor_Disp_Start_Low 0x01
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186 #define Index_VI_Win_Hor_Disp_End_Low 0x02
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187 #define Index_VI_Win_Hor_Over 0x03 /* Overflow */
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188
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189 /* Video overlay vertical start/end, unit=screen pixels */
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190 #define Index_VI_Win_Ver_Disp_Start_Low 0x04
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191 #define Index_VI_Win_Ver_Disp_End_Low 0x05
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192 #define Index_VI_Win_Ver_Over 0x06 /* Overflow */
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193
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194 /* Y Plane (4:2:0) or YUV (4:2:2) buffer start address, unit=word */
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195 #define Index_VI_Disp_Y_Buf_Start_Low 0x07
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196 #define Index_VI_Disp_Y_Buf_Start_Middle 0x08
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197 #define Index_VI_Disp_Y_Buf_Start_High 0x09
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198
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199 /* U Plane (4:2:0) buffer start address, unit=word */
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200 #define Index_VI_U_Buf_Start_Low 0x0A
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201 #define Index_VI_U_Buf_Start_Middle 0x0B
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202 #define Index_VI_U_Buf_Start_High 0x0C
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203
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204 /* V Plane (4:2:0) buffer start address, unit=word */
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205 #define Index_VI_V_Buf_Start_Low 0x0D
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206 #define Index_VI_V_Buf_Start_Middle 0x0E
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207 #define Index_VI_V_Buf_Start_High 0x0F
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208
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209 /* Pitch for Y, UV Planes, unit=word */
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210 #define Index_VI_Disp_Y_Buf_Pitch_Low 0x10
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211 #define Index_VI_Disp_UV_Buf_Pitch_Low 0x11
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212 #define Index_VI_Disp_Y_UV_Buf_Pitch_Middle 0x12
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213
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214 /* What is this ? */
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215 #define Index_VI_Disp_Y_Buf_Preset_Low 0x13
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216 #define Index_VI_Disp_Y_Buf_Preset_Middle 0x14
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217
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218 #define Index_VI_UV_Buf_Preset_Low 0x15
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219 #define Index_VI_UV_Buf_Preset_Middle 0x16
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220 #define Index_VI_Disp_Y_UV_Buf_Preset_High 0x17
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221
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222 /* Scaling control registers */
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223 #define Index_VI_Hor_Post_Up_Scale_Low 0x18
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224 #define Index_VI_Hor_Post_Up_Scale_High 0x19
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225 #define Index_VI_Ver_Up_Scale_Low 0x1A
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226 #define Index_VI_Ver_Up_Scale_High 0x1B
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227 #define Index_VI_Scale_Control 0x1C
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228
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229 /* Playback line buffer control */
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230 #define Index_VI_Play_Threshold_Low 0x1D
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231 #define Index_VI_Play_Threshold_High 0x1E
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232 #define Index_VI_Line_Buffer_Size 0x1F
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233
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234 /* Destination color key */
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235 #define Index_VI_Overlay_ColorKey_Red_Min 0x20
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236 #define Index_VI_Overlay_ColorKey_Green_Min 0x21
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237 #define Index_VI_Overlay_ColorKey_Blue_Min 0x22
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238 #define Index_VI_Overlay_ColorKey_Red_Max 0x23
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239 #define Index_VI_Overlay_ColorKey_Green_Max 0x24
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240 #define Index_VI_Overlay_ColorKey_Blue_Max 0x25
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241
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242 /* Source color key, YUV color space */
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243 #define Index_VI_Overlay_ChromaKey_Red_Y_Min 0x26
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244 #define Index_VI_Overlay_ChromaKey_Green_U_Min 0x27
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245 #define Index_VI_Overlay_ChromaKey_Blue_V_Min 0x28
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246 #define Index_VI_Overlay_ChromaKey_Red_Y_Max 0x29
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247 #define Index_VI_Overlay_ChromaKey_Green_U_Max 0x2A
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248 #define Index_VI_Overlay_ChromaKey_Blue_V_Max 0x2B
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249
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250 /* Contrast enhancement and brightness control */
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251 #define Index_VI_Contrast_Factor 0x2C /* obviously unused/undefined */
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252 #define Index_VI_Brightness 0x2D
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253 #define Index_VI_Contrast_Enh_Ctrl 0x2E
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254
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255 #define Index_VI_Key_Overlay_OP 0x2F
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256
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257 #define Index_VI_Control_Misc0 0x30
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258 #define Index_VI_Control_Misc1 0x31
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259 #define Index_VI_Control_Misc2 0x32
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260
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261 /* TW: Subpicture registers */
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262 #define Index_VI_SubPict_Buf_Start_Low 0x33
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263 #define Index_VI_SubPict_Buf_Start_Middle 0x34
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264 #define Index_VI_SubPict_Buf_Start_High 0x35
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265
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266 /* TW: What is this ? */
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267 #define Index_VI_SubPict_Buf_Preset_Low 0x36
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268 #define Index_VI_SubPict_Buf_Preset_Middle 0x37
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269
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270 /* TW: Subpicture pitch, unit=16 bytes */
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271 #define Index_VI_SubPict_Buf_Pitch 0x38
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272
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273 /* TW: Subpicture scaling control */
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274 #define Index_VI_SubPict_Hor_Scale_Low 0x39
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275 #define Index_VI_SubPict_Hor_Scale_High 0x3A
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276 #define Index_VI_SubPict_Vert_Scale_Low 0x3B
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277 #define Index_VI_SubPict_Vert_Scale_High 0x3C
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278
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279 #define Index_VI_SubPict_Scale_Control 0x3D
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280 /* (0x40 = enable/disable subpicture) */
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281
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282 /* TW: Subpicture line buffer control */
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283 #define Index_VI_SubPict_Threshold 0x3E
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284
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285 /* TW: What is this? */
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286 #define Index_VI_FIFO_Max 0x3F
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287
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288 /* TW: Subpicture palette; 16 colors, total 32 bytes address space */
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289 #define Index_VI_SubPict_Pal_Base_Low 0x40
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290 #define Index_VI_SubPict_Pal_Base_High 0x41
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291
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292 /* I wish I knew how to use these ... */
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293 #define Index_MPEG_Read_Ctrl0 0x60 /* MPEG auto flip */
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294 #define Index_MPEG_Read_Ctrl1 0x61 /* MPEG auto flip */
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295 #define Index_MPEG_Read_Ctrl2 0x62 /* MPEG auto flip */
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296 #define Index_MPEG_Read_Ctrl3 0x63 /* MPEG auto flip */
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297
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298 /* TW: MPEG AutoFlip scale */
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299 #define Index_MPEG_Ver_Up_Scale_Low 0x64
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300 #define Index_MPEG_Ver_Up_Scale_High 0x65
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301
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302 #define Index_MPEG_Y_Buf_Preset_Low 0x66
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303 #define Index_MPEG_Y_Buf_Preset_Middle 0x67
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304 #define Index_MPEG_UV_Buf_Preset_Low 0x68
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305 #define Index_MPEG_UV_Buf_Preset_Middle 0x69
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306 #define Index_MPEG_Y_UV_Buf_Preset_High 0x6A
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307
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308 /* TW: The following registers only exist on the 310/325 series */
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309
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310 /* TW: Bit 16:24 of Y_U_V buf start address (?) */
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311 #define Index_VI_Y_Buf_Start_Over 0x6B
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312 #define Index_VI_U_Buf_Start_Over 0x6C
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313 #define Index_VI_V_Buf_Start_Over 0x6D
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314
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315 #define Index_VI_Disp_Y_Buf_Pitch_High 0x6E
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316 #define Index_VI_Disp_UV_Buf_Pitch_High 0x6F
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317
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318 /* Hue and saturation */
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319 #define Index_VI_Hue 0x70
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320 #define Index_VI_Saturation 0x71
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321
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322 #define Index_VI_SubPict_Start_Over 0x72
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323 #define Index_VI_SubPict_Buf_Pitch_High 0x73
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324
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325 #define Index_VI_Control_Misc3 0x74
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326
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327
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328 /* TW: Bits (and helpers) for Index_VI_Control_Misc0 */
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329 #define VI_Misc0_Enable_Overlay 0x02
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330 #define VI_Misc0_420_Plane_Enable 0x04 /* Select Plane or Packed mode */
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331 #define VI_Misc0_422_Enable 0x20 /* Select 422 or 411 mode */
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332 #define VI_Misc0_Fmt_YVU420P 0x0C /* YUV420 Planar (I420, YV12) */
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333 #define VI_Misc0_Fmt_YUYV 0x28 /* YUYV Packed (YUY2) */
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334 #define VI_Misc0_Fmt_UYVY 0x08 /* (UYVY) */
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335
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336 /* TW: Bits for Index_VI_Control_Misc1 */
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337 /* #define VI_Misc1_? 0x01 */
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338 #define VI_Misc1_BOB_Enable 0x02
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339 #define VI_Misc1_Line_Merge 0x04
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340 #define VI_Misc1_Field_Mode 0x08
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341 /* #define VI_Misc1_? 0x10 */
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342 #define VI_Misc1_Non_Interleave 0x20 /* 300 series only? */
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343 #define VI_Misc1_Buf_Addr_Lock 0x20 /* 310 series only? */
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344 /* #define VI_Misc1_? 0x40 */
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345 /* #define VI_Misc1_? 0x80 */
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346
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347 /* TW: Bits for Index_VI_Control_Misc2 */
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348 #define VI_Misc2_Select_Video2 0x01
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349 #define VI_Misc2_Video2_On_Top 0x02
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350 /* #define VI_Misc2_? 0x04 */
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351 #define VI_Misc2_Vertical_Interpol 0x08
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352 #define VI_Misc2_Dual_Line_Merge 0x10
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353 #define VI_Misc2_All_Line_Merge 0x20 /* 310 series only? */
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354 #define VI_Misc2_Auto_Flip_Enable 0x40 /* 300 series only? */
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355 #define VI_Misc2_Video_Reg_Write_Enable 0x80 /* 310 series only? */
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356
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357 /* TW: Bits for Index_VI_Control_Misc3 */
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358 #define VI_Misc3_Submit_Video_1 0x01 /* AKA "address ready" */
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359 #define VI_Misc3_Submit_Video_2 0x02 /* AKA "address ready" */
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360 #define VI_Misc3_Submit_SubPict 0x04 /* AKA "address ready" */
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361
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362 /* TW: Values for Index_VI_Key_Overlay_OP (0x2F) */
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363 #define VI_ROP_Never 0x00
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364 #define VI_ROP_DestKey 0x03
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365 #define VI_ROP_Always 0x0F
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366
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367 /*
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368 * CRT_2 function control register ---------------------------------
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369 */
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370 #define Index_CRT2_FC_CONTROL 0x00
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371 #define Index_CRT2_FC_SCREEN_HIGH 0x04
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372 #define Index_CRT2_FC_SCREEN_MID 0x05
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373 #define Index_CRT2_FC_SCREEN_LOW 0x06
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374 #define Index_CRT2_FC_ENABLE_WRITE 0x24
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375 #define Index_CRT2_FC_VR 0x25
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376 #define Index_CRT2_FC_VCount 0x27
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377 #define Index_CRT2_FC_VCount1 0x28
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378
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379 #define Index_310_CRT2_FC_VR 0x30 /* d[1] = vertical retrace */
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380 #define Index_310_CRT2_FC_RT 0x33 /* d[7] = retrace in progress */
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381
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382 /* video attributes - these should probably be configurable on the fly
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383 * so users with different desktop sizes can keep
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384 * captured data off the desktop
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385 */
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386 #define VINWID 704
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387 #define VINHGT VINHGT_NTSC
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388 #define VINHGT_NTSC 240
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389 #define VINHGT_PAL 290
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390 #define VIN_WINDOW (704 * 291 * 2)
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391 #define VBI_WINDOW (704 * 64 * 2)
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392
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393 #define VIN_FIELD_EVEN 1
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394 #define VIN_FIELD_ODD 2
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395 #define VIN_FIELD_BOTH 4
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396
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397
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398 /* i2c registers (TW; not on 300/310/325 series) */
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399 #define X_INDEXREG 0x14
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400 #define X_PORTREG 0x15
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401 #define X_DATA 0x0f
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402 #define I2C_SCL 0x00
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403 #define I2C_SDA 0x01
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404 #define I2C_DELAY 10
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405
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406 /* mmio registers for video */
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407 #define REG_PRIM_CRT_COUNTER 0x8514
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408
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409 /* TW: MPEG MMIO registers (630 and later) ----------------------------*/
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410
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411 /* Not public (yet?) */
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412
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413 #endif /* MPLAYER_SIS_REGS_H */