Mercurial > mplayer.hg
annotate vidix/nvidia_vid.c @ 23510:a6c619ee9d30
Teletext support for tv:// (v4l and v4l2 only)
modified patch from Otvos Attila oattila at chello dot hu
Module uses zvbi library for all low-level VBI operations (like I/O with vbi
device, converting vbi pages into usefull vbi_page stuctures, rendering them
into RGB32 images).
All teletext related stuff (except properties, slave commands and rendering
osd in text mode or RGB32 rendered teletext pages in spu mode) is implemented
in tvi_vbi.c
New properties:
teletext_page - switching between pages
teletext_mode - switch between on/off/opaque/transparent modes
teletext_format - (currently read-only) allows to get format info
(black/white,gray,text)
teletext_half_page - trivial zooming (displaying top/bottom half of teletext
page)
New slave commands:
teletext_add_dec - user interface for jumping to any page by editing page number
interactively
teletext_go_link - goes though links, specified on current page
author | voroshil |
---|---|
date | Sun, 10 Jun 2007 00:06:12 +0000 |
parents | 91ad6d4d6a54 |
children | ee2cf48d6659 |
rev | line source |
---|---|
22850 | 1 /* |
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2 * VIDIX driver for nVidia chipsets. |
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3 * Copyright (C) 2003-2004 Sascha Sommer |
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4 * |
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5 * This file is part of MPlayer. |
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6 * |
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7 * MPlayer is free software; you can redistribute it and/or modify |
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8 * it under the terms of the GNU General Public License as published by |
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9 * the Free Software Foundation; either version 2 of the License, or |
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10 * (at your option) any later version. |
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11 * |
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12 * MPlayer is distributed in the hope that it will be useful, |
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 * GNU General Public License for more details. |
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16 * |
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17 * You should have received a copy of the GNU General Public License |
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18 * along with MPlayer; if not, write to the Free Software |
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19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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20 * |
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21 * This file is based on sources from RIVATV (rivatv.sf.net) |
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22 * Multi buffer support and TNT2 fixes by Dmitry Baryshkov. |
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23 */ |
22850 | 24 |
25 #include <errno.h> | |
26 #include <stdio.h> | |
27 #include <stdlib.h> | |
28 #include <string.h> | |
29 #include <math.h> | |
30 #include <inttypes.h> | |
31 #include <unistd.h> | |
32 | |
33 | |
34 #include "vidix.h" | |
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35 #include "vidixlib.h" |
22850 | 36 #include "fourcc.h" |
22901 | 37 #include "dha.h" |
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38 #include "pci_ids.h" |
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39 #include "pci_names.h" |
22905 | 40 #include "config.h" |
41 #include "libavutil/common.h" | |
42 #include "mpbswap.h" | |
22850 | 43 |
44 | |
23055 | 45 static pciinfo_t pci_info; |
22850 | 46 |
47 | |
48 #define MAX_FRAMES 3 | |
49 #define NV04_BES_SIZE 1024*2000*4 | |
50 | |
51 | |
52 static vidix_capability_t nvidia_cap = { | |
53 "NVIDIA RIVA OVERLAY DRIVER", | |
54 "Sascha Sommer <saschasommer@freenet.de>", | |
55 TYPE_OUTPUT, | |
56 { 0, 0, 0, 0 }, | |
57 2046, | |
58 2046, | |
59 4, | |
60 4, | |
61 -1, | |
62 FLAG_UPSCALER|FLAG_DOWNSCALER, | |
63 VENDOR_NVIDIA2, | |
64 -1, | |
65 { 0, 0, 0, 0 } | |
66 }; | |
67 | |
68 #define NV_ARCH_03 0x03 | |
69 #define NV_ARCH_04 0x04 | |
70 #define NV_ARCH_10 0x10 | |
71 #define NV_ARCH_20 0x20 | |
72 #define NV_ARCH_30 0x30 | |
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73 #define NV_ARCH_40 0x40 |
22850 | 74 |
75 // since no useful information whatsoever is passed | |
76 // to the equalizer functions we need this | |
77 static struct { | |
78 uint32_t lum; // luminance (brightness + contrast) | |
79 uint32_t chrom; // chrominance (saturation + hue) | |
80 uint8_t red_off; // for NV03/NV04 | |
81 uint8_t green_off; | |
82 uint8_t blue_off; | |
83 vidix_video_eq_t vals; | |
84 } eq; | |
85 | |
86 struct nvidia_cards { | |
87 unsigned short chip_id; | |
88 unsigned short arch; | |
89 }; | |
90 | |
91 | |
92 static struct nvidia_cards nvidia_card_ids[] = { | |
93 /*NV03*/ | |
94 {DEVICE_NVIDIA2_RIVA128, NV_ARCH_03}, | |
95 {DEVICE_NVIDIA2_RIVA128ZX,NV_ARCH_03}, | |
96 /*NV04*/ | |
97 {DEVICE_NVIDIA_NV4_RIVA_TNT,NV_ARCH_04}, | |
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98 {DEVICE_NVIDIA_NV5_RIVA_TNT2_TNT2,NV_ARCH_04}, |
22850 | 99 {DEVICE_NVIDIA_NV5_RIVA_TNT2,NV_ARCH_04}, |
100 {DEVICE_NVIDIA_NV5_RIVA_TNT22,NV_ARCH_04}, | |
101 {DEVICE_NVIDIA_NV5_RIVA_TNT23,NV_ARCH_04}, | |
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102 {DEVICE_NVIDIA_NV6_VANTA_VANTA_LT,NV_ARCH_04}, |
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103 {DEVICE_NVIDIA_NV5M64_RIVA_TNT2,NV_ARCH_04}, |
22850 | 104 {DEVICE_NVIDIA_NV6_VANTA,NV_ARCH_04}, |
105 {DEVICE_NVIDIA_NV6_VANTA2,NV_ARCH_04}, | |
106 {DEVICE_NVIDIA2_TNT,NV_ARCH_04}, | |
107 {DEVICE_NVIDIA2_TNT2,NV_ARCH_04}, | |
108 {DEVICE_NVIDIA2_VTNT2,NV_ARCH_04}, | |
109 {DEVICE_NVIDIA2_UTNT2 ,NV_ARCH_04}, | |
110 {DEVICE_NVIDIA2_ITNT2,NV_ARCH_04}, | |
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111 {DEVICE_NVIDIA_NV5_ALADDIN_TNT2,NV_ARCH_04}, |
22850 | 112 /*NV10*/ |
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113 {DEVICE_NVIDIA_NV18_GEFORCE_PCX,NV_ARCH_10}, |
22850 | 114 {DEVICE_NVIDIA_NV10_GEFORCE_256,NV_ARCH_10}, |
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115 {DEVICE_NVIDIA_NV10DDR_GEFORCE_256,NV_ARCH_10}, |
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116 {DEVICE_NVIDIA_NV10GL_QUADRO,NV_ARCH_10}, |
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117 {DEVICE_NVIDIA_NV11_GEFORCE2_MX_MX,NV_ARCH_10}, |
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118 {DEVICE_NVIDIA_NV11DDR_GEFORCE2_MX,NV_ARCH_10}, |
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119 {DEVICE_NVIDIA_NV11DDR_GEFORCE2_MX,NV_ARCH_10}, |
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120 {DEVICE_NVIDIA_NV11_GEFORCE2_GO,NV_ARCH_10}, |
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121 {DEVICE_NVIDIA_NV11GL_QUADRO2_MXR_EX_GO,NV_ARCH_10}, |
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122 {DEVICE_NVIDIA_NV15_GEFORCE2_GTS_PRO,NV_ARCH_10}, |
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123 {DEVICE_NVIDIA_NV15DDR_GEFORCE2_TI,NV_ARCH_10}, |
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124 {DEVICE_NVIDIA_NV15BR_GEFORCE2_ULTRA,NV_ARCH_10}, |
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125 {DEVICE_NVIDIA_NV15GL_QUADRO2_PRO,NV_ARCH_10}, |
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126 {DEVICE_NVIDIA_NV17_GEFORCE4_MX,NV_ARCH_10}, |
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127 {DEVICE_NVIDIA_NV17_GEFORCE4_MX2,NV_ARCH_10}, |
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128 {DEVICE_NVIDIA_NV17_GEFORCE4_MX3,NV_ARCH_10}, |
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129 {DEVICE_NVIDIA_NV17_GEFORCE4_MX4,NV_ARCH_10}, |
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130 {DEVICE_NVIDIA_NV17_GEFORCE4_440,NV_ARCH_10}, |
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131 {DEVICE_NVIDIA_NV17_GEFORCE4_420,NV_ARCH_10}, |
22850 | 132 {DEVICE_NVIDIA_NV17_GEFORCE4_4202,NV_ARCH_10}, |
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133 {DEVICE_NVIDIA_NV17_GEFORCE4_460,NV_ARCH_10}, |
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134 {DEVICE_NVIDIA_NV17GL_QUADRO4_550,NV_ARCH_10}, |
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135 {DEVICE_NVIDIA_NV17_GEFORCE4_4203,NV_ARCH_10}, |
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136 {DEVICE_NVIDIA_NV17GL_QUADRO4_200_400,NV_ARCH_10}, |
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137 {DEVICE_NVIDIA_NV17GL_QUADRO4_5502,NV_ARCH_10}, |
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138 {DEVICE_NVIDIA_NV17GL_QUADRO4_550,NV_ARCH_10}, |
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139 {DEVICE_NVIDIA_NV17_GEFORCE4_410,NV_ARCH_10}, |
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140 {DEVICE_NVIDIA_NV18_GEFORCE4_MX,NV_ARCH_10}, |
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141 {DEVICE_NVIDIA_NV18_GEFORCE4_MX2,NV_ARCH_10}, |
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142 {DEVICE_NVIDIA_NV18_GEFORCE4_MX3,NV_ARCH_10}, |
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143 {DEVICE_NVIDIA_NV18_GEFORCE4_MX4,NV_ARCH_10}, |
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144 {DEVICE_NVIDIA_NV18_GEFORCE4_MX5,NV_ARCH_10}, |
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145 {DEVICE_NVIDIA_NV18M_GEFORCE4_448,NV_ARCH_10}, |
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146 {DEVICE_NVIDIA_NV18M_GEFORCE4_488,NV_ARCH_10}, |
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147 {DEVICE_NVIDIA_NV18GL_QUADRO_FX,NV_ARCH_10}, |
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148 {DEVICE_NVIDIA_NV18GL_QUADRO4_580,NV_ARCH_10}, |
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149 {DEVICE_NVIDIA_NV18GL_QUADRO4_NVS,NV_ARCH_10}, |
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150 {DEVICE_NVIDIA_NV18GL_QUADRO4_380,NV_ARCH_10}, |
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151 {DEVICE_NVIDIA_NV18M_GEFORCE4_4482,NV_ARCH_10}, |
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152 {DEVICE_NVIDIA_NVCRUSH11_GEFORCE2_MX,NV_ARCH_10}, |
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153 {DEVICE_NVIDIA_NV18_GEFORCE4_MX5,NV_ARCH_10}, |
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154 {DEVICE_NVIDIA_NV18_GEFORCE_PCX,NV_ARCH_10}, |
22850 | 155 /*NV20*/ |
156 {DEVICE_NVIDIA_NV20_GEFORCE3,NV_ARCH_20}, | |
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157 {DEVICE_NVIDIA_NV20_GEFORCE3_TI,NV_ARCH_20}, |
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158 {DEVICE_NVIDIA_NV20_GEFORCE3_TI2,NV_ARCH_20}, |
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159 {DEVICE_NVIDIA_NV20DCC_QUADRO_DCC,NV_ARCH_20}, |
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160 {DEVICE_NVIDIA_NV25_GEFORCE4_TI,NV_ARCH_20}, |
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161 {DEVICE_NVIDIA_NV25_GEFORCE4_TI2,NV_ARCH_20}, |
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162 {DEVICE_NVIDIA_NV25_GEFORCE4_TI3,NV_ARCH_20}, |
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163 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4,NV_ARCH_20}, |
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164 {DEVICE_NVIDIA_NV25GL_QUADRO4_900,NV_ARCH_20}, |
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165 {DEVICE_NVIDIA_NV25GL_QUADRO4_750,NV_ARCH_20}, |
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166 {DEVICE_NVIDIA_NV25GL_QUADRO4_700,NV_ARCH_20}, |
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167 {DEVICE_NVIDIA_NV28_GEFORCE4_TI,NV_ARCH_20}, |
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168 {DEVICE_NVIDIA_NV28_GEFORCE4_TI2,NV_ARCH_20}, |
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169 {DEVICE_NVIDIA_NV28_GEFORCE4_TI3,NV_ARCH_20}, |
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170 {DEVICE_NVIDIA_NV28_GEFORCE4_TI4,NV_ARCH_20}, |
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171 {DEVICE_NVIDIA_NV28GL_QUADRO4_980,NV_ARCH_20}, |
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172 {DEVICE_NVIDIA_NV28GL_QUADRO4_780,NV_ARCH_20}, |
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|
173 {DEVICE_NVIDIA_NV28GLM_QUADRO4_700,NV_ARCH_20}, |
22850 | 174 /*NV30*/ |
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|
175 {DEVICE_NVIDIA_NV30_GEFORCE_FX,NV_ARCH_30}, |
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changeset
|
176 {DEVICE_NVIDIA_NV30_GEFORCE_FX2,NV_ARCH_30}, |
9a8f6901e888
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changeset
|
177 {DEVICE_NVIDIA_NV30_GEFORCE_FX3,NV_ARCH_30}, |
9a8f6901e888
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changeset
|
178 {DEVICE_NVIDIA_NV30GL_QUADRO_FX,NV_ARCH_30}, |
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changeset
|
179 {DEVICE_NVIDIA_NV30GL_QUADRO_FX2,NV_ARCH_30}, |
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changeset
|
180 {DEVICE_NVIDIA_NV31_GEFORCE_FX,NV_ARCH_30}, |
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changeset
|
181 {DEVICE_NVIDIA_NV31_GEFORCE_FX2,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
182 {DEVICE_NVIDIA_NV31,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
183 {DEVICE_NVIDIA_NV31_GEFORCE_FX3,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
184 {DEVICE_NVIDIA_NV31M,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
185 {DEVICE_NVIDIA_NV31M_PRO,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
186 {DEVICE_NVIDIA_NV31M_GEFORCE_FX,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
187 {DEVICE_NVIDIA_NV31M_GEFORCE_FX2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
188 {DEVICE_NVIDIA_NVIDIA_QUADRO_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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|
189 {DEVICE_NVIDIA_NV31GLM,NV_ARCH_30}, |
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|
190 {DEVICE_NVIDIA_NV31GLM_PRO,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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|
191 {DEVICE_NVIDIA_NV31GLM_PRO2,NV_ARCH_30}, |
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|
192 {DEVICE_NVIDIA_NV34_GEFORCE_FX,NV_ARCH_30}, |
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|
193 {DEVICE_NVIDIA_NV34_GEFORCE_FX2,NV_ARCH_30}, |
22850 | 194 {DEVICE_NVIDIA_NV34_GEFORCE_FX3,NV_ARCH_30}, |
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|
195 {DEVICE_NVIDIA_NV34_GEFORCE_FX4,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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|
196 {DEVICE_NVIDIA_NV34M_GEFORCE_FX,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
197 {DEVICE_NVIDIA_NV34M_GEFORCE_FX2,NV_ARCH_30}, |
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|
198 {DEVICE_NVIDIA_NV34_GEFORCE_FX5,NV_ARCH_30}, |
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|
199 {DEVICE_NVIDIA_NV34_GEFORCE_FX6,NV_ARCH_30}, |
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changeset
|
200 {DEVICE_NVIDIA_NV34M_GEFORCE_FX3,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
201 {DEVICE_NVIDIA_NV34M_GEFORCE_FX4,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
202 {DEVICE_NVIDIA_NV34GL_QUADRO_NVS,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
203 {DEVICE_NVIDIA_NV34GL_QUADRO_FX,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
204 {DEVICE_NVIDIA_NV34GLM_GEFORCE_FX,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
205 {DEVICE_NVIDIA_NV34_GEFORCE_FX7,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
206 {DEVICE_NVIDIA_NV34GL,NV_ARCH_30}, |
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parents:
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changeset
|
207 {DEVICE_NVIDIA_NV35_GEFORCE_FX,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
208 {DEVICE_NVIDIA_NV35_GEFORCE_FX2,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
209 {DEVICE_NVIDIA_NV35_GEFORCE_FX3,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
210 {DEVICE_NVIDIA_NV38_GEFORCE_FX,NV_ARCH_30}, |
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parents:
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changeset
|
211 {DEVICE_NVIDIA_NV35_GEFORCE_FX4,NV_ARCH_30}, |
22850 | 212 {DEVICE_NVIDIA_NV35GL_QUADRO_FX,NV_ARCH_30}, |
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changeset
|
213 {DEVICE_NVIDIA_NV35GL_QUADRO_FX2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
214 {DEVICE_NVIDIA_NV35_GEFORCE_PCX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
215 {DEVICE_NVIDIA_NV36_1_GEFORCE_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
216 {DEVICE_NVIDIA_NV36_2_GEFORCE_FX,NV_ARCH_30}, |
22850 | 217 {DEVICE_NVIDIA_NV36_GEFORCE_FX,NV_ARCH_30}, |
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changeset
|
218 {DEVICE_NVIDIA_NV36_4_GEFORCE_FX,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
219 {DEVICE_NVIDIA_NV36_5,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
220 {DEVICE_NVIDIA_NV36_GEFORCE_FX2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
221 {DEVICE_NVIDIA_NV36_GEFORCE_FX3,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
222 {DEVICE_NVIDIA_NV36_GEFORCE_PCX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
223 {DEVICE_NVIDIA_NV36M_PRO,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
224 {DEVICE_NVIDIA_NV36MAP,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
225 {DEVICE_NVIDIA_NV36_QUADRO_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
226 {DEVICE_NVIDIA_NV36GL_QUADRO_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
227 {DEVICE_NVIDIA_NV36GL,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
228 {DEVICE_NVIDIA_NV36_GEFORCE_PCX,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
229 {DEVICE_NVIDIA_NV35_GEFORCE_PCX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
230 {DEVICE_NVIDIA_NV37GL_QUADRO_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
231 {DEVICE_NVIDIA_NV37GL_QUADRO_FX2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
232 {DEVICE_NVIDIA_NV38GL_QUADRO_FX,NV_ARCH_30}, |
22880
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
233 /* NV40: GeForce 6x00 to 7x00 */ |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
234 {DEVICE_NVIDIA_NV40_GEFORCE_6800,NV_ARCH_40}, |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
235 {DEVICE_NVIDIA_NV40_GEFORCE_68002,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
236 {DEVICE_NVIDIA_NV40_2_GEFORCE_6800,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
237 {DEVICE_NVIDIA_NV40_3,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
238 {DEVICE_NVIDIA_NV40_GEFORCE_68003,NV_ARCH_40}, |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
239 {DEVICE_NVIDIA_NV40_GEFORCE_68004,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
240 {DEVICE_NVIDIA_NV40_GEFORCE_68005,NV_ARCH_40}, |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
241 {DEVICE_NVIDIA_NV40_GEFORCE_68006,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
242 {DEVICE_NVIDIA_NV40_GEFORCE_68007,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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changeset
|
243 {DEVICE_NVIDIA_NV40_GEFORCE_68008,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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changeset
|
244 {DEVICE_NVIDIA_NV40_GEFORCE_68009,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
245 {DEVICE_NVIDIA_NV40_GEFORCE_680010,NV_ARCH_40}, |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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changeset
|
246 {DEVICE_NVIDIA_NV40_GEFORCE_680011,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
247 {DEVICE_NVIDIA_NV40_GEFORCE_680012,NV_ARCH_40}, |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
248 {DEVICE_NVIDIA_NV40_GEFORCE_68008,NV_ARCH_40}, |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
249 {DEVICE_NVIDIA_NV40GL,NV_ARCH_40}, |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
250 {DEVICE_NVIDIA_NV40GL_QUADRO_FX,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
251 {DEVICE_NVIDIA_NV40GL_QUADRO_FX2,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
252 {DEVICE_NVIDIA_NV41_GEFORCE_6800,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
253 {DEVICE_NVIDIA_NV41_1_GEFORCE_6800,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
254 {DEVICE_NVIDIA_NV41_2_GEFORCE_6800,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
255 {DEVICE_NVIDIA_NV41_8_GEFORCE_GO,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
256 {DEVICE_NVIDIA_NV41_9_GEFORCE_GO,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
257 {DEVICE_NVIDIA_NV41_QUADRO_FX,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
258 {DEVICE_NVIDIA_NV41_QUADRO_FX2,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
259 {DEVICE_NVIDIA_NV41GL_QUADRO_FX,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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changeset
|
260 {DEVICE_NVIDIA_NV41GL_QUADRO_FX,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
261 {DEVICE_NVIDIA_NV40_GEFORCE_6800_GEFORCE,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
262 {DEVICE_NVIDIA_NV43_GEFORCE_6600_GEFORCE,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
263 {DEVICE_NVIDIA_NV43_GEFORCE_6600_GEFORCE2,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
264 {DEVICE_NVIDIA_NV43_GEFORCE_6200,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
265 {DEVICE_NVIDIA_NV43_GEFORCE_62002,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
266 {DEVICE_NVIDIA_NV43_GEFORCE_6600,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
267 {DEVICE_NVIDIA_NV43_GEFORCE_66002,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
268 {DEVICE_NVIDIA_NV43_GEFORCE_66003,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
269 {DEVICE_NVIDIA_NV43_GEFORCE_66004,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
270 {DEVICE_NVIDIA_NV43_GEFORCE_66005,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
271 {DEVICE_NVIDIA_NV43_GEFORCE_GO,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
272 {DEVICE_NVIDIA_NV43_GEFORCE_GO2,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
22874
diff
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|
273 {DEVICE_NVIDIA_NV43_GEFORCE_GO3,NV_ARCH_40}, |
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274 {DEVICE_NVIDIA_NV43_GEFORCE_GO4,NV_ARCH_40}, |
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275 {DEVICE_NVIDIA_NV43_GEFORCE_GO5,NV_ARCH_40}, |
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276 {DEVICE_NVIDIA_NV43_GEFORCE_GO6,NV_ARCH_40}, |
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277 {DEVICE_NVIDIA_NV43_GEFORCE_6610,NV_ARCH_40}, |
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278 {DEVICE_NVIDIA_NV43GL_QUADRO_FX,NV_ARCH_40}, |
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279 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE,NV_ARCH_40}, |
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280 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE2,NV_ARCH_40}, |
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281 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE3,NV_ARCH_40}, |
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282 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE4,NV_ARCH_40}, |
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283 {DEVICE_NVIDIA_C51G_GEFORCE_6100,NV_ARCH_40}, |
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284 {DEVICE_NVIDIA_C51PV_GEFORCE_6150,NV_ARCH_40}, |
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285 {DEVICE_NVIDIA_NV44_GEFORCE_6200,NV_ARCH_40}, |
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286 {DEVICE_NVIDIA_NV44_GEFORCE_62002,NV_ARCH_40}, |
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287 {DEVICE_NVIDIA_NV44_GEFORCE_62003,NV_ARCH_40}, |
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288 {DEVICE_NVIDIA_NV44_GEFORCE_GO,NV_ARCH_40}, |
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289 {DEVICE_NVIDIA_NV44_QUADRO_NVS,NV_ARCH_40}, |
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290 {DEVICE_NVIDIA_GEFORCE_GO_6200,NV_ARCH_40}, |
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291 {DEVICE_NVIDIA_NV44A_GEFORCE_6200,NV_ARCH_40}, |
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292 {DEVICE_NVIDIA_NV45GL_QUADRO_FX,NV_ARCH_40}, |
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293 {DEVICE_NVIDIA_GEFORCE_GO_7200,NV_ARCH_40}, |
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294 {DEVICE_NVIDIA_QUADRO_NVS_110M,NV_ARCH_40}, |
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295 {DEVICE_NVIDIA_GEFORCE_GO_7400,NV_ARCH_40}, |
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296 {DEVICE_NVIDIA_QUADRO_NVS_110M2,NV_ARCH_40}, |
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297 {DEVICE_NVIDIA_QUADRO_FX_350,NV_ARCH_40}, |
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298 {DEVICE_NVIDIA_G70_GEFORCE_7300,NV_ARCH_40}, |
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299 {DEVICE_NVIDIA_GEFORCE_7300_GS,NV_ARCH_40}, |
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300 {DEVICE_NVIDIA_G70_GEFORCE_7600,NV_ARCH_40}, |
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301 {DEVICE_NVIDIA_G70_GEFORCE_76002,NV_ARCH_40}, |
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302 {DEVICE_NVIDIA_GEFORCE_7600_GS,NV_ARCH_40}, |
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303 {DEVICE_NVIDIA_G70_GEFORCE_GO,NV_ARCH_40}, |
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304 {DEVICE_NVIDIA_QUADRO_FX_560,NV_ARCH_40}, |
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305 {DEVICE_NVIDIA_G70_GEFORCE_7800,NV_ARCH_40}, |
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306 {DEVICE_NVIDIA_G70_GEFORCE_78002,NV_ARCH_40}, |
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307 {DEVICE_NVIDIA_G70_GEFORCE_78003,NV_ARCH_40}, |
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308 {DEVICE_NVIDIA_G70_GEFORCE_78004,NV_ARCH_40}, |
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309 {DEVICE_NVIDIA_G70_GEFORCE_78005,NV_ARCH_40}, |
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310 {DEVICE_NVIDIA_GEFORCE_GO_7800,NV_ARCH_40}, |
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311 {DEVICE_NVIDIA_GEFORCE_7900_GTX,NV_ARCH_40}, |
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312 {DEVICE_NVIDIA_GEFORCE_7900_GT,NV_ARCH_40}, |
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313 {DEVICE_NVIDIA_GEFORCE_7900_GS,NV_ARCH_40}, |
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314 {DEVICE_NVIDIA_GEFORCE_GO_7900,NV_ARCH_40}, |
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315 {DEVICE_NVIDIA_GEFORCE_GO_79002,NV_ARCH_40}, |
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316 {DEVICE_NVIDIA_GE_FORCE_GO,NV_ARCH_40}, |
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317 {DEVICE_NVIDIA_G70GL_QUADRO_FX4500,NV_ARCH_40}, |
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318 {DEVICE_NVIDIA_G71_QUADRO_FX,NV_ARCH_40}, |
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319 {DEVICE_NVIDIA_G71_QUADRO_FX2,NV_ARCH_40} |
22850 | 320 }; |
321 | |
322 | |
323 static int find_chip(unsigned chip_id){ | |
324 unsigned i; | |
325 for(i = 0;i < sizeof(nvidia_card_ids)/sizeof(struct nvidia_cards);i++) | |
326 { | |
327 if(chip_id == nvidia_card_ids[i].chip_id)return i; | |
328 } | |
329 return -1; | |
330 } | |
331 | |
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332 static int nv_probe(int verbose, int force){ |
22850 | 333 pciinfo_t lst[MAX_PCI_DEVICES]; |
334 unsigned i,num_pci; | |
335 int err; | |
336 | |
337 if (force) | |
338 printf("[nvidia_vid]: warning: forcing not supported yet!\n"); | |
339 err = pci_scan(lst,&num_pci); | |
340 if(err){ | |
341 printf("[nvidia_vid] Error occurred during pci scan: %s\n",strerror(err)); | |
342 return err; | |
343 } | |
344 else { | |
345 err = ENXIO; | |
346 for(i=0; i < num_pci; i++){ | |
347 if(lst[i].vendor == VENDOR_NVIDIA2 || lst[i].vendor == VENDOR_NVIDIA){ | |
348 int idx; | |
349 const char *dname; | |
350 idx = find_chip(lst[i].device); | |
351 if(idx == -1) | |
352 continue; | |
353 dname = pci_device_name(lst[i].vendor, lst[i].device); | |
354 dname = dname ? dname : "Unknown chip"; | |
355 printf("[nvidia_vid] Found chip: %s\n", dname); | |
356 if ((lst[i].command & PCI_COMMAND_IO) == 0){ | |
357 printf("[nvidia_vid] Device is disabled, ignoring\n"); | |
358 continue; | |
359 } | |
360 nvidia_cap.device_id = lst[i].device; | |
361 err = 0; | |
362 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); | |
363 break; | |
364 } | |
365 } | |
366 } | |
367 if(err && verbose) printf("[nvidia_vid] Can't find chip\n"); | |
368 return err; | |
369 } | |
370 | |
371 | |
372 | |
373 | |
374 /* | |
375 * PCI-Memory IO access macros. | |
376 */ | |
377 | |
378 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") | |
379 | |
380 #undef VID_WR08 | |
381 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) | |
382 #undef VID_RD08 | |
383 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) | |
384 | |
385 #undef VID_WR32 | |
386 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=val; }) | |
387 #undef VID_RD32 | |
388 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) | |
389 | |
390 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) | |
391 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) | |
392 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) | |
393 | |
394 | |
395 | |
396 | |
397 | |
398 | |
399 struct rivatv_chip { | |
400 volatile uint32_t *PMC; /* general control */ | |
401 volatile uint32_t *PME; /* multimedia port */ | |
402 volatile uint32_t *PFB; /* framebuffer control */ | |
403 volatile uint32_t *PVIDEO; /* overlay control */ | |
404 volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ | |
405 volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ | |
406 volatile uint32_t *PRAMIN; /* instance memory */ | |
407 volatile uint32_t *PRAMHT; /* hash table */ | |
408 volatile uint32_t *PRAMFC; /* fifo context table */ | |
409 volatile uint32_t *PRAMRO; /* fifo runout table */ | |
410 volatile uint32_t *PFIFO; /* fifo control region */ | |
411 volatile uint32_t *FIFO; /* fifo channels (USER) */ | |
412 volatile uint32_t *PGRAPH; /* graphics engine */ | |
413 | |
414 unsigned long fbsize; /* framebuffer size */ | |
415 int arch; /* compatible NV_ARCH_XX define */ | |
416 int realarch; /* real architecture */ | |
417 void (* lock) (struct rivatv_chip *, int); | |
418 }; | |
419 typedef struct rivatv_chip rivatv_chip; | |
420 | |
421 | |
422 struct rivatv_info { | |
423 unsigned int use_colorkey; | |
424 unsigned int colorkey; /* saved xv colorkey*/ | |
425 unsigned int vidixcolorkey; /*currently used colorkey*/ | |
426 unsigned int depth; | |
427 unsigned int format; | |
428 unsigned int pitch; | |
429 unsigned int width,height; | |
430 unsigned int d_width,d_height; /*scaled width && height*/ | |
431 unsigned int wx,wy; /*window x && y*/ | |
432 unsigned int screen_x; /*screen width*/ | |
433 unsigned int screen_y; /*screen height*/ | |
434 unsigned long buffer_size; /* size of the image buffer */ | |
435 struct rivatv_chip chip; /* NV architecture structure */ | |
436 void* video_base; /* virtual address of control region */ | |
437 void* control_base; /* virtual address of fb region */ | |
438 void* picture_base; /* direct pointer to video picture */ | |
439 unsigned long picture_offset; /* offset of video picture in frame buffer */ | |
440 // struct rivatv_dma dma; /* DMA structure */ | |
441 unsigned int cur_frame; | |
442 unsigned int num_frames; /* number of buffers */ | |
443 int bps; /* bytes per line */ | |
444 }; | |
445 typedef struct rivatv_info rivatv_info; | |
446 | |
447 //framebuffer size funcs | |
448 static unsigned long rivatv_fbsize_nv03 (struct rivatv_chip *chip){ | |
449 if (VID_RD32 (chip->PFB, 0) & 0x00000020) { | |
450 if (((VID_RD32 (chip->PMC, 0) & 0xF0) == 0x20) | |
451 && ((VID_RD32 (chip->PMC, 0) & 0x0F) >= 0x02)) { | |
452 /* SDRAM 128 ZX. */ | |
453 return ((1 << (VID_RD32 (chip->PFB, 0) & 0x03)) * 1024 * 1024); | |
454 } | |
455 else { | |
456 return 1024 * 1024 * 8; | |
457 } | |
458 } | |
459 else { | |
460 /* SGRAM 128. */ | |
461 switch (VID_RD32(chip->PFB, 0) & 0x00000003) { | |
462 case 0: | |
463 return 1024 * 1024 * 8; | |
464 break; | |
465 case 2: | |
466 return 1024 * 1024 * 4; | |
467 break; | |
468 default: | |
469 return 1024 * 1024 * 2; | |
470 break; | |
471 } | |
472 } | |
473 } | |
474 static unsigned long rivatv_fbsize_nv04 (struct rivatv_chip *chip){ | |
475 if (VID_RD32 (chip->PFB, 0) & 0x00000100) { | |
476 return ((VID_RD32 (chip->PFB, 0) >> 12) & 0x0F) * 1024 * 1024 * 2 | |
477 + 1024 * 1024 * 2; | |
478 } else { | |
479 switch (VID_RD32 (chip->PFB, 0) & 0x00000003) { | |
480 case 0: | |
481 return 1024 * 1024 * 32; | |
482 break; | |
483 case 1: | |
484 return 1024 * 1024 * 4; | |
485 break; | |
486 case 2: | |
487 return 1024 * 1024 * 8; | |
488 break; | |
489 case 3: | |
490 default: | |
491 return 1024 * 1024 * 16; | |
492 break; | |
493 } | |
494 } | |
495 } | |
496 | |
497 static unsigned long rivatv_fbsize_nv10 (struct rivatv_chip *chip){ | |
498 return VID_RD32 (chip->PFB, 0x20C) & 0xFFF00000; | |
499 } | |
500 | |
501 //lock funcs | |
502 static void rivatv_lock_nv03 (struct rivatv_chip *chip, int LockUnlock){ | |
503 VID_WR08 (chip->PVIO, 0x3C4, 0x06); | |
504 VID_WR08 (chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57); | |
505 } | |
506 | |
507 static void rivatv_lock_nv04 (struct rivatv_chip *chip, int LockUnlock){ | |
508 VID_WR08 (chip->PCIO, 0x3C4, 0x06); | |
509 VID_WR08 (chip->PCIO, 0x3C5, LockUnlock ? 0x99 : 0x57); | |
510 VID_WR08 (chip->PCIO, 0x3D4, 0x1F); | |
511 VID_WR08 (chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57); | |
512 } | |
513 | |
514 | |
515 | |
516 | |
517 /* Enable PFB (Framebuffer), PVIDEO (Overlay unit) and PME (Mediaport) if neccessary. */ | |
518 static void rivatv_enable_PMEDIA (struct rivatv_info *info){ | |
519 uint32_t reg; | |
520 | |
521 /* switch off interrupts once for a while */ | |
522 // VID_WR32 (info->chip.PME, 0x200140, 0x00); | |
523 // VID_WR32 (info->chip.PMC, 0x000140, 0x00); | |
524 | |
525 reg = VID_RD32 (info->chip.PMC, 0x000200); | |
526 | |
527 /* NV3 (0x10100010): NV03_PMC_ENABLE_PMEDIA, NV03_PMC_ENABLE_PFB, NV03_PMC_ENABLE_PVIDEO */ | |
528 | |
529 if ((reg & 0x10100010) != 0x10100010) { | |
530 printf("PVIDEO and PFB disabled, enabling...\n"); | |
531 VID_OR32 (info->chip.PMC, 0x000200, 0x10100010); | |
532 } | |
533 | |
534 /* save the current colorkey */ | |
535 switch (info->chip.arch ) { | |
536 case NV_ARCH_10: | |
537 case NV_ARCH_20: | |
538 case NV_ARCH_30: | |
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539 case NV_ARCH_40: |
22850 | 540 /* NV_PVIDEO_COLOR_KEY */ |
541 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0xB00); | |
542 break; | |
543 case NV_ARCH_03: | |
544 case NV_ARCH_04: | |
545 /* NV_PVIDEO_KEY */ | |
546 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0x240); | |
547 break; | |
548 } | |
549 | |
550 | |
551 /* re-enable interrupts again */ | |
552 // VID_WR32 (info->chip.PMC, 0x000140, 0x01); | |
553 // VID_WR32 (info->chip.PME, 0x200140, 0x01); | |
554 } | |
555 | |
556 /* Stop overlay video. */ | |
557 static void rivatv_overlay_stop (struct rivatv_info *info) { | |
558 switch (info->chip.arch ) { | |
559 case NV_ARCH_10: | |
560 case NV_ARCH_20: | |
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561 case NV_ARCH_30: |
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562 case NV_ARCH_40: |
22850 | 563 /* NV_PVIDEO_COLOR_KEY */ |
564 /* Xv-Extension-Hack: Restore previously saved value. */ | |
565 VID_WR32 (info->chip.PVIDEO, 0xB00, info->colorkey); | |
566 /* NV_PVIDEO_STOP */ | |
567 VID_OR32 (info->chip.PVIDEO, 0x704, 0x11); | |
568 /* NV_PVIDEO_BUFFER */ | |
569 VID_AND32 (info->chip.PVIDEO, 0x700, ~0x11); | |
570 /* NV_PVIDEO_INTR_EN_BUFFER */ | |
571 // VID_AND32 (info->chip.PVIDEO, 0x140, ~0x11); | |
572 break; | |
573 case NV_ARCH_03: | |
574 case NV_ARCH_04: | |
575 /* NV_PVIDEO_KEY */ | |
576 VID_WR32 (info->chip.PVIDEO, 0x240, info->colorkey); | |
577 /* NV_PVIDEO_OVERLAY_VIDEO_OFF */ | |
578 VID_AND32 (info->chip.PVIDEO, 0x244, ~0x01); | |
579 /* NV_PVIDEO_INTR_EN_0_NOTIFY */ | |
580 // VID_AND32 (info->chip.PVIDEO, 0x140, ~0x01); | |
581 /* NV_PVIDEO_OE_STATE */ | |
582 VID_WR32 (info->chip.PVIDEO, 0x224, 0); | |
583 /* NV_PVIDEO_SU_STATE */ | |
584 VID_WR32 (info->chip.PVIDEO, 0x228, 0); | |
585 /* NV_PVIDEO_RM_STATE */ | |
586 VID_WR32 (info->chip.PVIDEO, 0x22C, 0); | |
587 break; | |
588 } | |
589 } | |
590 | |
591 /* Get pan offset of the physical screen. */ | |
592 static uint32_t rivatv_overlay_pan (struct rivatv_info *info){ | |
593 uint32_t pan; | |
594 info->chip.lock (&info->chip, 0); | |
595 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0D); | |
596 pan = VID_RD08 (info->chip.PCIO, 0x3D5); | |
597 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0C); | |
598 pan |= VID_RD08 (info->chip.PCIO, 0x3D5) << 8; | |
599 VID_WR08 (info->chip.PCIO, 0x3D4, 0x19); | |
600 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x1F) << 16; | |
601 VID_WR08 (info->chip.PCIO, 0x3D4, 0x2D); | |
602 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x60) << 16; | |
603 return pan << 2; | |
604 } | |
605 | |
606 /* Compute and set colorkey depending on the colour depth. */ | |
607 static void rivatv_overlay_colorkey (rivatv_info* info, unsigned int chromakey){ | |
608 uint32_t r, g, b, key = 0; | |
609 | |
610 r = (chromakey & 0x00FF0000) >> 16; | |
611 g = (chromakey & 0x0000FF00) >> 8; | |
612 b = chromakey & 0x000000FF; | |
613 switch (info->depth) { | |
614 case 15: | |
615 key = ((r >> 3) << 10) | ((g >> 3) << 5) | ((b >> 3)); | |
616 #ifndef WIN32 | |
617 key = key | 0x00008000; | |
618 #endif | |
619 break; | |
620 case 16: // XXX unchecked | |
621 key = ((r >> 3) << 11) | ((g >> 2) << 5) | ((b >> 3)); | |
622 #ifndef WIN32 | |
623 key = key | 0x00008000; | |
624 #endif | |
625 break; | |
626 case 24: // XXX unchecked, maybe swap order of masking - FIXME Can the card be in 24 bit mode anyway? | |
627 key = (chromakey & 0x00FFFFFF) | 0x00800000; | |
628 break; | |
629 case 32: | |
630 key = chromakey; | |
631 #ifndef WIN32 | |
632 key = key | 0x80000000; | |
633 #endif | |
634 break; | |
635 } | |
636 //printf("[nvidia_vid] depth=%d %08X \n", info->depth, chromakey); | |
637 switch (info->chip.arch) { | |
638 case NV_ARCH_10: | |
639 case NV_ARCH_20: | |
640 case NV_ARCH_30: | |
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641 case NV_ARCH_40: |
22850 | 642 VID_WR32 (info->chip.PVIDEO, 0xB00, key); |
643 break; | |
644 case NV_ARCH_03: | |
645 case NV_ARCH_04: | |
646 VID_WR32 (info->chip.PVIDEO, 0x240, key); | |
647 break; | |
648 } | |
649 } | |
650 | |
651 static void nv_getscreenproperties(struct rivatv_info *info){ | |
652 uint32_t bpp=0,x; | |
653 info->chip.lock(&info->chip, 0); | |
654 /*get screen depth*/ | |
655 VID_WR08(info->chip.PCIO, 0x03D4,0x28); | |
656 bpp = VID_RD08(info->chip.PCIO,0x03D5)&0x3; | |
657 if((bpp == 2) && (VID_RD32(info->chip.PVIDEO,0x600) & 0x00001000) == 0x0)info->depth=15; | |
658 else info->depth = 0x04 << bpp; | |
659 /*get screen width*/ | |
660 VID_WR08(info->chip.PCIO, 0x03D4, 0x1); | |
661 info->screen_x = (1 + VID_RD08(info->chip.PCIO, 0x3D5)) * 8; | |
662 /*get screen height*/ | |
663 /* get first 8 bits in VT_DISPLAY_END*/ | |
664 VID_WR08(info->chip.PCIO, 0x03D4, 0x12); | |
665 info->screen_y = VID_RD08(info->chip.PCIO,0x03D5); | |
666 VID_WR08(info->chip.PCIO,0x03D4,0x07); | |
667 /* get 9th bit in CRTC_OVERFLOW*/ | |
668 info->screen_y |= (VID_RD08(info->chip.PCIO,0x03D5) &0x02)<<7; | |
669 /* and the 10th in CRTC_OVERFLOW*/ | |
670 info->screen_y |=(VID_RD08(info->chip.PCIO,0x03D5) &0x40)<<3; | |
671 ++info->screen_y; | |
672 | |
673 /* NV_PCRTC_OFFSET */ | |
674 VID_WR08 (info->chip.PCIO, 0x3D4, 0x13); | |
675 x = VID_RD08 (info->chip.PCIO, 0x3D5); | |
676 /* NV_PCRTC_REPAINT0_OFFSET_10_8 */ | |
677 VID_WR08 (info->chip.PCIO, 0x3D4, 0x19); | |
678 x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0xE0) << 3; | |
679 /* NV_PCRTC_EXTRA_OFFSET_11 */ | |
680 VID_WR08 (info->chip.PCIO, 0x3D4, 0x25); | |
681 x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x20) << 6; x <<= 3; | |
682 info->bps = x * bpp; | |
683 } | |
684 | |
685 | |
686 | |
687 | |
688 /* Start overlay video. */ | |
689 static void rivatv_overlay_start (struct rivatv_info *info,int bufno){ | |
690 uint32_t base, size, offset, xscale, yscale, pan; | |
691 uint32_t value; | |
692 int x=info->wx, y=info->wy; | |
693 int lwidth=info->d_width, lheight=info->d_height; | |
694 | |
695 size = info->buffer_size; | |
696 base = info->picture_offset; | |
697 offset = bufno*size; | |
698 /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/ | |
699 nv_getscreenproperties(info); | |
700 | |
701 if(info->depth){ | |
702 /* get pan offset of the physical screen */ | |
703 pan = rivatv_overlay_pan (info); | |
704 /* adjust window position depending on the pan offset */ | |
705 if (info->bps != 0) | |
706 { | |
707 x = info->wx - (pan % info->bps) * 8 / info->depth; | |
708 y = info->wy - (pan / info->bps); | |
709 } | |
710 } else { | |
711 // we can't adjust the window position correctly in textmode | |
712 // setting y to 8 seems to work ok, though | |
713 if(info->chip.arch < NV_ARCH_10 && y < 8) y = 8; | |
714 } | |
715 | |
716 /* adjust negative output window variables */ | |
717 if (x < 0) { | |
718 lwidth = info->d_width + x; | |
719 offset += (-x * info->width / info->d_width) << 1; | |
720 // offset += (-window->x * port->vld_width / window->width) << 1; | |
721 x = 0; | |
722 } | |
723 if (y < 0) { | |
724 lheight = info->d_height + y; | |
725 offset += (-y * info->height / info->d_height * info->width) << 1; | |
726 // offset += (-window->y * port->vld_height / window->height * port->org_width) << 1; | |
727 y = 0; | |
728 } | |
729 | |
730 switch (info->chip.arch) { | |
731 case NV_ARCH_10: | |
732 case NV_ARCH_20: | |
733 case NV_ARCH_30: | |
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734 case NV_ARCH_40: |
22850 | 735 |
736 /* NV_PVIDEO_BASE */ | |
737 VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base + offset); | |
738 //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base); | |
739 /* NV_PVIDEO_LIMIT */ | |
740 VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + offset + size - 1); | |
741 //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1); | |
742 | |
743 /* extra code for NV20 && NV30 architectures */ | |
22880
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ben
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diff
changeset
|
744 if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30 || info->chip.arch == NV_ARCH_40) { |
22850 | 745 VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base + offset); |
746 //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base); | |
747 VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + offset + size - 1); | |
748 //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1); | |
749 } | |
750 | |
751 /* NV_PVIDEO_LUMINANCE */ | |
752 VID_WR32 (info->chip.PVIDEO, 0x910 + 0, eq.lum); | |
753 //VID_WR32 (info->chip.PVIDEO, 0x910 + 4, 0x00001000); | |
754 /* NV_PVIDEO_CHROMINANCE */ | |
755 VID_WR32 (info->chip.PVIDEO, 0x918 + 0, eq.chrom); | |
756 //VID_WR32 (info->chip.PVIDEO, 0x918 + 4, 0x00001000); | |
757 | |
758 /* NV_PVIDEO_OFFSET */ | |
759 VID_WR32 (info->chip.PVIDEO, 0x920 + 0, 0x0); | |
760 //VID_WR32 (info->chip.PVIDEO, 0x920 + 4, offset + pitch); | |
761 /* NV_PVIDEO_SIZE_IN */ | |
762 VID_WR32 (info->chip.PVIDEO, 0x928 + 0, ((info->height) << 16) | info->width); | |
763 //VID_WR32 (info->chip.PVIDEO, 0x928 + 4, ((port->org_height/2) << 16) | port->org_width); | |
764 /* NV_PVIDEO_POINT_IN */ | |
765 VID_WR32 (info->chip.PVIDEO, 0x930 + 0, 0x00000000); | |
766 //VID_WR32 (info->chip.PVIDEO, 0x930 + 4, 0x00000000); | |
767 /* NV_PVIDEO_DS_DX_RATIO */ | |
768 VID_WR32 (info->chip.PVIDEO, 0x938 + 0, (info->width << 20) / info->d_width); | |
769 //VID_WR32 (info->chip.PVIDEO, 0x938 + 4, (port->org_width << 20) / window->width); | |
770 /* NV_PVIDEO_DT_DY_RATIO */ | |
771 VID_WR32 (info->chip.PVIDEO, 0x940 + 0, ((info->height) << 20) / info->d_height); | |
772 //VID_WR32 (info->chip.PVIDEO, 0x940 + 4, ((port->org_height/2) << 20) / window->height); | |
773 | |
774 /* NV_PVIDEO_POINT_OUT */ | |
775 VID_WR32 (info->chip.PVIDEO, 0x948 + 0, ((y + 0) << 16) | x); | |
776 //VID_WR32 (info->chip.PVIDEO, 0x948 + 4, ((y + 0) << 16) | x); | |
777 /* NV_PVIDEO_SIZE_OUT */ | |
778 VID_WR32 (info->chip.PVIDEO, 0x950 + 0, (lheight << 16) | lwidth); | |
779 //VID_WR32 (info->chip.PVIDEO, 0x950 + 4, (height << 16) | width); | |
780 | |
781 /* NV_PVIDEO_FORMAT */ | |
782 value = info->pitch; | |
783 if(info->use_colorkey)value |= 1 << 20; | |
784 if(info->format == IMGFMT_YUY2)value |= 1 << 16; | |
785 VID_WR32 (info->chip.PVIDEO, 0x958 + 0, value); | |
786 //VID_WR32 (info->chip.PVIDEO, 0x958 + 4, (pitch << 1) | 0x00100000); | |
787 | |
788 /* NV_PVIDEO_INTR_EN_BUFFER */ | |
789 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01/*0x11*/); | |
790 /* NV_PVIDEO_STOP */ | |
791 VID_WR32 (info->chip.PVIDEO, 0x704,0x0); | |
792 /* NV_PVIDEO_BUFFER */ | |
793 VID_WR32 (info->chip.PVIDEO, 0x700, 0x01/*0x11*/); | |
794 break; | |
795 | |
796 case NV_ARCH_03: | |
797 case NV_ARCH_04: | |
798 | |
799 | |
800 /* NV_PVIDEO_OE_STATE */ | |
801 VID_WR32 (info->chip.PVIDEO, 0x224, 0); | |
802 /* NV_PVIDEO_SU_STATE */ | |
803 VID_WR32 (info->chip.PVIDEO, 0x228, 0); | |
804 /* NV_PVIDEO_RM_STATE */ | |
805 VID_WR32 (info->chip.PVIDEO, 0x22C, 0); | |
806 | |
807 /* NV_PVIDEO_BUFF0_START_ADDRESS */ | |
808 VID_WR32 (info->chip.PVIDEO, 0x20C + 0, base + offset + 0); | |
809 VID_WR32 (info->chip.PVIDEO, 0x20C + 4, base + offset + 0); | |
810 /* NV_PVIDEO_BUFF0_PITCH_LENGTH */ | |
811 VID_WR32 (info->chip.PVIDEO, 0x214 + 0, info->pitch); | |
812 VID_WR32 (info->chip.PVIDEO, 0x214 + 4, info->pitch); | |
813 | |
814 /* NV_PVIDEO_WINDOW_START */ | |
815 VID_WR32 (info->chip.PVIDEO, 0x230, (y << 16) | x); | |
816 /* NV_PVIDEO_WINDOW_SIZE */ | |
817 VID_WR32 (info->chip.PVIDEO, 0x234, (lheight << 16) | lwidth); | |
818 /* NV_PVIDEO_STEP_SIZE */ | |
819 yscale = ((info->height - 1) << 11) / (info->d_height - 1); | |
820 xscale = ((info->width - 1) << 11) / (info->d_width - 1); | |
821 VID_WR32 (info->chip.PVIDEO, 0x200, (yscale << 16) | xscale); | |
822 | |
823 /* NV_PVIDEO_RED_CSC_OFFSET */ | |
824 VID_WR32 (info->chip.PVIDEO, 0x280, eq.red_off); | |
825 /* NV_PVIDEO_GREEN_CSC_OFFSET */ | |
826 VID_WR32 (info->chip.PVIDEO, 0x284, eq.green_off); | |
827 /* NV_PVIDEO_BLUE_CSC_OFFSET */ | |
828 VID_WR32 (info->chip.PVIDEO, 0x288, eq.blue_off); | |
829 /* NV_PVIDEO_CSC_ADJUST */ | |
830 VID_WR32 (info->chip.PVIDEO, 0x28C, 0x00000); /* No colour correction! */ | |
831 | |
832 /* NV_PVIDEO_CONTROL_Y (BLUR_ON, LINE_HALF) */ | |
833 VID_WR32 (info->chip.PVIDEO, 0x204, 0x001); | |
834 /* NV_PVIDEO_CONTROL_X (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */ | |
835 VID_WR32 (info->chip.PVIDEO, 0x208, 0x111); /*directx overlay 0x110 */ | |
836 | |
837 /* NV_PVIDEO_FIFO_BURST_LENGTH */ | |
838 VID_WR32 (info->chip.PVIDEO, 0x23C, 0x03); | |
839 /* NV_PVIDEO_FIFO_THRES_SIZE */ | |
840 VID_WR32 (info->chip.PVIDEO, 0x238, 0x38); /*windows uses 0x40*/ | |
841 | |
842 /* NV_PVIDEO_BUFF0_OFFSET */ | |
843 VID_WR32 (info->chip.PVIDEO, 0x21C + 0, 0); | |
844 VID_WR32 (info->chip.PVIDEO, 0x21C + 4, 0); | |
845 | |
846 /* NV_PVIDEO_INTR_EN_0_NOTIFY_ENABLED */ | |
847 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01); | |
848 | |
849 /* NV_PVIDEO_OVERLAY (KEY_ON, VIDEO_ON, FORMAT_CCIR) */ | |
850 value = 0x1; /*video on*/ | |
851 if(info->format==IMGFMT_YUY2)value |= 0x100; | |
852 if(info->use_colorkey)value |=0x10; | |
853 VID_WR32 (info->chip.PVIDEO, 0x244, value); | |
854 | |
855 /* NV_PVIDEO_SU_STATE */ | |
856 VID_XOR32 (info->chip.PVIDEO, 0x228, 1 << 16); | |
857 break; | |
858 } | |
859 /*set colorkey*/ | |
860 rivatv_overlay_colorkey(info,info->vidixcolorkey); | |
861 | |
862 } | |
863 | |
864 | |
865 | |
866 | |
867 | |
868 | |
869 | |
870 static rivatv_info* info; | |
871 | |
872 | |
873 | |
874 | |
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875 static int nv_init(void){ |
22850 | 876 int mtrr; |
877 info = calloc(1,sizeof(rivatv_info)); | |
878 info->control_base = map_phys_mem(pci_info.base0, 0x00C00000 + 0x00008000); | |
879 info->chip.arch = nvidia_card_ids[find_chip(pci_info.device)].arch; | |
880 printf("[nvidia_vid] arch %x register base %p\n",info->chip.arch,info->control_base); | |
881 info->chip.PFIFO = (uint32_t *) (info->control_base + 0x00002000); | |
882 info->chip.FIFO = (uint32_t *) (info->control_base + 0x00800000); | |
883 info->chip.PMC = (uint32_t *) (info->control_base + 0x00000000); | |
884 info->chip.PFB = (uint32_t *) (info->control_base + 0x00100000); | |
885 info->chip.PME = (uint32_t *) (info->control_base + 0x00000000); | |
886 info->chip.PCIO = (uint8_t *) (info->control_base + 0x00601000); | |
887 info->chip.PVIO = (uint8_t *) (info->control_base + 0x000C0000); | |
888 info->chip.PGRAPH = (uint32_t *) (info->control_base + 0x00400000); | |
889 /* setup chip specific functions */ | |
890 switch (info->chip.arch) { | |
891 case NV_ARCH_03: | |
892 info->chip.lock = rivatv_lock_nv03; | |
893 info->chip.fbsize = rivatv_fbsize_nv03 (&info->chip); | |
894 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); | |
895 break; | |
896 case NV_ARCH_04: | |
897 info->chip.lock = rivatv_lock_nv04; | |
898 info->chip.fbsize = rivatv_fbsize_nv04 (&info->chip); | |
899 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); | |
900 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); | |
901 break; | |
902 case NV_ARCH_10: | |
903 case NV_ARCH_20: | |
904 case NV_ARCH_30: | |
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ben
parents:
22874
diff
changeset
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905 case NV_ARCH_40: |
22850 | 906 info->chip.lock = rivatv_lock_nv04; |
907 info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip); | |
908 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); | |
909 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000); | |
910 break; | |
911 } | |
912 switch (info->chip.arch) { | |
913 case NV_ARCH_03: | |
914 { | |
915 /* This maps framebuffer @6MB, thus 2MB are left for video. */ | |
916 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
917 /* This may trash your screen for resolutions greater than 1024x768, sorry. */ | |
918 info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1); | |
919 info->picture_base = info->video_base + info->picture_offset; | |
920 info->chip.PRAMIN = (uint32_t *) (info->video_base + 0x00C00000); | |
921 break; | |
922 } | |
923 case NV_ARCH_04: | |
924 case NV_ARCH_10: | |
925 case NV_ARCH_20: | |
926 case NV_ARCH_30: | |
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changeset
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927 case NV_ARCH_40: |
22850 | 928 { |
929 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
930 info->picture_offset = info->chip.fbsize - NV04_BES_SIZE; | |
931 if(info->chip.fbsize > 16*1024*1024) | |
932 info->picture_offset -= NV04_BES_SIZE; | |
933 // info->picture_base = (unsigned long)map_phys_mem(pci_info.base1+info->picture_offset,NV04_BES_SIZE); | |
934 info->picture_base = info->video_base + info->picture_offset; | |
935 break; | |
936 } | |
937 } | |
938 | |
939 printf("[nvidia_vid] detected memory size %u MB\n",(uint32_t)(info->chip.fbsize /1024/1024)); | |
940 | |
941 if ((mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB))!= 0) | |
942 printf("[nvidia_vid] unable to setup MTRR: %s\n", strerror(mtrr)); | |
943 else | |
944 printf("[nvidia_vid] MTRR set up\n"); | |
945 | |
946 nv_getscreenproperties(info); | |
947 if(!info->depth)printf("[nvidia_vid] text mode: %ux%u\n",info->screen_x,info->screen_y); | |
948 else printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x,info->screen_y, info->depth); | |
949 | |
950 | |
951 rivatv_enable_PMEDIA(info); | |
952 info->cur_frame = 0; | |
953 info->use_colorkey = 0; | |
954 | |
955 eq.lum = 0x00001000; | |
956 eq.chrom = 0x00001000; | |
957 memset(&eq.vals, 0, sizeof(vidix_video_eq_t)); | |
958 eq.vals.cap = VEQ_CAP_BRIGHTNESS; | |
959 if (info->chip.arch > NV_ARCH_04) | |
960 eq.vals.cap |= VEQ_CAP_CONTRAST | VEQ_CAP_SATURATION | VEQ_CAP_HUE; | |
961 eq.red_off = 0x69; | |
962 eq.green_off = 0x3e; | |
963 eq.blue_off = 0x89; | |
964 return 0; | |
965 } | |
966 | |
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changeset
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967 static void nv_destroy(void){ |
22850 | 968 unmap_phys_mem(info->control_base ,0x00C00000 + 0x00008000); |
969 unmap_phys_mem(info->video_base, info->chip.fbsize); | |
970 free(info); | |
971 } | |
972 | |
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changeset
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973 static int nv_get_caps(vidix_capability_t *to){ |
22850 | 974 memcpy(to, &nvidia_cap, sizeof(vidix_capability_t)); |
975 return 0; | |
976 } | |
977 | |
978 inline static int is_supported_fourcc(uint32_t fourcc) | |
979 { | |
980 if (fourcc == IMGFMT_UYVY || fourcc == IMGFMT_YUY2) | |
981 return 1; | |
982 else | |
983 return 0; | |
984 } | |
985 | |
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switch to new internal vidix API, no more dlopen/dlsym, libvidix is now a fully static library with all drivers built-in
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changeset
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986 static int nv_query_fourcc(vidix_fourcc_t *to){ |
22850 | 987 if(is_supported_fourcc(to->fourcc)){ |
23060 | 988 to->depth = VID_DEPTH_ALL; |
22850 | 989 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; |
990 return 0; | |
991 } | |
992 else to->depth = to->flags = 0; | |
993 return ENOSYS; | |
994 } | |
995 | |
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996 static int nv_config_playback(vidix_playback_t *vinfo){ |
22850 | 997 uint32_t i; |
998 printf("called %s\n", __FUNCTION__); | |
999 if (! is_supported_fourcc(vinfo->fourcc)) | |
1000 return ENOSYS; | |
1001 | |
1002 info->width = vinfo->src.w; | |
1003 info->height = vinfo->src.h; | |
1004 | |
1005 info->d_width = vinfo->dest.w; | |
1006 info->d_height = vinfo->dest.h; | |
1007 info->wx = vinfo->dest.x; | |
1008 info->wy = vinfo->dest.y; | |
1009 info->format = vinfo->fourcc; | |
1010 | |
1011 printf("[nvidia_vid] setting up a %dx%d-%dx%d video window (src %dx%d), format 0x%X\n", | |
1012 info->d_width, info->d_height, info->wx, info->wy, info->width, info->height, vinfo->fourcc); | |
1013 | |
1014 | |
1015 vinfo->dga_addr=info->picture_base; | |
1016 | |
1017 switch (vinfo->fourcc) | |
1018 { | |
1019 case IMGFMT_YUY2: | |
1020 case IMGFMT_UYVY: | |
1021 | |
1022 vinfo->dest.pitch.y = 64; | |
1023 vinfo->dest.pitch.u = 0; | |
1024 vinfo->dest.pitch.v = 0; | |
1025 | |
1026 vinfo->offset.y = 0; | |
1027 vinfo->offset.v = 0; | |
1028 vinfo->offset.u = 0; | |
1029 info->pitch = ((info->width << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1); | |
1030 vinfo->frame_size = info->pitch * info->height; | |
1031 break; | |
1032 } | |
1033 info->buffer_size = vinfo->frame_size; | |
1034 info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; | |
1035 if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; | |
1036 // vinfo->num_frames = 1; | |
1037 // printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); | |
1038 for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; | |
1039 return 0; | |
1040 } | |
1041 | |
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1042 static int nv_playback_on(void){ |
22850 | 1043 rivatv_overlay_start(info,info->cur_frame); |
1044 return 0; | |
1045 } | |
1046 | |
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1047 static int nv_playback_off(void){ |
22850 | 1048 rivatv_overlay_stop(info); |
1049 return 0; | |
1050 } | |
1051 | |
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1052 static int nv_set_gkeys( const vidix_grkey_t * grkey){ |
22850 | 1053 if (grkey->ckey.op == CKEY_FALSE) |
1054 { | |
1055 info->use_colorkey = 0; | |
1056 printf("[nvidia_vid] colorkeying disabled\n"); | |
1057 } | |
1058 else { | |
1059 info->use_colorkey = 1; | |
1060 info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); | |
1061 printf("[nvidia_vid] set colorkey 0x%x\n",info->vidixcolorkey); | |
1062 } | |
1063 if(info->d_width && info->d_height)rivatv_overlay_start(info,0); | |
1064 return 0; | |
1065 } | |
1066 | |
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1067 static int nv_frame_sel(unsigned int frame){ |
22850 | 1068 // printf("selecting buffer %d\n", frame); |
1069 rivatv_overlay_start(info, frame); | |
1070 if (info->num_frames >= 1) | |
1071 info->cur_frame = frame/*(frame+1)%info->num_frames*/; | |
1072 return 0; | |
1073 } | |
1074 | |
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1075 static int nv_set_eq(const vidix_video_eq_t *eq_parm) { |
22850 | 1076 double angle; |
1077 int16_t chrom_cos, chrom_sin; | |
1078 if (eq_parm->cap & VEQ_CAP_BRIGHTNESS) | |
1079 eq.vals.brightness = eq_parm->brightness; | |
1080 if (eq_parm->cap & VEQ_CAP_CONTRAST) | |
1081 eq.vals.contrast = eq_parm->contrast; | |
1082 if (eq_parm->cap & VEQ_CAP_SATURATION) | |
1083 eq.vals.saturation = eq_parm->saturation; | |
1084 if (eq_parm->cap & VEQ_CAP_HUE) | |
1085 eq.vals.hue = eq_parm->hue; | |
1086 eq.lum = (((eq.vals.brightness * 512 + 500) / 1000) << 16) | | |
1087 ((((eq.vals.contrast + 1000) * 8191 + 1000) / 2000) & 0xffff); | |
1088 angle = (double)eq.vals.hue / 1000.0 * 3.1415927; | |
1089 chrom_cos = ((eq.vals.saturation + 1000) * 8191 * cos(angle) + 1000) / 2000; | |
1090 chrom_sin = ((eq.vals.saturation + 1000) * 8191 * sin(angle) + 1000) / 2000; | |
1091 eq.chrom = chrom_sin << 16 | chrom_cos; | |
1092 eq.red_off = 0x69 - eq.vals.brightness * 62 / 1000; | |
1093 eq.green_off = 0x3e + eq.vals.brightness * 62 / 1000; | |
1094 eq.blue_off = 0x89 - eq.vals.brightness * 62 / 1000; | |
1095 return 0; | |
1096 } | |
1097 | |
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1098 static int nv_get_eq(vidix_video_eq_t *eq_parm) { |
22850 | 1099 memcpy(eq_parm, &eq.vals, sizeof(vidix_video_eq_t)); |
1100 return 0; | |
1101 } | |
1102 | |
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1103 VDXDriver nvidia_drv = { |
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1104 "nvidia", |
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1105 NULL, |
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1106 .probe = nv_probe, |
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1107 .get_caps = nv_get_caps, |
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1108 .query_fourcc = nv_query_fourcc, |
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1109 .init = nv_init, |
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1110 .destroy = nv_destroy, |
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1111 .config_playback = nv_config_playback, |
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1112 .playback_on = nv_playback_on, |
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1113 .playback_off = nv_playback_off, |
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1114 .frame_sel = nv_frame_sel, |
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1115 .get_eq = nv_get_eq, |
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1116 .set_eq = nv_set_eq, |
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1117 .set_gkey = nv_set_gkeys, |
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1118 }; |