Mercurial > mplayer.hg
annotate vidix/savage_regs.h @ 25992:a9e86b2def64
Merge the two conditional definitions of get_current_dir_name.
author | diego |
---|---|
date | Mon, 18 Feb 2008 19:37:59 +0000 |
parents | af2aadfbabc3 |
children | a93e46adb54c |
rev | line source |
---|---|
22850 | 1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/savage/savage_regs.h,v 1.10 2001/11/04 22:17:48 alanh Exp $ */ |
2 | |
23934
88bed2131f19
Identifiers starting with underscores are reserved.
diego
parents:
22850
diff
changeset
|
3 #ifndef SAVAGE_REGS_H |
88bed2131f19
Identifiers starting with underscores are reserved.
diego
parents:
22850
diff
changeset
|
4 #define SAVAGE_REGS_H |
22850 | 5 |
6 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) | |
7 | |
8 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE)) | |
9 | |
10 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) | |
11 | |
12 #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) | |
13 | |
14 | |
15 /* Chip tags. These are used to group the adapters into | |
16 * related families. | |
17 */ | |
18 | |
19 | |
20 enum S3CHIPTAGS { | |
21 S3_UNKNOWN = 0, | |
22 S3_SAVAGE3D, | |
23 S3_SAVAGE_MX, | |
24 S3_SAVAGE4, | |
25 S3_PROSAVAGE, | |
26 S3_SUPERSAVAGE, | |
27 S3_SAVAGE2000, | |
28 S3_LAST | |
29 }; | |
30 | |
31 typedef struct { | |
32 unsigned int mode, refresh; | |
33 unsigned char SR08, SR0E, SR0F; | |
34 unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR1B, SR29, SR30; | |
35 unsigned char SR54[8]; | |
36 unsigned char Clock; | |
37 unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C; | |
38 unsigned char CR40, CR41, CR42, CR43, CR45; | |
39 unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E; | |
40 unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F; | |
41 unsigned char CR86, CR88; | |
42 unsigned char CR90, CR91, CRB0; | |
43 unsigned int STREAMS[22]; /* yuck, streams regs */ | |
44 unsigned int MMPR0, MMPR1, MMPR2, MMPR3; | |
45 } SavageRegRec, *SavageRegPtr; | |
46 | |
47 | |
48 | |
49 #define BIOS_BSIZE 1024 | |
50 #define BIOS_BASE 0xc0000 | |
51 | |
52 #define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */ | |
53 #define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000 | |
54 #define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */ | |
55 #define SAVAGE_NEWMMIO_VGABASE 0x8000 | |
56 | |
57 #define BASE_FREQ 14.31818 | |
58 | |
59 #define FIFO_CONTROL_REG 0x8200 | |
60 #define MIU_CONTROL_REG 0x8204 | |
61 #define STREAMS_TIMEOUT_REG 0x8208 | |
62 #define MISC_TIMEOUT_REG 0x820c | |
63 | |
64 /* Stream Processor 1 */ | |
65 | |
66 /* Primary Stream 1 Frame Buffer Address 0 */ | |
67 #define PRI_STREAM_FBUF_ADDR0 0x81c0 | |
68 /* Primary Stream 1 Frame Buffer Address 0 */ | |
69 #define PRI_STREAM_FBUF_ADDR1 0x81c4 | |
70 /* Primary Stream 1 Stride */ | |
71 #define PRI_STREAM_STRIDE 0x81c8 | |
72 /* Primary Stream 1 Frame Buffer Size */ | |
73 #define PRI_STREAM_BUFFERSIZE 0x8214 | |
74 | |
75 /* Secondary stream 1 Color/Chroma Key Control */ | |
76 #define SEC_STREAM_CKEY_LOW 0x8184 | |
77 /* Secondary stream 1 Chroma Key Upper Bound */ | |
78 #define SEC_STREAM_CKEY_UPPER 0x8194 | |
79 /* Blend Control of Secondary Stream 1 & 2 */ | |
80 #define BLEND_CONTROL 0x8190 | |
81 /* Secondary Stream 1 Color conversion/Adjustment 1 */ | |
82 #define SEC_STREAM_COLOR_CONVERT1 0x8198 | |
83 /* Secondary Stream 1 Color conversion/Adjustment 2 */ | |
84 #define SEC_STREAM_COLOR_CONVERT2 0x819c | |
85 /* Secondary Stream 1 Color conversion/Adjustment 3 */ | |
86 #define SEC_STREAM_COLOR_CONVERT3 0x81e4 | |
87 /* Secondary Stream 1 Horizontal Scaling */ | |
88 #define SEC_STREAM_HSCALING 0x81a0 | |
89 /* Secondary Stream 1 Frame Buffer Size */ | |
90 #define SEC_STREAM_BUFFERSIZE 0x81a8 | |
91 /* Secondary Stream 1 Horizontal Scaling Normalization (2K only) */ | |
92 #define SEC_STREAM_HSCALE_NORMALIZE 0x81ac | |
93 /* Secondary Stream 1 Horizontal Scaling */ | |
94 #define SEC_STREAM_VSCALING 0x81e8 | |
95 /* Secondary Stream 1 Frame Buffer Address 0 */ | |
96 #define SEC_STREAM_FBUF_ADDR0 0x81d0 | |
97 /* Secondary Stream 1 Frame Buffer Address 1 */ | |
98 #define SEC_STREAM_FBUF_ADDR1 0x81d4 | |
99 /* Secondary Stream 1 Frame Buffer Address 2 */ | |
100 #define SEC_STREAM_FBUF_ADDR2 0x81ec | |
101 /* Secondary Stream 1 Stride */ | |
102 #define SEC_STREAM_STRIDE 0x81d8 | |
103 /* Secondary Stream 1 Window Start Coordinates */ | |
104 #define SEC_STREAM_WINDOW_START 0x81f8 | |
105 /* Secondary Stream 1 Window Size */ | |
106 #define SEC_STREAM_WINDOW_SZ 0x81fc | |
107 /* Secondary Streams Tile Offset */ | |
108 #define SEC_STREAM_TILE_OFF 0x821c | |
109 /* Secondary Stream 1 Opaque Overlay Control */ | |
110 #define SEC_STREAM_OPAQUE_OVERLAY 0x81dc | |
111 | |
112 | |
113 /* Stream Processor 2 */ | |
114 | |
115 /* Primary Stream 2 Frame Buffer Address 0 */ | |
116 #define PRI_STREAM2_FBUF_ADDR0 0x81b0 | |
117 /* Primary Stream 2 Frame Buffer Address 1 */ | |
118 #define PRI_STREAM2_FBUF_ADDR1 0x81b4 | |
119 /* Primary Stream 2 Stride */ | |
120 #define PRI_STREAM2_STRIDE 0x81b8 | |
121 /* Primary Stream 2 Frame Buffer Size */ | |
122 #define PRI_STREAM2_BUFFERSIZE 0x8218 | |
123 | |
124 /* Secondary Stream 2 Color/Chroma Key Control */ | |
125 #define SEC_STREAM2_CKEY_LOW 0x8188 | |
126 /* Secondary Stream 2 Chroma Key Upper Bound */ | |
127 #define SEC_STREAM2_CKEY_UPPER 0x818c | |
128 /* Secondary Stream 2 Horizontal Scaling */ | |
129 #define SEC_STREAM2_HSCALING 0x81a4 | |
130 /* Secondary Stream 2 Horizontal Scaling */ | |
131 #define SEC_STREAM2_VSCALING 0x8204 | |
132 /* Secondary Stream 2 Frame Buffer Size */ | |
133 #define SEC_STREAM2_BUFFERSIZE 0x81ac | |
134 /* Secondary Stream 2 Frame Buffer Address 0 */ | |
135 #define SEC_STREAM2_FBUF_ADDR0 0x81bc | |
136 /* Secondary Stream 2 Frame Buffer Address 1 */ | |
137 #define SEC_STREAM2_FBUF_ADDR1 0x81e0 | |
138 /* Secondary Stream 2 Frame Buffer Address 2 */ | |
139 #define SEC_STREAM2_FBUF_ADDR2 0x8208 | |
140 /* Multiple Buffer/LPB and Secondary Stream 2 Stride */ | |
141 #define SEC_STREAM2_STRIDE_LPB 0x81cc | |
142 /* Secondary Stream 2 Color conversion/Adjustment 1 */ | |
143 #define SEC_STREAM2_COLOR_CONVERT1 0x81f0 | |
144 /* Secondary Stream 2 Color conversion/Adjustment 2 */ | |
145 #define SEC_STREAM2_COLOR_CONVERT2 0x81f4 | |
146 /* Secondary Stream 2 Color conversion/Adjustment 3 */ | |
147 #define SEC_STREAM2_COLOR_CONVERT3 0x8200 | |
148 /* Secondary Stream 2 Window Start Coordinates */ | |
149 #define SEC_STREAM2_WINDOW_START 0x820c | |
150 /* Secondary Stream 2 Window Size */ | |
151 #define SEC_STREAM2_WINDOW_SZ 0x8210 | |
152 /* Secondary Stream 2 Opaque Overlay Control */ | |
153 #define SEC_STREAM2_OPAQUE_OVERLAY 0x8180 | |
154 | |
155 | |
156 /* savage 2000 */ | |
157 #define SEC_STREAM_COLOR_CONVERT0_2000 0x8198 | |
158 #define SEC_STREAM_COLOR_CONVERT1_2000 0x819c | |
159 #define SEC_STREAM_COLOR_CONVERT2_2000 0x81e0 | |
160 #define SEC_STREAM_COLOR_CONVERT3_2000 0x81e4 | |
161 | |
162 #define SUBSYS_STAT_REG 0x8504 | |
163 | |
164 #define SRC_BASE 0xa4d4 | |
165 #define DEST_BASE 0xa4d8 | |
166 #define CLIP_L_R 0xa4dc | |
167 #define CLIP_T_B 0xa4e0 | |
168 #define DEST_SRC_STR 0xa4e4 | |
169 #define MONO_PAT_0 0xa4e8 | |
170 #define MONO_PAT_1 0xa4ec | |
171 | |
172 /* Constants for CR69. */ | |
173 | |
174 #define CRT_ACTIVE 0x01 | |
175 #define LCD_ACTIVE 0x02 | |
176 #define TV_ACTIVE 0x04 | |
177 #define CRT_ATTACHED 0x10 | |
178 #define LCD_ATTACHED 0x20 | |
179 #define TV_ATTACHED 0x40 | |
180 | |
181 | |
182 /* | |
183 * reads from SUBSYS_STAT | |
184 */ | |
185 #define STATUS_WORD0 (INREG(0x48C00)) | |
186 #define ALT_STATUS_WORD0 (INREG(0x48C60)) | |
187 #define MAXLOOP 0xffffff | |
188 #define IN_SUBSYS_STAT() (INREG(SUBSYS_STAT_REG)) | |
189 | |
190 #define MAXFIFO 0x7f00 | |
191 | |
192 /* | |
193 * NOTE: don't remove 'VGAIN8(vgaCRIndex);'. | |
194 * If not present it will cause lockups on Savage4. | |
195 * Ask S3, why. | |
196 */ | |
197 /*#define VerticalRetraceWait() \ | |
198 { \ | |
199 VGAIN8(0x3d0+4); \ | |
200 VGAOUT8(0x3d0+4, 0x17); \ | |
201 if (VGAIN8(0x3d0+5) & 0x80) { \ | |
202 while ((VGAIN8(0x3d0 + 0x0a) & 0x08) == 0x08) ; \ | |
203 while ((VGAIN8(0x3d0 + 0x0a) & 0x08) == 0x00) ; \ | |
204 } \ | |
205 } | |
206 */ | |
207 | |
208 #define VerticalRetraceWait() \ | |
209 do { \ | |
210 VGAIN8(0x3d4); \ | |
211 VGAOUT8(0x3d4, 0x17); \ | |
212 if (VGAIN8(0x3d5) & 0x80) { \ | |
213 int i = 0x10000; \ | |
214 while ((VGAIN8(0x3da) & 0x08) == 0x08 && i--) ; \ | |
215 i = 0x10000; \ | |
216 while ((VGAIN8(0x3da) & 0x08) == 0x00 && i--) ; \ | |
217 } \ | |
218 } while (0) | |
219 | |
220 | |
221 #define I2C_REG 0xa0 | |
222 #define InI2CREG(a) \ | |
223 { \ | |
224 VGAOUT8(0x3d0 + 4, I2C_REG); \ | |
225 a = VGAIN8(0x3d0 + 5); \ | |
226 } | |
227 | |
228 #define OutI2CREG(a) \ | |
229 { \ | |
230 VGAOUT8(0x3d0 + 4, I2C_REG); \ | |
231 VGAOUT8(0x3d0 + 5, a); \ | |
232 } | |
233 | |
234 #define HZEXP_COMP_1 0x54 | |
235 #define HZEXP_BORDER 0x58 | |
236 #define HZEXP_FACTOR_IGA1 0x59 | |
237 | |
238 #define VTEXP_COMP_1 0x56 | |
239 #define VTEXP_BORDER 0x5a | |
240 #define VTEXP_FACTOR_IGA1 0x5b | |
241 | |
242 #define EC1_CENTER_ON 0x10 | |
243 #define EC1_EXPAND_ON 0x0c | |
244 | |
245 #define MODE_24 24 | |
246 | |
247 #if (MODE_24 == 32) | |
248 # define BYTES_PP24 4 | |
249 #else | |
250 # define BYTES_PP24 3 | |
251 #endif | |
252 | |
253 #define OVERLAY_DEPTH 16 | |
254 | |
255 #define STREAMS_MODE32 0x7 | |
256 #define STREAMS_MODE24 0x6 | |
257 #define STREAMS_MODE16 0x5 /* @@@ */ | |
258 | |
259 | |
260 #define DEPTH_BPP(depth) (depth == 24 ? (BYTES_PP24 << 3) : (depth + 7) & ~0x7) | |
261 #define DEPTH_2ND(depth) (depth > 8 ? depth\ | |
262 : OVERLAY_DEPTH) | |
263 #define SSTREAMS_MODE(bpp) (bpp > 16 ? (bpp > 24 ? STREAMS_MODE32 :\ | |
264 STREAMS_MODE24) : STREAMS_MODE16) | |
265 | |
266 #define HSCALING_Shift 0 | |
267 #define HSCALING_Mask (((1L << 16)-1) << HSCALING_Shift) | |
268 #define HSCALING(w0,w1) ((((unsigned int)(((double)w0/(double)w1) * (1 << 15))) \ | |
269 << HSCALING_Shift) \ | |
270 & HSCALING_Mask) | |
271 | |
272 #define VSCALING_Shift 0 | |
273 #define VSCALING_Mask (((1L << 20)-1) << VSCALING_Shift) | |
274 #define VSCALING(h0,h1) ((((unsigned int) (((double)h0/(double)h1) * (1 << 15))) \ | |
275 << VSCALING_Shift) \ | |
276 & VSCALING_Mask) | |
277 | |
278 | |
23934
88bed2131f19
Identifiers starting with underscores are reserved.
diego
parents:
22850
diff
changeset
|
279 #endif /* SAVAGE_REGS_H */ |