Mercurial > mplayer.hg
annotate drivers/mga_vid.c @ 1139:d8128ae8d087
*** empty log message ***
author | gabucino |
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date | Sun, 17 Jun 2001 06:21:05 +0000 |
parents | 76ca00724e12 |
children | bddeddc2cf42 |
rev | line source |
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1 | 1 // YUY2 support (see config.format) added by A'rpi/ESP-team |
57 | 2 // double buffering added by A'rpi/ESP-team |
3 | |
4 // Set this value, if autodetection fails! (video ram size in megabytes) | |
91 | 5 // #define MGA_MEMORY_SIZE 16 |
1 | 6 |
68 | 7 //#define MGA_ALLOW_IRQ |
8 | |
9 #define MGA_VSYNC_POS 2 | |
10 | |
1 | 11 /* |
12 * | |
13 * mga_vid.c | |
14 * | |
15 * Copyright (C) 1999 Aaron Holtzman | |
16 * | |
17 * Module skeleton based on gutted agpgart module by Jeff Hartmann | |
18 * <slicer@ionet.net> | |
19 * | |
20 * Matrox MGA G200/G400 YUV Video Interface module Version 0.1.0 | |
21 * | |
22 * BES == Back End Scaler | |
23 * | |
24 * This software has been released under the terms of the GNU Public | |
25 * license. See http://www.gnu.org/copyleft/gpl.html for details. | |
26 */ | |
27 | |
28 //It's entirely possible this major conflicts with something else | |
29 /* mknod /dev/mga_vid c 178 0 */ | |
30 | |
31 #include <linux/config.h> | |
32 #include <linux/version.h> | |
33 #include <linux/module.h> | |
34 #include <linux/types.h> | |
35 #include <linux/kernel.h> | |
36 #include <linux/sched.h> | |
37 #include <linux/mm.h> | |
38 #include <linux/string.h> | |
39 #include <linux/errno.h> | |
40 #include <linux/malloc.h> | |
41 #include <linux/pci.h> | |
63 | 42 #include <linux/ioport.h> |
1 | 43 #include <linux/init.h> |
44 | |
45 #include "mga_vid.h" | |
46 | |
47 #ifdef CONFIG_MTRR | |
48 #include <asm/mtrr.h> | |
49 #endif | |
50 | |
51 #include <asm/uaccess.h> | |
52 #include <asm/system.h> | |
53 #include <asm/io.h> | |
54 | |
55 #define TRUE 1 | |
56 #define FALSE 0 | |
57 | |
58 #define MGA_VID_MAJOR 178 | |
59 | |
57 | 60 //#define MGA_VIDMEM_SIZE mga_ram_size |
1 | 61 |
62 #ifndef PCI_DEVICE_ID_MATROX_G200_PCI | |
63 #define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520 | |
64 #endif | |
65 | |
66 #ifndef PCI_DEVICE_ID_MATROX_G200_AGP | |
67 #define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521 | |
68 #endif | |
69 | |
70 #ifndef PCI_DEVICE_ID_MATROX_G400 | |
71 #define PCI_DEVICE_ID_MATROX_G400 0x0525 | |
72 #endif | |
73 | |
74 MODULE_AUTHOR("Aaron Holtzman <aholtzma@engr.uvic.ca>"); | |
75 | |
76 | |
77 typedef struct bes_registers_s | |
78 { | |
79 //BES Control | |
80 uint32_t besctl; | |
81 //BES Global control | |
82 uint32_t besglobctl; | |
83 //Luma control (brightness and contrast) | |
84 uint32_t beslumactl; | |
85 //Line pitch | |
86 uint32_t bespitch; | |
87 | |
88 //Buffer A-1 Chroma 3 plane org | |
89 uint32_t besa1c3org; | |
90 //Buffer A-1 Chroma org | |
91 uint32_t besa1corg; | |
92 //Buffer A-1 Luma org | |
93 uint32_t besa1org; | |
94 | |
95 //Buffer A-2 Chroma 3 plane org | |
96 uint32_t besa2c3org; | |
97 //Buffer A-2 Chroma org | |
98 uint32_t besa2corg; | |
99 //Buffer A-2 Luma org | |
100 uint32_t besa2org; | |
101 | |
102 //Buffer B-1 Chroma 3 plane org | |
103 uint32_t besb1c3org; | |
104 //Buffer B-1 Chroma org | |
105 uint32_t besb1corg; | |
106 //Buffer B-1 Luma org | |
107 uint32_t besb1org; | |
108 | |
109 //Buffer B-2 Chroma 3 plane org | |
110 uint32_t besb2c3org; | |
111 //Buffer B-2 Chroma org | |
112 uint32_t besb2corg; | |
113 //Buffer B-2 Luma org | |
114 uint32_t besb2org; | |
115 | |
116 //BES Horizontal coord | |
117 uint32_t beshcoord; | |
118 //BES Horizontal inverse scaling [5.14] | |
119 uint32_t beshiscal; | |
120 //BES Horizontal source start [10.14] (for scaling) | |
121 uint32_t beshsrcst; | |
122 //BES Horizontal source ending [10.14] (for scaling) | |
123 uint32_t beshsrcend; | |
124 //BES Horizontal source last | |
125 uint32_t beshsrclst; | |
126 | |
127 | |
128 //BES Vertical coord | |
129 uint32_t besvcoord; | |
130 //BES Vertical inverse scaling [5.14] | |
131 uint32_t besviscal; | |
132 //BES Field 1 vertical source last position | |
133 uint32_t besv1srclst; | |
134 //BES Field 1 weight start | |
135 uint32_t besv1wght; | |
136 //BES Field 2 vertical source last position | |
137 uint32_t besv2srclst; | |
138 //BES Field 2 weight start | |
139 uint32_t besv2wght; | |
140 | |
141 } bes_registers_t; | |
142 | |
143 static bes_registers_t regs; | |
144 static uint32_t mga_vid_in_use = 0; | |
145 static uint32_t is_g400 = 0; | |
146 static uint32_t vid_src_ready = 0; | |
147 static uint32_t vid_overlay_on = 0; | |
148 | |
149 static uint8_t *mga_mmio_base = 0; | |
150 static uint32_t mga_mem_base = 0; | |
151 | |
57 | 152 static int mga_src_base = 0; // YUV buffer position in video memory |
153 | |
154 static uint32_t mga_ram_size = 0; // how much megabytes videoram we have | |
1 | 155 |
95 | 156 //static int mga_force_memsize = 0; |
90 | 157 |
95 | 158 MODULE_PARM(mga_ram_size, "i"); |
90 | 159 |
1 | 160 static struct pci_dev *pci_dev; |
161 | |
162 static mga_vid_config_t mga_config; | |
163 | |
48 | 164 static int mga_irq = -1; |
1 | 165 |
166 //All register offsets are converted to word aligned offsets (32 bit) | |
167 //because we want all our register accesses to be 32 bits | |
168 #define VCOUNT 0x1e20 | |
169 | |
170 #define PALWTADD 0x3c00 // Index register for X_DATAREG port | |
171 #define X_DATAREG 0x3c0a | |
172 | |
173 #define XMULCTRL 0x19 | |
174 #define BPP_8 0x00 | |
175 #define BPP_15 0x01 | |
176 #define BPP_16 0x02 | |
177 #define BPP_24 0x03 | |
178 #define BPP_32_DIR 0x04 | |
179 #define BPP_32_PAL 0x07 | |
180 | |
181 #define XCOLMSK 0x40 | |
182 #define X_COLKEY 0x42 | |
183 #define XKEYOPMODE 0x51 | |
184 #define XCOLMSK0RED 0x52 | |
185 #define XCOLMSK0GREEN 0x53 | |
186 #define XCOLMSK0BLUE 0x54 | |
187 #define XCOLKEY0RED 0x55 | |
188 #define XCOLKEY0GREEN 0x56 | |
189 #define XCOLKEY0BLUE 0x57 | |
190 | |
191 // Backend Scaler registers | |
192 #define BESCTL 0x3d20 | |
193 #define BESGLOBCTL 0x3dc0 | |
194 #define BESLUMACTL 0x3d40 | |
195 #define BESPITCH 0x3d24 | |
48 | 196 |
1 | 197 #define BESA1C3ORG 0x3d60 |
198 #define BESA1CORG 0x3d10 | |
199 #define BESA1ORG 0x3d00 | |
48 | 200 |
1 | 201 #define BESA2C3ORG 0x3d64 |
202 #define BESA2CORG 0x3d14 | |
203 #define BESA2ORG 0x3d04 | |
48 | 204 |
1 | 205 #define BESB1C3ORG 0x3d68 |
206 #define BESB1CORG 0x3d18 | |
207 #define BESB1ORG 0x3d08 | |
48 | 208 |
1 | 209 #define BESB2C3ORG 0x3d6C |
210 #define BESB2CORG 0x3d1C | |
211 #define BESB2ORG 0x3d0C | |
48 | 212 |
1 | 213 #define BESHCOORD 0x3d28 |
214 #define BESHISCAL 0x3d30 | |
215 #define BESHSRCEND 0x3d3C | |
216 #define BESHSRCLST 0x3d50 | |
217 #define BESHSRCST 0x3d38 | |
218 #define BESV1WGHT 0x3d48 | |
219 #define BESV2WGHT 0x3d4c | |
220 #define BESV1SRCLST 0x3d54 | |
221 #define BESV2SRCLST 0x3d58 | |
222 #define BESVISCAL 0x3d34 | |
223 #define BESVCOORD 0x3d2c | |
224 #define BESSTATUS 0x3dc4 | |
225 | |
48 | 226 #define CRTCX 0x1fd4 |
227 #define CRTCD 0x1fd5 | |
228 #define IEN 0x1e1c | |
229 #define ICLEAR 0x1e18 | |
230 #define STATUS 0x1e14 | |
231 | |
232 static int mga_next_frame=0; | |
1 | 233 |
234 static void mga_vid_frame_sel(int frame) | |
235 { | |
48 | 236 if ( mga_irq != -1 ) { |
237 mga_next_frame=frame; | |
238 } else { | |
239 | |
1 | 240 //we don't need the vcount protection as we're only hitting |
241 //one register (and it doesn't seem to be double buffered) | |
242 regs.besctl = (regs.besctl & ~0x07000000) + (frame << 25); | |
243 writel( regs.besctl, mga_mmio_base + BESCTL ); | |
68 | 244 |
245 // writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), | |
246 writel( regs.besglobctl + (MGA_VSYNC_POS<<16), | |
247 mga_mmio_base + BESGLOBCTL); | |
248 | |
48 | 249 } |
1 | 250 } |
251 | |
252 | |
253 static void mga_vid_write_regs(void) | |
254 { | |
255 //Make sure internal registers don't get updated until we're done | |
256 writel( (readl(mga_mmio_base + VCOUNT)-1)<<16, | |
257 mga_mmio_base + BESGLOBCTL); | |
258 | |
259 // color or coordinate keying | |
260 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); | |
261 writeb( mga_config.colkey_on, mga_mmio_base + X_DATAREG); | |
262 if ( mga_config.colkey_on ) | |
263 { | |
264 uint32_t r=0, g=0, b=0; | |
265 | |
266 writeb( XMULCTRL, mga_mmio_base + PALWTADD); | |
267 switch (readb (mga_mmio_base + X_DATAREG)) | |
268 { | |
269 case BPP_8: | |
270 /* Need to look up the color index, just using | |
271 color 0 for now. */ | |
272 break; | |
273 | |
274 case BPP_15: | |
275 r = mga_config.colkey_red >> 3; | |
276 g = mga_config.colkey_green >> 3; | |
277 b = mga_config.colkey_blue >> 3; | |
278 break; | |
279 | |
280 case BPP_16: | |
281 r = mga_config.colkey_red >> 3; | |
282 g = mga_config.colkey_green >> 2; | |
283 b = mga_config.colkey_blue >> 3; | |
284 break; | |
285 | |
286 case BPP_24: | |
287 case BPP_32_DIR: | |
288 case BPP_32_PAL: | |
289 r = mga_config.colkey_red; | |
290 g = mga_config.colkey_green; | |
291 b = mga_config.colkey_blue; | |
292 break; | |
293 } | |
294 | |
295 // Disable color keying on alpha channel | |
296 writeb( XCOLMSK, mga_mmio_base + PALWTADD); | |
297 writeb( 0x00, mga_mmio_base + X_DATAREG); | |
298 writeb( X_COLKEY, mga_mmio_base + PALWTADD); | |
299 writeb( 0x00, mga_mmio_base + X_DATAREG); | |
300 | |
301 // Set up color key registers | |
302 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); | |
303 writeb( r, mga_mmio_base + X_DATAREG); | |
304 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); | |
305 writeb( g, mga_mmio_base + X_DATAREG); | |
306 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); | |
307 writeb( b, mga_mmio_base + X_DATAREG); | |
308 | |
309 // Set up color key mask registers | |
310 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); | |
311 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
312 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); | |
313 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
314 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); | |
315 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
316 } | |
317 | |
318 // Backend Scaler | |
319 writel( regs.besctl, mga_mmio_base + BESCTL); | |
320 if(is_g400) | |
321 writel( regs.beslumactl, mga_mmio_base + BESLUMACTL); | |
322 writel( regs.bespitch, mga_mmio_base + BESPITCH); | |
323 | |
324 writel( regs.besa1org, mga_mmio_base + BESA1ORG); | |
325 writel( regs.besa1corg, mga_mmio_base + BESA1CORG); | |
48 | 326 writel( regs.besa2org, mga_mmio_base + BESA2ORG); |
327 writel( regs.besa2corg, mga_mmio_base + BESA2CORG); | |
1 | 328 writel( regs.besb1org, mga_mmio_base + BESB1ORG); |
329 writel( regs.besb1corg, mga_mmio_base + BESB1CORG); | |
48 | 330 writel( regs.besb2org, mga_mmio_base + BESB2ORG); |
331 writel( regs.besb2corg, mga_mmio_base + BESB2CORG); | |
1 | 332 if(is_g400) |
333 { | |
334 writel( regs.besa1c3org, mga_mmio_base + BESA1C3ORG); | |
48 | 335 writel( regs.besa2c3org, mga_mmio_base + BESA2C3ORG); |
1 | 336 writel( regs.besb1c3org, mga_mmio_base + BESB1C3ORG); |
48 | 337 writel( regs.besb2c3org, mga_mmio_base + BESB2C3ORG); |
1 | 338 } |
339 | |
340 writel( regs.beshcoord, mga_mmio_base + BESHCOORD); | |
341 writel( regs.beshiscal, mga_mmio_base + BESHISCAL); | |
342 writel( regs.beshsrcst, mga_mmio_base + BESHSRCST); | |
343 writel( regs.beshsrcend, mga_mmio_base + BESHSRCEND); | |
344 writel( regs.beshsrclst, mga_mmio_base + BESHSRCLST); | |
345 | |
346 writel( regs.besvcoord, mga_mmio_base + BESVCOORD); | |
347 writel( regs.besviscal, mga_mmio_base + BESVISCAL); | |
48 | 348 |
1 | 349 writel( regs.besv1srclst, mga_mmio_base + BESV1SRCLST); |
350 writel( regs.besv1wght, mga_mmio_base + BESV1WGHT); | |
48 | 351 writel( regs.besv2srclst, mga_mmio_base + BESV2SRCLST); |
352 writel( regs.besv2wght, mga_mmio_base + BESV2WGHT); | |
1 | 353 |
354 //update the registers somewhere between 1 and 2 frames from now. | |
355 writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), | |
356 mga_mmio_base + BESGLOBCTL); | |
357 | |
77 | 358 #if 0 |
61 | 359 printk(KERN_DEBUG "mga_vid: wrote BES registers\n"); |
360 printk(KERN_DEBUG "mga_vid: BESCTL = 0x%08x\n", | |
1 | 361 readl(mga_mmio_base + BESCTL)); |
61 | 362 printk(KERN_DEBUG "mga_vid: BESGLOBCTL = 0x%08x\n", |
1 | 363 readl(mga_mmio_base + BESGLOBCTL)); |
61 | 364 printk(KERN_DEBUG "mga_vid: BESSTATUS= 0x%08x\n", |
1 | 365 readl(mga_mmio_base + BESSTATUS)); |
77 | 366 #endif |
1 | 367 } |
368 | |
369 static int mga_vid_set_config(mga_vid_config_t *config) | |
370 { | |
371 int x, y, sw, sh, dw, dh; | |
372 int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights; | |
57 | 373 int frame_size=config->frame_size; |
1 | 374 x = config->x_org; |
375 y = config->y_org; | |
376 sw = config->src_width; | |
377 sh = config->src_height; | |
378 dw = config->dest_width; | |
379 dh = config->dest_height; | |
380 | |
61 | 381 printk(KERN_DEBUG "mga_vid: Setting up a %dx%d+%d+%d video window (src %dx%d) format %X\n", |
1 | 382 dw, dh, x, y, sw, sh, config->format); |
383 | |
384 //FIXME check that window is valid and inside desktop | |
385 | |
386 //FIXME figure out a better way to allocate memory on card | |
387 //allocate 2 megs | |
388 //mga_src_base = mga_mem_base + (MGA_VIDMEM_SIZE-2) * 0x100000; | |
57 | 389 //mga_src_base = (MGA_VIDMEM_SIZE-3) * 0x100000; |
1 | 390 |
391 | |
392 //Setup the BES registers for a three plane 4:2:0 video source | |
393 | |
466 | 394 regs.besglobctl = 0; |
395 | |
1 | 396 switch(config->format){ |
397 case MGA_VID_FORMAT_YV12: | |
470 | 398 case MGA_VID_FORMAT_I420: |
399 case MGA_VID_FORMAT_IYUV: | |
1 | 400 regs.besctl = 1 // BES enabled |
401 + (0<<6) // even start polarity | |
402 + (1<<10) // x filtering enabled | |
403 + (1<<11) // y filtering enabled | |
404 + (1<<16) // chroma upsampling | |
405 + (1<<17) // 4:2:0 mode | |
406 + (1<<18); // dither enabled | |
466 | 407 #if 0 |
1 | 408 if(is_g400) |
409 { | |
410 //zoom disabled, zoom filter disabled, 420 3 plane format, proc amp | |
411 //disabled, rgb mode disabled | |
412 regs.besglobctl = (1<<5); | |
413 } | |
414 else | |
415 { | |
416 //zoom disabled, zoom filter disabled, Cb samples in 0246, Cr | |
417 //in 1357, BES register update on besvcnt | |
466 | 418 regs.besglobctl = 0; |
1 | 419 } |
466 | 420 #endif |
1 | 421 break; |
422 | |
423 case MGA_VID_FORMAT_YUY2: | |
424 regs.besctl = 1 // BES enabled | |
425 + (0<<6) // even start polarity | |
426 + (1<<10) // x filtering enabled | |
427 + (1<<11) // y filtering enabled | |
428 + (1<<16) // chroma upsampling | |
429 + (0<<17) // 4:2:2 mode | |
430 + (1<<18); // dither enabled | |
431 | |
432 regs.besglobctl = 0; // YUY2 format selected | |
433 break; | |
466 | 434 |
435 case MGA_VID_FORMAT_UYVY: | |
436 regs.besctl = 1 // BES enabled | |
437 + (0<<6) // even start polarity | |
438 + (1<<10) // x filtering enabled | |
439 + (1<<11) // y filtering enabled | |
440 + (1<<16) // chroma upsampling | |
441 + (0<<17) // 4:2:2 mode | |
442 + (1<<18); // dither enabled | |
443 | |
444 regs.besglobctl = 1<<6; // UYVY format selected | |
445 break; | |
446 | |
1 | 447 default: |
61 | 448 printk(KERN_ERR "mga_vid: Unsupported pixel format: 0x%X\n",config->format); |
1 | 449 return -1; |
450 } | |
451 | |
452 | |
453 //Disable contrast and brightness control | |
466 | 454 regs.besglobctl |= (1<<5) + (1<<7); |
1 | 455 regs.beslumactl = (0x7f << 16) + (0x80<<0); |
456 regs.beslumactl = 0x80<<0; | |
457 | |
458 //Setup destination window boundaries | |
459 besleft = x > 0 ? x : 0; | |
460 bestop = y > 0 ? y : 0; | |
461 regs.beshcoord = (besleft<<16) + (x + dw-1); | |
462 regs.besvcoord = (bestop<<16) + (y + dh-1); | |
463 | |
464 //Setup source dimensions | |
465 regs.beshsrclst = (sw - 1) << 16; | |
466 regs.bespitch = (sw + 31) & ~31 ; | |
467 | |
468 //Setup horizontal scaling | |
469 ifactor = ((sw-1)<<14)/(dw-1); | |
470 ofsleft = besleft - x; | |
471 | |
472 regs.beshiscal = ifactor<<2; | |
473 regs.beshsrcst = (ofsleft*ifactor)<<2; | |
474 regs.beshsrcend = regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2); | |
475 | |
476 //Setup vertical scaling | |
477 ifactor = ((sh-1)<<14)/(dh-1); | |
478 ofstop = bestop - y; | |
479 | |
480 regs.besviscal = ifactor<<2; | |
481 | |
482 baseadrofs = ((ofstop*regs.besviscal)>>16)*regs.bespitch; | |
57 | 483 //frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2; |
1 | 484 regs.besa1org = (uint32_t) mga_src_base + baseadrofs; |
48 | 485 regs.besa2org = (uint32_t) mga_src_base + baseadrofs + 1*frame_size; |
486 regs.besb1org = (uint32_t) mga_src_base + baseadrofs + 2*frame_size; | |
487 regs.besb2org = (uint32_t) mga_src_base + baseadrofs + 3*frame_size; | |
1 | 488 |
470 | 489 if(config->format==MGA_VID_FORMAT_YV12 |
490 ||config->format==MGA_VID_FORMAT_IYUV | |
491 ||config->format==MGA_VID_FORMAT_I420 | |
492 ){ | |
57 | 493 // planar YUV frames: |
1 | 494 if (is_g400) |
495 baseadrofs = (((ofstop*regs.besviscal)/4)>>16)*regs.bespitch; | |
496 else | |
497 baseadrofs = (((ofstop*regs.besviscal)/2)>>16)*regs.bespitch; | |
498 | |
470 | 499 if(config->format==MGA_VID_FORMAT_YV12){ |
1 | 500 regs.besa1corg = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; |
48 | 501 regs.besa2corg = (uint32_t) mga_src_base + baseadrofs + 1*frame_size + regs.bespitch * sh; |
502 regs.besb1corg = (uint32_t) mga_src_base + baseadrofs + 2*frame_size + regs.bespitch * sh; | |
503 regs.besb2corg = (uint32_t) mga_src_base + baseadrofs + 3*frame_size + regs.bespitch * sh; | |
1 | 504 regs.besa1c3org = regs.besa1corg + ((regs.bespitch * sh) / 4); |
48 | 505 regs.besa2c3org = regs.besa2corg + ((regs.bespitch * sh) / 4); |
1 | 506 regs.besb1c3org = regs.besb1corg + ((regs.bespitch * sh) / 4); |
48 | 507 regs.besb2c3org = regs.besb2corg + ((regs.bespitch * sh) / 4); |
470 | 508 } else { |
509 regs.besa1c3org = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; | |
510 regs.besa2c3org = (uint32_t) mga_src_base + baseadrofs + 1*frame_size + regs.bespitch * sh; | |
511 regs.besb1c3org = (uint32_t) mga_src_base + baseadrofs + 2*frame_size + regs.bespitch * sh; | |
512 regs.besb2c3org = (uint32_t) mga_src_base + baseadrofs + 3*frame_size + regs.bespitch * sh; | |
513 regs.besa1corg = regs.besa1c3org + ((regs.bespitch * sh) / 4); | |
514 regs.besa2corg = regs.besa2c3org + ((regs.bespitch * sh) / 4); | |
515 regs.besb1corg = regs.besb1c3org + ((regs.bespitch * sh) / 4); | |
516 regs.besb2corg = regs.besb2c3org + ((regs.bespitch * sh) / 4); | |
517 } | |
518 | |
57 | 519 } |
1 | 520 |
521 weight = ofstop * (regs.besviscal >> 2); | |
522 weights = weight < 0 ? 1 : 0; | |
48 | 523 regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2); |
524 regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF); | |
1 | 525 |
526 mga_vid_write_regs(); | |
527 return 0; | |
528 } | |
529 | |
68 | 530 #ifdef MGA_ALLOW_IRQ |
531 | |
48 | 532 static void enable_irq(){ |
533 long int cc; | |
534 | |
535 cc = readl(mga_mmio_base + IEN); | |
63 | 536 // printk(KERN_ALERT "*** !!! IRQREG = %d\n", (int)(cc&0xff)); |
48 | 537 |
538 writeb( 0x11, mga_mmio_base + CRTCX); | |
539 | |
540 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ | |
541 writeb(0x00, mga_mmio_base + CRTCD ); /* enable on */ | |
542 writeb(0x10, mga_mmio_base + CRTCD ); /* clear = 1 */ | |
543 | |
544 writel( regs.besglobctl , mga_mmio_base + BESGLOBCTL); | |
545 | |
546 } | |
547 | |
548 static void disable_irq(){ | |
549 | |
550 writeb( 0x11, mga_mmio_base + CRTCX); | |
551 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ | |
552 | |
553 } | |
554 | |
555 void mga_handle_irq(int irq, void *dev_id, struct pt_regs *pregs) { | |
556 // static int frame=0; | |
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557 // static int counter=0; |
48 | 558 long int cc; |
559 // if ( ! mga_enabled_flag ) return; | |
560 | |
68 | 561 // printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT)); |
562 | |
48 | 563 //printk("mga_interrupt #%d\n", irq); |
564 | |
565 if ( irq != -1 ) { | |
566 | |
567 cc = readl(mga_mmio_base + STATUS); | |
568 if ( ! (cc & 0x10) ) return; /* vsyncpen */ | |
569 // debug_irqcnt++; | |
570 } | |
571 | |
572 // if ( debug_irqignore ) { | |
573 // debug_irqignore = 0; | |
574 | |
575 | |
576 /* | |
577 if ( mga_conf_deinterlace ) { | |
578 if ( mga_first_field ) { | |
579 // printk("mga_interrupt first field\n"); | |
580 if ( syncfb_interrupt() ) | |
581 mga_first_field = 0; | |
582 } else { | |
583 // printk("mga_interrupt second field\n"); | |
584 mga_select_buffer( mga_current_field | 2 ); | |
585 mga_first_field = 1; | |
586 } | |
587 } else { | |
588 syncfb_interrupt(); | |
589 } | |
590 */ | |
591 | |
592 // frame=(frame+1)&1; | |
593 regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25); | |
594 writel( regs.besctl, mga_mmio_base + BESCTL ); | |
595 | |
596 #if 0 | |
597 ++counter; | |
598 if(!(counter&63)){ | |
599 printk("mga irq counter = %d\n",counter); | |
600 } | |
601 #endif | |
602 | |
603 // } else { | |
604 // debug_irqignore = 1; | |
605 // } | |
606 | |
607 if ( irq != -1 ) { | |
608 writeb( 0x11, mga_mmio_base + CRTCX); | |
609 writeb( 0, mga_mmio_base + CRTCD ); | |
610 writeb( 0x10, mga_mmio_base + CRTCD ); | |
611 } | |
612 | |
613 // writel( regs.besglobctl, mga_mmio_base + BESGLOBCTL); | |
614 | |
615 | |
616 return; | |
617 | |
618 } | |
619 | |
68 | 620 #endif |
1 | 621 |
622 static int mga_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) | |
623 { | |
624 int frame; | |
625 | |
626 switch(cmd) | |
627 { | |
628 case MGA_VID_CONFIG: | |
629 //FIXME remove | |
68 | 630 // printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT)); |
61 | 631 printk(KERN_DEBUG "mga_mmio_base = %p\n",mga_mmio_base); |
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632 printk(KERN_DEBUG "mga_mem_base = %08x\n",mga_mem_base); |
1 | 633 //FIXME remove |
634 | |
61 | 635 printk(KERN_DEBUG "mga_vid: Received configuration\n"); |
1 | 636 |
637 if(copy_from_user(&mga_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t))) | |
638 { | |
61 | 639 printk(KERN_ERR "mga_vid: failed copy from userspace\n"); |
1 | 640 return(-EFAULT); |
641 } | |
57 | 642 if(mga_config.version != MGA_VID_VERSION){ |
61 | 643 printk(KERN_ERR "mga_vid: incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,mga_config.version); |
57 | 644 return(-EFAULT); |
645 } | |
646 | |
647 if(mga_config.frame_size==0 || mga_config.frame_size>1024*768*2){ | |
61 | 648 printk(KERN_ERR "mga_vid: illegal frame_size: %d\n",mga_config.frame_size); |
57 | 649 return(-EFAULT); |
650 } | |
651 | |
652 if(mga_config.num_frames<1 || mga_config.num_frames>4){ | |
61 | 653 printk(KERN_ERR "mga_vid: illegal num_frames: %d\n",mga_config.num_frames); |
57 | 654 return(-EFAULT); |
655 } | |
656 | |
657 mga_src_base = (mga_ram_size*0x100000-mga_config.num_frames*mga_config.frame_size); | |
658 if(mga_src_base<0){ | |
61 | 659 printk(KERN_ERR "mga_vid: not enough memory for frames!\n"); |
57 | 660 return(-EFAULT); |
661 } | |
662 mga_src_base &= (~0xFFFF); // 64k boundary | |
61 | 663 printk(KERN_DEBUG "mga YUV buffer base: 0x%X\n", mga_src_base); |
57 | 664 |
1 | 665 if (is_g400) |
666 mga_config.card_type = MGA_G400; | |
667 else | |
668 mga_config.card_type = MGA_G200; | |
669 | |
670 mga_config.ram_size = mga_ram_size; | |
671 | |
672 if (copy_to_user((mga_vid_config_t *) arg, &mga_config, sizeof(mga_vid_config_t))) | |
673 { | |
61 | 674 printk(KERN_ERR "mga_vid: failed copy to userspace\n"); |
1 | 675 return(-EFAULT); |
676 } | |
677 return mga_vid_set_config(&mga_config); | |
678 break; | |
679 | |
680 case MGA_VID_ON: | |
61 | 681 printk(KERN_DEBUG "mga_vid: Video ON\n"); |
1 | 682 vid_src_ready = 1; |
683 if(vid_overlay_on) | |
684 { | |
685 regs.besctl |= 1; | |
686 mga_vid_write_regs(); | |
687 } | |
68 | 688 #ifdef MGA_ALLOW_IRQ |
48 | 689 if ( mga_irq != -1 ) enable_irq(); |
68 | 690 #endif |
48 | 691 mga_next_frame=0; |
1 | 692 break; |
693 | |
694 case MGA_VID_OFF: | |
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695 printk(KERN_DEBUG "mga_vid: Video OFF (ioctl)\n"); |
1 | 696 vid_src_ready = 0; |
68 | 697 #ifdef MGA_ALLOW_IRQ |
48 | 698 if ( mga_irq != -1 ) disable_irq(); |
68 | 699 #endif |
1 | 700 regs.besctl &= ~1; |
466 | 701 regs.besglobctl &= ~(1<<6); // UYVY format selected |
1 | 702 mga_vid_write_regs(); |
703 break; | |
704 | |
705 case MGA_VID_FSEL: | |
706 if(copy_from_user(&frame,(int *) arg,sizeof(int))) | |
707 { | |
61 | 708 printk(KERN_ERR "mga_vid: FSEL failed copy from userspace\n"); |
1 | 709 return(-EFAULT); |
710 } | |
711 | |
712 mga_vid_frame_sel(frame); | |
713 break; | |
714 | |
715 default: | |
61 | 716 printk(KERN_ERR "mga_vid: Invalid ioctl\n"); |
1 | 717 return (-EINVAL); |
718 } | |
719 | |
720 return 0; | |
721 } | |
722 | |
723 | |
724 static int mga_vid_find_card(void) | |
725 { | |
726 struct pci_dev *dev = NULL; | |
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727 unsigned int card_option; |
1 | 728 |
729 if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400, NULL))) | |
730 { | |
731 is_g400 = 1; | |
77 | 732 printk(KERN_INFO "mga_vid: Found MGA G400/G450\n"); |
1 | 733 } |
734 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, NULL))) | |
735 { | |
736 is_g400 = 0; | |
63 | 737 printk(KERN_INFO "mga_vid: Found MGA G200 AGP\n"); |
1 | 738 } |
739 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_PCI, NULL))) | |
740 { | |
741 is_g400 = 0; | |
63 | 742 printk(KERN_INFO "mga_vid: Found MGA G200 PCI\n"); |
1 | 743 } |
744 else | |
745 { | |
61 | 746 printk(KERN_ERR "mga_vid: No supported cards found\n"); |
1 | 747 return FALSE; |
748 } | |
749 | |
750 pci_dev = dev; | |
48 | 751 |
752 mga_irq = pci_dev->irq; | |
1 | 753 |
754 #if LINUX_VERSION_CODE >= 0x020300 | |
755 mga_mmio_base = ioremap_nocache(dev->resource[1].start,0x4000); | |
756 mga_mem_base = dev->resource[0].start; | |
757 #else | |
758 mga_mmio_base = ioremap_nocache(dev->base_address[1] & PCI_BASE_ADDRESS_MEM_MASK,0x4000); | |
759 mga_mem_base = dev->base_address[0] & PCI_BASE_ADDRESS_MEM_MASK; | |
760 #endif | |
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761 printk(KERN_INFO "mga_vid: MMIO at 0x%p IRQ: %d framebuffer: 0x%08X\n", mga_mmio_base, mga_irq, mga_mem_base); |
1 | 762 |
763 pci_read_config_dword(dev, 0x40, &card_option); | |
77 | 764 printk(KERN_INFO "mga_vid: OPTION word: 0x%08X mem: 0x%02X %s\n", card_option, |
765 (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM"); | |
1 | 766 |
57 | 767 // temp = (card_option >> 10) & 0x17; |
768 | |
95 | 769 if (mga_ram_size) { |
770 printk(KERN_INFO "mga_vid: RAMSIZE forced to %d MB\n", mga_ram_size); | |
91 | 771 } else { |
90 | 772 |
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773 #ifdef MGA_MEMORY_SIZE |
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774 mga_ram_size = MGA_MEMORY_SIZE; |
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775 printk(KERN_INFO "mga_vid: hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); |
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776 |
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777 #else |
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778 |
95 | 779 if (is_g400){ |
75 | 780 switch((card_option>>10)&0x17){ |
781 // SDRAM: | |
782 case 0x00: | |
783 case 0x04: mga_ram_size = 16; break; | |
105 | 784 case 0x03: mga_ram_size = 32; break; |
75 | 785 // SGRAM: |
786 case 0x10: | |
787 case 0x14: mga_ram_size = 32; break; | |
788 case 0x11: | |
789 case 0x12: mga_ram_size = 16; break; | |
790 default: | |
791 mga_ram_size = 16; | |
792 printk(KERN_INFO "mga_vid: Couldn't detect RAMSIZE, assuming 16MB!"); | |
793 } | |
95 | 794 }else{ |
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795 switch((card_option>>10)&0x17){ |
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796 // case 0x10: |
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797 // case 0x13: mga_ram_size = 8; break; |
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798 default: mga_ram_size = 8; |
64 | 799 } |
95 | 800 } |
64 | 801 #if 0 |
95 | 802 // printk("List resources -----------\n"); |
803 for(temp=0;temp<DEVICE_COUNT_RESOURCE;temp++){ | |
804 struct resource *res=&pci_dev->resource[temp]; | |
805 if(res->flags){ | |
806 int size=(1+res->end-res->start)>>20; | |
807 printk(KERN_DEBUG "res %d: start: 0x%X end: 0x%X (%d MB) flags=0x%X\n",temp,res->start,res->end,size,res->flags); | |
808 if(res->flags&(IORESOURCE_MEM|IORESOURCE_PREFETCH)){ | |
809 if(size>mga_ram_size && size<=64) mga_ram_size=size; | |
810 } | |
811 } | |
57 | 812 } |
64 | 813 #endif |
95 | 814 printk(KERN_INFO "mga_vid: detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); |
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815 #endif |
95 | 816 } |
57 | 817 |
48 | 818 |
68 | 819 #ifdef MGA_ALLOW_IRQ |
48 | 820 if ( mga_irq != -1 ) { |
821 int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq); | |
822 if ( tmp ) { | |
61 | 823 printk(KERN_INFO "syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp); |
48 | 824 mga_irq=-1; |
825 } else { | |
61 | 826 printk(KERN_DEBUG "syncfb (mga): registered irq %d\n", mga_irq); |
48 | 827 } |
828 } else { | |
61 | 829 printk(KERN_INFO "syncfb (mga): No valid irq was found\n"); |
48 | 830 mga_irq=-1; |
831 } | |
68 | 832 #else |
833 printk(KERN_INFO "syncfb (mga): IRQ disabled in mga_vid.c\n"); | |
834 mga_irq=-1; | |
835 #endif | |
48 | 836 |
1 | 837 return TRUE; |
838 } | |
839 | |
840 | |
841 static ssize_t mga_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) | |
842 { | |
843 return -EINVAL; | |
844 } | |
845 | |
846 static ssize_t mga_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) | |
847 { | |
848 return -EINVAL; | |
849 } | |
850 | |
851 static int mga_vid_mmap(struct file *file, struct vm_area_struct *vma) | |
852 { | |
853 | |
61 | 854 printk(KERN_DEBUG "mga_vid: mapping video memory into userspace\n"); |
57 | 855 if(remap_page_range(vma->vm_start, mga_mem_base + mga_src_base, |
1 | 856 vma->vm_end - vma->vm_start, vma->vm_page_prot)) |
857 { | |
63 | 858 printk(KERN_ERR "mga_vid: error mapping video memory\n"); |
1 | 859 return(-EAGAIN); |
860 } | |
861 | |
862 return(0); | |
863 } | |
864 | |
865 static int mga_vid_release(struct inode *inode, struct file *file) | |
866 { | |
867 //Close the window just in case | |
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868 printk(KERN_DEBUG "mga_vid: Video OFF (release)\n"); |
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869 |
1 | 870 vid_src_ready = 0; |
871 regs.besctl &= ~1; | |
466 | 872 regs.besglobctl &= ~(1<<6); // UYVY format selected |
1 | 873 mga_vid_write_regs(); |
874 mga_vid_in_use = 0; | |
875 | |
93 | 876 MOD_DEC_USE_COUNT; |
1 | 877 return 0; |
878 } | |
879 | |
880 static long long mga_vid_lseek(struct file *file, long long offset, int origin) | |
881 { | |
882 return -ESPIPE; | |
883 } | |
884 | |
885 static int mga_vid_open(struct inode *inode, struct file *file) | |
886 { | |
887 int minor = MINOR(inode->i_rdev); | |
888 | |
889 if(minor != 0) | |
890 return(-ENXIO); | |
891 | |
892 if(mga_vid_in_use == 1) | |
893 return(-EBUSY); | |
894 | |
895 mga_vid_in_use = 1; | |
93 | 896 MOD_INC_USE_COUNT; |
1 | 897 return(0); |
898 } | |
899 | |
900 #if LINUX_VERSION_CODE >= 0x020400 | |
901 static struct file_operations mga_vid_fops = | |
902 { | |
903 llseek: mga_vid_lseek, | |
904 read: mga_vid_read, | |
905 write: mga_vid_write, | |
906 ioctl: mga_vid_ioctl, | |
907 mmap: mga_vid_mmap, | |
908 open: mga_vid_open, | |
909 release: mga_vid_release | |
910 }; | |
911 #else | |
912 static struct file_operations mga_vid_fops = | |
913 { | |
914 mga_vid_lseek, | |
915 mga_vid_read, | |
916 mga_vid_write, | |
917 NULL, | |
918 NULL, | |
919 mga_vid_ioctl, | |
920 mga_vid_mmap, | |
921 mga_vid_open, | |
922 NULL, | |
923 mga_vid_release | |
924 }; | |
925 #endif | |
926 | |
927 | |
928 /* | |
929 * Main Initialization Function | |
930 */ | |
931 | |
932 static int mga_vid_initialize(void) | |
933 { | |
934 mga_vid_in_use = 0; | |
935 | |
77 | 936 // printk(KERN_INFO "Matrox MGA G200/G400 YUV Video interface v0.01 (c) Aaron Holtzman \n"); |
937 printk(KERN_INFO "Matrox MGA G200/G400/G450 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n"); | |
90 | 938 |
95 | 939 if (mga_ram_size) { |
940 if (mga_ram_size<4 || mga_ram_size>64) { | |
941 printk(KERN_ERR "mga_vid: invalid RAMSIZE: %d MB\n", mga_ram_size); | |
90 | 942 return -EINVAL; |
943 } | |
944 } | |
945 | |
1 | 946 if(register_chrdev(MGA_VID_MAJOR, "mga_vid", &mga_vid_fops)) |
947 { | |
61 | 948 printk(KERN_ERR "mga_vid: unable to get major: %d\n", MGA_VID_MAJOR); |
1 | 949 return -EIO; |
950 } | |
951 | |
952 if (!mga_vid_find_card()) | |
953 { | |
61 | 954 printk(KERN_ERR "mga_vid: no supported devices found\n"); |
1 | 955 unregister_chrdev(MGA_VID_MAJOR, "mga_vid"); |
956 return -EINVAL; | |
957 } | |
958 | |
959 return(0); | |
960 } | |
961 | |
962 int init_module(void) | |
963 { | |
964 return mga_vid_initialize(); | |
965 } | |
966 | |
967 void cleanup_module(void) | |
968 { | |
48 | 969 |
68 | 970 #ifdef MGA_ALLOW_IRQ |
48 | 971 if ( mga_irq != -1) |
972 free_irq(mga_irq, &mga_irq); | |
68 | 973 #endif |
48 | 974 |
1 | 975 if(mga_mmio_base) |
976 iounmap(mga_mmio_base); | |
977 | |
978 //FIXME turn off BES | |
63 | 979 printk(KERN_INFO "mga_vid: Cleaning up module\n"); |
1 | 980 unregister_chrdev(MGA_VID_MAJOR, "mga_vid"); |
981 } | |
982 |