Mercurial > mplayer.hg
annotate vidix/nvidia_vid.c @ 22864:e15beff67d91
Move pci.db out of its single-file subdirectory.
author | diego |
---|---|
date | Sun, 01 Apr 2007 12:31:15 +0000 |
parents | 6c57087c5a2d |
children | 9a8f6901e888 |
rev | line source |
---|---|
22850 | 1 /* |
2 nvidia_vid - VIDIX based video driver for NVIDIA chips | |
3 Copyrights 2003 - 2004 Sascha Sommer. This file is based on sources from | |
4 RIVATV (rivatv.sf.net) | |
5 Licence: GPL | |
6 WARNING: THIS DRIVER IS IN BETA STAGE | |
7 | |
8 multi buffer support and TNT2 fixes by Dmitry Baryshkov | |
9 */ | |
10 | |
11 | |
12 #include <errno.h> | |
13 #include <stdio.h> | |
14 #include <stdlib.h> | |
15 #include <string.h> | |
16 #include <math.h> | |
17 #include <inttypes.h> | |
18 #include <unistd.h> | |
19 | |
20 | |
21 #include "vidix.h" | |
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22850
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22 #include "vidixlib.h" |
22850 | 23 #include "fourcc.h" |
24 #include "../libdha/libdha.h" | |
25 #include "../libdha/pci_ids.h" | |
26 #include "../libdha/pci_names.h" | |
27 #include "../config.h" | |
28 #include "../libavutil/common.h" | |
29 #include "../mpbswap.h" | |
30 | |
31 | |
32 pciinfo_t pci_info; | |
33 | |
34 | |
35 #define MAX_FRAMES 3 | |
36 #define NV04_BES_SIZE 1024*2000*4 | |
37 | |
38 | |
39 static vidix_capability_t nvidia_cap = { | |
40 "NVIDIA RIVA OVERLAY DRIVER", | |
41 "Sascha Sommer <saschasommer@freenet.de>", | |
42 TYPE_OUTPUT, | |
43 { 0, 0, 0, 0 }, | |
44 2046, | |
45 2046, | |
46 4, | |
47 4, | |
48 -1, | |
49 FLAG_UPSCALER|FLAG_DOWNSCALER, | |
50 VENDOR_NVIDIA2, | |
51 -1, | |
52 { 0, 0, 0, 0 } | |
53 }; | |
54 | |
55 #define NV_ARCH_03 0x03 | |
56 #define NV_ARCH_04 0x04 | |
57 #define NV_ARCH_10 0x10 | |
58 #define NV_ARCH_20 0x20 | |
59 #define NV_ARCH_30 0x30 | |
60 | |
61 // since no useful information whatsoever is passed | |
62 // to the equalizer functions we need this | |
63 static struct { | |
64 uint32_t lum; // luminance (brightness + contrast) | |
65 uint32_t chrom; // chrominance (saturation + hue) | |
66 uint8_t red_off; // for NV03/NV04 | |
67 uint8_t green_off; | |
68 uint8_t blue_off; | |
69 vidix_video_eq_t vals; | |
70 } eq; | |
71 | |
72 struct nvidia_cards { | |
73 unsigned short chip_id; | |
74 unsigned short arch; | |
75 }; | |
76 | |
77 | |
78 static struct nvidia_cards nvidia_card_ids[] = { | |
79 /*NV03*/ | |
80 {DEVICE_NVIDIA2_RIVA128, NV_ARCH_03}, | |
81 {DEVICE_NVIDIA2_RIVA128ZX,NV_ARCH_03}, | |
82 /*NV04*/ | |
83 {DEVICE_NVIDIA_NV4_RIVA_TNT,NV_ARCH_04}, | |
84 {DEVICE_NVIDIA_NV5_RIVA_TNT2,NV_ARCH_04}, | |
85 {DEVICE_NVIDIA_NV5_RIVA_TNT22,NV_ARCH_04}, | |
86 {DEVICE_NVIDIA_NV5_RIVA_TNT23,NV_ARCH_04}, | |
87 {DEVICE_NVIDIA_NV5_RIVA_TNT24,NV_ARCH_04}, | |
88 {DEVICE_NVIDIA_NV6_VANTA,NV_ARCH_04}, | |
89 {DEVICE_NVIDIA_RIVA_TNT2_MODEL,NV_ARCH_04}, | |
90 {DEVICE_NVIDIA_NV6_VANTA2,NV_ARCH_04}, | |
91 {DEVICE_NVIDIA_NV6_VANTA3,NV_ARCH_04}, | |
92 {DEVICE_NVIDIA_NV5_RIVA_TNT25,NV_ARCH_04}, | |
93 {DEVICE_NVIDIA2_TNT,NV_ARCH_04}, | |
94 {DEVICE_NVIDIA2_TNT2,NV_ARCH_04}, | |
95 {DEVICE_NVIDIA2_VTNT2,NV_ARCH_04}, | |
96 {DEVICE_NVIDIA2_UTNT2 ,NV_ARCH_04}, | |
97 {DEVICE_NVIDIA2_ITNT2,NV_ARCH_04}, | |
98 /*NV10*/ | |
99 {DEVICE_NVIDIA_NV10_GEFORCE_256,NV_ARCH_10}, | |
100 {DEVICE_NVIDIA_NV10_GEFORCE_2562,NV_ARCH_10}, | |
101 {DEVICE_NVIDIA_NV11_GEFORCE2_MX,NV_ARCH_10}, | |
102 {DEVICE_NVIDIA_NV11_GEFORCE2_MX2,NV_ARCH_10}, | |
103 {DEVICE_NVIDIA_NV11_GEFORCE2_GO,NV_ARCH_10}, | |
104 {DEVICE_NVIDIA_NV11_GEFORCE2_MXR ,NV_ARCH_10}, | |
105 {DEVICE_NVIDIA_NV15_GEFORCE2_GTS,NV_ARCH_10}, | |
106 {DEVICE_NVIDIA_NV15_GEFORCE2_TI,NV_ARCH_10}, | |
107 {DEVICE_NVIDIA_NV15_GEFORCE2_ULTRA,NV_ARCH_10}, | |
108 {DEVICE_NVIDIA_NV17_GEFORCE4_MX460,NV_ARCH_10}, | |
109 {DEVICE_NVIDIA_NV17_GEFORCE4_MX440,NV_ARCH_10}, | |
110 {DEVICE_NVIDIA_NV17_GEFORCE4_MX420,NV_ARCH_10}, | |
111 {DEVICE_NVIDIA_NV17_GEFORCE4_440,NV_ARCH_10}, | |
112 {DEVICE_NVIDIA_NV17_GEFORCE4_420,NV_ARCH_10}, | |
113 {DEVICE_NVIDIA_NV17_GEFORCE4_4202,NV_ARCH_10}, | |
114 {DEVICE_NVIDIA_NV17_GEFORCE4_4402,NV_ARCH_10}, | |
115 {DEVICE_NVIDIA_NV18_GEFORCE4_MX440,NV_ARCH_10}, | |
116 {DEVICE_NVIDIA_NV15_GEFORCE2,NV_ARCH_10}, | |
117 /*NV20*/ | |
118 {DEVICE_NVIDIA_NV20_GEFORCE3,NV_ARCH_20}, | |
119 {DEVICE_NVIDIA_NV20_GEFORCE3_TI200,NV_ARCH_20}, | |
120 {DEVICE_NVIDIA_NV20_GEFORCE3_TI500,NV_ARCH_20}, | |
121 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4600,NV_ARCH_20}, | |
122 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4400,NV_ARCH_20}, | |
123 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4200,NV_ARCH_20}, | |
124 {DEVICE_NVIDIA_QUADRO4_900XGL,NV_ARCH_20}, | |
125 {DEVICE_NVIDIA_QUADRO4_750XGL,NV_ARCH_20}, | |
126 {DEVICE_NVIDIA_QUADRO4_700XGL,NV_ARCH_20}, | |
127 {DEVICE_NVIDIA_NV28_GEFORCE4_TI,NV_ARCH_20}, | |
128 {DEVICE_NVIDIA_NV28_GEFORCE4_TI2,NV_ARCH_20}, | |
129 {DEVICE_NVIDIA_NV28_GEFORCE4_TI3,NV_ARCH_20}, | |
130 {DEVICE_NVIDIA_NV28_GEFORCE4_TI4,NV_ARCH_20}, | |
131 {DEVICE_NVIDIA_NV28GL_QUADRO4_980,NV_ARCH_20}, | |
132 {DEVICE_NVIDIA_NV28GL_QUADRO4_780,NV_ARCH_20}, | |
133 /*NV30*/ | |
134 {DEVICE_NVIDIA_NV30_GEFORCE_FX,NV_ARCH_30}, | |
135 {DEVICE_NVIDIA_NV30_GEFORCE_FX2,NV_ARCH_30}, | |
136 {DEVICE_NVIDIA_NV30_GEFORCE_FX3,NV_ARCH_30}, | |
137 {DEVICE_NVIDIA_NV30GL_QUADRO_FX,NV_ARCH_30}, | |
138 {DEVICE_NVIDIA_NV30GL_QUADRO_FX2,NV_ARCH_30}, | |
139 {DEVICE_NVIDIA_NV31_GEFORCE_FX,NV_ARCH_30}, | |
140 {DEVICE_NVIDIA_NV31_GEFORCE_FX2,NV_ARCH_30}, | |
141 {DEVICE_NVIDIA_NV34_GEFORCE_FX,NV_ARCH_30}, | |
142 {DEVICE_NVIDIA_NV34_GEFORCE_FX2,NV_ARCH_30}, | |
143 {DEVICE_NVIDIA_NV34_GEFORCE_FX3,NV_ARCH_30}, | |
144 {DEVICE_NVIDIA_NV34M_GEFORCE_FX,NV_ARCH_30}, | |
145 {DEVICE_NVIDIA_NV34GL_QUADRO_FX,NV_ARCH_30}, | |
146 {DEVICE_NVIDIA_NV35_GEFORCE_FX,NV_ARCH_30}, | |
147 {DEVICE_NVIDIA_NV35_GEFORCE_FX2,NV_ARCH_30}, | |
148 {DEVICE_NVIDIA_NV35GL_QUADRO_FX,NV_ARCH_30}, | |
149 {DEVICE_NVIDIA_NV36_GEFORCE_FX,NV_ARCH_30}, | |
150 }; | |
151 | |
152 | |
153 static int find_chip(unsigned chip_id){ | |
154 unsigned i; | |
155 for(i = 0;i < sizeof(nvidia_card_ids)/sizeof(struct nvidia_cards);i++) | |
156 { | |
157 if(chip_id == nvidia_card_ids[i].chip_id)return i; | |
158 } | |
159 return -1; | |
160 } | |
161 | |
22857
77def5093daf
switch to new internal vidix API, no more dlopen/dlsym, libvidix is now a fully static library with all drivers built-in
ben
parents:
22850
diff
changeset
|
162 static int nv_probe(int verbose, int force){ |
22850 | 163 pciinfo_t lst[MAX_PCI_DEVICES]; |
164 unsigned i,num_pci; | |
165 int err; | |
166 | |
167 if (force) | |
168 printf("[nvidia_vid]: warning: forcing not supported yet!\n"); | |
169 err = pci_scan(lst,&num_pci); | |
170 if(err){ | |
171 printf("[nvidia_vid] Error occurred during pci scan: %s\n",strerror(err)); | |
172 return err; | |
173 } | |
174 else { | |
175 err = ENXIO; | |
176 for(i=0; i < num_pci; i++){ | |
177 if(lst[i].vendor == VENDOR_NVIDIA2 || lst[i].vendor == VENDOR_NVIDIA){ | |
178 int idx; | |
179 const char *dname; | |
180 idx = find_chip(lst[i].device); | |
181 if(idx == -1) | |
182 continue; | |
183 dname = pci_device_name(lst[i].vendor, lst[i].device); | |
184 dname = dname ? dname : "Unknown chip"; | |
185 printf("[nvidia_vid] Found chip: %s\n", dname); | |
186 if ((lst[i].command & PCI_COMMAND_IO) == 0){ | |
187 printf("[nvidia_vid] Device is disabled, ignoring\n"); | |
188 continue; | |
189 } | |
190 nvidia_cap.device_id = lst[i].device; | |
191 err = 0; | |
192 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); | |
193 break; | |
194 } | |
195 } | |
196 } | |
197 if(err && verbose) printf("[nvidia_vid] Can't find chip\n"); | |
198 return err; | |
199 } | |
200 | |
201 | |
202 | |
203 | |
204 /* | |
205 * PCI-Memory IO access macros. | |
206 */ | |
207 | |
208 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") | |
209 | |
210 #undef VID_WR08 | |
211 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) | |
212 #undef VID_RD08 | |
213 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) | |
214 | |
215 #undef VID_WR32 | |
216 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=val; }) | |
217 #undef VID_RD32 | |
218 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) | |
219 | |
220 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) | |
221 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) | |
222 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) | |
223 | |
224 | |
225 | |
226 | |
227 | |
228 | |
229 struct rivatv_chip { | |
230 volatile uint32_t *PMC; /* general control */ | |
231 volatile uint32_t *PME; /* multimedia port */ | |
232 volatile uint32_t *PFB; /* framebuffer control */ | |
233 volatile uint32_t *PVIDEO; /* overlay control */ | |
234 volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ | |
235 volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ | |
236 volatile uint32_t *PRAMIN; /* instance memory */ | |
237 volatile uint32_t *PRAMHT; /* hash table */ | |
238 volatile uint32_t *PRAMFC; /* fifo context table */ | |
239 volatile uint32_t *PRAMRO; /* fifo runout table */ | |
240 volatile uint32_t *PFIFO; /* fifo control region */ | |
241 volatile uint32_t *FIFO; /* fifo channels (USER) */ | |
242 volatile uint32_t *PGRAPH; /* graphics engine */ | |
243 | |
244 unsigned long fbsize; /* framebuffer size */ | |
245 int arch; /* compatible NV_ARCH_XX define */ | |
246 int realarch; /* real architecture */ | |
247 void (* lock) (struct rivatv_chip *, int); | |
248 }; | |
249 typedef struct rivatv_chip rivatv_chip; | |
250 | |
251 | |
252 struct rivatv_info { | |
253 unsigned int use_colorkey; | |
254 unsigned int colorkey; /* saved xv colorkey*/ | |
255 unsigned int vidixcolorkey; /*currently used colorkey*/ | |
256 unsigned int depth; | |
257 unsigned int format; | |
258 unsigned int pitch; | |
259 unsigned int width,height; | |
260 unsigned int d_width,d_height; /*scaled width && height*/ | |
261 unsigned int wx,wy; /*window x && y*/ | |
262 unsigned int screen_x; /*screen width*/ | |
263 unsigned int screen_y; /*screen height*/ | |
264 unsigned long buffer_size; /* size of the image buffer */ | |
265 struct rivatv_chip chip; /* NV architecture structure */ | |
266 void* video_base; /* virtual address of control region */ | |
267 void* control_base; /* virtual address of fb region */ | |
268 void* picture_base; /* direct pointer to video picture */ | |
269 unsigned long picture_offset; /* offset of video picture in frame buffer */ | |
270 // struct rivatv_dma dma; /* DMA structure */ | |
271 unsigned int cur_frame; | |
272 unsigned int num_frames; /* number of buffers */ | |
273 int bps; /* bytes per line */ | |
274 }; | |
275 typedef struct rivatv_info rivatv_info; | |
276 | |
277 //framebuffer size funcs | |
278 static unsigned long rivatv_fbsize_nv03 (struct rivatv_chip *chip){ | |
279 if (VID_RD32 (chip->PFB, 0) & 0x00000020) { | |
280 if (((VID_RD32 (chip->PMC, 0) & 0xF0) == 0x20) | |
281 && ((VID_RD32 (chip->PMC, 0) & 0x0F) >= 0x02)) { | |
282 /* SDRAM 128 ZX. */ | |
283 return ((1 << (VID_RD32 (chip->PFB, 0) & 0x03)) * 1024 * 1024); | |
284 } | |
285 else { | |
286 return 1024 * 1024 * 8; | |
287 } | |
288 } | |
289 else { | |
290 /* SGRAM 128. */ | |
291 switch (VID_RD32(chip->PFB, 0) & 0x00000003) { | |
292 case 0: | |
293 return 1024 * 1024 * 8; | |
294 break; | |
295 case 2: | |
296 return 1024 * 1024 * 4; | |
297 break; | |
298 default: | |
299 return 1024 * 1024 * 2; | |
300 break; | |
301 } | |
302 } | |
303 } | |
304 static unsigned long rivatv_fbsize_nv04 (struct rivatv_chip *chip){ | |
305 if (VID_RD32 (chip->PFB, 0) & 0x00000100) { | |
306 return ((VID_RD32 (chip->PFB, 0) >> 12) & 0x0F) * 1024 * 1024 * 2 | |
307 + 1024 * 1024 * 2; | |
308 } else { | |
309 switch (VID_RD32 (chip->PFB, 0) & 0x00000003) { | |
310 case 0: | |
311 return 1024 * 1024 * 32; | |
312 break; | |
313 case 1: | |
314 return 1024 * 1024 * 4; | |
315 break; | |
316 case 2: | |
317 return 1024 * 1024 * 8; | |
318 break; | |
319 case 3: | |
320 default: | |
321 return 1024 * 1024 * 16; | |
322 break; | |
323 } | |
324 } | |
325 } | |
326 | |
327 static unsigned long rivatv_fbsize_nv10 (struct rivatv_chip *chip){ | |
328 return VID_RD32 (chip->PFB, 0x20C) & 0xFFF00000; | |
329 } | |
330 | |
331 //lock funcs | |
332 static void rivatv_lock_nv03 (struct rivatv_chip *chip, int LockUnlock){ | |
333 VID_WR08 (chip->PVIO, 0x3C4, 0x06); | |
334 VID_WR08 (chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57); | |
335 } | |
336 | |
337 static void rivatv_lock_nv04 (struct rivatv_chip *chip, int LockUnlock){ | |
338 VID_WR08 (chip->PCIO, 0x3C4, 0x06); | |
339 VID_WR08 (chip->PCIO, 0x3C5, LockUnlock ? 0x99 : 0x57); | |
340 VID_WR08 (chip->PCIO, 0x3D4, 0x1F); | |
341 VID_WR08 (chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57); | |
342 } | |
343 | |
344 | |
345 | |
346 | |
347 /* Enable PFB (Framebuffer), PVIDEO (Overlay unit) and PME (Mediaport) if neccessary. */ | |
348 static void rivatv_enable_PMEDIA (struct rivatv_info *info){ | |
349 uint32_t reg; | |
350 | |
351 /* switch off interrupts once for a while */ | |
352 // VID_WR32 (info->chip.PME, 0x200140, 0x00); | |
353 // VID_WR32 (info->chip.PMC, 0x000140, 0x00); | |
354 | |
355 reg = VID_RD32 (info->chip.PMC, 0x000200); | |
356 | |
357 /* NV3 (0x10100010): NV03_PMC_ENABLE_PMEDIA, NV03_PMC_ENABLE_PFB, NV03_PMC_ENABLE_PVIDEO */ | |
358 | |
359 if ((reg & 0x10100010) != 0x10100010) { | |
360 printf("PVIDEO and PFB disabled, enabling...\n"); | |
361 VID_OR32 (info->chip.PMC, 0x000200, 0x10100010); | |
362 } | |
363 | |
364 /* save the current colorkey */ | |
365 switch (info->chip.arch ) { | |
366 case NV_ARCH_10: | |
367 case NV_ARCH_20: | |
368 case NV_ARCH_30: | |
369 /* NV_PVIDEO_COLOR_KEY */ | |
370 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0xB00); | |
371 break; | |
372 case NV_ARCH_03: | |
373 case NV_ARCH_04: | |
374 /* NV_PVIDEO_KEY */ | |
375 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0x240); | |
376 break; | |
377 } | |
378 | |
379 | |
380 /* re-enable interrupts again */ | |
381 // VID_WR32 (info->chip.PMC, 0x000140, 0x01); | |
382 // VID_WR32 (info->chip.PME, 0x200140, 0x01); | |
383 } | |
384 | |
385 /* Stop overlay video. */ | |
386 static void rivatv_overlay_stop (struct rivatv_info *info) { | |
387 switch (info->chip.arch ) { | |
388 case NV_ARCH_10: | |
389 case NV_ARCH_20: | |
390 case NV_ARCH_30: | |
391 /* NV_PVIDEO_COLOR_KEY */ | |
392 /* Xv-Extension-Hack: Restore previously saved value. */ | |
393 VID_WR32 (info->chip.PVIDEO, 0xB00, info->colorkey); | |
394 /* NV_PVIDEO_STOP */ | |
395 VID_OR32 (info->chip.PVIDEO, 0x704, 0x11); | |
396 /* NV_PVIDEO_BUFFER */ | |
397 VID_AND32 (info->chip.PVIDEO, 0x700, ~0x11); | |
398 /* NV_PVIDEO_INTR_EN_BUFFER */ | |
399 // VID_AND32 (info->chip.PVIDEO, 0x140, ~0x11); | |
400 break; | |
401 case NV_ARCH_03: | |
402 case NV_ARCH_04: | |
403 /* NV_PVIDEO_KEY */ | |
404 VID_WR32 (info->chip.PVIDEO, 0x240, info->colorkey); | |
405 /* NV_PVIDEO_OVERLAY_VIDEO_OFF */ | |
406 VID_AND32 (info->chip.PVIDEO, 0x244, ~0x01); | |
407 /* NV_PVIDEO_INTR_EN_0_NOTIFY */ | |
408 // VID_AND32 (info->chip.PVIDEO, 0x140, ~0x01); | |
409 /* NV_PVIDEO_OE_STATE */ | |
410 VID_WR32 (info->chip.PVIDEO, 0x224, 0); | |
411 /* NV_PVIDEO_SU_STATE */ | |
412 VID_WR32 (info->chip.PVIDEO, 0x228, 0); | |
413 /* NV_PVIDEO_RM_STATE */ | |
414 VID_WR32 (info->chip.PVIDEO, 0x22C, 0); | |
415 break; | |
416 } | |
417 } | |
418 | |
419 /* Get pan offset of the physical screen. */ | |
420 static uint32_t rivatv_overlay_pan (struct rivatv_info *info){ | |
421 uint32_t pan; | |
422 info->chip.lock (&info->chip, 0); | |
423 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0D); | |
424 pan = VID_RD08 (info->chip.PCIO, 0x3D5); | |
425 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0C); | |
426 pan |= VID_RD08 (info->chip.PCIO, 0x3D5) << 8; | |
427 VID_WR08 (info->chip.PCIO, 0x3D4, 0x19); | |
428 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x1F) << 16; | |
429 VID_WR08 (info->chip.PCIO, 0x3D4, 0x2D); | |
430 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x60) << 16; | |
431 return pan << 2; | |
432 } | |
433 | |
434 /* Compute and set colorkey depending on the colour depth. */ | |
435 static void rivatv_overlay_colorkey (rivatv_info* info, unsigned int chromakey){ | |
436 uint32_t r, g, b, key = 0; | |
437 | |
438 r = (chromakey & 0x00FF0000) >> 16; | |
439 g = (chromakey & 0x0000FF00) >> 8; | |
440 b = chromakey & 0x000000FF; | |
441 switch (info->depth) { | |
442 case 15: | |
443 key = ((r >> 3) << 10) | ((g >> 3) << 5) | ((b >> 3)); | |
444 #ifndef WIN32 | |
445 key = key | 0x00008000; | |
446 #endif | |
447 break; | |
448 case 16: // XXX unchecked | |
449 key = ((r >> 3) << 11) | ((g >> 2) << 5) | ((b >> 3)); | |
450 #ifndef WIN32 | |
451 key = key | 0x00008000; | |
452 #endif | |
453 break; | |
454 case 24: // XXX unchecked, maybe swap order of masking - FIXME Can the card be in 24 bit mode anyway? | |
455 key = (chromakey & 0x00FFFFFF) | 0x00800000; | |
456 break; | |
457 case 32: | |
458 key = chromakey; | |
459 #ifndef WIN32 | |
460 key = key | 0x80000000; | |
461 #endif | |
462 break; | |
463 } | |
464 //printf("[nvidia_vid] depth=%d %08X \n", info->depth, chromakey); | |
465 switch (info->chip.arch) { | |
466 case NV_ARCH_10: | |
467 case NV_ARCH_20: | |
468 case NV_ARCH_30: | |
469 VID_WR32 (info->chip.PVIDEO, 0xB00, key); | |
470 break; | |
471 case NV_ARCH_03: | |
472 case NV_ARCH_04: | |
473 VID_WR32 (info->chip.PVIDEO, 0x240, key); | |
474 break; | |
475 } | |
476 } | |
477 | |
478 static void nv_getscreenproperties(struct rivatv_info *info){ | |
479 uint32_t bpp=0,x; | |
480 info->chip.lock(&info->chip, 0); | |
481 /*get screen depth*/ | |
482 VID_WR08(info->chip.PCIO, 0x03D4,0x28); | |
483 bpp = VID_RD08(info->chip.PCIO,0x03D5)&0x3; | |
484 if((bpp == 2) && (VID_RD32(info->chip.PVIDEO,0x600) & 0x00001000) == 0x0)info->depth=15; | |
485 else info->depth = 0x04 << bpp; | |
486 /*get screen width*/ | |
487 VID_WR08(info->chip.PCIO, 0x03D4, 0x1); | |
488 info->screen_x = (1 + VID_RD08(info->chip.PCIO, 0x3D5)) * 8; | |
489 /*get screen height*/ | |
490 /* get first 8 bits in VT_DISPLAY_END*/ | |
491 VID_WR08(info->chip.PCIO, 0x03D4, 0x12); | |
492 info->screen_y = VID_RD08(info->chip.PCIO,0x03D5); | |
493 VID_WR08(info->chip.PCIO,0x03D4,0x07); | |
494 /* get 9th bit in CRTC_OVERFLOW*/ | |
495 info->screen_y |= (VID_RD08(info->chip.PCIO,0x03D5) &0x02)<<7; | |
496 /* and the 10th in CRTC_OVERFLOW*/ | |
497 info->screen_y |=(VID_RD08(info->chip.PCIO,0x03D5) &0x40)<<3; | |
498 ++info->screen_y; | |
499 | |
500 /* NV_PCRTC_OFFSET */ | |
501 VID_WR08 (info->chip.PCIO, 0x3D4, 0x13); | |
502 x = VID_RD08 (info->chip.PCIO, 0x3D5); | |
503 /* NV_PCRTC_REPAINT0_OFFSET_10_8 */ | |
504 VID_WR08 (info->chip.PCIO, 0x3D4, 0x19); | |
505 x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0xE0) << 3; | |
506 /* NV_PCRTC_EXTRA_OFFSET_11 */ | |
507 VID_WR08 (info->chip.PCIO, 0x3D4, 0x25); | |
508 x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x20) << 6; x <<= 3; | |
509 info->bps = x * bpp; | |
510 } | |
511 | |
512 | |
513 | |
514 | |
515 /* Start overlay video. */ | |
516 static void rivatv_overlay_start (struct rivatv_info *info,int bufno){ | |
517 uint32_t base, size, offset, xscale, yscale, pan; | |
518 uint32_t value; | |
519 int x=info->wx, y=info->wy; | |
520 int lwidth=info->d_width, lheight=info->d_height; | |
521 | |
522 size = info->buffer_size; | |
523 base = info->picture_offset; | |
524 offset = bufno*size; | |
525 /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/ | |
526 nv_getscreenproperties(info); | |
527 | |
528 if(info->depth){ | |
529 /* get pan offset of the physical screen */ | |
530 pan = rivatv_overlay_pan (info); | |
531 /* adjust window position depending on the pan offset */ | |
532 if (info->bps != 0) | |
533 { | |
534 x = info->wx - (pan % info->bps) * 8 / info->depth; | |
535 y = info->wy - (pan / info->bps); | |
536 } | |
537 } else { | |
538 // we can't adjust the window position correctly in textmode | |
539 // setting y to 8 seems to work ok, though | |
540 if(info->chip.arch < NV_ARCH_10 && y < 8) y = 8; | |
541 } | |
542 | |
543 /* adjust negative output window variables */ | |
544 if (x < 0) { | |
545 lwidth = info->d_width + x; | |
546 offset += (-x * info->width / info->d_width) << 1; | |
547 // offset += (-window->x * port->vld_width / window->width) << 1; | |
548 x = 0; | |
549 } | |
550 if (y < 0) { | |
551 lheight = info->d_height + y; | |
552 offset += (-y * info->height / info->d_height * info->width) << 1; | |
553 // offset += (-window->y * port->vld_height / window->height * port->org_width) << 1; | |
554 y = 0; | |
555 } | |
556 | |
557 switch (info->chip.arch) { | |
558 case NV_ARCH_10: | |
559 case NV_ARCH_20: | |
560 case NV_ARCH_30: | |
561 | |
562 /* NV_PVIDEO_BASE */ | |
563 VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base + offset); | |
564 //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base); | |
565 /* NV_PVIDEO_LIMIT */ | |
566 VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + offset + size - 1); | |
567 //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1); | |
568 | |
569 /* extra code for NV20 && NV30 architectures */ | |
570 if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30) { | |
571 VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base + offset); | |
572 //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base); | |
573 VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + offset + size - 1); | |
574 //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1); | |
575 } | |
576 | |
577 /* NV_PVIDEO_LUMINANCE */ | |
578 VID_WR32 (info->chip.PVIDEO, 0x910 + 0, eq.lum); | |
579 //VID_WR32 (info->chip.PVIDEO, 0x910 + 4, 0x00001000); | |
580 /* NV_PVIDEO_CHROMINANCE */ | |
581 VID_WR32 (info->chip.PVIDEO, 0x918 + 0, eq.chrom); | |
582 //VID_WR32 (info->chip.PVIDEO, 0x918 + 4, 0x00001000); | |
583 | |
584 /* NV_PVIDEO_OFFSET */ | |
585 VID_WR32 (info->chip.PVIDEO, 0x920 + 0, 0x0); | |
586 //VID_WR32 (info->chip.PVIDEO, 0x920 + 4, offset + pitch); | |
587 /* NV_PVIDEO_SIZE_IN */ | |
588 VID_WR32 (info->chip.PVIDEO, 0x928 + 0, ((info->height) << 16) | info->width); | |
589 //VID_WR32 (info->chip.PVIDEO, 0x928 + 4, ((port->org_height/2) << 16) | port->org_width); | |
590 /* NV_PVIDEO_POINT_IN */ | |
591 VID_WR32 (info->chip.PVIDEO, 0x930 + 0, 0x00000000); | |
592 //VID_WR32 (info->chip.PVIDEO, 0x930 + 4, 0x00000000); | |
593 /* NV_PVIDEO_DS_DX_RATIO */ | |
594 VID_WR32 (info->chip.PVIDEO, 0x938 + 0, (info->width << 20) / info->d_width); | |
595 //VID_WR32 (info->chip.PVIDEO, 0x938 + 4, (port->org_width << 20) / window->width); | |
596 /* NV_PVIDEO_DT_DY_RATIO */ | |
597 VID_WR32 (info->chip.PVIDEO, 0x940 + 0, ((info->height) << 20) / info->d_height); | |
598 //VID_WR32 (info->chip.PVIDEO, 0x940 + 4, ((port->org_height/2) << 20) / window->height); | |
599 | |
600 /* NV_PVIDEO_POINT_OUT */ | |
601 VID_WR32 (info->chip.PVIDEO, 0x948 + 0, ((y + 0) << 16) | x); | |
602 //VID_WR32 (info->chip.PVIDEO, 0x948 + 4, ((y + 0) << 16) | x); | |
603 /* NV_PVIDEO_SIZE_OUT */ | |
604 VID_WR32 (info->chip.PVIDEO, 0x950 + 0, (lheight << 16) | lwidth); | |
605 //VID_WR32 (info->chip.PVIDEO, 0x950 + 4, (height << 16) | width); | |
606 | |
607 /* NV_PVIDEO_FORMAT */ | |
608 value = info->pitch; | |
609 if(info->use_colorkey)value |= 1 << 20; | |
610 if(info->format == IMGFMT_YUY2)value |= 1 << 16; | |
611 VID_WR32 (info->chip.PVIDEO, 0x958 + 0, value); | |
612 //VID_WR32 (info->chip.PVIDEO, 0x958 + 4, (pitch << 1) | 0x00100000); | |
613 | |
614 /* NV_PVIDEO_INTR_EN_BUFFER */ | |
615 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01/*0x11*/); | |
616 /* NV_PVIDEO_STOP */ | |
617 VID_WR32 (info->chip.PVIDEO, 0x704,0x0); | |
618 /* NV_PVIDEO_BUFFER */ | |
619 VID_WR32 (info->chip.PVIDEO, 0x700, 0x01/*0x11*/); | |
620 break; | |
621 | |
622 case NV_ARCH_03: | |
623 case NV_ARCH_04: | |
624 | |
625 | |
626 /* NV_PVIDEO_OE_STATE */ | |
627 VID_WR32 (info->chip.PVIDEO, 0x224, 0); | |
628 /* NV_PVIDEO_SU_STATE */ | |
629 VID_WR32 (info->chip.PVIDEO, 0x228, 0); | |
630 /* NV_PVIDEO_RM_STATE */ | |
631 VID_WR32 (info->chip.PVIDEO, 0x22C, 0); | |
632 | |
633 /* NV_PVIDEO_BUFF0_START_ADDRESS */ | |
634 VID_WR32 (info->chip.PVIDEO, 0x20C + 0, base + offset + 0); | |
635 VID_WR32 (info->chip.PVIDEO, 0x20C + 4, base + offset + 0); | |
636 /* NV_PVIDEO_BUFF0_PITCH_LENGTH */ | |
637 VID_WR32 (info->chip.PVIDEO, 0x214 + 0, info->pitch); | |
638 VID_WR32 (info->chip.PVIDEO, 0x214 + 4, info->pitch); | |
639 | |
640 /* NV_PVIDEO_WINDOW_START */ | |
641 VID_WR32 (info->chip.PVIDEO, 0x230, (y << 16) | x); | |
642 /* NV_PVIDEO_WINDOW_SIZE */ | |
643 VID_WR32 (info->chip.PVIDEO, 0x234, (lheight << 16) | lwidth); | |
644 /* NV_PVIDEO_STEP_SIZE */ | |
645 yscale = ((info->height - 1) << 11) / (info->d_height - 1); | |
646 xscale = ((info->width - 1) << 11) / (info->d_width - 1); | |
647 VID_WR32 (info->chip.PVIDEO, 0x200, (yscale << 16) | xscale); | |
648 | |
649 /* NV_PVIDEO_RED_CSC_OFFSET */ | |
650 VID_WR32 (info->chip.PVIDEO, 0x280, eq.red_off); | |
651 /* NV_PVIDEO_GREEN_CSC_OFFSET */ | |
652 VID_WR32 (info->chip.PVIDEO, 0x284, eq.green_off); | |
653 /* NV_PVIDEO_BLUE_CSC_OFFSET */ | |
654 VID_WR32 (info->chip.PVIDEO, 0x288, eq.blue_off); | |
655 /* NV_PVIDEO_CSC_ADJUST */ | |
656 VID_WR32 (info->chip.PVIDEO, 0x28C, 0x00000); /* No colour correction! */ | |
657 | |
658 /* NV_PVIDEO_CONTROL_Y (BLUR_ON, LINE_HALF) */ | |
659 VID_WR32 (info->chip.PVIDEO, 0x204, 0x001); | |
660 /* NV_PVIDEO_CONTROL_X (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */ | |
661 VID_WR32 (info->chip.PVIDEO, 0x208, 0x111); /*directx overlay 0x110 */ | |
662 | |
663 /* NV_PVIDEO_FIFO_BURST_LENGTH */ | |
664 VID_WR32 (info->chip.PVIDEO, 0x23C, 0x03); | |
665 /* NV_PVIDEO_FIFO_THRES_SIZE */ | |
666 VID_WR32 (info->chip.PVIDEO, 0x238, 0x38); /*windows uses 0x40*/ | |
667 | |
668 /* NV_PVIDEO_BUFF0_OFFSET */ | |
669 VID_WR32 (info->chip.PVIDEO, 0x21C + 0, 0); | |
670 VID_WR32 (info->chip.PVIDEO, 0x21C + 4, 0); | |
671 | |
672 /* NV_PVIDEO_INTR_EN_0_NOTIFY_ENABLED */ | |
673 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01); | |
674 | |
675 /* NV_PVIDEO_OVERLAY (KEY_ON, VIDEO_ON, FORMAT_CCIR) */ | |
676 value = 0x1; /*video on*/ | |
677 if(info->format==IMGFMT_YUY2)value |= 0x100; | |
678 if(info->use_colorkey)value |=0x10; | |
679 VID_WR32 (info->chip.PVIDEO, 0x244, value); | |
680 | |
681 /* NV_PVIDEO_SU_STATE */ | |
682 VID_XOR32 (info->chip.PVIDEO, 0x228, 1 << 16); | |
683 break; | |
684 } | |
685 /*set colorkey*/ | |
686 rivatv_overlay_colorkey(info,info->vidixcolorkey); | |
687 | |
688 } | |
689 | |
690 | |
691 | |
692 | |
693 | |
694 | |
695 | |
696 static rivatv_info* info; | |
697 | |
698 | |
699 | |
700 | |
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701 static int nv_init(void){ |
22850 | 702 int mtrr; |
703 info = calloc(1,sizeof(rivatv_info)); | |
704 info->control_base = map_phys_mem(pci_info.base0, 0x00C00000 + 0x00008000); | |
705 info->chip.arch = nvidia_card_ids[find_chip(pci_info.device)].arch; | |
706 printf("[nvidia_vid] arch %x register base %p\n",info->chip.arch,info->control_base); | |
707 info->chip.PFIFO = (uint32_t *) (info->control_base + 0x00002000); | |
708 info->chip.FIFO = (uint32_t *) (info->control_base + 0x00800000); | |
709 info->chip.PMC = (uint32_t *) (info->control_base + 0x00000000); | |
710 info->chip.PFB = (uint32_t *) (info->control_base + 0x00100000); | |
711 info->chip.PME = (uint32_t *) (info->control_base + 0x00000000); | |
712 info->chip.PCIO = (uint8_t *) (info->control_base + 0x00601000); | |
713 info->chip.PVIO = (uint8_t *) (info->control_base + 0x000C0000); | |
714 info->chip.PGRAPH = (uint32_t *) (info->control_base + 0x00400000); | |
715 /* setup chip specific functions */ | |
716 switch (info->chip.arch) { | |
717 case NV_ARCH_03: | |
718 info->chip.lock = rivatv_lock_nv03; | |
719 info->chip.fbsize = rivatv_fbsize_nv03 (&info->chip); | |
720 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); | |
721 break; | |
722 case NV_ARCH_04: | |
723 info->chip.lock = rivatv_lock_nv04; | |
724 info->chip.fbsize = rivatv_fbsize_nv04 (&info->chip); | |
725 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); | |
726 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); | |
727 break; | |
728 case NV_ARCH_10: | |
729 case NV_ARCH_20: | |
730 case NV_ARCH_30: | |
731 info->chip.lock = rivatv_lock_nv04; | |
732 info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip); | |
733 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); | |
734 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000); | |
735 break; | |
736 } | |
737 switch (info->chip.arch) { | |
738 case NV_ARCH_03: | |
739 { | |
740 /* This maps framebuffer @6MB, thus 2MB are left for video. */ | |
741 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
742 /* This may trash your screen for resolutions greater than 1024x768, sorry. */ | |
743 info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1); | |
744 info->picture_base = info->video_base + info->picture_offset; | |
745 info->chip.PRAMIN = (uint32_t *) (info->video_base + 0x00C00000); | |
746 break; | |
747 } | |
748 case NV_ARCH_04: | |
749 case NV_ARCH_10: | |
750 case NV_ARCH_20: | |
751 case NV_ARCH_30: | |
752 { | |
753 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
754 info->picture_offset = info->chip.fbsize - NV04_BES_SIZE; | |
755 if(info->chip.fbsize > 16*1024*1024) | |
756 info->picture_offset -= NV04_BES_SIZE; | |
757 // info->picture_base = (unsigned long)map_phys_mem(pci_info.base1+info->picture_offset,NV04_BES_SIZE); | |
758 info->picture_base = info->video_base + info->picture_offset; | |
759 break; | |
760 } | |
761 } | |
762 | |
763 printf("[nvidia_vid] detected memory size %u MB\n",(uint32_t)(info->chip.fbsize /1024/1024)); | |
764 | |
765 if ((mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB))!= 0) | |
766 printf("[nvidia_vid] unable to setup MTRR: %s\n", strerror(mtrr)); | |
767 else | |
768 printf("[nvidia_vid] MTRR set up\n"); | |
769 | |
770 nv_getscreenproperties(info); | |
771 if(!info->depth)printf("[nvidia_vid] text mode: %ux%u\n",info->screen_x,info->screen_y); | |
772 else printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x,info->screen_y, info->depth); | |
773 | |
774 | |
775 rivatv_enable_PMEDIA(info); | |
776 info->cur_frame = 0; | |
777 info->use_colorkey = 0; | |
778 | |
779 eq.lum = 0x00001000; | |
780 eq.chrom = 0x00001000; | |
781 memset(&eq.vals, 0, sizeof(vidix_video_eq_t)); | |
782 eq.vals.cap = VEQ_CAP_BRIGHTNESS; | |
783 if (info->chip.arch > NV_ARCH_04) | |
784 eq.vals.cap |= VEQ_CAP_CONTRAST | VEQ_CAP_SATURATION | VEQ_CAP_HUE; | |
785 eq.red_off = 0x69; | |
786 eq.green_off = 0x3e; | |
787 eq.blue_off = 0x89; | |
788 return 0; | |
789 } | |
790 | |
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791 static void nv_destroy(void){ |
22850 | 792 unmap_phys_mem(info->control_base ,0x00C00000 + 0x00008000); |
793 unmap_phys_mem(info->video_base, info->chip.fbsize); | |
794 free(info); | |
795 } | |
796 | |
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797 static int nv_get_caps(vidix_capability_t *to){ |
22850 | 798 memcpy(to, &nvidia_cap, sizeof(vidix_capability_t)); |
799 return 0; | |
800 } | |
801 | |
802 inline static int is_supported_fourcc(uint32_t fourcc) | |
803 { | |
804 if (fourcc == IMGFMT_UYVY || fourcc == IMGFMT_YUY2) | |
805 return 1; | |
806 else | |
807 return 0; | |
808 } | |
809 | |
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810 static int nv_query_fourcc(vidix_fourcc_t *to){ |
22850 | 811 if(is_supported_fourcc(to->fourcc)){ |
812 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
813 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
814 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
815 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
816 VID_DEPTH_32BPP; | |
817 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; | |
818 return 0; | |
819 } | |
820 else to->depth = to->flags = 0; | |
821 return ENOSYS; | |
822 } | |
823 | |
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824 static int nv_config_playback(vidix_playback_t *vinfo){ |
22850 | 825 uint32_t i; |
826 printf("called %s\n", __FUNCTION__); | |
827 if (! is_supported_fourcc(vinfo->fourcc)) | |
828 return ENOSYS; | |
829 | |
830 info->width = vinfo->src.w; | |
831 info->height = vinfo->src.h; | |
832 | |
833 info->d_width = vinfo->dest.w; | |
834 info->d_height = vinfo->dest.h; | |
835 info->wx = vinfo->dest.x; | |
836 info->wy = vinfo->dest.y; | |
837 info->format = vinfo->fourcc; | |
838 | |
839 printf("[nvidia_vid] setting up a %dx%d-%dx%d video window (src %dx%d), format 0x%X\n", | |
840 info->d_width, info->d_height, info->wx, info->wy, info->width, info->height, vinfo->fourcc); | |
841 | |
842 | |
843 vinfo->dga_addr=info->picture_base; | |
844 | |
845 switch (vinfo->fourcc) | |
846 { | |
847 case IMGFMT_YUY2: | |
848 case IMGFMT_UYVY: | |
849 | |
850 vinfo->dest.pitch.y = 64; | |
851 vinfo->dest.pitch.u = 0; | |
852 vinfo->dest.pitch.v = 0; | |
853 | |
854 vinfo->offset.y = 0; | |
855 vinfo->offset.v = 0; | |
856 vinfo->offset.u = 0; | |
857 info->pitch = ((info->width << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1); | |
858 vinfo->frame_size = info->pitch * info->height; | |
859 break; | |
860 } | |
861 info->buffer_size = vinfo->frame_size; | |
862 info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; | |
863 if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; | |
864 // vinfo->num_frames = 1; | |
865 // printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); | |
866 for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; | |
867 return 0; | |
868 } | |
869 | |
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870 static int nv_playback_on(void){ |
22850 | 871 rivatv_overlay_start(info,info->cur_frame); |
872 return 0; | |
873 } | |
874 | |
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875 static int nv_playback_off(void){ |
22850 | 876 rivatv_overlay_stop(info); |
877 return 0; | |
878 } | |
879 | |
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880 static int nv_set_gkeys( const vidix_grkey_t * grkey){ |
22850 | 881 if (grkey->ckey.op == CKEY_FALSE) |
882 { | |
883 info->use_colorkey = 0; | |
884 printf("[nvidia_vid] colorkeying disabled\n"); | |
885 } | |
886 else { | |
887 info->use_colorkey = 1; | |
888 info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); | |
889 printf("[nvidia_vid] set colorkey 0x%x\n",info->vidixcolorkey); | |
890 } | |
891 if(info->d_width && info->d_height)rivatv_overlay_start(info,0); | |
892 return 0; | |
893 } | |
894 | |
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895 static int nv_frame_sel(unsigned int frame){ |
22850 | 896 // printf("selecting buffer %d\n", frame); |
897 rivatv_overlay_start(info, frame); | |
898 if (info->num_frames >= 1) | |
899 info->cur_frame = frame/*(frame+1)%info->num_frames*/; | |
900 return 0; | |
901 } | |
902 | |
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903 static int nv_set_eq(const vidix_video_eq_t *eq_parm) { |
22850 | 904 double angle; |
905 int16_t chrom_cos, chrom_sin; | |
906 if (eq_parm->cap & VEQ_CAP_BRIGHTNESS) | |
907 eq.vals.brightness = eq_parm->brightness; | |
908 if (eq_parm->cap & VEQ_CAP_CONTRAST) | |
909 eq.vals.contrast = eq_parm->contrast; | |
910 if (eq_parm->cap & VEQ_CAP_SATURATION) | |
911 eq.vals.saturation = eq_parm->saturation; | |
912 if (eq_parm->cap & VEQ_CAP_HUE) | |
913 eq.vals.hue = eq_parm->hue; | |
914 eq.lum = (((eq.vals.brightness * 512 + 500) / 1000) << 16) | | |
915 ((((eq.vals.contrast + 1000) * 8191 + 1000) / 2000) & 0xffff); | |
916 angle = (double)eq.vals.hue / 1000.0 * 3.1415927; | |
917 chrom_cos = ((eq.vals.saturation + 1000) * 8191 * cos(angle) + 1000) / 2000; | |
918 chrom_sin = ((eq.vals.saturation + 1000) * 8191 * sin(angle) + 1000) / 2000; | |
919 eq.chrom = chrom_sin << 16 | chrom_cos; | |
920 eq.red_off = 0x69 - eq.vals.brightness * 62 / 1000; | |
921 eq.green_off = 0x3e + eq.vals.brightness * 62 / 1000; | |
922 eq.blue_off = 0x89 - eq.vals.brightness * 62 / 1000; | |
923 return 0; | |
924 } | |
925 | |
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926 static int nv_get_eq(vidix_video_eq_t *eq_parm) { |
22850 | 927 memcpy(eq_parm, &eq.vals, sizeof(vidix_video_eq_t)); |
928 return 0; | |
929 } | |
930 | |
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931 VDXDriver nvidia_drv = { |
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932 "nvidia", |
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933 NULL, |
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934 .probe = nv_probe, |
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935 .get_caps = nv_get_caps, |
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936 .query_fourcc = nv_query_fourcc, |
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937 .init = nv_init, |
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938 .destroy = nv_destroy, |
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939 .config_playback = nv_config_playback, |
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940 .playback_on = nv_playback_on, |
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941 .playback_off = nv_playback_off, |
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942 .frame_sel = nv_frame_sel, |
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943 .get_eq = nv_get_eq, |
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944 .set_eq = nv_set_eq, |
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945 .set_gkey = nv_set_gkeys, |
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946 }; |