Mercurial > mplayer.hg
annotate vidix/radeon_vid.c @ 22864:e15beff67d91
Move pci.db out of its single-file subdirectory.
author | diego |
---|---|
date | Sun, 01 Apr 2007 12:31:15 +0000 |
parents | 6c57087c5a2d |
children | 204c351b6720 |
rev | line source |
---|---|
22850 | 1 /* |
2 radeon_vid - VIDIX based video driver for Radeon and Rage128 chips | |
3 Copyrights 2002 Nick Kurshev. This file is based on sources from | |
4 GATOS (gatos.sf.net) and X11 (www.xfree86.org) | |
5 Licence: GPL | |
6 | |
7 31.12.2002 added support for fglrx drivers by Marcel Naziri (zwobbl@zwobbl.de) | |
8 6.04.2004 fixes to allow compiling vidix without X11 (broken in original patch) | |
9 PPC support by Alex Beregszaszi | |
10 */ | |
11 | |
12 #include <errno.h> | |
13 #include <stdio.h> | |
14 #include <stdlib.h> | |
15 #include <string.h> | |
16 #include <math.h> | |
17 #include <inttypes.h> | |
18 | |
19 #include "../config.h" | |
20 #include "../libavutil/common.h" | |
21 #include "../mpbswap.h" | |
22 #include "../libdha/pci_ids.h" | |
23 #include "../libdha/pci_names.h" | |
24 #include "vidix.h" | |
22857
77def5093daf
switch to new internal vidix API, no more dlopen/dlsym, libvidix is now a fully static library with all drivers built-in
ben
parents:
22850
diff
changeset
|
25 #include "vidixlib.h" |
22850 | 26 #include "fourcc.h" |
27 #include "../libdha/libdha.h" | |
28 #include "radeon.h" | |
29 | |
30 #ifdef HAVE_X11 | |
31 #include <X11/Xlib.h> | |
32 #endif | |
33 | |
34 #ifdef RAGE128 | |
35 #define RADEON_MSG "[rage128]" | |
36 #define X_ADJUST 0 | |
37 #else | |
38 #define RADEON_MSG "[radeon]" | |
39 #define X_ADJUST (is_shift_required ? 8 : 0) | |
40 #ifndef RADEON | |
41 #define RADEON | |
42 #endif | |
43 #endif | |
44 | |
45 static int __verbose = 0; | |
46 #ifdef RADEON | |
47 static int is_shift_required = 0; | |
48 #endif | |
49 | |
50 typedef struct bes_registers_s | |
51 { | |
52 /* base address of yuv framebuffer */ | |
53 uint32_t yuv_base; | |
54 uint32_t fourcc; | |
55 uint32_t dest_bpp; | |
56 /* YUV BES registers */ | |
57 uint32_t reg_load_cntl; | |
58 uint32_t h_inc; | |
59 uint32_t step_by; | |
60 uint32_t y_x_start; | |
61 uint32_t y_x_end; | |
62 uint32_t v_inc; | |
63 uint32_t p1_blank_lines_at_top; | |
64 uint32_t p23_blank_lines_at_top; | |
65 uint32_t vid_buf_pitch0_value; | |
66 uint32_t vid_buf_pitch1_value; | |
67 uint32_t p1_x_start_end; | |
68 uint32_t p2_x_start_end; | |
69 uint32_t p3_x_start_end; | |
70 uint32_t base_addr; | |
71 uint32_t vid_buf_base_adrs_y[VID_PLAY_MAXFRAMES]; | |
72 uint32_t vid_buf_base_adrs_u[VID_PLAY_MAXFRAMES]; | |
73 uint32_t vid_buf_base_adrs_v[VID_PLAY_MAXFRAMES]; | |
74 uint32_t vid_nbufs; | |
75 | |
76 uint32_t p1_v_accum_init; | |
77 uint32_t p1_h_accum_init; | |
78 uint32_t p23_v_accum_init; | |
79 uint32_t p23_h_accum_init; | |
80 uint32_t scale_cntl; | |
81 uint32_t exclusive_horz; | |
82 uint32_t auto_flip_cntl; | |
83 uint32_t filter_cntl; | |
84 uint32_t key_cntl; | |
85 uint32_t test; | |
86 /* Configurable stuff */ | |
87 int double_buff; | |
88 | |
89 int brightness; | |
90 int saturation; | |
91 | |
92 int ckey_on; | |
93 uint32_t graphics_key_clr; | |
94 uint32_t graphics_key_msk; | |
95 uint32_t ckey_cntl; | |
96 | |
97 int deinterlace_on; | |
98 uint32_t deinterlace_pattern; | |
99 | |
100 } bes_registers_t; | |
101 | |
102 typedef struct video_registers_s | |
103 { | |
104 const char * sname; | |
105 uint32_t name; | |
106 uint32_t value; | |
107 }video_registers_t; | |
108 | |
109 static bes_registers_t besr; | |
110 #ifndef RAGE128 | |
111 static int RadeonFamily=100; | |
112 #endif | |
113 #define DECLARE_VREG(name) { #name, name, 0 } | |
114 static video_registers_t vregs[] = | |
115 { | |
116 DECLARE_VREG(VIDEOMUX_CNTL), | |
117 DECLARE_VREG(VIPPAD_MASK), | |
118 DECLARE_VREG(VIPPAD1_A), | |
119 DECLARE_VREG(VIPPAD1_EN), | |
120 DECLARE_VREG(VIPPAD1_Y), | |
121 DECLARE_VREG(OV0_Y_X_START), | |
122 DECLARE_VREG(OV0_Y_X_END), | |
123 DECLARE_VREG(OV0_PIPELINE_CNTL), | |
124 DECLARE_VREG(OV0_EXCLUSIVE_HORZ), | |
125 DECLARE_VREG(OV0_EXCLUSIVE_VERT), | |
126 DECLARE_VREG(OV0_REG_LOAD_CNTL), | |
127 DECLARE_VREG(OV0_SCALE_CNTL), | |
128 DECLARE_VREG(OV0_V_INC), | |
129 DECLARE_VREG(OV0_P1_V_ACCUM_INIT), | |
130 DECLARE_VREG(OV0_P23_V_ACCUM_INIT), | |
131 DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), | |
132 DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), | |
133 #ifdef RADEON | |
134 DECLARE_VREG(OV0_BASE_ADDR), | |
135 #endif | |
136 DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), | |
137 DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), | |
138 DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), | |
139 DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), | |
140 DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), | |
141 DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), | |
142 DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), | |
143 DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), | |
144 DECLARE_VREG(OV0_AUTO_FLIP_CNTL), | |
145 DECLARE_VREG(OV0_DEINTERLACE_PATTERN), | |
146 DECLARE_VREG(OV0_SUBMIT_HISTORY), | |
147 DECLARE_VREG(OV0_H_INC), | |
148 DECLARE_VREG(OV0_STEP_BY), | |
149 DECLARE_VREG(OV0_P1_H_ACCUM_INIT), | |
150 DECLARE_VREG(OV0_P23_H_ACCUM_INIT), | |
151 DECLARE_VREG(OV0_P1_X_START_END), | |
152 DECLARE_VREG(OV0_P2_X_START_END), | |
153 DECLARE_VREG(OV0_P3_X_START_END), | |
154 DECLARE_VREG(OV0_FILTER_CNTL), | |
155 DECLARE_VREG(OV0_FOUR_TAP_COEF_0), | |
156 DECLARE_VREG(OV0_FOUR_TAP_COEF_1), | |
157 DECLARE_VREG(OV0_FOUR_TAP_COEF_2), | |
158 DECLARE_VREG(OV0_FOUR_TAP_COEF_3), | |
159 DECLARE_VREG(OV0_FOUR_TAP_COEF_4), | |
160 DECLARE_VREG(OV0_FLAG_CNTL), | |
161 #ifdef RAGE128 | |
162 DECLARE_VREG(OV0_COLOUR_CNTL), | |
163 #else | |
164 DECLARE_VREG(OV0_SLICE_CNTL), | |
165 #endif | |
166 DECLARE_VREG(OV0_VID_KEY_CLR), | |
167 DECLARE_VREG(OV0_VID_KEY_MSK), | |
168 DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), | |
169 DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), | |
170 DECLARE_VREG(OV0_KEY_CNTL), | |
171 DECLARE_VREG(OV0_TEST), | |
172 DECLARE_VREG(OV0_LIN_TRANS_A), | |
173 DECLARE_VREG(OV0_LIN_TRANS_B), | |
174 DECLARE_VREG(OV0_LIN_TRANS_C), | |
175 DECLARE_VREG(OV0_LIN_TRANS_D), | |
176 DECLARE_VREG(OV0_LIN_TRANS_E), | |
177 DECLARE_VREG(OV0_LIN_TRANS_F), | |
178 DECLARE_VREG(OV0_GAMMA_0_F), | |
179 DECLARE_VREG(OV0_GAMMA_10_1F), | |
180 DECLARE_VREG(OV0_GAMMA_20_3F), | |
181 DECLARE_VREG(OV0_GAMMA_40_7F), | |
182 DECLARE_VREG(OV0_GAMMA_380_3BF), | |
183 DECLARE_VREG(OV0_GAMMA_3C0_3FF), | |
184 DECLARE_VREG(SUBPIC_CNTL), | |
185 DECLARE_VREG(SUBPIC_DEFCOLCON), | |
186 DECLARE_VREG(SUBPIC_Y_X_START), | |
187 DECLARE_VREG(SUBPIC_Y_X_END), | |
188 DECLARE_VREG(SUBPIC_V_INC), | |
189 DECLARE_VREG(SUBPIC_H_INC), | |
190 DECLARE_VREG(SUBPIC_BUF0_OFFSET), | |
191 DECLARE_VREG(SUBPIC_BUF1_OFFSET), | |
192 DECLARE_VREG(SUBPIC_LC0_OFFSET), | |
193 DECLARE_VREG(SUBPIC_LC1_OFFSET), | |
194 DECLARE_VREG(SUBPIC_PITCH), | |
195 DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), | |
196 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), | |
197 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), | |
198 DECLARE_VREG(SUBPIC_PALETTE_INDEX), | |
199 DECLARE_VREG(SUBPIC_PALETTE_DATA), | |
200 DECLARE_VREG(SUBPIC_H_ACCUM_INIT), | |
201 DECLARE_VREG(SUBPIC_V_ACCUM_INIT), | |
202 DECLARE_VREG(IDCT_RUNS), | |
203 DECLARE_VREG(IDCT_LEVELS), | |
204 DECLARE_VREG(IDCT_AUTH_CONTROL), | |
205 DECLARE_VREG(IDCT_AUTH), | |
206 DECLARE_VREG(IDCT_CONTROL), | |
207 DECLARE_VREG(CONFIG_CNTL) | |
208 }; | |
209 | |
210 #ifdef HAVE_X11 | |
211 static uint32_t firegl_shift = 0; | |
212 #endif | |
213 static void * radeon_mmio_base = 0; | |
214 static void * radeon_mem_base = 0; | |
215 static int32_t radeon_overlay_off = 0; | |
216 static uint32_t radeon_ram_size = 0; | |
217 /* Restore on exit */ | |
218 static uint32_t SAVED_OV0_GRAPHICS_KEY_CLR = 0; | |
219 static uint32_t SAVED_OV0_GRAPHICS_KEY_MSK = 0; | |
220 static uint32_t SAVED_OV0_VID_KEY_CLR = 0; | |
221 static uint32_t SAVED_OV0_VID_KEY_MSK = 0; | |
222 static uint32_t SAVED_OV0_KEY_CNTL = 0; | |
223 #ifdef WORDS_BIGENDIAN | |
224 static uint32_t SAVED_CONFIG_CNTL = 0; | |
225 #if defined(RAGE128) | |
226 #define APER_0_BIG_ENDIAN_16BPP_SWAP (1<<0) | |
227 #define APER_0_BIG_ENDIAN_32BPP_SWAP (2<<0) | |
228 #else | |
229 #define RADEON_SURFACE_CNTL 0x0b00 | |
230 #define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) | |
231 #define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) | |
232 #endif | |
233 #endif | |
234 | |
235 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) | |
236 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
237 | |
238 #define INREG8(addr) GETREG(uint8_t,(uint8_t*)(radeon_mmio_base),addr) | |
239 #define OUTREG8(addr,val) SETREG(uint8_t,(uint8_t*)(radeon_mmio_base),addr,val) | |
240 | |
241 static inline uint32_t INREG (uint32_t addr) { | |
242 uint32_t tmp = GETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr); | |
243 return le2me_32(tmp); | |
244 } | |
245 //#define OUTREG(addr,val) SETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr,val) | |
246 #define OUTREG(addr,val) SETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr,le2me_32(val)) | |
247 #define OUTREGP(addr,val,mask) \ | |
248 do { \ | |
249 unsigned int _tmp = INREG(addr); \ | |
250 _tmp &= (mask); \ | |
251 _tmp |= (val); \ | |
252 OUTREG(addr, _tmp); \ | |
253 } while (0) | |
254 | |
255 static __inline__ uint32_t INPLL(uint32_t addr) | |
256 { | |
257 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f); | |
258 return (INREG(CLOCK_CNTL_DATA)); | |
259 } | |
260 | |
261 #define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \ | |
262 OUTREG(CLOCK_CNTL_DATA, val) | |
263 #define OUTPLLP(addr,val,mask) \ | |
264 do { \ | |
265 unsigned int _tmp = INPLL(addr); \ | |
266 _tmp &= (mask); \ | |
267 _tmp |= (val); \ | |
268 OUTPLL(addr, _tmp); \ | |
269 } while (0) | |
270 | |
271 static uint32_t radeon_vid_get_dbpp( void ) | |
272 { | |
273 uint32_t dbpp,retval; | |
274 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; | |
275 switch(dbpp) | |
276 { | |
277 case DST_8BPP: retval = 8; break; | |
278 case DST_15BPP: retval = 15; break; | |
279 case DST_16BPP: retval = 16; break; | |
280 case DST_24BPP: retval = 24; break; | |
281 default: retval=32; break; | |
282 } | |
283 return retval; | |
284 } | |
285 | |
286 static int radeon_is_dbl_scan( void ) | |
287 { | |
288 return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; | |
289 } | |
290 | |
291 static int radeon_is_interlace( void ) | |
292 { | |
293 return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; | |
294 } | |
295 | |
296 static uint32_t radeon_get_xres( void ) | |
297 { | |
298 /* FIXME: currently we extract that from CRTC!!!*/ | |
299 uint32_t xres,h_total; | |
300 h_total = INREG(CRTC_H_TOTAL_DISP); | |
301 xres = (h_total >> 16) & 0xffff; | |
302 return (xres + 1)*8; | |
303 } | |
304 | |
305 static uint32_t radeon_get_yres( void ) | |
306 { | |
307 /* FIXME: currently we extract that from CRTC!!!*/ | |
308 uint32_t yres,v_total; | |
309 v_total = INREG(CRTC_V_TOTAL_DISP); | |
310 yres = (v_total >> 16) & 0xffff; | |
311 return yres + 1; | |
312 } | |
313 | |
314 /* get flat panel x resolution*/ | |
315 static uint32_t radeon_get_fp_xres( void ){ | |
316 uint32_t xres=(INREG(FP_HORZ_STRETCH)&0x00fff000)>>16; | |
317 xres=(xres+1)*8; | |
318 return xres; | |
319 } | |
320 | |
321 /* get flat panel y resolution*/ | |
322 static uint32_t radeon_get_fp_yres( void ){ | |
323 uint32_t yres=(INREG(FP_VERT_STRETCH)&0x00fff000)>>12; | |
324 return yres+1; | |
325 } | |
326 | |
327 static void radeon_wait_vsync(void) | |
328 { | |
329 int i; | |
330 | |
331 OUTREG(GEN_INT_STATUS, VSYNC_INT_AK); | |
332 for (i = 0; i < 2000000; i++) | |
333 { | |
334 if (INREG(GEN_INT_STATUS) & VSYNC_INT) break; | |
335 } | |
336 } | |
337 | |
338 #ifdef RAGE128 | |
339 static void _radeon_engine_idle(void); | |
340 static void _radeon_fifo_wait(unsigned); | |
341 #define radeon_engine_idle() _radeon_engine_idle() | |
342 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) | |
343 /* Flush all dirty data in the Pixel Cache to memory. */ | |
344 static __inline__ void radeon_engine_flush ( void ) | |
345 { | |
346 unsigned i; | |
347 | |
348 OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL); | |
349 for (i = 0; i < 2000000; i++) { | |
350 if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break; | |
351 } | |
352 } | |
353 | |
354 /* Reset graphics card to known state. */ | |
355 static void radeon_engine_reset( void ) | |
356 { | |
357 uint32_t clock_cntl_index; | |
358 uint32_t mclk_cntl; | |
359 uint32_t gen_reset_cntl; | |
360 | |
361 radeon_engine_flush(); | |
362 | |
363 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); | |
364 mclk_cntl = INPLL(MCLK_CNTL); | |
365 | |
366 OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP); | |
367 | |
368 gen_reset_cntl = INREG(GEN_RESET_CNTL); | |
369 | |
370 OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); | |
371 INREG(GEN_RESET_CNTL); | |
372 OUTREG(GEN_RESET_CNTL, | |
373 gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI)); | |
374 INREG(GEN_RESET_CNTL); | |
375 | |
376 OUTPLL(MCLK_CNTL, mclk_cntl); | |
377 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); | |
378 OUTREG(GEN_RESET_CNTL, gen_reset_cntl); | |
379 } | |
380 #else | |
381 | |
382 static __inline__ void radeon_engine_flush ( void ) | |
383 { | |
384 int i; | |
385 | |
386 /* initiate flush */ | |
387 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, | |
388 ~RB2D_DC_FLUSH_ALL); | |
389 | |
390 for (i=0; i < 2000000; i++) { | |
391 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) | |
392 break; | |
393 } | |
394 } | |
395 | |
396 static void _radeon_engine_idle(void); | |
397 static void _radeon_fifo_wait(unsigned); | |
398 #define radeon_engine_idle() _radeon_engine_idle() | |
399 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) | |
400 | |
401 static void radeon_engine_reset( void ) | |
402 { | |
403 uint32_t clock_cntl_index, mclk_cntl, rbbm_soft_reset; | |
404 | |
405 radeon_engine_flush (); | |
406 | |
407 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); | |
408 mclk_cntl = INPLL(MCLK_CNTL); | |
409 | |
410 OUTPLL(MCLK_CNTL, (mclk_cntl | | |
411 FORCEON_MCLKA | | |
412 FORCEON_MCLKB | | |
413 FORCEON_YCLKA | | |
414 FORCEON_YCLKB | | |
415 FORCEON_MC | | |
416 FORCEON_AIC)); | |
417 rbbm_soft_reset = INREG(RBBM_SOFT_RESET); | |
418 | |
419 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | | |
420 SOFT_RESET_CP | | |
421 SOFT_RESET_HI | | |
422 SOFT_RESET_SE | | |
423 SOFT_RESET_RE | | |
424 SOFT_RESET_PP | | |
425 SOFT_RESET_E2 | | |
426 SOFT_RESET_RB | | |
427 SOFT_RESET_HDP); | |
428 INREG(RBBM_SOFT_RESET); | |
429 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (uint32_t) | |
430 ~(SOFT_RESET_CP | | |
431 SOFT_RESET_HI | | |
432 SOFT_RESET_SE | | |
433 SOFT_RESET_RE | | |
434 SOFT_RESET_PP | | |
435 SOFT_RESET_E2 | | |
436 SOFT_RESET_RB | | |
437 SOFT_RESET_HDP)); | |
438 INREG(RBBM_SOFT_RESET); | |
439 | |
440 OUTPLL(MCLK_CNTL, mclk_cntl); | |
441 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); | |
442 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); | |
443 | |
444 return; | |
445 } | |
446 #endif | |
447 static void radeon_engine_restore( void ) | |
448 { | |
449 #ifndef RAGE128 | |
450 int pitch64; | |
451 uint32_t xres,yres,bpp; | |
452 radeon_fifo_wait(1); | |
453 xres = radeon_get_xres(); | |
454 yres = radeon_get_yres(); | |
455 bpp = radeon_vid_get_dbpp(); | |
456 /* turn of all automatic flushing - we'll do it all */ | |
457 OUTREG(RB2D_DSTCACHE_MODE, 0); | |
458 | |
459 pitch64 = ((xres * (bpp / 8) + 0x3f)) >> 6; | |
460 | |
461 radeon_fifo_wait(1); | |
462 OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) | | |
463 (pitch64 << 22)); | |
464 | |
465 radeon_fifo_wait(1); | |
466 #if defined(WORDS_BIGENDIAN) | |
467 #ifdef RADEON | |
468 OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); | |
469 #endif | |
470 #else | |
471 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); | |
472 #endif | |
473 | |
474 radeon_fifo_wait(1); | |
475 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | |
476 | DEFAULT_SC_BOTTOM_MAX)); | |
477 radeon_fifo_wait(1); | |
478 OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL) | |
479 | GMC_BRUSH_SOLID_COLOR | |
480 | GMC_SRC_DATATYPE_COLOR)); | |
481 | |
482 radeon_fifo_wait(7); | |
483 OUTREG(DST_LINE_START, 0); | |
484 OUTREG(DST_LINE_END, 0); | |
485 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); | |
486 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); | |
487 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); | |
488 OUTREG(DP_SRC_BKGD_CLR, 0x00000000); | |
489 OUTREG(DP_WRITE_MASK, 0xffffffff); | |
490 | |
491 radeon_engine_idle(); | |
492 #endif | |
493 } | |
494 #ifdef RAGE128 | |
495 static void _radeon_fifo_wait (unsigned entries) | |
496 { | |
497 unsigned i; | |
498 | |
499 for(;;) | |
500 { | |
501 for (i=0; i<2000000; i++) | |
502 if ((INREG(GUI_STAT) & GUI_FIFOCNT_MASK) >= entries) | |
503 return; | |
504 radeon_engine_reset(); | |
505 radeon_engine_restore(); | |
506 } | |
507 } | |
508 | |
509 static void _radeon_engine_idle ( void ) | |
510 { | |
511 unsigned i; | |
512 | |
513 /* ensure FIFO is empty before waiting for idle */ | |
514 radeon_fifo_wait (64); | |
515 for(;;) | |
516 { | |
517 for (i=0; i<2000000; i++) { | |
518 if ((INREG(GUI_STAT) & GUI_ACTIVE) == 0) { | |
519 radeon_engine_flush (); | |
520 return; | |
521 } | |
522 } | |
523 radeon_engine_reset(); | |
524 radeon_engine_restore(); | |
525 } | |
526 } | |
527 #else | |
528 static void _radeon_fifo_wait (unsigned entries) | |
529 { | |
530 unsigned i; | |
531 | |
532 for(;;) | |
533 { | |
534 for (i=0; i<2000000; i++) | |
535 if ((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries) | |
536 return; | |
537 radeon_engine_reset(); | |
538 radeon_engine_restore(); | |
539 } | |
540 } | |
541 static void _radeon_engine_idle ( void ) | |
542 { | |
543 int i; | |
544 | |
545 /* ensure FIFO is empty before waiting for idle */ | |
546 radeon_fifo_wait (64); | |
547 for(;;) | |
548 { | |
549 for (i=0; i<2000000; i++) { | |
550 if (((INREG(RBBM_STATUS) & RBBM_ACTIVE)) == 0) { | |
551 radeon_engine_flush (); | |
552 return; | |
553 } | |
554 } | |
555 radeon_engine_reset(); | |
556 radeon_engine_restore(); | |
557 } | |
558 } | |
559 #endif | |
560 | |
561 #ifndef RAGE128 | |
562 /* Reference color space transform data */ | |
563 typedef struct tagREF_TRANSFORM | |
564 { | |
565 float RefLuma; | |
566 float RefRCb; | |
567 float RefRCr; | |
568 float RefGCb; | |
569 float RefGCr; | |
570 float RefBCb; | |
571 float RefBCr; | |
572 } REF_TRANSFORM; | |
573 | |
574 /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ | |
575 REF_TRANSFORM trans[2] = | |
576 { | |
577 {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ | |
578 {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ | |
579 }; | |
580 /**************************************************************************** | |
581 * SetTransform * | |
582 * Function: Calculates and sets color space transform from supplied * | |
583 * reference transform, gamma, brightness, contrast, hue and * | |
584 * saturation. * | |
585 * Inputs: bright - brightness * | |
586 * cont - contrast * | |
587 * sat - saturation * | |
588 * hue - hue * | |
589 * red_intensity - intense of red component * | |
590 * green_intensity - intense of green component * | |
591 * blue_intensity - intense of blue component * | |
592 * ref - index to the table of refernce transforms * | |
593 * Outputs: NONE * | |
594 ****************************************************************************/ | |
595 | |
596 static void radeon_set_transform(float bright, float cont, float sat, | |
597 float hue, float red_intensity, | |
598 float green_intensity,float blue_intensity, | |
599 unsigned ref) | |
600 { | |
601 float OvHueSin, OvHueCos; | |
602 float CAdjLuma, CAdjOff; | |
603 float RedAdj,GreenAdj,BlueAdj; | |
604 float CAdjRCb, CAdjRCr; | |
605 float CAdjGCb, CAdjGCr; | |
606 float CAdjBCb, CAdjBCr; | |
607 float OvLuma, OvROff, OvGOff, OvBOff; | |
608 float OvRCb, OvRCr; | |
609 float OvGCb, OvGCr; | |
610 float OvBCb, OvBCr; | |
611 float Loff = 64.0; | |
612 float Coff = 512.0f; | |
613 | |
614 uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; | |
615 uint32_t dwOvRCb, dwOvRCr; | |
616 uint32_t dwOvGCb, dwOvGCr; | |
617 uint32_t dwOvBCb, dwOvBCr; | |
618 | |
619 if (ref >= 2) return; | |
620 | |
621 OvHueSin = sin((double)hue); | |
622 OvHueCos = cos((double)hue); | |
623 | |
624 CAdjLuma = cont * trans[ref].RefLuma; | |
625 CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; | |
626 RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0; | |
627 GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0; | |
628 BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0; | |
629 | |
630 CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; | |
631 CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; | |
632 CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); | |
633 CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); | |
634 CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; | |
635 CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; | |
636 | |
637 #if 0 /* default constants */ | |
638 CAdjLuma = 1.16455078125; | |
639 | |
640 CAdjRCb = 0.0; | |
641 CAdjRCr = 1.59619140625; | |
642 CAdjGCb = -0.39111328125; | |
643 CAdjGCr = -0.8125; | |
644 CAdjBCb = 2.01708984375; | |
645 CAdjBCr = 0; | |
646 #endif | |
647 OvLuma = CAdjLuma; | |
648 OvRCb = CAdjRCb; | |
649 OvRCr = CAdjRCr; | |
650 OvGCb = CAdjGCb; | |
651 OvGCr = CAdjGCr; | |
652 OvBCb = CAdjBCb; | |
653 OvBCr = CAdjBCr; | |
654 OvROff = RedAdj + CAdjOff - | |
655 OvLuma * Loff - (OvRCb + OvRCr) * Coff; | |
656 OvGOff = GreenAdj + CAdjOff - | |
657 OvLuma * Loff - (OvGCb + OvGCr) * Coff; | |
658 OvBOff = BlueAdj + CAdjOff - | |
659 OvLuma * Loff - (OvBCb + OvBCr) * Coff; | |
660 #if 0 /* default constants */ | |
661 OvROff = -888.5; | |
662 OvGOff = 545; | |
663 OvBOff = -1104; | |
664 #endif | |
665 | |
666 dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; | |
667 dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; | |
668 dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; | |
669 /* Whatever docs say about R200 having 3.8 format instead of 3.11 | |
670 as in Radeon is a lie */ | |
671 #if 0 | |
672 if(RadeonFamily == 100) | |
673 { | |
674 #endif | |
675 dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; | |
676 dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; | |
677 dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; | |
678 dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; | |
679 dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; | |
680 dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; | |
681 dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; | |
682 #if 0 | |
683 } | |
684 else | |
685 { | |
686 dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; | |
687 dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; | |
688 dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; | |
689 dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; | |
690 dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; | |
691 dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; | |
692 dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; | |
693 } | |
694 #endif | |
695 OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); | |
696 OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); | |
697 OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); | |
698 OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); | |
699 OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); | |
700 OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); | |
701 } | |
702 | |
703 /* Gamma curve definition */ | |
704 typedef struct | |
705 { | |
706 unsigned int gammaReg; | |
707 unsigned int gammaSlope; | |
708 unsigned int gammaOffset; | |
709 }GAMMA_SETTINGS; | |
710 | |
711 /* Recommended gamma curve parameters */ | |
712 GAMMA_SETTINGS r200_def_gamma[18] = | |
713 { | |
714 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
715 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
716 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
717 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
718 {OV0_GAMMA_80_BF, 0x100, 0x0100}, | |
719 {OV0_GAMMA_C0_FF, 0x100, 0x0100}, | |
720 {OV0_GAMMA_100_13F, 0x100, 0x0200}, | |
721 {OV0_GAMMA_140_17F, 0x100, 0x0200}, | |
722 {OV0_GAMMA_180_1BF, 0x100, 0x0300}, | |
723 {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, | |
724 {OV0_GAMMA_200_23F, 0x100, 0x0400}, | |
725 {OV0_GAMMA_240_27F, 0x100, 0x0400}, | |
726 {OV0_GAMMA_280_2BF, 0x100, 0x0500}, | |
727 {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, | |
728 {OV0_GAMMA_300_33F, 0x100, 0x0600}, | |
729 {OV0_GAMMA_340_37F, 0x100, 0x0600}, | |
730 {OV0_GAMMA_380_3BF, 0x100, 0x0700}, | |
731 {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} | |
732 }; | |
733 | |
734 GAMMA_SETTINGS r100_def_gamma[6] = | |
735 { | |
736 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
737 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
738 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
739 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
740 {OV0_GAMMA_380_3BF, 0x100, 0x0100}, | |
741 {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} | |
742 }; | |
743 | |
744 static void make_default_gamma_correction( void ) | |
745 { | |
746 size_t i; | |
747 if(RadeonFamily == 100) { | |
748 OUTREG(OV0_LIN_TRANS_A, 0x12A00000); | |
749 OUTREG(OV0_LIN_TRANS_B, 0x199018FE); | |
750 OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); | |
751 OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); | |
752 OUTREG(OV0_LIN_TRANS_E, 0x12A02050); | |
753 OUTREG(OV0_LIN_TRANS_F, 0x0000174E); | |
754 for(i=0; i<6; i++){ | |
755 OUTREG(r100_def_gamma[i].gammaReg, | |
756 (r100_def_gamma[i].gammaSlope<<16) | | |
757 r100_def_gamma[i].gammaOffset); | |
758 } | |
759 } | |
760 else{ | |
761 OUTREG(OV0_LIN_TRANS_A, 0x12a00000); | |
762 OUTREG(OV0_LIN_TRANS_B, 0x1990190e); | |
763 OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); | |
764 OUTREG(OV0_LIN_TRANS_D, 0xf3000442); | |
765 OUTREG(OV0_LIN_TRANS_E, 0x12a02040); | |
766 OUTREG(OV0_LIN_TRANS_F, 0x175f); | |
767 | |
768 /* Default Gamma, | |
769 Of 18 segments for gamma cure, all segments in R200 are programmable, | |
770 while only lower 4 and upper 2 segments are programmable in Radeon*/ | |
771 for(i=0; i<18; i++){ | |
772 OUTREG(r200_def_gamma[i].gammaReg, | |
773 (r200_def_gamma[i].gammaSlope<<16) | | |
774 r200_def_gamma[i].gammaOffset); | |
775 } | |
776 } | |
777 } | |
778 #endif | |
779 | |
780 static void radeon_vid_make_default(void) | |
781 { | |
782 #ifdef RAGE128 | |
783 OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brightness and saturation for Rage128 */ | |
784 #else | |
785 make_default_gamma_correction(); | |
786 #endif | |
787 besr.deinterlace_pattern = 0x900AAAAA; | |
788 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
789 besr.deinterlace_on=1; | |
790 besr.double_buff=1; | |
791 besr.ckey_on=0; | |
792 besr.graphics_key_msk=0; | |
793 besr.graphics_key_clr=0; | |
794 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; | |
795 } | |
796 | |
797 static unsigned short ati_card_ids[] = | |
798 { | |
799 #ifdef RAGE128 | |
800 /* | |
801 This driver should be compatible with Rage128 (pro) chips. | |
802 (include adaptive deinterlacing!!!). | |
803 Moreover: the same logic can be used with Mach64 chips. | |
804 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
805 but they are incompatible by i/o ports. So if enthusiasts will want | |
806 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
807 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
808 fourccs (422 and 420 formats only). | |
809 */ | |
810 /* Rage128 Pro GL */ | |
811 DEVICE_ATI_RAGE_128_PA_PRO, | |
812 DEVICE_ATI_RAGE_128_PB_PRO, | |
813 DEVICE_ATI_RAGE_128_PC_PRO, | |
814 DEVICE_ATI_RAGE_128_PD_PRO, | |
815 DEVICE_ATI_RAGE_128_PE_PRO, | |
816 DEVICE_ATI_RAGE_128_PF_PRO, | |
817 /* Rage128 Pro VR */ | |
818 DEVICE_ATI_RAGE_128_PG_PRO, | |
819 DEVICE_ATI_RAGE_128_PH_PRO, | |
820 DEVICE_ATI_RAGE_128_PI_PRO, | |
821 DEVICE_ATI_RAGE_128_PJ_PRO, | |
822 DEVICE_ATI_RAGE_128_PK_PRO, | |
823 DEVICE_ATI_RAGE_128_PL_PRO, | |
824 DEVICE_ATI_RAGE_128_PM_PRO, | |
825 DEVICE_ATI_RAGE_128_PN_PRO, | |
826 DEVICE_ATI_RAGE_128_PO_PRO, | |
827 DEVICE_ATI_RAGE_128_PP_PRO, | |
828 DEVICE_ATI_RAGE_128_PQ_PRO, | |
829 DEVICE_ATI_RAGE_128_PR_PRO, | |
830 DEVICE_ATI_RAGE_128_PS_PRO, | |
831 DEVICE_ATI_RAGE_128_PT_PRO, | |
832 DEVICE_ATI_RAGE_128_PU_PRO, | |
833 DEVICE_ATI_RAGE_128_PV_PRO, | |
834 DEVICE_ATI_RAGE_128_PW_PRO, | |
835 DEVICE_ATI_RAGE_128_PX_PRO, | |
836 /* Rage128 GL */ | |
837 DEVICE_ATI_RAGE_128_RE_SG, | |
838 DEVICE_ATI_RAGE_128_RF_SG, | |
839 DEVICE_ATI_RAGE_128_RG, | |
840 DEVICE_ATI_RAGE_128_RK_VR, | |
841 DEVICE_ATI_RAGE_128_RL_VR, | |
842 DEVICE_ATI_RAGE_128_SE_4X, | |
843 DEVICE_ATI_RAGE_128_SF_4X, | |
844 DEVICE_ATI_RAGE_128_SG_4X, | |
845 DEVICE_ATI_RAGE_128_SH, | |
846 DEVICE_ATI_RAGE_128_SK_4X, | |
847 DEVICE_ATI_RAGE_128_SL_4X, | |
848 DEVICE_ATI_RAGE_128_SM_4X, | |
849 DEVICE_ATI_RAGE_128_4X, | |
850 DEVICE_ATI_RAGE_128_PRO, | |
851 DEVICE_ATI_RAGE_128_PRO2, | |
852 DEVICE_ATI_RAGE_128_PRO3, | |
853 /* these seem to be based on rage 128 instead of mach64 */ | |
854 DEVICE_ATI_RAGE_MOBILITY_M3, | |
855 DEVICE_ATI_RAGE_MOBILITY_M32 | |
856 #else | |
857 /* Radeons (indeed: Rage 256 Pro ;) */ | |
858 DEVICE_ATI_RADEON_R100_QD, | |
859 DEVICE_ATI_RADEON_R100_QE, | |
860 DEVICE_ATI_RADEON_R100_QF, | |
861 DEVICE_ATI_RADEON_R100_QG, | |
862 DEVICE_ATI_RADEON_VE_QY, | |
863 DEVICE_ATI_RADEON_VE_QZ, | |
864 DEVICE_ATI_RADEON_MOBILITY_M7, | |
865 DEVICE_ATI_RADEON_MOBILITY_M72, | |
866 DEVICE_ATI_RADEON_MOBILITY_M6, | |
867 DEVICE_ATI_RADEON_MOBILITY_M62, | |
868 DEVICE_ATI_RADEON_MOBILITY_U1, | |
869 DEVICE_ATI_RADEON_R200_BB, | |
870 DEVICE_ATI_RADEON_R200_QH, | |
871 DEVICE_ATI_RADEON_R200_QI, | |
872 DEVICE_ATI_RADEON_R200_QJ, | |
873 DEVICE_ATI_RADEON_R200_QK, | |
874 DEVICE_ATI_RADEON_R200_QL, | |
875 DEVICE_ATI_RADEON_R200_QM, | |
876 DEVICE_ATI_RADEON_R200_QH2, | |
877 DEVICE_ATI_RADEON_R200_QI2, | |
878 DEVICE_ATI_RADEON_R200_QJ2, | |
879 DEVICE_ATI_RADEON_R200_QK2, | |
880 DEVICE_ATI_RADEON_RV200_QW, | |
881 DEVICE_ATI_RADEON_RV200_QX, | |
882 DEVICE_ATI_RADEON_R250_ID, | |
883 DEVICE_ATI_RADEON_R250_IE, | |
884 DEVICE_ATI_RADEON_R250_IF, | |
885 DEVICE_ATI_RADEON_R250_IG, | |
886 DEVICE_ATI_RADEON_R250_LD, | |
887 DEVICE_ATI_RADEON_R250_LE, | |
888 DEVICE_ATI_RADEON_R250_LF, | |
889 DEVICE_ATI_RADEON_R250_LG, | |
890 DEVICE_ATI_RV370_5B60_RADEON, | |
891 DEVICE_ATI_RV250_5C61_RADEON, | |
892 DEVICE_ATI_RV250_5C63_RADEON, | |
893 DEVICE_ATI_RV280_RADEON_9200, | |
894 DEVICE_ATI_RV280_RADEON_92002, | |
895 DEVICE_ATI_RV280_RADEON_92003, | |
896 DEVICE_ATI_RV280_RADEON_92004, | |
897 DEVICE_ATI_RV280_RADEON_92005, | |
898 DEVICE_ATI_RV280_RADEON_92006, | |
899 DEVICE_ATI_RADEON_R300_ND, | |
900 DEVICE_ATI_RADEON_R300_NE, | |
901 DEVICE_ATI_RADEON_R300_NF, | |
902 DEVICE_ATI_RADEON_R300_NG, | |
903 DEVICE_ATI_RADEON_R300_AE, | |
904 DEVICE_ATI_RADEON_R300_AF, | |
905 DEVICE_ATI_RADEON_RV350_AP, | |
906 DEVICE_ATI_RADEON_RV350_AQ, | |
907 DEVICE_ATI_RADEON_RV350_AR, | |
908 DEVICE_ATI_RADEON_RV350_BK, | |
909 DEVICE_ATI_RADEON_R350_AH, | |
910 DEVICE_ATI_RADEON_R350_AI, | |
911 DEVICE_ATI_RADEON_R350_NH, | |
912 DEVICE_ATI_RADEON_R360_NJ, | |
913 DEVICE_ATI_RV350_MOBILITY_RADEON, | |
914 DEVICE_ATI_RV350_MOBILITY_RADEON2 | |
915 #endif | |
916 }; | |
917 | |
918 static int find_chip(unsigned chip_id) | |
919 { | |
920 unsigned i; | |
921 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) | |
922 { | |
923 if(chip_id == ati_card_ids[i]) return i; | |
924 } | |
925 return -1; | |
926 } | |
927 | |
928 static pciinfo_t pci_info; | |
929 static int probed=0; | |
930 | |
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931 static vidix_capability_t def_cap = |
22850 | 932 { |
933 #ifdef RAGE128 | |
934 "BES driver for Rage128 cards", | |
935 #else | |
936 "BES driver for Radeon cards", | |
937 #endif | |
938 "Nick Kurshev", | |
939 TYPE_OUTPUT | TYPE_FX, | |
940 { 0, 0, 0, 0 }, | |
941 2048, | |
942 2048, | |
943 4, | |
944 4, | |
945 -1, | |
946 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, | |
947 VENDOR_ATI, | |
948 0, | |
949 { 0, 0, 0, 0} | |
950 }; | |
951 | |
952 #ifdef HAVE_X11 | |
953 static void probe_fireGL_driver(void) { | |
954 Display *dp = XOpenDisplay ((void*)0); | |
955 int n = 0; | |
956 char **extlist; | |
957 if (dp==NULL) { | |
958 return; | |
959 } | |
960 extlist = XListExtensions (dp, &n); | |
961 XCloseDisplay (dp); | |
962 if (extlist) { | |
963 int i; | |
964 int ext_fgl = 0, ext_fglrx = 0; | |
965 for (i = 0; i < n; i++) { | |
966 if (!strcmp(extlist[i], "ATIFGLEXTENSION")) ext_fgl = 1; | |
967 if (!strcmp(extlist[i], "ATIFGLRXDRI")) ext_fglrx = 1; | |
968 } | |
969 if (ext_fgl) { | |
970 printf(RADEON_MSG" ATI FireGl driver detected"); | |
971 firegl_shift = 0x500000; | |
972 if (!ext_fglrx) { | |
973 printf(", but DRI seems not to be activated\n"); | |
974 printf(RADEON_MSG" Output may not work correctly, check your DRI configuration!"); | |
975 } | |
976 printf("\n"); | |
977 } | |
978 } | |
979 } | |
980 #endif | |
981 | |
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982 static int radeon_probe( int verbose,int force ) |
22850 | 983 { |
984 pciinfo_t lst[MAX_PCI_DEVICES]; | |
985 unsigned i,num_pci; | |
986 int err; | |
987 __verbose = verbose; | |
988 err = pci_scan(lst,&num_pci); | |
989 if(err) | |
990 { | |
991 printf(RADEON_MSG" Error occurred during pci scan: %s\n",strerror(err)); | |
992 return err; | |
993 } | |
994 else | |
995 { | |
996 err = ENXIO; | |
997 for(i=0;i<num_pci;i++) | |
998 { | |
999 if(lst[i].vendor == VENDOR_ATI) | |
1000 { | |
1001 int idx; | |
1002 const char *dname; | |
1003 idx = find_chip(lst[i].device); | |
1004 if(idx == -1 && force == PROBE_NORMAL) continue; | |
1005 dname = pci_device_name(VENDOR_ATI,lst[i].device); | |
1006 dname = dname ? dname : "Unknown chip"; | |
1007 printf(RADEON_MSG" Found chip: %s\n",dname); | |
1008 #if 0 | |
1009 if ((lst[i].command & PCI_COMMAND_IO) == 0) | |
1010 { | |
1011 printf("[radeon] Device is disabled, ignoring\n"); | |
1012 continue; | |
1013 } | |
1014 #endif | |
1015 #ifndef RAGE128 | |
1016 if(idx != -1) | |
1017 #ifdef HAVE_X11 | |
1018 probe_fireGL_driver(); | |
1019 #endif | |
1020 { | |
1021 switch(ati_card_ids[idx]) { | |
1022 /* Original radeon */ | |
1023 case DEVICE_ATI_RADEON_R100_QD: | |
1024 case DEVICE_ATI_RADEON_R100_QE: | |
1025 case DEVICE_ATI_RADEON_R100_QF: | |
1026 case DEVICE_ATI_RADEON_R100_QG: | |
1027 RadeonFamily = 100; | |
1028 break; | |
1029 | |
1030 /* Radeon VE / Radeon Mobility */ | |
1031 case DEVICE_ATI_RADEON_VE_QY: | |
1032 case DEVICE_ATI_RADEON_VE_QZ: | |
1033 case DEVICE_ATI_RADEON_MOBILITY_M6: | |
1034 case DEVICE_ATI_RADEON_MOBILITY_M62: | |
1035 case DEVICE_ATI_RADEON_MOBILITY_U1: | |
1036 RadeonFamily = 120; | |
1037 break; | |
1038 | |
1039 /* Radeon 7500 / Radeon Mobility 7500 */ | |
1040 case DEVICE_ATI_RADEON_RV200_QW: | |
1041 case DEVICE_ATI_RADEON_RV200_QX: | |
1042 case DEVICE_ATI_RADEON_MOBILITY_M7: | |
1043 case DEVICE_ATI_RADEON_MOBILITY_M72: | |
1044 RadeonFamily = 150; | |
1045 break; | |
1046 | |
1047 /* Radeon 8500 */ | |
1048 case DEVICE_ATI_RADEON_R200_BB: | |
1049 case DEVICE_ATI_RADEON_R200_QH: | |
1050 case DEVICE_ATI_RADEON_R200_QI: | |
1051 case DEVICE_ATI_RADEON_R200_QJ: | |
1052 case DEVICE_ATI_RADEON_R200_QK: | |
1053 case DEVICE_ATI_RADEON_R200_QL: | |
1054 case DEVICE_ATI_RADEON_R200_QM: | |
1055 case DEVICE_ATI_RADEON_R200_QH2: | |
1056 case DEVICE_ATI_RADEON_R200_QI2: | |
1057 case DEVICE_ATI_RADEON_R200_QJ2: | |
1058 case DEVICE_ATI_RADEON_R200_QK2: | |
1059 RadeonFamily = 200; | |
1060 break; | |
1061 | |
1062 /* Radeon 9000 */ | |
1063 case DEVICE_ATI_RADEON_R250_ID: | |
1064 case DEVICE_ATI_RADEON_R250_IE: | |
1065 case DEVICE_ATI_RADEON_R250_IF: | |
1066 case DEVICE_ATI_RADEON_R250_IG: | |
1067 case DEVICE_ATI_RADEON_R250_LD: | |
1068 case DEVICE_ATI_RADEON_R250_LE: | |
1069 case DEVICE_ATI_RADEON_R250_LF: | |
1070 case DEVICE_ATI_RADEON_R250_LG: | |
1071 case DEVICE_ATI_RV250_5C61_RADEON: | |
1072 case DEVICE_ATI_RV250_5C63_RADEON: | |
1073 RadeonFamily = 250; | |
1074 break; | |
1075 | |
1076 /* Radeon 9200 */ | |
1077 case DEVICE_ATI_RV280_RADEON_9200: | |
1078 case DEVICE_ATI_RV280_RADEON_92002: | |
1079 case DEVICE_ATI_RV280_RADEON_92003: | |
1080 case DEVICE_ATI_RV280_RADEON_92004: | |
1081 case DEVICE_ATI_RV280_RADEON_92005: | |
1082 case DEVICE_ATI_RV280_RADEON_92006: | |
1083 RadeonFamily = 280; | |
1084 break; | |
1085 | |
1086 /* Radeon 9700 */ | |
1087 case DEVICE_ATI_RADEON_R300_ND: | |
1088 case DEVICE_ATI_RADEON_R300_NE: | |
1089 case DEVICE_ATI_RADEON_R300_NF: | |
1090 case DEVICE_ATI_RADEON_R300_NG: | |
1091 case DEVICE_ATI_RADEON_R300_AE: | |
1092 case DEVICE_ATI_RADEON_R300_AF: | |
1093 RadeonFamily = 300; | |
1094 break; | |
1095 | |
1096 /* Radeon 9600/9800 */ | |
1097 case DEVICE_ATI_RV370_5B60_RADEON: | |
1098 case DEVICE_ATI_RADEON_RV350_AP: | |
1099 case DEVICE_ATI_RADEON_RV350_AQ: | |
1100 case DEVICE_ATI_RADEON_RV350_AR: | |
1101 case DEVICE_ATI_RADEON_RV350_BK: | |
1102 case DEVICE_ATI_RADEON_R350_NH: | |
1103 case DEVICE_ATI_RADEON_R350_AH: | |
1104 case DEVICE_ATI_RADEON_R350_AI: | |
1105 case DEVICE_ATI_RADEON_R360_NJ: | |
1106 case DEVICE_ATI_RV350_MOBILITY_RADEON: | |
1107 case DEVICE_ATI_RV350_MOBILITY_RADEON2: | |
1108 RadeonFamily = 350; | |
1109 break; | |
1110 | |
1111 default: | |
1112 break; | |
1113 } | |
1114 } | |
1115 #endif | |
1116 if(force > PROBE_NORMAL) | |
1117 { | |
1118 printf(RADEON_MSG" Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); | |
1119 if(idx == -1) | |
1120 #ifdef RAGE128 | |
1121 printf(RADEON_MSG" Assuming it as Rage128\n"); | |
1122 #else | |
1123 printf(RADEON_MSG" Assuming it as Radeon1\n"); | |
1124 #endif | |
1125 } | |
1126 def_cap.device_id = lst[i].device; | |
1127 err = 0; | |
1128 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); | |
1129 probed=1; | |
1130 break; | |
1131 } | |
1132 } | |
1133 } | |
1134 if(err && verbose) printf(RADEON_MSG" Can't find chip\n"); | |
1135 return err; | |
1136 } | |
1137 | |
1138 static void radeon_vid_dump_regs( void ); /* forward declaration */ | |
1139 | |
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1140 static int radeon_init( void ) |
22850 | 1141 { |
1142 int err; | |
1143 if(!probed) | |
1144 { | |
1145 printf(RADEON_MSG" Driver was not probed but is being initializing\n"); | |
1146 return EINTR; | |
1147 } | |
1148 if((radeon_mmio_base = map_phys_mem(pci_info.base2,0xFFFF))==(void *)-1) return ENOMEM; | |
1149 radeon_ram_size = INREG(CONFIG_MEMSIZE); | |
1150 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ | |
1151 radeon_ram_size &= CONFIG_MEMSIZE_MASK; | |
1152 #ifdef RADEON | |
1153 /* according to XFree86 4.2.0, some production M6's return 0 for 8MB */ | |
1154 if (radeon_ram_size == 0 && | |
1155 (def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M6 || | |
1156 def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M62)) | |
1157 { | |
1158 printf(RADEON_MSG" Workarounding buggy Radeon Mobility M6 (0 vs. 8MB ram)\n"); | |
1159 radeon_ram_size = 8192*1024; | |
1160 } | |
1161 #else | |
1162 /* Rage Mobility (rage128) also has memsize bug */ | |
1163 if (radeon_ram_size == 0 && | |
1164 (def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M3 || | |
1165 def_cap.device_id == DEVICE_ATI_RAGE_128_RL_VR || | |
1166 def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M32)) | |
1167 { | |
1168 printf(RADEON_MSG" Workarounding buggy Rage Mobility M3 (0 vs. 8MB ram)\n"); | |
1169 radeon_ram_size = 8192*1024; | |
1170 } | |
1171 #endif | |
1172 printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); | |
1173 #ifdef WIN32 | |
1174 //mapping large areas of video ram will fail on windows | |
1175 if(radeon_ram_size > 16*1024*1024)radeon_ram_size=16*1024*1024; | |
1176 #endif | |
1177 if((radeon_mem_base = map_phys_mem(pci_info.base0,radeon_ram_size))==(void *)-1) return ENOMEM; | |
1178 memset(&besr,0,sizeof(bes_registers_t)); | |
1179 radeon_vid_make_default(); | |
1180 err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB); | |
1181 if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n"); | |
1182 | |
1183 radeon_fifo_wait(3); | |
1184 SAVED_OV0_GRAPHICS_KEY_CLR = INREG(OV0_GRAPHICS_KEY_CLR); | |
1185 SAVED_OV0_GRAPHICS_KEY_MSK = INREG(OV0_GRAPHICS_KEY_MSK); | |
1186 SAVED_OV0_VID_KEY_CLR = INREG(OV0_VID_KEY_CLR); | |
1187 SAVED_OV0_VID_KEY_MSK = INREG(OV0_VID_KEY_MSK); | |
1188 SAVED_OV0_KEY_CNTL = INREG(OV0_KEY_CNTL); | |
1189 printf(RADEON_MSG" Saved overlay colorkey settings\n"); | |
1190 | |
1191 #ifdef RADEON | |
1192 switch(RadeonFamily) | |
1193 { | |
1194 case 100: | |
1195 case 120: | |
1196 case 150: | |
1197 case 250: | |
1198 case 280: | |
1199 is_shift_required=1; | |
1200 break; | |
1201 default: | |
1202 break; | |
1203 } | |
1204 #endif | |
1205 | |
1206 /* XXX: hack, but it works for me (tm) */ | |
1207 #ifdef WORDS_BIGENDIAN | |
1208 #if defined(RAGE128) | |
1209 /* code from gatos */ | |
1210 { | |
1211 SAVED_CONFIG_CNTL = INREG(CONFIG_CNTL); | |
1212 OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL & | |
1213 ~(APER_0_BIG_ENDIAN_16BPP_SWAP|APER_0_BIG_ENDIAN_32BPP_SWAP)); | |
1214 | |
1215 // printf("saved: %x, current: %x\n", SAVED_CONFIG_CNTL, | |
1216 // INREG(CONFIG_CNTL)); | |
1217 } | |
1218 #else | |
1219 /*code from radeon_video.c*/ | |
1220 { | |
1221 SAVED_CONFIG_CNTL = INREG(RADEON_SURFACE_CNTL); | |
1222 /* OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | | |
1223 RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP); | |
1224 */ | |
1225 OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL & ~(RADEON_NONSURF_AP0_SWP_32BPP | |
1226 | RADEON_NONSURF_AP0_SWP_16BPP)); | |
1227 | |
1228 /* | |
1229 OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | RADEON_NONSURF_AP0_SWP_32BPP) | |
1230 & ~RADEON_NONSURF_AP0_SWP_16BPP); | |
1231 */ | |
1232 } | |
1233 #endif | |
1234 #endif | |
1235 | |
1236 if(__verbose > 1) radeon_vid_dump_regs(); | |
1237 return 0; | |
1238 } | |
1239 | |
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1240 static void radeon_destroy( void ) |
22850 | 1241 { |
1242 /* remove colorkeying */ | |
1243 radeon_fifo_wait(3); | |
1244 OUTREG(OV0_GRAPHICS_KEY_CLR, SAVED_OV0_GRAPHICS_KEY_CLR); | |
1245 OUTREG(OV0_GRAPHICS_KEY_MSK, SAVED_OV0_GRAPHICS_KEY_MSK); | |
1246 OUTREG(OV0_VID_KEY_CLR, SAVED_OV0_VID_KEY_CLR); | |
1247 OUTREG(OV0_VID_KEY_MSK, SAVED_OV0_VID_KEY_MSK); | |
1248 OUTREG(OV0_KEY_CNTL, SAVED_OV0_KEY_CNTL); | |
1249 printf(RADEON_MSG" Restored overlay colorkey settings\n"); | |
1250 | |
1251 #ifdef WORDS_BIGENDIAN | |
1252 #if defined(RAGE128) | |
1253 OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL); | |
1254 // printf("saved: %x, restored: %x\n", SAVED_CONFIG_CNTL, | |
1255 // INREG(CONFIG_CNTL)); | |
1256 #else | |
1257 OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL); | |
1258 #endif | |
1259 #endif | |
1260 | |
1261 unmap_phys_mem(radeon_mem_base,radeon_ram_size); | |
1262 unmap_phys_mem(radeon_mmio_base,0xFFFF); | |
1263 } | |
1264 | |
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1265 static int radeon_get_caps(vidix_capability_t *to) |
22850 | 1266 { |
1267 memcpy(to,&def_cap,sizeof(vidix_capability_t)); | |
1268 return 0; | |
1269 } | |
1270 | |
1271 /* | |
1272 Full list of fourcc which are supported by Win2K redeon driver: | |
1273 YUY2, UYVY, DDES, OGLT, OGL2, OGLS, OGLB, OGNT, OGNZ, OGNS, | |
1274 IF09, YVU9, IMC4, M2IA, IYUV, VBID, DXT1, DXT2, DXT3, DXT4, DXT5 | |
1275 */ | |
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1276 static uint32_t supported_fourcc[] = |
22850 | 1277 { |
1278 IMGFMT_Y800, IMGFMT_Y8, IMGFMT_YVU9, IMGFMT_IF09, | |
1279 IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV, | |
1280 IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU, | |
1281 IMGFMT_RGB15, IMGFMT_BGR15, | |
1282 IMGFMT_RGB16, IMGFMT_BGR16, | |
1283 IMGFMT_RGB32, IMGFMT_BGR32 | |
1284 }; | |
1285 | |
1286 inline static int is_supported_fourcc(uint32_t fourcc) | |
1287 { | |
1288 unsigned int i; | |
1289 for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++) | |
1290 { | |
1291 if(fourcc==supported_fourcc[i]) return 1; | |
1292 } | |
1293 return 0; | |
1294 } | |
1295 | |
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1296 static int radeon_query_fourcc(vidix_fourcc_t *to) |
22850 | 1297 { |
1298 if(is_supported_fourcc(to->fourcc)) | |
1299 { | |
1300 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
1301 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
1302 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
1303 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
1304 VID_DEPTH_32BPP; | |
1305 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; | |
1306 return 0; | |
1307 } | |
1308 else to->depth = to->flags = 0; | |
1309 return ENOSYS; | |
1310 } | |
1311 | |
1312 static void radeon_vid_dump_regs( void ) | |
1313 { | |
1314 size_t i; | |
1315 printf(RADEON_MSG"*** Begin of DRIVER variables dump ***\n"); | |
1316 printf(RADEON_MSG"radeon_mmio_base=%p\n",radeon_mmio_base); | |
1317 printf(RADEON_MSG"radeon_mem_base=%p\n",radeon_mem_base); | |
1318 printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off); | |
1319 printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size); | |
1320 printf(RADEON_MSG"video mode: %ux%u@%u\n",radeon_get_xres(),radeon_get_yres(),radeon_vid_get_dbpp()); | |
1321 printf(RADEON_MSG"flatpanel size: %ux%u\n",radeon_get_fp_xres(),radeon_get_fp_yres()); | |
1322 printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n"); | |
1323 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
1324 printf(RADEON_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); | |
1325 printf(RADEON_MSG"*** End of OV0 registers dump ***\n"); | |
1326 } | |
1327 | |
1328 static void radeon_vid_stop_video( void ) | |
1329 { | |
1330 radeon_engine_idle(); | |
1331 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
1332 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
1333 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
1334 OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); | |
1335 #ifdef RADEON | |
1336 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_EQ); | |
1337 #else | |
1338 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); | |
1339 #endif | |
1340 OUTREG(OV0_TEST, 0); | |
1341 } | |
1342 | |
1343 static void radeon_vid_display_video( void ) | |
1344 { | |
1345 int bes_flags; | |
1346 /** workaround for Xorg-6.8 not saving the surface registers on bigendian architectures */ | |
1347 #ifdef WORDS_BIGENDIAN | |
1348 #if defined(RAGE128) | |
1349 /* code from gatos */ | |
1350 { | |
1351 SAVED_CONFIG_CNTL = INREG(CONFIG_CNTL); | |
1352 OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL & | |
1353 ~(APER_0_BIG_ENDIAN_16BPP_SWAP|APER_0_BIG_ENDIAN_32BPP_SWAP)); | |
1354 | |
1355 // printf("saved: %x, current: %x\n", SAVED_CONFIG_CNTL, | |
1356 // INREG(CONFIG_CNTL)); | |
1357 } | |
1358 #else | |
1359 /*code from radeon_video.c*/ | |
1360 { | |
1361 SAVED_CONFIG_CNTL = INREG(RADEON_SURFACE_CNTL); | |
1362 /* OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | | |
1363 RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP); | |
1364 */ | |
1365 OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL & ~(RADEON_NONSURF_AP0_SWP_32BPP | |
1366 | RADEON_NONSURF_AP0_SWP_16BPP)); | |
1367 | |
1368 /* | |
1369 OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | RADEON_NONSURF_AP0_SWP_32BPP) | |
1370 & ~RADEON_NONSURF_AP0_SWP_16BPP); | |
1371 */ | |
1372 } | |
1373 #endif | |
1374 #endif | |
1375 | |
1376 | |
1377 | |
1378 radeon_fifo_wait(2); | |
1379 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1380 radeon_engine_idle(); | |
1381 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1382 radeon_fifo_wait(15); | |
1383 | |
1384 /* Shutdown capturing */ | |
1385 OUTREG(FCP_CNTL, FCP_CNTL__GND); | |
1386 OUTREG(CAP0_TRIG_CNTL, 0); | |
1387 | |
1388 OUTREG(VID_BUFFER_CONTROL, (1<<16) | 0x01); | |
1389 OUTREG(DISP_TEST_DEBUG_CNTL, 0); | |
1390 | |
1391 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); | |
1392 | |
1393 if(besr.deinterlace_on) OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
1394 #ifdef RAGE128 | |
1395 OUTREG(OV0_COLOUR_CNTL, (((besr.brightness*64)/1000) & 0x7f) | | |
1396 (((besr.saturation*31+31000)/2000) << 8) | | |
1397 (((besr.saturation*31+31000)/2000) << 16)); | |
1398 #endif | |
1399 radeon_fifo_wait(2); | |
1400 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); | |
1401 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1402 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
1403 | |
1404 OUTREG(OV0_H_INC, besr.h_inc); | |
1405 OUTREG(OV0_STEP_BY, besr.step_by); | |
1406 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
1407 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
1408 OUTREG(OV0_V_INC, besr.v_inc); | |
1409 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
1410 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); | |
1411 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); | |
1412 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); | |
1413 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); | |
1414 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
1415 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
1416 #ifdef RADEON | |
1417 OUTREG(OV0_BASE_ADDR, besr.base_addr); | |
1418 #endif | |
1419 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); | |
1420 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); | |
1421 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
1422 radeon_fifo_wait(9); | |
1423 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); | |
1424 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); | |
1425 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
1426 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); | |
1427 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
1428 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
1429 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); | |
1430 | |
1431 #ifdef RADEON | |
1432 bes_flags = SCALER_ENABLE | | |
1433 SCALER_SMART_SWITCH; | |
1434 // SCALER_HORZ_PICK_NEAREST | | |
1435 // SCALER_VERT_PICK_NEAREST | | |
1436 #endif | |
1437 bes_flags = SCALER_ENABLE | | |
1438 SCALER_SMART_SWITCH | | |
1439 SCALER_Y2R_TEMP | | |
1440 SCALER_PIX_EXPAND; | |
1441 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; | |
1442 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
1443 #ifdef RAGE128 | |
1444 bes_flags |= SCALER_BURST_PER_PLANE; | |
1445 #endif | |
1446 switch(besr.fourcc) | |
1447 { | |
1448 case IMGFMT_RGB15: | |
1449 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
1450 case IMGFMT_RGB16: | |
1451 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; | |
1452 /* | |
1453 case IMGFMT_RGB24: | |
1454 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
1455 */ | |
1456 case IMGFMT_RGB32: | |
1457 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
1458 /* 4:1:0 */ | |
1459 case IMGFMT_IF09: | |
1460 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; | |
1461 /* 4:0:0 */ | |
1462 case IMGFMT_Y800: | |
1463 case IMGFMT_Y8: | |
1464 /* 4:2:0 */ | |
1465 case IMGFMT_IYUV: | |
1466 case IMGFMT_I420: | |
1467 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break; | |
1468 /* 4:2:2 */ | |
1469 case IMGFMT_YVYU: | |
1470 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; | |
1471 case IMGFMT_YUY2: | |
1472 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
1473 } | |
1474 OUTREG(OV0_SCALE_CNTL, bes_flags); | |
1475 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
1476 if(__verbose > 1) printf(RADEON_MSG"we wanted: scaler=%08X\n",bes_flags); | |
1477 if(__verbose > 1) radeon_vid_dump_regs(); | |
1478 } | |
1479 | |
1480 static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) | |
1481 { | |
1482 unsigned pitch,spy,spv,spu; | |
1483 spy = spv = spu = 0; | |
1484 switch(spitch->y) | |
1485 { | |
1486 case 16: | |
1487 case 32: | |
1488 case 64: | |
1489 case 128: | |
1490 case 256: spy = spitch->y; break; | |
1491 default: break; | |
1492 } | |
1493 switch(spitch->u) | |
1494 { | |
1495 case 16: | |
1496 case 32: | |
1497 case 64: | |
1498 case 128: | |
1499 case 256: spu = spitch->u; break; | |
1500 default: break; | |
1501 } | |
1502 switch(spitch->v) | |
1503 { | |
1504 case 16: | |
1505 case 32: | |
1506 case 64: | |
1507 case 128: | |
1508 case 256: spv = spitch->v; break; | |
1509 default: break; | |
1510 } | |
1511 switch(fourcc) | |
1512 { | |
1513 /* 4:2:0 */ | |
1514 case IMGFMT_IYUV: | |
1515 case IMGFMT_YV12: | |
1516 case IMGFMT_I420: | |
1517 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; | |
1518 else pitch = 32; | |
1519 break; | |
1520 /* 4:1:0 */ | |
1521 case IMGFMT_IF09: | |
1522 case IMGFMT_YVU9: | |
1523 if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; | |
1524 else pitch = 64; | |
1525 break; | |
1526 default: | |
1527 if(spy >= 16) pitch = spy; | |
1528 else pitch = 16; | |
1529 break; | |
1530 } | |
1531 return pitch; | |
1532 } | |
1533 | |
1534 static int radeon_vid_init_video( vidix_playback_t *config ) | |
1535 { | |
1536 uint32_t i,tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top; | |
1537 int is_400,is_410,is_420,is_rgb32,is_rgb,best_pitch,mpitch; | |
1538 radeon_vid_stop_video(); | |
1539 left = config->src.x << 16; | |
1540 top = config->src.y << 16; | |
1541 src_h = config->src.h; | |
1542 src_w = config->src.w; | |
1543 is_400 = is_410 = is_420 = is_rgb32 = is_rgb = 0; | |
1544 if(config->fourcc == IMGFMT_YV12 || | |
1545 config->fourcc == IMGFMT_I420 || | |
1546 config->fourcc == IMGFMT_IYUV) is_420 = 1; | |
1547 if(config->fourcc == IMGFMT_YVU9 || | |
1548 config->fourcc == IMGFMT_IF09) is_410 = 1; | |
1549 if(config->fourcc == IMGFMT_Y800 || | |
1550 config->fourcc == IMGFMT_Y8) is_400 = 1; | |
1551 if(config->fourcc == IMGFMT_RGB32 || | |
1552 config->fourcc == IMGFMT_BGR32) is_rgb32 = 1; | |
1553 if(config->fourcc == IMGFMT_RGB32 || | |
1554 config->fourcc == IMGFMT_BGR32 || | |
1555 config->fourcc == IMGFMT_RGB24 || | |
1556 config->fourcc == IMGFMT_BGR24 || | |
1557 config->fourcc == IMGFMT_RGB16 || | |
1558 config->fourcc == IMGFMT_BGR16 || | |
1559 config->fourcc == IMGFMT_RGB15 || | |
1560 config->fourcc == IMGFMT_BGR15) is_rgb = 1; | |
1561 best_pitch = radeon_query_pitch(config->fourcc,&config->src.pitch); | |
1562 mpitch = best_pitch-1; | |
1563 switch(config->fourcc) | |
1564 { | |
1565 /* 4:0:0 */ | |
1566 case IMGFMT_Y800: | |
1567 case IMGFMT_Y8: | |
1568 /* 4:1:0 */ | |
1569 case IMGFMT_YVU9: | |
1570 case IMGFMT_IF09: | |
1571 /* 4:2:0 */ | |
1572 case IMGFMT_IYUV: | |
1573 case IMGFMT_YV12: | |
1574 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; | |
1575 config->dest.pitch.y = | |
1576 config->dest.pitch.u = | |
1577 config->dest.pitch.v = best_pitch; | |
1578 break; | |
1579 /* RGB 4:4:4:4 */ | |
1580 case IMGFMT_RGB32: | |
1581 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; | |
1582 config->dest.pitch.y = | |
1583 config->dest.pitch.u = | |
1584 config->dest.pitch.v = best_pitch; | |
1585 break; | |
1586 /* 4:2:2 */ | |
1587 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ | |
1588 pitch = ((src_w*2) + mpitch) & ~mpitch; | |
1589 config->dest.pitch.y = | |
1590 config->dest.pitch.u = | |
1591 config->dest.pitch.v = best_pitch; | |
1592 break; | |
1593 } | |
1594 dest_w = config->dest.w; | |
1595 dest_h = config->dest.h; | |
1596 if(radeon_is_dbl_scan()) dest_h *= 2; | |
1597 besr.dest_bpp = radeon_vid_get_dbpp(); | |
1598 besr.fourcc = config->fourcc; | |
1599 | |
1600 /* flat panel */ | |
1601 if(INREG(FP_VERT_STRETCH)&VERT_STRETCH_ENABLE){ | |
1602 besr.v_inc = (src_h * radeon_get_yres() / radeon_get_fp_yres() << 20) / dest_h; | |
1603 } | |
1604 else besr.v_inc = (src_h << 20) / dest_h; | |
1605 if(radeon_is_interlace()) besr.v_inc *= 2; | |
1606 h_inc = (src_w << 12) / dest_w; | |
1607 | |
1608 { | |
1609 unsigned int ecp_div; | |
1610 ecp_div = (INPLL(VCLK_ECP_CNTL) >> 8) & 3; | |
1611 h_inc <<= ecp_div; | |
1612 } | |
1613 | |
1614 | |
1615 step_by = 1; | |
1616 while(h_inc >= (2 << 12)) { | |
1617 step_by++; | |
1618 h_inc >>= 1; | |
1619 } | |
1620 | |
1621 /* keep everything in 16.16 */ | |
1622 besr.base_addr = INREG(DISPLAY_BASE_ADDR); | |
1623 config->offsets[0] = 0; | |
1624 for(i=1;i<besr.vid_nbufs;i++) | |
1625 config->offsets[i] = config->offsets[i-1]+config->frame_size; | |
1626 if(is_420 || is_410 || is_400) | |
1627 { | |
1628 uint32_t d1line,d2line,d3line; | |
1629 d1line = top*pitch; | |
1630 if(is_420) | |
1631 { | |
1632 d2line = src_h*pitch+(d1line>>2); | |
1633 d3line = d2line+((src_h*pitch)>>2); | |
1634 } | |
1635 else | |
1636 if(is_410) | |
1637 { | |
1638 d2line = src_h*pitch+(d1line>>4); | |
1639 d3line = d2line+((src_h*pitch)>>4); | |
1640 } | |
1641 else | |
1642 { | |
1643 d2line = 0; | |
1644 d3line = 0; | |
1645 } | |
1646 d1line += (left >> 16) & ~15; | |
1647 if(is_420) | |
1648 { | |
1649 d2line += (left >> 17) & ~15; | |
1650 d3line += (left >> 17) & ~15; | |
1651 } | |
1652 else | |
1653 if(is_410) | |
1654 { | |
1655 d2line += (left >> 18) & ~15; | |
1656 d3line += (left >> 18) & ~15; | |
1657 } | |
1658 config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK; | |
1659 if(is_400) | |
1660 { | |
1661 config->offset.v = 0; | |
1662 config->offset.u = 0; | |
1663 } | |
1664 else | |
1665 { | |
1666 config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; | |
1667 config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; | |
1668 } | |
1669 for(i=0;i<besr.vid_nbufs;i++) | |
1670 { | |
1671 besr.vid_buf_base_adrs_y[i]=((radeon_overlay_off+config->offsets[i]+config->offset.y)&VIF_BUF0_BASE_ADRS_MASK); | |
1672 if(is_400) | |
1673 { | |
1674 besr.vid_buf_base_adrs_v[i]=0; | |
1675 besr.vid_buf_base_adrs_u[i]=0; | |
1676 } | |
1677 else | |
1678 { | |
1679 if (besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) | |
1680 { | |
1681 besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
1682 besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
1683 } | |
1684 else | |
1685 { | |
1686 besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
1687 besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
1688 } | |
1689 } | |
1690 } | |
1691 config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off; | |
1692 if(is_400) | |
1693 { | |
1694 config->offset.v = 0; | |
1695 config->offset.u = 0; | |
1696 } | |
1697 else | |
1698 { | |
1699 config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off; | |
1700 config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off; | |
1701 } | |
1702 } | |
1703 else | |
1704 { | |
1705 config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; | |
1706 for(i=0;i<besr.vid_nbufs;i++) | |
1707 { | |
1708 besr.vid_buf_base_adrs_y[i] = | |
1709 besr.vid_buf_base_adrs_u[i] = | |
1710 besr.vid_buf_base_adrs_v[i] = radeon_overlay_off + config->offsets[i] + config->offset.y; | |
1711 } | |
1712 } | |
1713 | |
1714 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); | |
1715 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1716 ((tmp << 12) & 0xf0000000); | |
1717 | |
1718 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); | |
1719 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1720 ((tmp << 12) & 0x70000000); | |
1721 tmp = (top & 0x0000ffff) + 0x00018000; | |
1722 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) | |
1723 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
1724 | |
1725 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
1726 besr.p23_v_accum_init = (is_420||is_410) ? | |
1727 ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) | |
1728 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; | |
1729 | |
1730 leftUV = (left >> (is_410?18:17)) & 15; | |
1731 left = (left >> 16) & 15; | |
1732 if(is_rgb && !is_rgb32) h_inc<<=1; | |
1733 if(is_rgb32) | |
1734 besr.h_inc = (h_inc >> 1) | ((h_inc >> 1) << 16); | |
1735 else | |
1736 if(is_410) | |
1737 besr.h_inc = h_inc | ((h_inc >> 2) << 16); | |
1738 else | |
1739 besr.h_inc = h_inc | ((h_inc >> 1) << 16); | |
1740 besr.step_by = step_by | (step_by << 8); | |
1741 besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16); | |
1742 besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16); | |
1743 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
1744 if(is_420 || is_410) | |
1745 { | |
1746 src_h = (src_h + 1) >> (is_410?2:1); | |
1747 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
1748 } | |
1749 else besr.p23_blank_lines_at_top = 0; | |
1750 besr.vid_buf_pitch0_value = pitch; | |
1751 besr.vid_buf_pitch1_value = is_410 ? pitch>>2 : is_420 ? pitch>>1 : pitch; | |
1752 besr.p1_x_start_end = (src_w+left-1)|(left<<16); | |
1753 if (is_410||is_420) src_w>>=is_410?2:1; | |
1754 if(is_400) | |
1755 { | |
1756 besr.p2_x_start_end = 0; | |
1757 besr.p3_x_start_end = 0; | |
1758 } | |
1759 else | |
1760 { | |
1761 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
1762 besr.p3_x_start_end = besr.p2_x_start_end; | |
1763 } | |
1764 | |
1765 return 0; | |
1766 } | |
1767 | |
1768 static void radeon_compute_framesize(vidix_playback_t *info) | |
1769 { | |
1770 unsigned pitch,awidth,dbpp; | |
1771 pitch = radeon_query_pitch(info->fourcc,&info->src.pitch); | |
1772 dbpp = radeon_vid_get_dbpp(); | |
1773 switch(info->fourcc) | |
1774 { | |
1775 case IMGFMT_I420: | |
1776 case IMGFMT_YV12: | |
1777 case IMGFMT_IYUV: | |
1778 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1779 info->frame_size = awidth*(info->src.h+info->src.h/2); | |
1780 break; | |
1781 case IMGFMT_Y800: | |
1782 case IMGFMT_Y8: | |
1783 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1784 info->frame_size = awidth*info->src.h; | |
1785 break; | |
1786 case IMGFMT_IF09: | |
1787 case IMGFMT_YVU9: | |
1788 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1789 info->frame_size = awidth*(info->src.h+info->src.h/8); | |
1790 break; | |
1791 case IMGFMT_RGB32: | |
1792 case IMGFMT_BGR32: | |
1793 awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); | |
1794 info->frame_size = awidth*info->src.h; | |
1795 break; | |
1796 /* YUY2 YVYU, RGB15, RGB16 */ | |
1797 default: | |
1798 awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); | |
1799 info->frame_size = awidth*info->src.h; | |
1800 break; | |
1801 } | |
1802 } | |
1803 | |
22857
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switch to new internal vidix API, no more dlopen/dlsym, libvidix is now a fully static library with all drivers built-in
ben
parents:
22850
diff
changeset
|
1804 static int radeon_config_playback(vidix_playback_t *info) |
22850 | 1805 { |
1806 unsigned rgb_size,nfr; | |
1807 if(!is_supported_fourcc(info->fourcc)) return ENOSYS; | |
1808 if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; | |
1809 if(info->num_frames==1) besr.double_buff=0; | |
1810 else besr.double_buff=1; | |
1811 radeon_compute_framesize(info); | |
1812 | |
1813 rgb_size = radeon_get_xres()*radeon_get_yres()*((radeon_vid_get_dbpp()+7)/8); | |
1814 nfr = info->num_frames; | |
1815 for(;nfr>0; nfr--) | |
1816 { | |
1817 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; | |
1818 #ifdef HAVE_X11 | |
1819 radeon_overlay_off -= firegl_shift; | |
1820 #endif | |
1821 radeon_overlay_off &= 0xffff0000; | |
1822 if(radeon_overlay_off >= (int)rgb_size ) break; | |
1823 } | |
1824 if(nfr <= 3) | |
1825 { | |
1826 nfr = info->num_frames; | |
1827 for(;nfr>0; nfr--) | |
1828 { | |
1829 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; | |
1830 #ifdef HAVE_X11 | |
1831 radeon_overlay_off -= firegl_shift; | |
1832 #endif | |
1833 radeon_overlay_off &= 0xffff0000; | |
1834 if(radeon_overlay_off > 0) break; | |
1835 } | |
1836 } | |
1837 if(nfr <= 0) return EINVAL; | |
1838 info->num_frames = nfr; | |
1839 besr.vid_nbufs = info->num_frames; | |
1840 info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off; | |
1841 radeon_vid_init_video(info); | |
1842 return 0; | |
1843 } | |
1844 | |
22857
77def5093daf
switch to new internal vidix API, no more dlopen/dlsym, libvidix is now a fully static library with all drivers built-in
ben
parents:
22850
diff
changeset
|
1845 static int radeon_playback_on( void ) |
22850 | 1846 { |
1847 radeon_vid_display_video(); | |
1848 return 0; | |
1849 } | |
1850 | |
22857
77def5093daf
switch to new internal vidix API, no more dlopen/dlsym, libvidix is now a fully static library with all drivers built-in
ben
parents:
22850
diff
changeset
|
1851 static int radeon_playback_off( void ) |
22850 | 1852 { |
1853 radeon_vid_stop_video(); | |
1854 return 0; | |
1855 } | |
1856 | |
22857
77def5093daf
switch to new internal vidix API, no more dlopen/dlsym, libvidix is now a fully static library with all drivers built-in
ben
parents:
22850
diff
changeset
|
1857 static int radeon_frame_select(unsigned frame) |
22850 | 1858 { |
1859 uint32_t off[6]; | |
1860 int prev_frame= (frame-1+besr.vid_nbufs) % besr.vid_nbufs; | |
1861 /* | |
1862 buf3-5 always should point onto second buffer for better | |
1863 deinterlacing and TV-in | |
1864 */ | |
1865 if(!besr.double_buff) return 0; | |
1866 if(frame > besr.vid_nbufs) frame = besr.vid_nbufs-1; | |
1867 if(prev_frame > (int)besr.vid_nbufs) prev_frame = besr.vid_nbufs-1; | |
1868 off[0] = besr.vid_buf_base_adrs_y[frame]; | |
1869 off[1] = besr.vid_buf_base_adrs_v[frame]; | |
1870 off[2] = besr.vid_buf_base_adrs_u[frame]; | |
1871 off[3] = besr.vid_buf_base_adrs_y[prev_frame]; | |
1872 off[4] = besr.vid_buf_base_adrs_v[prev_frame]; | |
1873 off[5] = besr.vid_buf_base_adrs_u[prev_frame]; | |
1874 radeon_fifo_wait(8); | |
1875 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1876 radeon_engine_idle(); | |
1877 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1878 OUTREG(OV0_VID_BUF0_BASE_ADRS, off[0]); | |
1879 OUTREG(OV0_VID_BUF1_BASE_ADRS, off[1]); | |
1880 OUTREG(OV0_VID_BUF2_BASE_ADRS, off[2]); | |
1881 OUTREG(OV0_VID_BUF3_BASE_ADRS, off[3]); | |
1882 OUTREG(OV0_VID_BUF4_BASE_ADRS, off[4]); | |
1883 OUTREG(OV0_VID_BUF5_BASE_ADRS, off[5]); | |
1884 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
1885 if(besr.vid_nbufs == 2) radeon_wait_vsync(); | |
1886 if(__verbose > 1) radeon_vid_dump_regs(); | |
1887 return 0; | |
1888 } | |
1889 | |
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1890 static vidix_video_eq_t equal = |
22850 | 1891 { |
1892 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | |
1893 #ifndef RAGE128 | |
1894 | VEQ_CAP_CONTRAST | VEQ_CAP_HUE | VEQ_CAP_RGB_INTENSITY | |
1895 #endif | |
1896 , | |
1897 0, 0, 0, 0, 0, 0, 0, 0 }; | |
1898 | |
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1899 static int radeon_get_eq( vidix_video_eq_t * eq) |
22850 | 1900 { |
1901 memcpy(eq,&equal,sizeof(vidix_video_eq_t)); | |
1902 return 0; | |
1903 } | |
1904 | |
1905 #ifndef RAGE128 | |
1906 #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) | |
1907 #define RTFBrightness(a) (((a)*1.0)/2000.0) | |
1908 #define RTFIntensity(a) (((a)*1.0)/2000.0) | |
1909 #define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) | |
1910 #define RTFHue(a) (((a)*3.1416)/1000.0) | |
1911 #define RTFCheckParam(a) {if((a)<-1000) (a)=-1000; if((a)>1000) (a)=1000;} | |
1912 #endif | |
1913 | |
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1914 static int radeon_set_eq( const vidix_video_eq_t * eq) |
22850 | 1915 { |
1916 #ifdef RAGE128 | |
1917 int br,sat; | |
1918 #else | |
1919 int itu_space; | |
1920 #endif | |
1921 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; | |
1922 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; | |
1923 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; | |
1924 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; | |
1925 if(eq->cap & VEQ_CAP_RGB_INTENSITY) | |
1926 { | |
1927 equal.red_intensity = eq->red_intensity; | |
1928 equal.green_intensity = eq->green_intensity; | |
1929 equal.blue_intensity = eq->blue_intensity; | |
1930 } | |
1931 equal.flags = eq->flags; | |
1932 #ifdef RAGE128 | |
1933 br = equal.brightness * 64 / 1000; | |
1934 if(br < -64) br = -64; if(br > 63) br = 63; | |
1935 sat = (equal.saturation + 1000) * 16 / 1000; | |
1936 if(sat < 0) sat = 0; if(sat > 31) sat = 31; | |
1937 OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); | |
1938 #else | |
1939 itu_space = equal.flags == VEQ_FLG_ITU_R_BT_709 ? 1 : 0; | |
1940 RTFCheckParam(equal.brightness); | |
1941 RTFCheckParam(equal.saturation); | |
1942 RTFCheckParam(equal.contrast); | |
1943 RTFCheckParam(equal.hue); | |
1944 RTFCheckParam(equal.red_intensity); | |
1945 RTFCheckParam(equal.green_intensity); | |
1946 RTFCheckParam(equal.blue_intensity); | |
1947 radeon_set_transform(RTFBrightness(equal.brightness), | |
1948 RTFContrast(equal.contrast), | |
1949 RTFSaturation(equal.saturation), | |
1950 RTFHue(equal.hue), | |
1951 RTFIntensity(equal.red_intensity), | |
1952 RTFIntensity(equal.green_intensity), | |
1953 RTFIntensity(equal.blue_intensity), | |
1954 itu_space); | |
1955 #endif | |
1956 return 0; | |
1957 } | |
1958 | |
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1959 static int radeon_playback_set_deint (const vidix_deinterlace_t * info) |
22850 | 1960 { |
1961 unsigned sflg; | |
1962 switch(info->flags) | |
1963 { | |
1964 default: | |
1965 case CFG_NON_INTERLACED: | |
1966 besr.deinterlace_on = 0; | |
1967 break; | |
1968 case CFG_EVEN_ODD_INTERLACING: | |
1969 case CFG_INTERLACED: | |
1970 besr.deinterlace_on = 1; | |
1971 besr.deinterlace_pattern = 0x900AAAAA; | |
1972 break; | |
1973 case CFG_ODD_EVEN_INTERLACING: | |
1974 besr.deinterlace_on = 1; | |
1975 besr.deinterlace_pattern = 0x00055555; | |
1976 break; | |
1977 case CFG_UNIQUE_INTERLACING: | |
1978 besr.deinterlace_on = 1; | |
1979 besr.deinterlace_pattern = info->deinterlace_pattern; | |
1980 break; | |
1981 } | |
1982 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1983 radeon_engine_idle(); | |
1984 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1985 radeon_fifo_wait(15); | |
1986 sflg = INREG(OV0_SCALE_CNTL); | |
1987 if(besr.deinterlace_on) | |
1988 { | |
1989 OUTREG(OV0_SCALE_CNTL,sflg | SCALER_ADAPTIVE_DEINT); | |
1990 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
1991 } | |
1992 else OUTREG(OV0_SCALE_CNTL,sflg & (~SCALER_ADAPTIVE_DEINT)); | |
1993 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
1994 return 0; | |
1995 } | |
1996 | |
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1997 static int radeon_playback_get_deint (vidix_deinterlace_t * info) |
22850 | 1998 { |
1999 if(!besr.deinterlace_on) info->flags = CFG_NON_INTERLACED; | |
2000 else | |
2001 { | |
2002 info->flags = CFG_UNIQUE_INTERLACING; | |
2003 info->deinterlace_pattern = besr.deinterlace_pattern; | |
2004 } | |
2005 return 0; | |
2006 } | |
2007 | |
2008 | |
2009 /* Graphic keys */ | |
2010 static vidix_grkey_t radeon_grkey; | |
2011 | |
2012 static void set_gr_key( void ) | |
2013 { | |
2014 if(radeon_grkey.ckey.op == CKEY_TRUE) | |
2015 { | |
2016 int dbpp=radeon_vid_get_dbpp(); | |
2017 besr.ckey_on=1; | |
2018 | |
2019 switch(dbpp) | |
2020 { | |
2021 case 15: | |
2022 #ifdef RADEON | |
2023 if(RadeonFamily > 100) | |
2024 besr.graphics_key_clr= | |
2025 ((radeon_grkey.ckey.blue &0xF8)) | |
2026 | ((radeon_grkey.ckey.green&0xF8)<<8) | |
2027 | ((radeon_grkey.ckey.red &0xF8)<<16); | |
2028 else | |
2029 #endif | |
2030 besr.graphics_key_clr= | |
2031 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
2032 | ((radeon_grkey.ckey.green&0xF8)<<2) | |
2033 | ((radeon_grkey.ckey.red &0xF8)<<7); | |
2034 break; | |
2035 case 16: | |
2036 #ifdef RADEON | |
2037 /* This test may be too general/specific */ | |
2038 if(RadeonFamily > 100) | |
2039 besr.graphics_key_clr= | |
2040 ((radeon_grkey.ckey.blue &0xF8)) | |
2041 | ((radeon_grkey.ckey.green&0xFC)<<8) | |
2042 | ((radeon_grkey.ckey.red &0xF8)<<16); | |
2043 else | |
2044 #endif | |
2045 besr.graphics_key_clr= | |
2046 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
2047 | ((radeon_grkey.ckey.green&0xFC)<<3) | |
2048 | ((radeon_grkey.ckey.red &0xF8)<<8); | |
2049 break; | |
2050 case 24: | |
2051 besr.graphics_key_clr= | |
2052 ((radeon_grkey.ckey.blue &0xFF)) | |
2053 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
2054 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
2055 break; | |
2056 case 32: | |
2057 besr.graphics_key_clr= | |
2058 ((radeon_grkey.ckey.blue &0xFF)) | |
2059 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
2060 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
2061 break; | |
2062 default: | |
2063 besr.ckey_on=0; | |
2064 besr.graphics_key_msk=0; | |
2065 besr.graphics_key_clr=0; | |
2066 } | |
2067 #ifdef RAGE128 | |
2068 besr.graphics_key_msk=(1<<dbpp)-1; | |
2069 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_NE|CMP_MIX_AND; | |
2070 #else | |
2071 besr.graphics_key_msk=besr.graphics_key_clr; | |
2072 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|CMP_MIX_AND|GRAPHIC_KEY_FN_EQ; | |
2073 #endif | |
2074 } | |
2075 else | |
2076 { | |
2077 besr.ckey_on=0; | |
2078 besr.graphics_key_msk=0; | |
2079 besr.graphics_key_clr=0; | |
2080 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; | |
2081 } | |
2082 radeon_fifo_wait(3); | |
2083 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); | |
2084 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
2085 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
2086 } | |
2087 | |
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2088 static int radeon_get_gkey(vidix_grkey_t *grkey) |
22850 | 2089 { |
2090 memcpy(grkey, &radeon_grkey, sizeof(vidix_grkey_t)); | |
2091 return(0); | |
2092 } | |
2093 | |
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2094 static int radeon_set_gkey(const vidix_grkey_t *grkey) |
22850 | 2095 { |
2096 memcpy(&radeon_grkey, grkey, sizeof(vidix_grkey_t)); | |
2097 set_gr_key(); | |
2098 return(0); | |
2099 } | |
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2100 |
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2101 #ifdef RAGE128 |
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2102 VDXDriver rage128_drv = { |
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2103 "rage128", |
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2104 #else |
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2105 VDXDriver radeon_drv = { |
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2106 "radeon", |
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2107 #endif |
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2108 NULL, |
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2109 |
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2110 .probe = radeon_probe, |
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2111 .get_caps = radeon_get_caps, |
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2112 .query_fourcc = radeon_query_fourcc, |
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2113 .init = radeon_init, |
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2114 .destroy = radeon_destroy, |
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2115 .config_playback = radeon_config_playback, |
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2116 .playback_on = radeon_playback_on, |
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2117 .playback_off = radeon_playback_off, |
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2118 .frame_sel = radeon_frame_select, |
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2119 .get_eq = radeon_get_eq, |
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2120 .set_eq = radeon_set_eq, |
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2121 .get_deint = radeon_playback_get_deint, |
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2122 .set_deint = radeon_playback_set_deint, |
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2123 .get_gkey = radeon_get_gkey, |
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2124 .set_gkey = radeon_set_gkey, |
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2125 }; |