4691
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1 /*
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2 mach64_vid - VIDIX based video driver for Mach64 and 3DRage chips
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3 Copyrights 2002 Nick Kurshev. This file is based on sources from
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4 GATOS (gatos.sf.net) and X11 (www.xfree86.org)
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5 Licence: GPL
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6 WARNING: THIS DRIVER IS IN BETTA STAGE AND DOESN'T WORK WITH PLANAR FOURCCS!
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7 */
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8 #include <errno.h>
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9 #include <stdio.h>
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10 #include <stdlib.h>
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11 #include <string.h>
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12 #include <math.h>
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13 #include <inttypes.h>
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14 #include <fcntl.h>
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15
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16 #include "../vidix.h"
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17 #include "../fourcc.h"
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18 #include "../../libdha/libdha.h"
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19 #include "../../libdha/pci_ids.h"
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20 #include "../../libdha/pci_names.h"
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21
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22 #include "mach64.h"
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23
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24 #define UNUSED(x) ((void)(x)) /**< Removes warning about unused arguments */
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25
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26 static void *mach64_mmio_base = 0;
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27 static void *mach64_mem_base = 0;
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28 static int32_t mach64_overlay_offset = 0;
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29 static uint32_t mach64_ram_size = 0;
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30
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31 pciinfo_t pci_info;
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32 static int probed = 0;
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33 static int __verbose = 0;
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34
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35 typedef struct bes_registers_s
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36 {
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37 /* base address of yuv framebuffer */
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38 uint32_t yuv_base;
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39 uint32_t fourcc;
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40 /* YUV BES registers */
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41 uint32_t reg_load_cntl;
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42 uint32_t scale_inc;
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43 uint32_t y_x_start;
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44 uint32_t y_x_end;
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45 uint32_t vid_buf_pitch;
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46 uint32_t height_width;
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47 uint32_t vid_buf0_base_adrs;
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48 uint32_t vid_buf1_base_adrs;
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49 uint32_t vid_buf2_base_adrs;
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50 uint32_t vid_buf3_base_adrs;
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51 uint32_t vid_buf4_base_adrs;
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52 uint32_t vid_buf5_base_adrs;
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53
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54 uint32_t scale_cntl;
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55 uint32_t exclusive_horz;
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56 uint32_t auto_flip_cntl;
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57 uint32_t filter_cntl;
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58 uint32_t key_cntl;
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59 uint32_t test;
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60 /* Configurable stuff */
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61 int double_buff;
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62
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63 int brightness;
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64 int saturation;
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65
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66 int ckey_on;
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67 uint32_t graphics_key_clr;
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68 uint32_t graphics_key_msk;
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69
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70 int deinterlace_on;
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71 uint32_t deinterlace_pattern;
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72
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73 } bes_registers_t;
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74
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75 static bes_registers_t besr;
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76
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77 typedef struct video_registers_s
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78 {
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79 const char * sname;
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80 uint32_t name;
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81 uint32_t value;
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82 }video_registers_t;
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83
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84 static bes_registers_t besr;
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85 #define DECLARE_VREG(name) { #name, name, 0 }
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86 static video_registers_t vregs[] =
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87 {
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88 DECLARE_VREG(OVERLAY_SCALE_INC),
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89 DECLARE_VREG(OVERLAY_Y_X_START),
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90 DECLARE_VREG(OVERLAY_Y_X_END),
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91 DECLARE_VREG(OVERLAY_SCALE_CNTL),
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92 DECLARE_VREG(OVERLAY_EXCLUSIVE_HORZ),
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93 DECLARE_VREG(OVERLAY_EXCLUSIVE_VERT),
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94 DECLARE_VREG(OVERLAY_TEST),
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95 DECLARE_VREG(SCALER_BUF_PITCH),
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96 DECLARE_VREG(SCALER_HEIGHT_WIDTH),
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97 DECLARE_VREG(SCALER_BUF0_OFFSET),
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98 DECLARE_VREG(SCALER_BUF0_OFFSET_U),
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99 DECLARE_VREG(SCALER_BUF0_OFFSET_V),
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100 DECLARE_VREG(SCALER_BUF1_OFFSET),
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101 DECLARE_VREG(SCALER_BUF1_OFFSET_U),
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102 DECLARE_VREG(SCALER_BUF1_OFFSET_V),
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103 DECLARE_VREG(SCALER_H_COEFF0),
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104 DECLARE_VREG(SCALER_H_COEFF1),
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105 DECLARE_VREG(SCALER_H_COEFF2),
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106 DECLARE_VREG(SCALER_H_COEFF3),
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107 DECLARE_VREG(SCALER_H_COEFF4),
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108 DECLARE_VREG(SCALER_COLOUR_CNTL),
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109 DECLARE_VREG(SCALER_THRESHOLD),
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110 DECLARE_VREG(VIDEO_FORMAT),
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111 DECLARE_VREG(VIDEO_CONFIG),
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112 DECLARE_VREG(VIDEO_SYNC_TEST),
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113 DECLARE_VREG(VIDEO_SYNC_TEST_B)
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114 };
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115
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116 /* VIDIX exports */
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117
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118 /* MMIO space*/
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119 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ))))
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120 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL
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121
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122 #define INREG8(addr) GETREG(uint8_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2)
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123 #define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2,val)
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124 #define INREG(addr) GETREG(uint32_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2)
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125 #define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2,val)
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126
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127 #define OUTREGP(addr,val,mask) \
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128 do { \
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129 unsigned int _tmp = INREG(addr); \
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130 _tmp &= (mask); \
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131 _tmp |= (val); \
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132 OUTREG(addr, _tmp); \
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133 } while (0)
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134
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135 static __inline__ uint32_t INPLL(uint32_t addr)
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136 {
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137 uint32_t res;
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138
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139 /* write addr byte */
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140 OUTREG8(CLOCK_CNTL + 1, (addr << 2));
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141 /* read the register value */
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142 res = INREG(CLOCK_CNTL + 2);
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143 return res;
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144 }
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145
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146 static __inline__ void OUTPLL(uint32_t addr,uint32_t val)
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147 {
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148 /* write addr byte */
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149 OUTREG8(CLOCK_CNTL + 1, (addr << 2) | PLL_WR_EN);
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150 /* write the register value */
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151 OUTREG(CLOCK_CNTL + 2, val);
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152 OUTREG8(CLOCK_CNTL + 1, (addr << 2) & ~PLL_WR_EN);
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153 }
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154
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155 #define OUTPLLP(addr,val,mask) \
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156 do { \
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157 unsigned int _tmp = INPLL(addr); \
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158 _tmp &= (mask); \
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159 _tmp |= (val); \
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160 OUTPLL(addr, _tmp); \
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161 } while (0)
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162
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163 static void mach64_fifo_wait(unsigned n)
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164 {
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165 while ((INREG(FIFO_STAT) & 0xffff) > ((uint32_t)(0x8000 >> n)));
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166 }
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167
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168 static void mach64_wait_for_idle( void )
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169 {
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170 mach64_fifo_wait(16);
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171 while ((INREG(GUI_STAT) & 1)!= 0);
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172 }
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173
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174 static vidix_capability_t mach64_cap =
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175 {
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176 "BES driver for Mach64/3DRage cards",
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177 "Nick Kurshev",
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178 TYPE_OUTPUT,
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179 { 0, 0, 0, 0 },
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180 2048,
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181 2048,
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182 4,
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183 4,
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184 -1,
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185 FLAG_UPSCALER|FLAG_DOWNSCALER,
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186 VENDOR_ATI,
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187 -1,
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188 { 0, 0, 0, 0 }
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189 };
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190
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191 static uint32_t mach64_vid_get_dbpp( void )
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192 {
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193 uint32_t dbpp,retval;
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194 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0x7;
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195 switch(dbpp)
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196 {
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197 case 1: retval = 4; break;
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198 case 2: retval = 8; break;
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199 case 3: retval = 15; break;
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200 case 4: retval = 16; break;
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201 case 5: retval = 24; break;
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202 default: retval=32; break;
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203 }
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204 return retval;
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205 }
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206
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207 static int mach64_is_dbl_scan( void )
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208 {
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209 return INREG(CRTC_GEN_CNTL) & CRTC_DBL_SCAN_EN;
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210 }
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211
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212 static int mach64_is_interlace( void )
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213 {
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214 return INREG(CRTC_GEN_CNTL) & CRTC_INTERLACE_EN;
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215 }
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216
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217 static uint32_t mach64_get_xres( void )
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218 {
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219 /* FIXME: currently we extract that from CRTC!!!*/
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220 uint32_t xres,h_total;
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221 h_total = INREG(CRTC_H_TOTAL_DISP);
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222 xres = (h_total >> 16) & 0xffff;
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223 return (xres + 1)*8;
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224 }
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225
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226 static uint32_t mach64_get_yres( void )
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227 {
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228 /* FIXME: currently we extract that from CRTC!!!*/
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229 uint32_t yres,v_total;
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230 v_total = INREG(CRTC_V_TOTAL_DISP);
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231 yres = (v_total >> 16) & 0xffff;
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232 return yres + 1;
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233 }
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234
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235 static void mach64_vid_make_default()
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236 {
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237 mach64_fifo_wait(2);
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238 OUTREG(SCALER_COLOUR_CNTL,0x0010103f);
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239 }
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240
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241 static void mach64_vid_dump_regs( void )
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242 {
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243 size_t i;
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244 printf("[mach64] *** Begin of DRIVER variables dump ***\n");
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245 printf("[mach64] mach64_mmio_base=%p\n",mach64_mmio_base);
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246 printf("[mach64] mach64_mem_base=%p\n",mach64_mem_base);
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247 printf("[mach64] mach64_overlay_off=%08X\n",mach64_overlay_offset);
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248 printf("[mach64] mach64_ram_size=%08X\n",mach64_ram_size);
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249 printf("[mach64] video mode: %ux%u@%u\n",mach64_get_xres(),mach64_get_yres(),mach64_vid_get_dbpp());
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250 printf("[mach64] *** Begin of OV0 registers dump ***\n");
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251 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++)
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252 {
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253 mach64_wait_for_idle();
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254 printf("[mach64] %s = %08X\n",vregs[i].sname,INREG(vregs[i].name));
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255 }
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256 printf("[mach64] *** End of OV0 registers dump ***\n");
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257 }
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258
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259
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260 unsigned int vixGetVersion(void)
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261 {
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262 return(VIDIX_VERSION);
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263 }
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264
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265 static unsigned short ati_card_ids[] =
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266 {
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267 DEVICE_ATI_215CT_MACH64_CT,
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268 DEVICE_ATI_210888CX_MACH64_CX,
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269 DEVICE_ATI_210888ET_MACH64_ET,
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270 DEVICE_ATI_MACH64_VT,
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271 DEVICE_ATI_210888GX_MACH64_GX,
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272 DEVICE_ATI_264LT_MACH64_LT,
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273 DEVICE_ATI_264VT_MACH64_VT,
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274 DEVICE_ATI_264VT3_MACH64_VT3,
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275 DEVICE_ATI_264VT4_MACH64_VT4,
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276 /**/
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277 DEVICE_ATI_3D_RAGE_PRO,
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278 DEVICE_ATI_3D_RAGE_PRO2,
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279 DEVICE_ATI_3D_RAGE_PRO3,
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280 DEVICE_ATI_3D_RAGE_PRO4,
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281 DEVICE_ATI_RAGE_XC,
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282 DEVICE_ATI_RAGE_XL_AGP,
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283 DEVICE_ATI_RAGE_XC_AGP,
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284 DEVICE_ATI_RAGE_XL,
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285 DEVICE_ATI_3D_RAGE_PRO5,
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286 DEVICE_ATI_3D_RAGE_PRO6,
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287 DEVICE_ATI_RAGE_XL2,
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288 DEVICE_ATI_RAGE_XC2,
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289 DEVICE_ATI_3D_RAGE_I_II,
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290 DEVICE_ATI_3D_RAGE_II,
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291 DEVICE_ATI_3D_RAGE_IIC,
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292 DEVICE_ATI_3D_RAGE_IIC2,
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293 DEVICE_ATI_3D_RAGE_IIC3,
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294 DEVICE_ATI_3D_RAGE_IIC4,
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295 DEVICE_ATI_3D_RAGE_LT,
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296 DEVICE_ATI_3D_RAGE_LT2,
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297 DEVICE_ATI_RAGE_MOBILITY_M3,
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298 DEVICE_ATI_RAGE_MOBILITY_M32,
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299 DEVICE_ATI_3D_RAGE_LT_G,
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300 DEVICE_ATI_3D_RAGE_LT3,
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301 DEVICE_ATI_RAGE_MOBILITY_P_M,
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302 DEVICE_ATI_RAGE_MOBILITY_L,
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303 DEVICE_ATI_3D_RAGE_LT4,
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304 DEVICE_ATI_3D_RAGE_LT5,
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305 DEVICE_ATI_RAGE_MOBILITY_P_M2,
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306 DEVICE_ATI_RAGE_MOBILITY_L2
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307 };
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308
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309 static int find_chip(unsigned chip_id)
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310 {
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311 unsigned i;
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312 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++)
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313 {
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314 if(chip_id == ati_card_ids[i]) return i;
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315 }
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316 return -1;
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317 }
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318
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319 int vixProbe(int verbose,int force)
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320 {
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321 pciinfo_t lst[MAX_PCI_DEVICES];
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322 unsigned i,num_pci;
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323 int err;
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324 __verbose = verbose;
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325 err = pci_scan(lst,&num_pci);
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326 if(err)
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327 {
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328 printf("[mach64] Error occured during pci scan: %s\n",strerror(err));
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329 return err;
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330 }
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331 else
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332 {
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333 err = ENXIO;
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334 for(i=0;i<num_pci;i++)
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335 {
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336 if(lst[i].vendor == VENDOR_ATI)
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337 {
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338 int idx;
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339 const char *dname;
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340 idx = find_chip(lst[i].device);
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341 if(idx == -1 && force == PROBE_NORMAL) continue;
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342 dname = pci_device_name(VENDOR_ATI,lst[i].device);
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343 dname = dname ? dname : "Unknown chip";
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344 printf("[mach64] Found chip: %s\n",dname);
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345 if(force > PROBE_NORMAL)
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346 {
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347 printf("[mach64] Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : "");
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348 if(idx == -1)
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349 printf("[mach64] Assuming it as Mach64\n");
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350 }
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351 mach64_cap.device_id = lst[i].device;
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352 err = 0;
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353 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t));
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354 probed=1;
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355 break;
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356 }
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357 }
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358 }
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359 if(err && verbose) printf("[mach64] Can't find chip\n");
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360 return err;
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361 }
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362
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363 static void reset_regs( void )
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364 {
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365 size_t i;
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366 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++)
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367 {
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368 mach64_fifo_wait(2);
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369 OUTREG(vregs[i].name,-1);
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370 }
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371 }
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372
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373
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374 int vixInit(void)
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375 {
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376 int err;
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377 if(!probed)
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378 {
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379 printf("[mach64] Driver was not probed but is being initializing\n");
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380 return EINTR;
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381 }
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382 if((mach64_mmio_base = map_phys_mem(pci_info.base2,0x4000))==(void *)-1) return ENOMEM;
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383 mach64_wait_for_idle();
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384 mach64_ram_size = INREG(MEM_CNTL) & CTL_MEM_SIZEB;
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385 if (mach64_ram_size < 8) mach64_ram_size = (mach64_ram_size + 1) * 512;
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386 else if (mach64_ram_size < 12) mach64_ram_size = (mach64_ram_size - 3) * 1024;
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387 else mach64_ram_size = (mach64_ram_size - 7) * 2048;
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388 mach64_ram_size *= 0x400; /* KB -> bytes */
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389 if((mach64_mem_base = map_phys_mem(pci_info.base0,mach64_ram_size))==(void *)-1) return ENOMEM;
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390 // memset(&besr,0,sizeof(bes_registers_t));
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391 mach64_vid_make_default();
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392 printf("[mach64] Video memory = %uMb\n",mach64_ram_size/0x100000);
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393 err = mtrr_set_type(pci_info.base0,mach64_ram_size,MTRR_TYPE_WRCOMB);
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394 if(!err) printf("[mach64] Set write-combining type of video memory\n");
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395 reset_regs();
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396 mach64_vid_dump_regs();
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397 return 0;
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398 }
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399
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400 void vixDestroy(void)
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401 {
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402 unmap_phys_mem(mach64_mem_base,mach64_ram_size);
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403 unmap_phys_mem(mach64_mmio_base,0x4000);
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404 }
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405
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406 int vixGetCapability(vidix_capability_t *to)
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407 {
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408 memcpy(to, &mach64_cap, sizeof(vidix_capability_t));
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409 return 0;
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410 }
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411
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4721
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412 static unsigned mach64_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch)
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413 {
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414 unsigned pitch,spy,spv,spu;
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415 spy = spv = spu = 0;
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416 switch(spitch->y)
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417 {
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418 case 16:
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419 case 32:
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420 case 64:
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421 case 128:
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422 case 256: spy = spitch->y; break;
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423 default: break;
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424 }
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425 switch(spitch->u)
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426 {
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427 case 16:
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428 case 32:
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429 case 64:
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430 case 128:
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431 case 256: spu = spitch->u; break;
|
|
432 default: break;
|
|
433 }
|
|
434 switch(spitch->v)
|
|
435 {
|
|
436 case 16:
|
|
437 case 32:
|
|
438 case 64:
|
|
439 case 128:
|
|
440 case 256: spv = spitch->v; break;
|
|
441 default: break;
|
|
442 }
|
|
443 switch(fourcc)
|
|
444 {
|
|
445 /* 4:2:0 */
|
|
446 case IMGFMT_IYUV:
|
|
447 case IMGFMT_YV12:
|
|
448 case IMGFMT_I420:
|
|
449 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy;
|
|
450 else pitch = 32;
|
|
451 break;
|
|
452 default:
|
|
453 if(spy > 16) pitch = spy;
|
|
454 else pitch = 32;
|
|
455 break;
|
|
456 }
|
|
457 return pitch;
|
|
458 }
|
|
459
|
|
460 static void mach64_compute_framesize(vidix_playback_t *info)
|
|
461 {
|
|
462 unsigned pitch,awidth;
|
|
463 pitch = mach64_query_pitch(info->fourcc,&info->src.pitch);
|
|
464 switch(info->fourcc)
|
|
465 {
|
|
466 case IMGFMT_I420:
|
|
467 case IMGFMT_YV12:
|
|
468 case IMGFMT_IYUV:
|
|
469 awidth = (info->src.w + (pitch-1)) & ~(pitch-1);
|
|
470 info->frame_size = awidth*(info->src.h+info->src.h/2);
|
|
471 break;
|
|
472 case IMGFMT_RGB32:
|
|
473 case IMGFMT_BGR32:
|
|
474 awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1);
|
|
475 info->frame_size = (awidth*info->src.h);
|
|
476 break;
|
|
477 /* YUY2 YVYU, RGB15, RGB16 */
|
|
478 default:
|
|
479 awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1);
|
|
480 info->frame_size = (awidth*info->src.h);
|
|
481 break;
|
|
482 }
|
|
483 }
|
|
484
|
|
485 static void mach64_vid_stop_video( void )
|
|
486 {
|
|
487 mach64_fifo_wait(14);
|
|
488 OUTREG(OVERLAY_SCALE_CNTL, 0x80000000);
|
|
489 OUTREG(OVERLAY_EXCLUSIVE_HORZ, 0);
|
|
490 OUTREG(OVERLAY_EXCLUSIVE_VERT, 0);
|
|
491 OUTREG(SCALER_H_COEFF0, 0x00002000);
|
|
492 OUTREG(SCALER_H_COEFF1, 0x0D06200D);
|
|
493 OUTREG(SCALER_H_COEFF2, 0x0D0A1C0D);
|
|
494 OUTREG(SCALER_H_COEFF3, 0x0C0E1A0C);
|
|
495 OUTREG(SCALER_H_COEFF4, 0x0C14140C);
|
|
496 OUTREG(VIDEO_FORMAT, 0xB000B);
|
|
497 OUTREG(OVERLAY_GRAPHICS_KEY_MSK, 0);
|
|
498 OUTREG(OVERLAY_GRAPHICS_KEY_CLR, 0);
|
|
499 OUTREG(OVERLAY_KEY_CNTL, 0x50);
|
|
500 OUTREG(OVERLAY_TEST, 0x0);
|
|
501 }
|
|
502
|
|
503 static void mach64_vid_display_video( void )
|
|
504 {
|
|
505 uint32_t vf;
|
|
506 mach64_fifo_wait(14);
|
|
507
|
|
508 OUTREG(OVERLAY_Y_X_START, besr.y_x_start);
|
|
509 OUTREG(OVERLAY_Y_X_END, besr.y_x_end);
|
|
510 OUTREG(OVERLAY_SCALE_INC, besr.scale_inc);
|
|
511 OUTREG(SCALER_BUF_PITCH, besr.vid_buf_pitch);
|
|
512 OUTREG(SCALER_HEIGHT_WIDTH, besr.height_width);
|
|
513 OUTREG(SCALER_BUF0_OFFSET, besr.vid_buf0_base_adrs);
|
|
514 OUTREG(SCALER_BUF0_OFFSET_U, besr.vid_buf1_base_adrs);
|
|
515 OUTREG(SCALER_BUF0_OFFSET_V, besr.vid_buf2_base_adrs);
|
|
516 OUTREG(SCALER_BUF1_OFFSET, besr.vid_buf3_base_adrs);
|
|
517 OUTREG(SCALER_BUF1_OFFSET_U, besr.vid_buf4_base_adrs);
|
|
518 OUTREG(SCALER_BUF1_OFFSET_V, besr.vid_buf5_base_adrs);
|
|
519 OUTREG(OVERLAY_SCALE_CNTL, 0x04000001 | (3<<30));
|
|
520 mach64_wait_for_idle();
|
|
521 vf = INREG(VIDEO_FORMAT);
|
|
522 switch(besr.fourcc)
|
|
523 {
|
|
524 /* 4:2:0 */
|
|
525 case IMGFMT_IYUV:
|
|
526 case IMGFMT_I420:
|
|
527 case IMGFMT_YV12: OUTREG(VIDEO_FORMAT, (vf & ~0xF000) | 0xA000); break;
|
|
528 /* 4:2:2 */
|
|
529 case IMGFMT_YVYU:
|
|
530 case IMGFMT_UYVY: OUTREG(VIDEO_FORMAT, (vf & ~0xF000) | 0xB000); break;
|
|
531 case IMGFMT_YUY2:
|
|
532 default: OUTREG(VIDEO_FORMAT, (vf & ~0xF000) | 0xC000); break;
|
|
533 }
|
|
534 // OUTPLL(PLL_SCALER_LOCK_EN, 0);
|
|
535 if(__verbose > 1) mach64_vid_dump_regs();
|
|
536 }
|
|
537
|
|
538 static int mach64_vid_init_video( vidix_playback_t *config )
|
|
539 {
|
|
540 uint32_t src_w,src_h,dest_w,dest_h,pitch,h_inc,v_inc,left,leftUV,top,ecp;
|
|
541 int is_420,best_pitch,mpitch;
|
|
542 mach64_vid_stop_video();
|
|
543 left = config->src.x << 16;
|
|
544 top = config->src.y << 16;
|
|
545 src_h = config->src.h;
|
|
546 src_w = config->src.w;
|
|
547 is_420 = 0;
|
|
548 if(config->fourcc == IMGFMT_YV12 ||
|
|
549 config->fourcc == IMGFMT_I420 ||
|
|
550 config->fourcc == IMGFMT_IYUV) is_420 = 1;
|
|
551 best_pitch = mach64_query_pitch(config->fourcc,&config->src.pitch);
|
|
552 mpitch = best_pitch-1;
|
|
553 switch(config->fourcc)
|
|
554 {
|
|
555 /* 4:2:0 */
|
|
556 case IMGFMT_IYUV:
|
|
557 case IMGFMT_YV12:
|
|
558 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch;
|
|
559 config->dest.pitch.y =
|
|
560 config->dest.pitch.u =
|
|
561 config->dest.pitch.v = best_pitch;
|
|
562 break;
|
|
563 /* RGB 4:4:4:4 */
|
|
564 case IMGFMT_RGB32:
|
|
565 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch;
|
|
566 config->dest.pitch.y =
|
|
567 config->dest.pitch.u =
|
|
568 config->dest.pitch.v = best_pitch;
|
|
569 break;
|
|
570 /* 4:2:2 */
|
|
571 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */
|
|
572 pitch = ((src_w*2) + mpitch) & ~mpitch;
|
|
573 config->dest.pitch.y =
|
|
574 config->dest.pitch.u =
|
|
575 config->dest.pitch.v = best_pitch;
|
|
576 break;
|
|
577 }
|
|
578 dest_w = config->dest.w;
|
|
579 dest_h = config->dest.h;
|
|
580 besr.fourcc = config->fourcc;
|
|
581 ecp = (INPLL(PLL_VCLK_CNTL) & PLL_ECP_DIV) >> 4;
|
|
582 v_inc = (src_h << (12
|
|
583 +(mach64_is_interlace()?1:0)
|
|
584 -(mach64_is_dbl_scan()?1:0)
|
|
585 )) / dest_h;
|
|
586 h_inc = (src_w << (12+ecp)) / dest_w;
|
|
587 v_inc /= 2;
|
|
588 /* keep everything in 16.16 */
|
|
589 config->offsets[0] = 0;
|
|
590 config->offsets[1] = config->frame_size;
|
|
591 if(is_420)
|
|
592 {
|
|
593 uint32_t d1line,d2line,d3line;
|
|
594 d1line = top*pitch;
|
|
595 d2line = src_h*pitch+(d1line>>2);
|
|
596 d3line = d2line+((src_h*pitch)>>2);
|
|
597 d1line += (left >> 16) & ~15;
|
|
598 d2line += (left >> 17) & ~15;
|
|
599 d3line += (left >> 17) & ~15;
|
|
600 config->offset.y = d1line & ~15;
|
|
601 config->offset.v = d2line & ~15;
|
|
602 config->offset.u = d3line & ~15;
|
|
603 besr.vid_buf0_base_adrs=((mach64_overlay_offset+config->offsets[0]+config->offset.y)&~15);
|
|
604 besr.vid_buf1_base_adrs=((mach64_overlay_offset+config->offsets[0]+config->offset.v)&~15);
|
|
605 besr.vid_buf2_base_adrs=((mach64_overlay_offset+config->offsets[0]+config->offset.u)&~15);
|
|
606 besr.vid_buf3_base_adrs=((mach64_overlay_offset+config->offsets[1]+config->offset.y)&~15);
|
|
607 besr.vid_buf4_base_adrs=((mach64_overlay_offset+config->offsets[1]+config->offset.v)&~15);
|
|
608 besr.vid_buf5_base_adrs=((mach64_overlay_offset+config->offsets[1]+config->offset.u)&~15);
|
|
609 config->offset.y = ((besr.vid_buf0_base_adrs)&~15) - mach64_overlay_offset;
|
|
610 config->offset.v = ((besr.vid_buf1_base_adrs)&~15) - mach64_overlay_offset;
|
|
611 config->offset.u = ((besr.vid_buf2_base_adrs)&~15) - mach64_overlay_offset;
|
|
612 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV)
|
|
613 {
|
|
614 uint32_t tmp;
|
|
615 tmp = config->offset.u;
|
|
616 config->offset.u = config->offset.v;
|
|
617 config->offset.v = tmp;
|
|
618 }
|
|
619 }
|
|
620 else
|
|
621 {
|
|
622 besr.vid_buf0_base_adrs = mach64_overlay_offset;
|
|
623 config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&~15;
|
|
624 besr.vid_buf0_base_adrs += config->offset.y;
|
|
625 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs;
|
|
626 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs;
|
|
627 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size;
|
|
628 besr.vid_buf4_base_adrs = besr.vid_buf0_base_adrs+config->frame_size;
|
|
629 besr.vid_buf5_base_adrs = besr.vid_buf0_base_adrs+config->frame_size;
|
|
630 }
|
|
631
|
|
632 leftUV = (left >> 17) & 15;
|
|
633 left = (left >> 16) & 15;
|
|
634 besr.scale_inc = ( h_inc << 16 ) | v_inc;
|
|
635 besr.y_x_start = config->dest.y | (config->dest.x << 16);
|
|
636 besr.y_x_end = (config->dest.y + dest_h) | ((config->dest.x + dest_w) << 16);
|
|
637 besr.height_width = ((src_w - left)<<16) | (src_h - top);
|
|
638 besr.vid_buf_pitch = pitch;
|
|
639 return 0;
|
|
640 }
|
|
641
|
|
642
|
|
643 uint32_t supported_fourcc[] =
|
|
644 {
|
|
645 IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV,
|
|
646 IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU
|
|
647 };
|
|
648
|
|
649 __inline__ static int is_supported_fourcc(uint32_t fourcc)
|
|
650 {
|
|
651 unsigned i;
|
|
652 for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++)
|
|
653 {
|
|
654 if(fourcc==supported_fourcc[i]) return 1;
|
|
655 }
|
|
656 return 0;
|
|
657 }
|
|
658
|
4691
|
659 int vixQueryFourcc(vidix_fourcc_t *to)
|
|
660 {
|
4721
|
661 if(is_supported_fourcc(to->fourcc))
|
|
662 {
|
|
663 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP |
|
|
664 VID_DEPTH_4BPP | VID_DEPTH_8BPP |
|
|
665 VID_DEPTH_12BPP| VID_DEPTH_15BPP|
|
|
666 VID_DEPTH_16BPP| VID_DEPTH_24BPP|
|
|
667 VID_DEPTH_32BPP;
|
|
668 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK;
|
|
669 return 0;
|
|
670 }
|
|
671 else to->depth = to->flags = 0;
|
4691
|
672 return ENOSYS;
|
|
673 }
|
|
674
|
|
675 int vixConfigPlayback(vidix_playback_t *info)
|
|
676 {
|
4721
|
677 if(!is_supported_fourcc(info->fourcc)) return ENOSYS;
|
|
678 if(info->num_frames>2) info->num_frames=2;
|
|
679 if(info->num_frames==1) besr.double_buff=0;
|
|
680 else besr.double_buff=1;
|
|
681 mach64_compute_framesize(info);
|
|
682 mach64_overlay_offset = mach64_ram_size - info->frame_size*info->num_frames;
|
|
683 mach64_overlay_offset &= 0xffff0000;
|
|
684 if(mach64_overlay_offset < 0) return EINVAL;
|
|
685 info->dga_addr = (char *)mach64_mem_base + mach64_overlay_offset;
|
|
686 mach64_vid_init_video(info);
|
|
687 return 0;
|
4691
|
688 }
|
|
689
|
|
690 int vixPlaybackOn(void)
|
|
691 {
|
4721
|
692 mach64_vid_display_video();
|
|
693 return 0;
|
4691
|
694 }
|
|
695
|
|
696 int vixPlaybackOff(void)
|
|
697 {
|
4721
|
698 mach64_vid_stop_video();
|
|
699 return 0;
|
|
700 }
|
|
701
|
|
702 static void mach64_wait_vsync( void )
|
|
703 {
|
|
704 #warning MACH64 VSYNC WAS NOT IMPLEMENTED!!!
|
4691
|
705 }
|
|
706
|
|
707 int vixPlaybackFrameSelect(unsigned int frame)
|
|
708 {
|
4721
|
709 uint32_t off[6];
|
|
710 /*
|
|
711 buf3-5 always should point onto second buffer for better
|
|
712 deinterlacing and TV-in
|
|
713 */
|
|
714 if(!besr.double_buff) return 0;
|
|
715 if((frame%2))
|
|
716 {
|
|
717 off[0] = besr.vid_buf3_base_adrs;
|
|
718 off[1] = besr.vid_buf4_base_adrs;
|
|
719 off[2] = besr.vid_buf5_base_adrs;
|
|
720 off[3] = besr.vid_buf0_base_adrs;
|
|
721 off[4] = besr.vid_buf1_base_adrs;
|
|
722 off[5] = besr.vid_buf2_base_adrs;
|
|
723 }
|
|
724 else
|
|
725 {
|
|
726 off[0] = besr.vid_buf0_base_adrs;
|
|
727 off[1] = besr.vid_buf1_base_adrs;
|
|
728 off[2] = besr.vid_buf2_base_adrs;
|
|
729 off[3] = besr.vid_buf3_base_adrs;
|
|
730 off[4] = besr.vid_buf4_base_adrs;
|
|
731 off[5] = besr.vid_buf5_base_adrs;
|
|
732 }
|
|
733
|
|
734 mach64_wait_vsync();
|
|
735 mach64_wait_for_idle();
|
|
736 mach64_fifo_wait(7);
|
|
737 OUTREG(SCALER_BUF0_OFFSET, off[0]);
|
|
738 OUTREG(SCALER_BUF0_OFFSET_U, off[1]);
|
|
739 OUTREG(SCALER_BUF0_OFFSET_V, off[2]);
|
|
740 OUTREG(SCALER_BUF1_OFFSET, off[3]);
|
|
741 OUTREG(SCALER_BUF1_OFFSET_U, off[4]);
|
|
742 OUTREG(SCALER_BUF1_OFFSET_V, off[5]);
|
|
743 if(__verbose > 1) mach64_vid_dump_regs();
|
|
744 return 0;
|
4691
|
745 }
|
4721
|
746
|
|
747 vidix_video_eq_t equal =
|
|
748 {
|
|
749 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION
|
|
750 ,
|
|
751 0, 0, 0, 0, 0, 0, 0, 0 };
|
|
752
|
|
753 int vixPlaybackGetEq( vidix_video_eq_t * eq)
|
|
754 {
|
|
755 memcpy(eq,&equal,sizeof(vidix_video_eq_t));
|
|
756 return 0;
|
|
757 }
|
|
758
|
|
759 int vixPlaybackSetEq( const vidix_video_eq_t * eq)
|
|
760 {
|
|
761 int br,sat;
|
|
762 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness;
|
|
763 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast;
|
|
764 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation;
|
|
765 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue;
|
|
766 if(eq->cap & VEQ_CAP_RGB_INTENSITY)
|
|
767 {
|
|
768 equal.red_intensity = eq->red_intensity;
|
|
769 equal.green_intensity = eq->green_intensity;
|
|
770 equal.blue_intensity = eq->blue_intensity;
|
|
771 }
|
|
772 equal.flags = eq->flags;
|
|
773 br = equal.brightness * 64 / 1000;
|
|
774 if(br < -64) br = -64; if(br > 63) br = 63;
|
|
775 sat = (equal.saturation + 1000) * 16 / 1000;
|
|
776 if(sat < 0) sat = 0; if(sat > 31) sat = 31;
|
|
777 OUTREG(SCALER_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16));
|
|
778 return 0;
|
|
779 }
|