Mercurial > mplayer.hg
annotate vidix/mach64_vid.c @ 27025:e598c9756181
Ability for specifying TV standard individually for each TV channel.
Slightly modified patch by Ildar devel at pop3 dot ru
author | voroshil |
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date | Sat, 14 Jun 2008 09:14:16 +0000 |
parents | 0e250247255f |
children | df448e1248b2 |
rev | line source |
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22850 | 1 /* |
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2 * VIDIX driver for ATI Mach64 and 3DRage chipsets. |
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3 * |
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4 * Copyright (C) 2002 Nick Kurshev |
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5 * This file is based on sources from |
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6 * GATOS (gatos.sf.net) and X11 (www.xfree86.org) |
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7 * |
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8 * This file is part of MPlayer. |
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9 * |
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10 * MPlayer is free software; you can redistribute it and/or modify |
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11 * it under the terms of the GNU General Public License as published by |
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12 * the Free Software Foundation; either version 2 of the License, or |
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13 * (at your option) any later version. |
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14 * |
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15 * MPlayer is distributed in the hope that it will be useful, |
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16 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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18 * GNU General Public License for more details. |
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19 * |
26719 | 20 * You should have received a copy of the GNU General Public License along |
21 * with MPlayer; if not, write to the Free Software Foundation, Inc., | |
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
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23 */ |
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24 |
22850 | 25 #include <errno.h> |
26 #include <stdio.h> | |
27 #include <stdlib.h> | |
28 #include <string.h> | |
29 #include <math.h> | |
30 #include <inttypes.h> | |
31 #include <fcntl.h> | |
32 | |
22905 | 33 #include "config.h" |
34 #include "libavutil/common.h" | |
35 #include "mpbswap.h" | |
22850 | 36 #include "vidix.h" |
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37 #include "vidixlib.h" |
22850 | 38 #include "fourcc.h" |
22901 | 39 #include "dha.h" |
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40 #include "pci_ids.h" |
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41 #include "pci_names.h" |
22850 | 42 |
43 #include "mach64.h" | |
44 | |
45 #define UNUSED(x) ((void)(x)) /**< Removes warning about unused arguments */ | |
46 | |
47 static void *mach64_mmio_base = 0; | |
48 static void *mach64_mem_base = 0; | |
49 static int32_t mach64_overlay_offset = 0; | |
50 static uint32_t mach64_ram_size = 0; | |
51 static uint32_t mach64_buffer_base[10][3]; | |
52 static int num_mach64_buffers=-1; | |
53 static int supports_planar=0; | |
54 static int supports_lcd_v_stretch=0; | |
55 | |
23053 | 56 static pciinfo_t pci_info; |
22850 | 57 static int probed = 0; |
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58 static int verbosity = 0; |
22850 | 59 |
60 #define VERBOSE_LEVEL 1 | |
61 | |
62 typedef struct bes_registers_s | |
63 { | |
64 /* base address of yuv framebuffer */ | |
65 uint32_t yuv_base; | |
66 uint32_t fourcc; | |
67 /* YUV BES registers */ | |
68 uint32_t reg_load_cntl; | |
69 uint32_t scale_inc; | |
70 uint32_t y_x_start; | |
71 uint32_t y_x_end; | |
72 uint32_t vid_buf_pitch; | |
73 uint32_t height_width; | |
74 | |
75 uint32_t scale_cntl; | |
76 uint32_t exclusive_horz; | |
77 uint32_t auto_flip_cntl; | |
78 uint32_t filter_cntl; | |
79 uint32_t key_cntl; | |
80 uint32_t test; | |
81 /* Configurable stuff */ | |
82 | |
83 int brightness; | |
84 int saturation; | |
85 | |
86 int ckey_on; | |
87 uint32_t graphics_key_clr; | |
88 uint32_t graphics_key_msk; | |
89 | |
90 int deinterlace_on; | |
91 uint32_t deinterlace_pattern; | |
92 | |
93 } bes_registers_t; | |
94 | |
95 static bes_registers_t besr; | |
96 | |
97 typedef struct video_registers_s | |
98 { | |
99 const char * sname; | |
100 uint32_t name; | |
101 uint32_t value; | |
102 }video_registers_t; | |
103 | |
104 /* Graphic keys */ | |
105 static vidix_grkey_t mach64_grkey; | |
106 | |
107 #define DECLARE_VREG(name) { #name, name, 0 } | |
108 static video_registers_t vregs[] = | |
109 { | |
110 DECLARE_VREG(OVERLAY_SCALE_INC), | |
111 DECLARE_VREG(OVERLAY_Y_X_START), | |
112 DECLARE_VREG(OVERLAY_Y_X_END), | |
113 DECLARE_VREG(OVERLAY_SCALE_CNTL), | |
114 DECLARE_VREG(OVERLAY_EXCLUSIVE_HORZ), | |
115 DECLARE_VREG(OVERLAY_EXCLUSIVE_VERT), | |
116 DECLARE_VREG(OVERLAY_TEST), | |
117 DECLARE_VREG(SCALER_BUF_PITCH), | |
118 DECLARE_VREG(SCALER_HEIGHT_WIDTH), | |
119 DECLARE_VREG(SCALER_BUF0_OFFSET), | |
120 DECLARE_VREG(SCALER_BUF0_OFFSET_U), | |
121 DECLARE_VREG(SCALER_BUF0_OFFSET_V), | |
122 DECLARE_VREG(SCALER_BUF1_OFFSET), | |
123 DECLARE_VREG(SCALER_BUF1_OFFSET_U), | |
124 DECLARE_VREG(SCALER_BUF1_OFFSET_V), | |
125 DECLARE_VREG(SCALER_H_COEFF0), | |
126 DECLARE_VREG(SCALER_H_COEFF1), | |
127 DECLARE_VREG(SCALER_H_COEFF2), | |
128 DECLARE_VREG(SCALER_H_COEFF3), | |
129 DECLARE_VREG(SCALER_H_COEFF4), | |
130 DECLARE_VREG(SCALER_COLOUR_CNTL), | |
131 DECLARE_VREG(SCALER_THRESHOLD), | |
132 DECLARE_VREG(VIDEO_FORMAT), | |
133 DECLARE_VREG(VIDEO_CONFIG), | |
134 DECLARE_VREG(VIDEO_SYNC_TEST), | |
135 DECLARE_VREG(VIDEO_SYNC_TEST_B) | |
136 }; | |
137 | |
138 /* have to restore it on exit */ | |
139 static uint32_t SAVED_OVERLAY_GRAPHICS_KEY_CLR; | |
140 | |
141 /* VIDIX exports */ | |
142 | |
143 /* MMIO space*/ | |
144 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) | |
145 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
146 | |
147 #define INREG8(addr) GETREG(uint8_t,(uint8_t *)mach64_mmio_base,((addr)^0x100)<<2) | |
148 #define OUTREG8(addr,val) SETREG(uint8_t,(uint8_t *)mach64_mmio_base,((addr)^0x100)<<2,val) | |
149 | |
150 static inline uint32_t INREG (uint32_t addr) { | |
151 uint32_t tmp = GETREG(uint32_t,(uint8_t *)mach64_mmio_base,((addr)^0x100)<<2); | |
152 return le2me_32(tmp); | |
153 } | |
154 #define OUTREG(addr,val) SETREG(uint32_t,(uint8_t *)mach64_mmio_base,((addr)^0x100)<<2,le2me_32(val)) | |
155 | |
156 #define OUTREGP(addr,val,mask) \ | |
157 do { \ | |
158 unsigned int _tmp = INREG(addr); \ | |
159 _tmp &= (mask); \ | |
160 _tmp |= (val); \ | |
161 OUTREG(addr, _tmp); \ | |
162 } while (0) | |
163 | |
164 static __inline__ int ATIGetMach64LCDReg(int _Index) | |
165 { | |
166 OUTREG8(LCD_INDEX, _Index); | |
167 return INREG(LCD_DATA); | |
168 } | |
169 | |
170 static __inline__ uint32_t INPLL(uint32_t addr) | |
171 { | |
172 uint32_t res; | |
173 uint32_t in; | |
174 | |
175 in= INREG(CLOCK_CNTL); | |
176 in &= ~((PLL_WR_EN | PLL_ADDR)); //clean some stuff | |
177 OUTREG(CLOCK_CNTL, in | (addr<<10)); | |
178 | |
179 /* read the register value */ | |
180 res = (INREG(CLOCK_CNTL)>>16)&0xFF; | |
181 return res; | |
182 } | |
183 | |
184 static __inline__ void OUTPLL(uint32_t addr,uint32_t val) | |
185 { | |
186 //FIXME buggy but its not used | |
187 /* write addr byte */ | |
188 OUTREG8(CLOCK_CNTL + 1, (addr << 2) | PLL_WR_EN); | |
189 /* write the register value */ | |
190 OUTREG(CLOCK_CNTL + 2, val); | |
191 OUTREG8(CLOCK_CNTL + 1, (addr << 2) & ~PLL_WR_EN); | |
192 } | |
193 | |
194 #define OUTPLLP(addr,val,mask) \ | |
195 do { \ | |
196 unsigned int _tmp = INPLL(addr); \ | |
197 _tmp &= (mask); \ | |
198 _tmp |= (val); \ | |
199 OUTPLL(addr, _tmp); \ | |
200 } while (0) | |
201 | |
202 static void mach64_fifo_wait(unsigned n) | |
203 { | |
204 while ((INREG(FIFO_STAT) & 0xffff) > ((uint32_t)(0x8000 >> n))); | |
205 } | |
206 | |
207 static void mach64_wait_for_idle( void ) | |
208 { | |
209 mach64_fifo_wait(16); | |
210 while ((INREG(GUI_STAT) & 1)!= 0); | |
211 } | |
212 | |
213 static void mach64_wait_vsync( void ) | |
214 { | |
215 int i; | |
216 | |
217 for(i=0; i<2000000; i++) | |
218 if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK)==0 ) break; | |
219 for(i=0; i<2000000; i++) | |
220 if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK) ) break; | |
221 | |
222 } | |
223 | |
224 static vidix_capability_t mach64_cap = | |
225 { | |
226 "BES driver for Mach64/3DRage cards", | |
227 "Nick Kurshev and Michael Niedermayer", | |
228 TYPE_OUTPUT, | |
229 { 0, 0, 0, 0 }, | |
230 2048, | |
231 2048, | |
232 4, | |
233 4, | |
234 -1, | |
235 FLAG_UPSCALER|FLAG_DOWNSCALER, | |
236 VENDOR_ATI, | |
237 -1, | |
238 { 0, 0, 0, 0 } | |
239 }; | |
240 | |
241 static uint32_t mach64_vid_get_dbpp( void ) | |
242 { | |
243 uint32_t dbpp,retval; | |
244 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0x7; | |
245 switch(dbpp) | |
246 { | |
247 case 1: retval = 4; break; | |
248 case 2: retval = 8; break; | |
249 case 3: retval = 15; break; | |
250 case 4: retval = 16; break; | |
251 case 5: retval = 24; break; | |
252 default: retval=32; break; | |
253 } | |
254 return retval; | |
255 } | |
256 | |
257 static int mach64_is_dbl_scan( void ) | |
258 { | |
259 return INREG(CRTC_GEN_CNTL) & CRTC_DBL_SCAN_EN; | |
260 } | |
261 | |
262 static int mach64_is_interlace( void ) | |
263 { | |
264 return INREG(CRTC_GEN_CNTL) & CRTC_INTERLACE_EN; | |
265 } | |
266 | |
267 static uint32_t mach64_get_xres( void ) | |
268 { | |
269 /* FIXME: currently we extract that from CRTC!!!*/ | |
270 uint32_t xres,h_total; | |
271 h_total = INREG(CRTC_H_TOTAL_DISP); | |
272 xres = (h_total >> 16) & 0xffff; | |
273 return (xres + 1)*8; | |
274 } | |
275 | |
276 static uint32_t mach64_get_yres( void ) | |
277 { | |
278 /* FIXME: currently we extract that from CRTC!!!*/ | |
279 uint32_t yres,v_total; | |
280 v_total = INREG(CRTC_V_TOTAL_DISP); | |
281 yres = (v_total >> 16) & 0xffff; | |
282 return yres + 1; | |
283 } | |
284 | |
285 // returns the verical stretch factor in 16.16 | |
286 static int mach64_get_vert_stretch(void) | |
287 { | |
288 int lcd_index; | |
289 int vert_stretching; | |
290 int ext_vert_stretch; | |
291 int ret; | |
292 int yres= mach64_get_yres(); | |
293 | |
294 if(!supports_lcd_v_stretch){ | |
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295 if(verbosity > 0) printf("[mach64] vertical stretching not supported\n"); |
22850 | 296 return 1<<16; |
297 } | |
298 | |
299 lcd_index= INREG(LCD_INDEX); | |
300 | |
301 vert_stretching= ATIGetMach64LCDReg(LCD_VERT_STRETCHING); | |
302 if(!(vert_stretching&VERT_STRETCH_EN)) ret= 1<<16; | |
303 else | |
304 { | |
305 int panel_size; | |
306 | |
307 ext_vert_stretch= ATIGetMach64LCDReg(LCD_EXT_VERT_STRETCH); | |
308 panel_size= (ext_vert_stretch&VERT_PANEL_SIZE)>>11; | |
309 panel_size++; | |
310 | |
311 ret= ((yres<<16) + (panel_size>>1))/panel_size; | |
312 } | |
313 | |
314 // lcd_gen_ctrl = ATIGetMach64LCDReg(LCD_GEN_CNTL); | |
315 | |
316 OUTREG(LCD_INDEX, lcd_index); | |
317 | |
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318 if(verbosity > 0) printf("[mach64] vertical stretching factor= %d\n", ret); |
22850 | 319 |
320 return ret; | |
321 } | |
322 | |
323 static void mach64_vid_make_default(void) | |
324 { | |
325 mach64_fifo_wait(5); | |
326 OUTREG(SCALER_COLOUR_CNTL,0x00101000); | |
327 | |
328 besr.ckey_on=0; | |
329 besr.graphics_key_msk=0; | |
330 besr.graphics_key_clr=0; | |
331 | |
332 OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk); | |
333 OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
334 OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND); | |
335 | |
336 } | |
337 | |
338 static void mach64_vid_dump_regs( void ) | |
339 { | |
340 size_t i; | |
341 printf("[mach64] *** Begin of DRIVER variables dump ***\n"); | |
342 printf("[mach64] mach64_mmio_base=%p\n",mach64_mmio_base); | |
343 printf("[mach64] mach64_mem_base=%p\n",mach64_mem_base); | |
344 printf("[mach64] mach64_overlay_off=%08X\n",mach64_overlay_offset); | |
345 printf("[mach64] mach64_ram_size=%08X\n",mach64_ram_size); | |
346 printf("[mach64] video mode: %ux%u@%u\n",mach64_get_xres(),mach64_get_yres(),mach64_vid_get_dbpp()); | |
347 printf("[mach64] *** Begin of OV0 registers dump ***\n"); | |
348 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
349 { | |
350 mach64_wait_for_idle(); | |
351 printf("[mach64] %s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); | |
352 } | |
353 printf("[mach64] *** End of OV0 registers dump ***\n"); | |
354 } | |
355 | |
356 | |
357 static unsigned short ati_card_ids[] = | |
358 { | |
359 DEVICE_ATI_215CT_MACH64_CT, | |
360 DEVICE_ATI_210888CX_MACH64_CX, | |
361 DEVICE_ATI_210888ET_MACH64_ET, | |
362 DEVICE_ATI_MACH64_VT, | |
363 DEVICE_ATI_210888GX_MACH64_GX, | |
364 DEVICE_ATI_264LT_MACH64_LT, | |
365 DEVICE_ATI_264VT_MACH64_VT, | |
366 DEVICE_ATI_264VT3_MACH64_VT3, | |
367 DEVICE_ATI_264VT4_MACH64_VT4, | |
368 /**/ | |
369 DEVICE_ATI_3D_RAGE_PRO, | |
370 DEVICE_ATI_3D_RAGE_PRO2, | |
371 DEVICE_ATI_3D_RAGE_PRO3, | |
372 DEVICE_ATI_3D_RAGE_PRO4, | |
373 DEVICE_ATI_RAGE_XC, | |
374 DEVICE_ATI_RAGE_XL_AGP, | |
375 DEVICE_ATI_RAGE_XC_AGP, | |
376 DEVICE_ATI_RAGE_XL, | |
377 DEVICE_ATI_3D_RAGE_PRO5, | |
378 DEVICE_ATI_3D_RAGE_PRO6, | |
379 DEVICE_ATI_RAGE_XL2, | |
380 DEVICE_ATI_RAGE_XC2, | |
381 DEVICE_ATI_3D_RAGE_I_II, | |
382 DEVICE_ATI_3D_RAGE_II, | |
383 DEVICE_ATI_3D_RAGE_IIC, | |
384 DEVICE_ATI_3D_RAGE_IIC2, | |
385 DEVICE_ATI_3D_RAGE_IIC3, | |
386 DEVICE_ATI_3D_RAGE_IIC4, | |
387 DEVICE_ATI_3D_RAGE_LT, | |
388 DEVICE_ATI_3D_RAGE_LT2, | |
389 DEVICE_ATI_3D_RAGE_LT_G, | |
390 DEVICE_ATI_3D_RAGE_LT3, | |
391 DEVICE_ATI_RAGE_MOBILITY_P_M, | |
392 DEVICE_ATI_RAGE_MOBILITY_L, | |
393 DEVICE_ATI_3D_RAGE_LT4, | |
394 DEVICE_ATI_3D_RAGE_LT5, | |
395 DEVICE_ATI_RAGE_MOBILITY_P_M2, | |
396 DEVICE_ATI_RAGE_MOBILITY_L2 | |
397 }; | |
398 | |
399 static int find_chip(unsigned chip_id) | |
400 { | |
401 unsigned i; | |
402 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) | |
403 { | |
404 if(chip_id == ati_card_ids[i]) return i; | |
405 } | |
406 return -1; | |
407 } | |
408 | |
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409 static int mach64_probe(int verbose,int force) |
22850 | 410 { |
411 pciinfo_t lst[MAX_PCI_DEVICES]; | |
412 unsigned i,num_pci; | |
413 int err; | |
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414 verbosity = verbose; |
22850 | 415 err = pci_scan(lst,&num_pci); |
416 if(err) | |
417 { | |
418 printf("[mach64] Error occurred during pci scan: %s\n",strerror(err)); | |
419 return err; | |
420 } | |
421 else | |
422 { | |
423 err = ENXIO; | |
424 for(i=0;i<num_pci;i++) | |
425 { | |
426 if(lst[i].vendor == VENDOR_ATI) | |
427 { | |
428 int idx; | |
429 const char *dname; | |
430 idx = find_chip(lst[i].device); | |
431 if(idx == -1 && force == PROBE_NORMAL) continue; | |
432 dname = pci_device_name(VENDOR_ATI,lst[i].device); | |
433 dname = dname ? dname : "Unknown chip"; | |
434 printf("[mach64] Found chip: %s\n",dname); | |
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435 #if 0 |
22850 | 436 if ((lst[i].command & PCI_COMMAND_IO) == 0) |
437 { | |
438 printf("[mach64] Device is disabled, ignoring\n"); | |
439 continue; | |
440 } | |
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441 #endif |
22850 | 442 if(force > PROBE_NORMAL) |
443 { | |
444 printf("[mach64] Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); | |
445 if(idx == -1) | |
446 printf("[mach64] Assuming it as Mach64\n"); | |
447 } | |
448 mach64_cap.device_id = lst[i].device; | |
449 err = 0; | |
450 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); | |
451 probed=1; | |
452 break; | |
453 } | |
454 } | |
455 } | |
456 if(err && verbose) printf("[mach64] Can't find chip\n"); | |
457 return err; | |
458 } | |
459 | |
460 static void reset_regs( void ) | |
461 { | |
462 size_t i; | |
463 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
464 { | |
465 mach64_fifo_wait(2); | |
466 OUTREG(vregs[i].name,0); | |
467 } | |
468 } | |
469 | |
470 | |
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471 static int mach64_init(void) |
22850 | 472 { |
473 int err; | |
474 if(!probed) | |
475 { | |
476 printf("[mach64] Driver was not probed but is being initializing\n"); | |
477 return EINTR; | |
478 } | |
479 | |
480 if((mach64_mmio_base = map_phys_mem(pci_info.base2,0x1000))==(void *)-1) return ENOMEM; | |
481 mach64_wait_for_idle(); | |
482 mach64_ram_size = INREG(MEM_CNTL) & CTL_MEM_SIZEB; | |
483 if (mach64_ram_size < 8) mach64_ram_size = (mach64_ram_size + 1) * 512; | |
484 else if (mach64_ram_size < 12) mach64_ram_size = (mach64_ram_size - 3) * 1024; | |
485 else mach64_ram_size = (mach64_ram_size - 7) * 2048; | |
486 mach64_ram_size *= 0x400; /* KB -> bytes */ | |
487 if((mach64_mem_base = map_phys_mem(pci_info.base0,mach64_ram_size))==(void *)-1) return ENOMEM; | |
488 memset(&besr,0,sizeof(bes_registers_t)); | |
489 printf("[mach64] Video memory = %uMb\n",mach64_ram_size/0x100000); | |
490 err = mtrr_set_type(pci_info.base0,mach64_ram_size,MTRR_TYPE_WRCOMB); | |
491 if(!err) printf("[mach64] Set write-combining type of video memory\n"); | |
492 | |
493 /* save this */ | |
494 mach64_wait_for_idle(); | |
495 SAVED_OVERLAY_GRAPHICS_KEY_CLR = INREG(OVERLAY_GRAPHICS_KEY_CLR); | |
496 | |
497 /* check if planar formats are supported */ | |
498 supports_planar=0; | |
499 mach64_wait_for_idle(); | |
500 mach64_fifo_wait(2); | |
501 if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; | |
502 else | |
503 { | |
504 OUTREG(SCALER_BUF0_OFFSET_U, -1); | |
505 | |
506 mach64_wait_vsync(); | |
507 mach64_wait_for_idle(); | |
508 mach64_fifo_wait(2); | |
509 | |
510 if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; | |
511 } | |
512 if(supports_planar) printf("[mach64] Planar YUV formats are supported :)\n"); | |
513 else printf("[mach64] Planar YUV formats are not supported :(\n"); | |
514 | |
515 if( mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M | |
516 || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M2 | |
517 || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L | |
518 || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L2) | |
519 supports_lcd_v_stretch=1; | |
520 else | |
521 supports_lcd_v_stretch=0; | |
522 | |
523 reset_regs(); | |
524 mach64_vid_make_default(); | |
525 | |
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526 if(verbosity > VERBOSE_LEVEL) mach64_vid_dump_regs(); |
22850 | 527 return 0; |
528 } | |
529 | |
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530 static void mach64_destroy(void) |
22850 | 531 { |
532 /*restore this*/ | |
533 mach64_wait_for_idle(); | |
534 OUTREG(OVERLAY_GRAPHICS_KEY_CLR,SAVED_OVERLAY_GRAPHICS_KEY_CLR); | |
535 | |
536 unmap_phys_mem(mach64_mem_base,mach64_ram_size); | |
537 unmap_phys_mem(mach64_mmio_base,0x1000); | |
538 } | |
539 | |
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540 static int mach64_get_caps(vidix_capability_t *to) |
22850 | 541 { |
542 memcpy(to, &mach64_cap, sizeof(vidix_capability_t)); | |
543 return 0; | |
544 } | |
545 | |
546 static unsigned mach64_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) | |
547 { | |
548 unsigned pitch,spy,spv,spu; | |
549 spy = spv = spu = 0; | |
550 switch(spitch->y) | |
551 { | |
552 case 16: | |
553 case 32: | |
554 case 64: | |
555 case 128: | |
556 case 256: spy = spitch->y; break; | |
557 default: break; | |
558 } | |
559 switch(spitch->u) | |
560 { | |
561 case 16: | |
562 case 32: | |
563 case 64: | |
564 case 128: | |
565 case 256: spu = spitch->u; break; | |
566 default: break; | |
567 } | |
568 switch(spitch->v) | |
569 { | |
570 case 16: | |
571 case 32: | |
572 case 64: | |
573 case 128: | |
574 case 256: spv = spitch->v; break; | |
575 default: break; | |
576 } | |
577 switch(fourcc) | |
578 { | |
579 /* 4:2:0 */ | |
580 case IMGFMT_IYUV: | |
581 case IMGFMT_YV12: | |
582 case IMGFMT_I420: | |
583 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; | |
584 else pitch = 32; | |
585 break; | |
586 case IMGFMT_YVU9: | |
587 if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; | |
588 else pitch = 64; | |
589 break; | |
590 default: | |
591 if(spy >= 16) pitch = spy; | |
592 else pitch = 16; | |
593 break; | |
594 } | |
595 return pitch; | |
596 } | |
597 | |
598 static void mach64_compute_framesize(vidix_playback_t *info) | |
599 { | |
600 unsigned pitch,awidth; | |
601 pitch = mach64_query_pitch(info->fourcc,&info->src.pitch); | |
602 switch(info->fourcc) | |
603 { | |
604 case IMGFMT_I420: | |
605 case IMGFMT_YV12: | |
606 case IMGFMT_IYUV: | |
607 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
608 info->frame_size = awidth*(info->src.h+info->src.h/2); | |
609 break; | |
610 case IMGFMT_YVU9: | |
611 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
612 info->frame_size = awidth*(info->src.h+info->src.h/8); | |
613 break; | |
614 // case IMGFMT_RGB32: | |
615 case IMGFMT_BGR32: | |
616 awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); | |
617 info->frame_size = (awidth*info->src.h); | |
618 break; | |
619 /* YUY2 YVYU, RGB15, RGB16 */ | |
620 default: | |
621 awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); | |
622 info->frame_size = (awidth*info->src.h); | |
623 break; | |
624 } | |
625 info->frame_size+=256; // so we have some space for alignment & such | |
626 info->frame_size&=~16; | |
627 } | |
628 | |
629 static void mach64_vid_stop_video( void ) | |
630 { | |
631 mach64_fifo_wait(14); | |
632 OUTREG(OVERLAY_SCALE_CNTL, 0x80000000); | |
633 OUTREG(OVERLAY_EXCLUSIVE_HORZ, 0); | |
634 OUTREG(OVERLAY_EXCLUSIVE_VERT, 0); | |
635 OUTREG(SCALER_H_COEFF0, 0x00002000); | |
636 OUTREG(SCALER_H_COEFF1, 0x0D06200D); | |
637 OUTREG(SCALER_H_COEFF2, 0x0D0A1C0D); | |
638 OUTREG(SCALER_H_COEFF3, 0x0C0E1A0C); | |
639 OUTREG(SCALER_H_COEFF4, 0x0C14140C); | |
640 OUTREG(VIDEO_FORMAT, 0xB000B); | |
641 OUTREG(OVERLAY_TEST, 0x0); | |
642 } | |
643 | |
644 static void mach64_vid_display_video( void ) | |
645 { | |
646 uint32_t vf; | |
647 mach64_fifo_wait(14); | |
648 | |
649 OUTREG(OVERLAY_Y_X_START, besr.y_x_start); | |
650 OUTREG(OVERLAY_Y_X_END, besr.y_x_end); | |
651 OUTREG(OVERLAY_SCALE_INC, besr.scale_inc); | |
652 OUTREG(SCALER_BUF_PITCH, besr.vid_buf_pitch); | |
653 OUTREG(SCALER_HEIGHT_WIDTH, besr.height_width); | |
654 OUTREG(SCALER_BUF0_OFFSET, mach64_buffer_base[0][0]); | |
655 OUTREG(SCALER_BUF0_OFFSET_U, mach64_buffer_base[0][1]); | |
656 OUTREG(SCALER_BUF0_OFFSET_V, mach64_buffer_base[0][2]); | |
657 OUTREG(SCALER_BUF1_OFFSET, mach64_buffer_base[0][0]); | |
658 OUTREG(SCALER_BUF1_OFFSET_U, mach64_buffer_base[0][1]); | |
659 OUTREG(SCALER_BUF1_OFFSET_V, mach64_buffer_base[0][2]); | |
660 mach64_wait_vsync(); | |
661 | |
662 mach64_fifo_wait(4); | |
663 OUTREG(OVERLAY_SCALE_CNTL, 0xC4000003); | |
664 // OVERLAY_SCALE_CNTL bits & what they seem to affect | |
665 // bit 0 no effect | |
666 // bit 1 yuv2rgb coeff related | |
667 // bit 2 horizontal interpolation if 0 | |
668 // bit 3 vertical interpolation if 0 | |
669 // bit 4 chroma encoding (0-> 128=neutral / 1-> 0->neutral) | |
670 // bit 5-6 gamma correction | |
671 // bit 7 nothing visible if set | |
672 // bit 8-27 no effect | |
673 // bit 28-31 nothing interresting just crashed my system when i played with them :( | |
674 | |
675 mach64_wait_for_idle(); | |
676 vf = INREG(VIDEO_FORMAT); | |
677 | |
678 // Bits 16-19 seem to select the format | |
679 // 0x0 dunno behaves strange | |
680 // 0x1 dunno behaves strange | |
681 // 0x2 dunno behaves strange | |
682 // 0x3 BGR15 | |
683 // 0x4 BGR16 | |
684 // 0x5 BGR16 (hmm, that need investigation, 2 BGR16 formats, i guess 1 will have only 5bits for green) | |
685 // 0x6 BGR32 | |
686 // 0x7 BGR32 with somehow mixed even / odd pixels ? | |
687 // 0x8 YYYYUVUV | |
688 // 0x9 YVU9 | |
689 // 0xA YV12 | |
690 // 0xB YUY2 | |
691 // 0xC UYVY | |
692 // 0xD UYVY (no difference is visible if i switch between C/D for every even/odd frame) | |
693 // 0xE dunno behaves strange | |
694 // 0xF dunno behaves strange | |
695 // Bit 28 all values are assumed to be 7 bit with chroma=64 for black (tested with YV12 & YUY2) | |
696 // the remaining bits seem to have no effect | |
697 | |
698 | |
699 switch(besr.fourcc) | |
700 { | |
701 /* BGR formats */ | |
702 case IMGFMT_BGR15: OUTREG(VIDEO_FORMAT, 0x00030000); break; | |
703 case IMGFMT_BGR16: OUTREG(VIDEO_FORMAT, 0x00040000); break; | |
704 case IMGFMT_BGR32: OUTREG(VIDEO_FORMAT, 0x00060000); break; | |
705 /* 4:2:0 */ | |
706 case IMGFMT_IYUV: | |
707 case IMGFMT_I420: | |
708 case IMGFMT_YV12: OUTREG(VIDEO_FORMAT, 0x000A0000); break; | |
709 | |
710 case IMGFMT_YVU9: OUTREG(VIDEO_FORMAT, 0x00090000); break; | |
711 /* 4:2:2 */ | |
712 case IMGFMT_YVYU: | |
713 case IMGFMT_UYVY: OUTREG(VIDEO_FORMAT, 0x000C0000); break; | |
714 case IMGFMT_YUY2: | |
715 default: OUTREG(VIDEO_FORMAT, 0x000B0000); break; | |
716 } | |
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717 if(verbosity > VERBOSE_LEVEL) mach64_vid_dump_regs(); |
22850 | 718 } |
719 | |
720 static int mach64_vid_init_video( vidix_playback_t *config ) | |
721 { | |
722 uint32_t src_w,src_h,dest_w,dest_h,pitch,h_inc,v_inc,left,leftUV,top,ecp,y_pos; | |
723 int is_420,best_pitch,mpitch; | |
724 int src_offset_y, src_offset_u, src_offset_v; | |
725 unsigned int i; | |
726 | |
727 mach64_vid_stop_video(); | |
728 /* warning, if left or top are != 0 this will fail, as the framesize is too small then */ | |
729 left = config->src.x; | |
730 top = config->src.y; | |
731 src_h = config->src.h; | |
732 src_w = config->src.w; | |
733 is_420 = 0; | |
734 if(config->fourcc == IMGFMT_YV12 || | |
735 config->fourcc == IMGFMT_I420 || | |
736 config->fourcc == IMGFMT_IYUV) is_420 = 1; | |
737 best_pitch = mach64_query_pitch(config->fourcc,&config->src.pitch); | |
738 mpitch = best_pitch-1; | |
739 switch(config->fourcc) | |
740 { | |
741 case IMGFMT_YVU9: | |
742 /* 4:2:0 */ | |
743 case IMGFMT_IYUV: | |
744 case IMGFMT_YV12: | |
745 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; | |
746 config->dest.pitch.y = | |
747 config->dest.pitch.u = | |
748 config->dest.pitch.v = best_pitch; | |
749 besr.vid_buf_pitch= pitch; | |
750 break; | |
751 /* RGB 4:4:4:4 */ | |
752 case IMGFMT_RGB32: | |
753 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; | |
754 config->dest.pitch.y = | |
755 config->dest.pitch.u = | |
756 config->dest.pitch.v = best_pitch; | |
757 besr.vid_buf_pitch= pitch>>2; | |
758 break; | |
759 /* 4:2:2 */ | |
760 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ | |
761 pitch = ((src_w*2) + mpitch) & ~mpitch; | |
762 config->dest.pitch.y = | |
763 config->dest.pitch.u = | |
764 config->dest.pitch.v = best_pitch; | |
765 besr.vid_buf_pitch= pitch>>1; | |
766 break; | |
767 } | |
768 dest_w = config->dest.w; | |
769 dest_h = config->dest.h; | |
770 besr.fourcc = config->fourcc; | |
771 ecp = (INPLL(PLL_VCLK_CNTL) & PLL_ECP_DIV) >> 4; | |
23048 | 772 |
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773 if(verbosity > 0) printf("[mach64] ecp: %d\n", ecp); |
22850 | 774 v_inc = src_h * mach64_get_vert_stretch(); |
775 | |
776 if(mach64_is_interlace()) v_inc<<=1; | |
777 if(mach64_is_dbl_scan() ) v_inc>>=1; | |
778 v_inc>>=4; // convert 16.16 -> 20.12 | |
779 v_inc/= dest_h; | |
780 | |
781 h_inc = (src_w << (12+ecp)) / dest_w; | |
782 /* keep everything in 16.16 */ | |
783 config->offsets[0] = 0; | |
784 for(i=1; i<config->num_frames; i++) | |
785 config->offsets[i] = config->offsets[i-1] + config->frame_size; | |
786 | |
787 /*FIXME the left / top stuff is broken (= zoom a src rectangle from a larger one) | |
788 1. the framesize isn't known as the outer src rectangle dimensions aren't known | |
789 2. the mach64 needs aligned addresses so it can't work anyway | |
790 -> so we could shift the outer buffer to compensate that but that would mean | |
791 alignment problems for the code which writes into it | |
792 */ | |
793 | |
794 if(is_420) | |
795 { | |
796 config->offset.y= 0; | |
797 config->offset.u= (pitch*src_h + 15)&~15; | |
798 config->offset.v= (config->offset.u + (pitch*src_h>>2) + 15)&~15; | |
799 | |
800 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) | |
801 { | |
802 uint32_t tmp; | |
803 tmp = config->offset.u; | |
804 config->offset.u = config->offset.v; | |
805 config->offset.v = tmp; | |
806 } | |
807 | |
808 src_offset_y= config->offset.y + top*pitch + left; | |
809 src_offset_u= config->offset.u + (top*pitch>>2) + (left>>1); | |
810 src_offset_v= config->offset.v + (top*pitch>>2) + (left>>1); | |
811 } | |
812 else if(besr.fourcc == IMGFMT_YVU9) | |
813 { | |
814 config->offset.y= 0; | |
815 config->offset.u= (pitch*src_h + 15)&~15; | |
816 config->offset.v= (config->offset.u + (pitch*src_h>>4) + 15)&~15; | |
817 | |
818 src_offset_y= config->offset.y + top*pitch + left; | |
819 src_offset_u= config->offset.u + (top*pitch>>4) + (left>>1); | |
820 src_offset_v= config->offset.v + (top*pitch>>4) + (left>>1); | |
821 } | |
822 else if(besr.fourcc == IMGFMT_BGR32) | |
823 { | |
824 config->offset.y = config->offset.u = config->offset.v = 0; | |
825 src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 2); | |
826 } | |
827 else | |
828 { | |
829 config->offset.y = config->offset.u = config->offset.v = 0; | |
830 src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 1); | |
831 } | |
832 | |
833 num_mach64_buffers= config->num_frames; | |
834 for(i=0; i<config->num_frames; i++) | |
835 { | |
836 mach64_buffer_base[i][0]= (mach64_overlay_offset + config->offsets[i] + src_offset_y)&~15; | |
837 mach64_buffer_base[i][1]= (mach64_overlay_offset + config->offsets[i] + src_offset_u)&~15; | |
838 mach64_buffer_base[i][2]= (mach64_overlay_offset + config->offsets[i] + src_offset_v)&~15; | |
839 } | |
840 | |
841 leftUV = (left >> 17) & 15; | |
842 left = (left >> 16) & 15; | |
843 besr.scale_inc = ( h_inc << 16 ) | v_inc; | |
844 y_pos = config->dest.y; | |
845 if(mach64_is_dbl_scan()) y_pos*=2; | |
846 else | |
847 if(mach64_is_interlace()) y_pos/=2; | |
848 besr.y_x_start = y_pos | (config->dest.x << 16); | |
849 y_pos =config->dest.y + dest_h; | |
850 if(mach64_is_dbl_scan()) y_pos*=2; | |
851 else | |
852 if(mach64_is_interlace()) y_pos/=2; | |
853 besr.y_x_end = y_pos | ((config->dest.x + dest_w) << 16); | |
854 besr.height_width = ((src_w - left)<<16) | (src_h - top); | |
855 | |
856 return 0; | |
857 } | |
858 | |
859 static int is_supported_fourcc(uint32_t fourcc) | |
860 { | |
861 switch(fourcc) | |
862 { | |
863 case IMGFMT_YV12: | |
864 case IMGFMT_I420: | |
865 case IMGFMT_YVU9: | |
866 case IMGFMT_IYUV: | |
867 return supports_planar; | |
868 case IMGFMT_YUY2: | |
869 case IMGFMT_UYVY: | |
870 case IMGFMT_BGR15: | |
871 case IMGFMT_BGR16: | |
872 case IMGFMT_BGR32: | |
873 return 1; | |
874 default: | |
875 return 0; | |
876 } | |
877 } | |
878 | |
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879 static int mach64_query_fourcc(vidix_fourcc_t *to) |
22850 | 880 { |
881 if(is_supported_fourcc(to->fourcc)) | |
882 { | |
23060 | 883 to->depth = VID_DEPTH_ALL; |
22850 | 884 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; |
885 return 0; | |
886 } | |
887 else to->depth = to->flags = 0; | |
888 return ENOSYS; | |
889 } | |
890 | |
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891 static int mach64_config_playback(vidix_playback_t *info) |
22850 | 892 { |
893 if(!is_supported_fourcc(info->fourcc)) return ENOSYS; | |
894 | |
895 mach64_compute_framesize(info); | |
896 | |
897 if(info->num_frames>4) info->num_frames=4; | |
898 for(;info->num_frames>0; info->num_frames--) | |
899 { | |
900 mach64_overlay_offset = mach64_ram_size - info->frame_size*info->num_frames; | |
901 mach64_overlay_offset &= 0xffff0000; | |
902 if(mach64_overlay_offset>0) break; | |
903 } | |
904 if(info->num_frames <= 0) return EINVAL; | |
905 | |
906 info->dga_addr = (char *)mach64_mem_base + mach64_overlay_offset; | |
907 mach64_vid_init_video(info); | |
908 return 0; | |
909 } | |
910 | |
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911 static int mach64_playback_on(void) |
22850 | 912 { |
913 mach64_vid_display_video(); | |
914 return 0; | |
915 } | |
916 | |
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917 static int mach64_playback_off(void) |
22850 | 918 { |
919 mach64_vid_stop_video(); | |
920 return 0; | |
921 } | |
922 | |
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923 static int mach64_frame_sel(unsigned int frame) |
22850 | 924 { |
925 uint32_t off[6]; | |
926 int i; | |
927 int last_frame= (frame-1+num_mach64_buffers) % num_mach64_buffers; | |
928 //printf("Selecting frame %d\n", frame); | |
929 /* | |
930 buf3-5 always should point onto second buffer for better | |
931 deinterlacing and TV-in | |
932 */ | |
933 if(num_mach64_buffers==1) return 0; | |
934 | |
935 for(i=0; i<3; i++) | |
936 { | |
937 off[i] = mach64_buffer_base[frame][i]; | |
938 off[i+3]= mach64_buffer_base[last_frame][i]; | |
939 } | |
940 | |
941 mach64_wait_for_idle(); | |
942 mach64_fifo_wait(7); | |
943 | |
944 OUTREG(SCALER_BUF0_OFFSET, off[0]); | |
945 OUTREG(SCALER_BUF0_OFFSET_U, off[1]); | |
946 OUTREG(SCALER_BUF0_OFFSET_V, off[2]); | |
947 OUTREG(SCALER_BUF1_OFFSET, off[3]); | |
948 OUTREG(SCALER_BUF1_OFFSET_U, off[4]); | |
949 OUTREG(SCALER_BUF1_OFFSET_V, off[5]); | |
950 if(num_mach64_buffers==2) mach64_wait_vsync(); //only wait for vsync if we do double buffering | |
951 | |
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952 if(verbosity > VERBOSE_LEVEL) mach64_vid_dump_regs(); |
22850 | 953 return 0; |
954 } | |
955 | |
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956 static vidix_video_eq_t equal = |
22850 | 957 { |
958 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | |
959 , | |
960 0, 0, 0, 0, 0, 0, 0, 0 }; | |
961 | |
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962 static int mach64_get_eq( vidix_video_eq_t * eq) |
22850 | 963 { |
964 memcpy(eq,&equal,sizeof(vidix_video_eq_t)); | |
965 return 0; | |
966 } | |
967 | |
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968 static int mach64_set_eq( const vidix_video_eq_t * eq) |
22850 | 969 { |
970 int br,sat; | |
971 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; | |
972 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; | |
973 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; | |
974 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; | |
975 if(eq->cap & VEQ_CAP_RGB_INTENSITY) | |
976 { | |
977 equal.red_intensity = eq->red_intensity; | |
978 equal.green_intensity = eq->green_intensity; | |
979 equal.blue_intensity = eq->blue_intensity; | |
980 } | |
981 equal.flags = eq->flags; | |
982 br = equal.brightness * 64 / 1000; | |
983 if(br < -64) br = -64; if(br > 63) br = 63; | |
984 sat = (equal.saturation + 1000) * 16 / 1000; | |
985 if(sat < 0) sat = 0; if(sat > 31) sat = 31; | |
986 OUTREG(SCALER_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); | |
987 return 0; | |
988 } | |
989 | |
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990 static int mach64_get_gkeys(vidix_grkey_t *grkey) |
22850 | 991 { |
992 memcpy(grkey, &mach64_grkey, sizeof(vidix_grkey_t)); | |
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993 return 0; |
22850 | 994 } |
995 | |
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996 static int mach64_set_gkeys(const vidix_grkey_t *grkey) |
22850 | 997 { |
998 memcpy(&mach64_grkey, grkey, sizeof(vidix_grkey_t)); | |
999 | |
1000 if(mach64_grkey.ckey.op == CKEY_TRUE) | |
1001 { | |
1002 besr.ckey_on=1; | |
1003 | |
1004 switch(mach64_vid_get_dbpp()) | |
1005 { | |
1006 case 15: | |
1007 besr.graphics_key_msk=0x7FFF; | |
1008 besr.graphics_key_clr= | |
1009 ((mach64_grkey.ckey.blue &0xF8)>>3) | |
1010 | ((mach64_grkey.ckey.green&0xF8)<<2) | |
1011 | ((mach64_grkey.ckey.red &0xF8)<<7); | |
1012 break; | |
1013 case 16: | |
1014 besr.graphics_key_msk=0xFFFF; | |
1015 besr.graphics_key_clr= | |
1016 ((mach64_grkey.ckey.blue &0xF8)>>3) | |
1017 | ((mach64_grkey.ckey.green&0xFC)<<3) | |
1018 | ((mach64_grkey.ckey.red &0xF8)<<8); | |
1019 //besr.graphics_key_clr=le2me_32(besr.graphics_key_clr); | |
1020 break; | |
1021 case 24: | |
1022 besr.graphics_key_msk=0xFFFFFF; | |
1023 besr.graphics_key_clr= | |
1024 ((mach64_grkey.ckey.blue &0xFF)) | |
1025 | ((mach64_grkey.ckey.green&0xFF)<<8) | |
1026 | ((mach64_grkey.ckey.red &0xFF)<<16); | |
1027 break; | |
1028 case 32: | |
1029 besr.graphics_key_msk=0xFFFFFF; | |
1030 besr.graphics_key_clr= | |
1031 ((mach64_grkey.ckey.blue &0xFF)) | |
1032 | ((mach64_grkey.ckey.green&0xFF)<<8) | |
1033 | ((mach64_grkey.ckey.red &0xFF)<<16); | |
1034 break; | |
1035 default: | |
1036 besr.ckey_on=0; | |
1037 besr.graphics_key_msk=0; | |
1038 besr.graphics_key_clr=0; | |
1039 } | |
1040 } | |
1041 else | |
1042 { | |
1043 besr.ckey_on=0; | |
1044 besr.graphics_key_msk=0; | |
1045 besr.graphics_key_clr=0; | |
1046 } | |
1047 | |
1048 mach64_fifo_wait(4); | |
1049 OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk); | |
1050 OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1051 // OUTREG(OVERLAY_VIDEO_KEY_MSK, 0); | |
1052 // OUTREG(OVERLAY_VIDEO_KEY_CLR, 0); | |
1053 if(besr.ckey_on) | |
1054 OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND); | |
1055 else | |
1056 OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND); | |
1057 | |
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1058 return 0; |
22850 | 1059 } |
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1060 |
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1061 VDXDriver mach64_drv = { |
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1062 "mach64", |
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1063 NULL, |
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1064 .probe = mach64_probe, |
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1065 .get_caps = mach64_get_caps, |
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1066 .query_fourcc = mach64_query_fourcc, |
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1067 .init = mach64_init, |
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1068 .destroy = mach64_destroy, |
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1069 .config_playback = mach64_config_playback, |
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1070 .playback_on = mach64_playback_on, |
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1071 .playback_off = mach64_playback_off, |
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1072 .frame_sel = mach64_frame_sel, |
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1073 .get_eq = mach64_get_eq, |
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1074 .set_eq = mach64_set_eq, |
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1075 .get_gkey = mach64_get_gkeys, |
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1076 .set_gkey = mach64_set_gkeys, |
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1077 }; |