Mercurial > mplayer.hg
annotate vidix/nvidia_vid.c @ 23035:e8afcfccf359
Always deallocate glyphs. Fixes a memory leak.
author | eugeni |
---|---|
date | Sat, 21 Apr 2007 10:56:28 +0000 |
parents | 82be993061f4 |
children | 82216ef041e0 |
rev | line source |
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22850 | 1 /* |
2 nvidia_vid - VIDIX based video driver for NVIDIA chips | |
3 Copyrights 2003 - 2004 Sascha Sommer. This file is based on sources from | |
4 RIVATV (rivatv.sf.net) | |
5 Licence: GPL | |
6 WARNING: THIS DRIVER IS IN BETA STAGE | |
7 | |
8 multi buffer support and TNT2 fixes by Dmitry Baryshkov | |
9 */ | |
10 | |
11 | |
12 #include <errno.h> | |
13 #include <stdio.h> | |
14 #include <stdlib.h> | |
15 #include <string.h> | |
16 #include <math.h> | |
17 #include <inttypes.h> | |
18 #include <unistd.h> | |
19 | |
20 | |
21 #include "vidix.h" | |
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22 #include "vidixlib.h" |
22850 | 23 #include "fourcc.h" |
22901 | 24 #include "dha.h" |
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25 #include "pci_ids.h" |
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26 #include "pci_names.h" |
22905 | 27 #include "config.h" |
28 #include "libavutil/common.h" | |
29 #include "mpbswap.h" | |
22850 | 30 |
31 | |
32 pciinfo_t pci_info; | |
33 | |
34 | |
35 #define MAX_FRAMES 3 | |
36 #define NV04_BES_SIZE 1024*2000*4 | |
37 | |
38 | |
39 static vidix_capability_t nvidia_cap = { | |
40 "NVIDIA RIVA OVERLAY DRIVER", | |
41 "Sascha Sommer <saschasommer@freenet.de>", | |
42 TYPE_OUTPUT, | |
43 { 0, 0, 0, 0 }, | |
44 2046, | |
45 2046, | |
46 4, | |
47 4, | |
48 -1, | |
49 FLAG_UPSCALER|FLAG_DOWNSCALER, | |
50 VENDOR_NVIDIA2, | |
51 -1, | |
52 { 0, 0, 0, 0 } | |
53 }; | |
54 | |
55 #define NV_ARCH_03 0x03 | |
56 #define NV_ARCH_04 0x04 | |
57 #define NV_ARCH_10 0x10 | |
58 #define NV_ARCH_20 0x20 | |
59 #define NV_ARCH_30 0x30 | |
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60 #define NV_ARCH_40 0x40 |
22850 | 61 |
62 // since no useful information whatsoever is passed | |
63 // to the equalizer functions we need this | |
64 static struct { | |
65 uint32_t lum; // luminance (brightness + contrast) | |
66 uint32_t chrom; // chrominance (saturation + hue) | |
67 uint8_t red_off; // for NV03/NV04 | |
68 uint8_t green_off; | |
69 uint8_t blue_off; | |
70 vidix_video_eq_t vals; | |
71 } eq; | |
72 | |
73 struct nvidia_cards { | |
74 unsigned short chip_id; | |
75 unsigned short arch; | |
76 }; | |
77 | |
78 | |
79 static struct nvidia_cards nvidia_card_ids[] = { | |
80 /*NV03*/ | |
81 {DEVICE_NVIDIA2_RIVA128, NV_ARCH_03}, | |
82 {DEVICE_NVIDIA2_RIVA128ZX,NV_ARCH_03}, | |
83 /*NV04*/ | |
84 {DEVICE_NVIDIA_NV4_RIVA_TNT,NV_ARCH_04}, | |
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85 {DEVICE_NVIDIA_NV5_RIVA_TNT2_TNT2,NV_ARCH_04}, |
22850 | 86 {DEVICE_NVIDIA_NV5_RIVA_TNT2,NV_ARCH_04}, |
87 {DEVICE_NVIDIA_NV5_RIVA_TNT22,NV_ARCH_04}, | |
88 {DEVICE_NVIDIA_NV5_RIVA_TNT23,NV_ARCH_04}, | |
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89 {DEVICE_NVIDIA_NV6_VANTA_VANTA_LT,NV_ARCH_04}, |
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90 {DEVICE_NVIDIA_NV5M64_RIVA_TNT2,NV_ARCH_04}, |
22850 | 91 {DEVICE_NVIDIA_NV6_VANTA,NV_ARCH_04}, |
92 {DEVICE_NVIDIA_NV6_VANTA2,NV_ARCH_04}, | |
93 {DEVICE_NVIDIA2_TNT,NV_ARCH_04}, | |
94 {DEVICE_NVIDIA2_TNT2,NV_ARCH_04}, | |
95 {DEVICE_NVIDIA2_VTNT2,NV_ARCH_04}, | |
96 {DEVICE_NVIDIA2_UTNT2 ,NV_ARCH_04}, | |
97 {DEVICE_NVIDIA2_ITNT2,NV_ARCH_04}, | |
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98 {DEVICE_NVIDIA_NV5_ALADDIN_TNT2,NV_ARCH_04}, |
22850 | 99 /*NV10*/ |
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100 {DEVICE_NVIDIA_NV18_GEFORCE_PCX,NV_ARCH_10}, |
22850 | 101 {DEVICE_NVIDIA_NV10_GEFORCE_256,NV_ARCH_10}, |
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102 {DEVICE_NVIDIA_NV10DDR_GEFORCE_256,NV_ARCH_10}, |
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103 {DEVICE_NVIDIA_NV10GL_QUADRO,NV_ARCH_10}, |
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104 {DEVICE_NVIDIA_NV11_GEFORCE2_MX_MX,NV_ARCH_10}, |
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105 {DEVICE_NVIDIA_NV11DDR_GEFORCE2_MX,NV_ARCH_10}, |
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106 {DEVICE_NVIDIA_NV11DDR_GEFORCE2_MX,NV_ARCH_10}, |
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107 {DEVICE_NVIDIA_NV11_GEFORCE2_GO,NV_ARCH_10}, |
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108 {DEVICE_NVIDIA_NV11GL_QUADRO2_MXR_EX_GO,NV_ARCH_10}, |
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109 {DEVICE_NVIDIA_NV15_GEFORCE2_GTS_PRO,NV_ARCH_10}, |
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110 {DEVICE_NVIDIA_NV15DDR_GEFORCE2_TI,NV_ARCH_10}, |
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111 {DEVICE_NVIDIA_NV15BR_GEFORCE2_ULTRA,NV_ARCH_10}, |
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112 {DEVICE_NVIDIA_NV15GL_QUADRO2_PRO,NV_ARCH_10}, |
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113 {DEVICE_NVIDIA_NV17_GEFORCE4_MX,NV_ARCH_10}, |
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114 {DEVICE_NVIDIA_NV17_GEFORCE4_MX2,NV_ARCH_10}, |
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115 {DEVICE_NVIDIA_NV17_GEFORCE4_MX3,NV_ARCH_10}, |
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116 {DEVICE_NVIDIA_NV17_GEFORCE4_MX4,NV_ARCH_10}, |
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117 {DEVICE_NVIDIA_NV17_GEFORCE4_440,NV_ARCH_10}, |
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118 {DEVICE_NVIDIA_NV17_GEFORCE4_420,NV_ARCH_10}, |
22850 | 119 {DEVICE_NVIDIA_NV17_GEFORCE4_4202,NV_ARCH_10}, |
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120 {DEVICE_NVIDIA_NV17_GEFORCE4_460,NV_ARCH_10}, |
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121 {DEVICE_NVIDIA_NV17GL_QUADRO4_550,NV_ARCH_10}, |
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122 {DEVICE_NVIDIA_NV17_GEFORCE4_4203,NV_ARCH_10}, |
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123 {DEVICE_NVIDIA_NV17GL_QUADRO4_200_400,NV_ARCH_10}, |
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124 {DEVICE_NVIDIA_NV17GL_QUADRO4_5502,NV_ARCH_10}, |
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125 {DEVICE_NVIDIA_NV17GL_QUADRO4_550,NV_ARCH_10}, |
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126 {DEVICE_NVIDIA_NV17_GEFORCE4_410,NV_ARCH_10}, |
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127 {DEVICE_NVIDIA_NV18_GEFORCE4_MX,NV_ARCH_10}, |
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128 {DEVICE_NVIDIA_NV18_GEFORCE4_MX2,NV_ARCH_10}, |
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129 {DEVICE_NVIDIA_NV18_GEFORCE4_MX3,NV_ARCH_10}, |
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130 {DEVICE_NVIDIA_NV18_GEFORCE4_MX4,NV_ARCH_10}, |
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131 {DEVICE_NVIDIA_NV18_GEFORCE4_MX5,NV_ARCH_10}, |
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132 {DEVICE_NVIDIA_NV18M_GEFORCE4_448,NV_ARCH_10}, |
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133 {DEVICE_NVIDIA_NV18M_GEFORCE4_488,NV_ARCH_10}, |
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134 {DEVICE_NVIDIA_NV18GL_QUADRO_FX,NV_ARCH_10}, |
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135 {DEVICE_NVIDIA_NV18GL_QUADRO4_580,NV_ARCH_10}, |
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136 {DEVICE_NVIDIA_NV18GL_QUADRO4_NVS,NV_ARCH_10}, |
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137 {DEVICE_NVIDIA_NV18GL_QUADRO4_380,NV_ARCH_10}, |
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138 {DEVICE_NVIDIA_NV18M_GEFORCE4_4482,NV_ARCH_10}, |
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139 {DEVICE_NVIDIA_NVCRUSH11_GEFORCE2_MX,NV_ARCH_10}, |
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140 {DEVICE_NVIDIA_NV18_GEFORCE4_MX5,NV_ARCH_10}, |
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141 {DEVICE_NVIDIA_NV18_GEFORCE_PCX,NV_ARCH_10}, |
22850 | 142 /*NV20*/ |
143 {DEVICE_NVIDIA_NV20_GEFORCE3,NV_ARCH_20}, | |
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144 {DEVICE_NVIDIA_NV20_GEFORCE3_TI,NV_ARCH_20}, |
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145 {DEVICE_NVIDIA_NV20_GEFORCE3_TI2,NV_ARCH_20}, |
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146 {DEVICE_NVIDIA_NV20DCC_QUADRO_DCC,NV_ARCH_20}, |
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147 {DEVICE_NVIDIA_NV25_GEFORCE4_TI,NV_ARCH_20}, |
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148 {DEVICE_NVIDIA_NV25_GEFORCE4_TI2,NV_ARCH_20}, |
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149 {DEVICE_NVIDIA_NV25_GEFORCE4_TI3,NV_ARCH_20}, |
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150 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4,NV_ARCH_20}, |
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151 {DEVICE_NVIDIA_NV25GL_QUADRO4_900,NV_ARCH_20}, |
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152 {DEVICE_NVIDIA_NV25GL_QUADRO4_750,NV_ARCH_20}, |
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153 {DEVICE_NVIDIA_NV25GL_QUADRO4_700,NV_ARCH_20}, |
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154 {DEVICE_NVIDIA_NV28_GEFORCE4_TI,NV_ARCH_20}, |
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155 {DEVICE_NVIDIA_NV28_GEFORCE4_TI2,NV_ARCH_20}, |
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156 {DEVICE_NVIDIA_NV28_GEFORCE4_TI3,NV_ARCH_20}, |
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157 {DEVICE_NVIDIA_NV28_GEFORCE4_TI4,NV_ARCH_20}, |
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158 {DEVICE_NVIDIA_NV28GL_QUADRO4_980,NV_ARCH_20}, |
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159 {DEVICE_NVIDIA_NV28GL_QUADRO4_780,NV_ARCH_20}, |
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160 {DEVICE_NVIDIA_NV28GLM_QUADRO4_700,NV_ARCH_20}, |
22850 | 161 /*NV30*/ |
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162 {DEVICE_NVIDIA_NV30_GEFORCE_FX,NV_ARCH_30}, |
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163 {DEVICE_NVIDIA_NV30_GEFORCE_FX2,NV_ARCH_30}, |
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164 {DEVICE_NVIDIA_NV30_GEFORCE_FX3,NV_ARCH_30}, |
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165 {DEVICE_NVIDIA_NV30GL_QUADRO_FX,NV_ARCH_30}, |
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166 {DEVICE_NVIDIA_NV30GL_QUADRO_FX2,NV_ARCH_30}, |
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167 {DEVICE_NVIDIA_NV31_GEFORCE_FX,NV_ARCH_30}, |
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168 {DEVICE_NVIDIA_NV31_GEFORCE_FX2,NV_ARCH_30}, |
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169 {DEVICE_NVIDIA_NV31,NV_ARCH_30}, |
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170 {DEVICE_NVIDIA_NV31_GEFORCE_FX3,NV_ARCH_30}, |
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171 {DEVICE_NVIDIA_NV31M,NV_ARCH_30}, |
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172 {DEVICE_NVIDIA_NV31M_PRO,NV_ARCH_30}, |
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173 {DEVICE_NVIDIA_NV31M_GEFORCE_FX,NV_ARCH_30}, |
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174 {DEVICE_NVIDIA_NV31M_GEFORCE_FX2,NV_ARCH_30}, |
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175 {DEVICE_NVIDIA_NVIDIA_QUADRO_FX,NV_ARCH_30}, |
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176 {DEVICE_NVIDIA_NV31GLM,NV_ARCH_30}, |
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177 {DEVICE_NVIDIA_NV31GLM_PRO,NV_ARCH_30}, |
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178 {DEVICE_NVIDIA_NV31GLM_PRO2,NV_ARCH_30}, |
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changeset
|
179 {DEVICE_NVIDIA_NV34_GEFORCE_FX,NV_ARCH_30}, |
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180 {DEVICE_NVIDIA_NV34_GEFORCE_FX2,NV_ARCH_30}, |
22850 | 181 {DEVICE_NVIDIA_NV34_GEFORCE_FX3,NV_ARCH_30}, |
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|
182 {DEVICE_NVIDIA_NV34_GEFORCE_FX4,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
183 {DEVICE_NVIDIA_NV34M_GEFORCE_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
184 {DEVICE_NVIDIA_NV34M_GEFORCE_FX2,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
185 {DEVICE_NVIDIA_NV34_GEFORCE_FX5,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
186 {DEVICE_NVIDIA_NV34_GEFORCE_FX6,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
187 {DEVICE_NVIDIA_NV34M_GEFORCE_FX3,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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diff
changeset
|
188 {DEVICE_NVIDIA_NV34M_GEFORCE_FX4,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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diff
changeset
|
189 {DEVICE_NVIDIA_NV34GL_QUADRO_NVS,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
190 {DEVICE_NVIDIA_NV34GL_QUADRO_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
191 {DEVICE_NVIDIA_NV34GLM_GEFORCE_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
192 {DEVICE_NVIDIA_NV34_GEFORCE_FX7,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
193 {DEVICE_NVIDIA_NV34GL,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
194 {DEVICE_NVIDIA_NV35_GEFORCE_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
195 {DEVICE_NVIDIA_NV35_GEFORCE_FX2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
196 {DEVICE_NVIDIA_NV35_GEFORCE_FX3,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
197 {DEVICE_NVIDIA_NV38_GEFORCE_FX,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
198 {DEVICE_NVIDIA_NV35_GEFORCE_FX4,NV_ARCH_30}, |
22850 | 199 {DEVICE_NVIDIA_NV35GL_QUADRO_FX,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
200 {DEVICE_NVIDIA_NV35GL_QUADRO_FX2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
201 {DEVICE_NVIDIA_NV35_GEFORCE_PCX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
202 {DEVICE_NVIDIA_NV36_1_GEFORCE_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
203 {DEVICE_NVIDIA_NV36_2_GEFORCE_FX,NV_ARCH_30}, |
22850 | 204 {DEVICE_NVIDIA_NV36_GEFORCE_FX,NV_ARCH_30}, |
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updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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changeset
|
205 {DEVICE_NVIDIA_NV36_4_GEFORCE_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
206 {DEVICE_NVIDIA_NV36_5,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
207 {DEVICE_NVIDIA_NV36_GEFORCE_FX2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
208 {DEVICE_NVIDIA_NV36_GEFORCE_FX3,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
209 {DEVICE_NVIDIA_NV36_GEFORCE_PCX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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changeset
|
210 {DEVICE_NVIDIA_NV36M_PRO,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
211 {DEVICE_NVIDIA_NV36MAP,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
212 {DEVICE_NVIDIA_NV36_QUADRO_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
213 {DEVICE_NVIDIA_NV36GL_QUADRO_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
214 {DEVICE_NVIDIA_NV36GL,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
ben
parents:
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diff
changeset
|
215 {DEVICE_NVIDIA_NV36_GEFORCE_PCX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
216 {DEVICE_NVIDIA_NV35_GEFORCE_PCX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
217 {DEVICE_NVIDIA_NV37GL_QUADRO_FX,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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diff
changeset
|
218 {DEVICE_NVIDIA_NV37GL_QUADRO_FX2,NV_ARCH_30}, |
9a8f6901e888
updated pci ids list, fixed vidix drivers compilation and added nearly exhaustive pci ids for nvidia driver
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parents:
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|
219 {DEVICE_NVIDIA_NV38GL_QUADRO_FX,NV_ARCH_30}, |
22880
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
220 /* NV40: GeForce 6x00 to 7x00 */ |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
221 {DEVICE_NVIDIA_NV40_GEFORCE_6800,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
222 {DEVICE_NVIDIA_NV40_GEFORCE_68002,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
223 {DEVICE_NVIDIA_NV40_2_GEFORCE_6800,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
224 {DEVICE_NVIDIA_NV40_3,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
225 {DEVICE_NVIDIA_NV40_GEFORCE_68003,NV_ARCH_40}, |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
226 {DEVICE_NVIDIA_NV40_GEFORCE_68004,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
227 {DEVICE_NVIDIA_NV40_GEFORCE_68005,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
228 {DEVICE_NVIDIA_NV40_GEFORCE_68006,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
229 {DEVICE_NVIDIA_NV40_GEFORCE_68007,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
230 {DEVICE_NVIDIA_NV40_GEFORCE_68008,NV_ARCH_40}, |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
231 {DEVICE_NVIDIA_NV40_GEFORCE_68009,NV_ARCH_40}, |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
232 {DEVICE_NVIDIA_NV40_GEFORCE_680010,NV_ARCH_40}, |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
233 {DEVICE_NVIDIA_NV40_GEFORCE_680011,NV_ARCH_40}, |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
234 {DEVICE_NVIDIA_NV40_GEFORCE_680012,NV_ARCH_40}, |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
235 {DEVICE_NVIDIA_NV40_GEFORCE_68008,NV_ARCH_40}, |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
236 {DEVICE_NVIDIA_NV40GL,NV_ARCH_40}, |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
237 {DEVICE_NVIDIA_NV40GL_QUADRO_FX,NV_ARCH_40}, |
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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
238 {DEVICE_NVIDIA_NV40GL_QUADRO_FX2,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
239 {DEVICE_NVIDIA_NV41_GEFORCE_6800,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
240 {DEVICE_NVIDIA_NV41_1_GEFORCE_6800,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
241 {DEVICE_NVIDIA_NV41_2_GEFORCE_6800,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
242 {DEVICE_NVIDIA_NV41_8_GEFORCE_GO,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
243 {DEVICE_NVIDIA_NV41_9_GEFORCE_GO,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
244 {DEVICE_NVIDIA_NV41_QUADRO_FX,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
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|
245 {DEVICE_NVIDIA_NV41_QUADRO_FX2,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
246 {DEVICE_NVIDIA_NV41GL_QUADRO_FX,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
247 {DEVICE_NVIDIA_NV41GL_QUADRO_FX,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
248 {DEVICE_NVIDIA_NV40_GEFORCE_6800_GEFORCE,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
249 {DEVICE_NVIDIA_NV43_GEFORCE_6600_GEFORCE,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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changeset
|
250 {DEVICE_NVIDIA_NV43_GEFORCE_6600_GEFORCE2,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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changeset
|
251 {DEVICE_NVIDIA_NV43_GEFORCE_6200,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
252 {DEVICE_NVIDIA_NV43_GEFORCE_62002,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
253 {DEVICE_NVIDIA_NV43_GEFORCE_6600,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
254 {DEVICE_NVIDIA_NV43_GEFORCE_66002,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
255 {DEVICE_NVIDIA_NV43_GEFORCE_66003,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
256 {DEVICE_NVIDIA_NV43_GEFORCE_66004,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
257 {DEVICE_NVIDIA_NV43_GEFORCE_66005,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
258 {DEVICE_NVIDIA_NV43_GEFORCE_GO,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
259 {DEVICE_NVIDIA_NV43_GEFORCE_GO2,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
260 {DEVICE_NVIDIA_NV43_GEFORCE_GO3,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
261 {DEVICE_NVIDIA_NV43_GEFORCE_GO4,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
262 {DEVICE_NVIDIA_NV43_GEFORCE_GO5,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
263 {DEVICE_NVIDIA_NV43_GEFORCE_GO6,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
264 {DEVICE_NVIDIA_NV43_GEFORCE_6610,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
265 {DEVICE_NVIDIA_NV43GL_QUADRO_FX,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
266 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
267 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE2,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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|
268 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE3,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
269 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE4,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
270 {DEVICE_NVIDIA_C51G_GEFORCE_6100,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
271 {DEVICE_NVIDIA_C51PV_GEFORCE_6150,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
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diff
changeset
|
272 {DEVICE_NVIDIA_NV44_GEFORCE_6200,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
273 {DEVICE_NVIDIA_NV44_GEFORCE_62002,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
274 {DEVICE_NVIDIA_NV44_GEFORCE_62003,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
275 {DEVICE_NVIDIA_NV44_GEFORCE_GO,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
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changeset
|
276 {DEVICE_NVIDIA_NV44_QUADRO_NVS,NV_ARCH_40}, |
8b0cfdc71759
GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
ben
parents:
22874
diff
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277 {DEVICE_NVIDIA_GEFORCE_GO_6200,NV_ARCH_40}, |
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278 {DEVICE_NVIDIA_NV44A_GEFORCE_6200,NV_ARCH_40}, |
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279 {DEVICE_NVIDIA_NV45GL_QUADRO_FX,NV_ARCH_40}, |
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280 {DEVICE_NVIDIA_GEFORCE_GO_7200,NV_ARCH_40}, |
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281 {DEVICE_NVIDIA_QUADRO_NVS_110M,NV_ARCH_40}, |
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282 {DEVICE_NVIDIA_GEFORCE_GO_7400,NV_ARCH_40}, |
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283 {DEVICE_NVIDIA_QUADRO_NVS_110M2,NV_ARCH_40}, |
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284 {DEVICE_NVIDIA_QUADRO_FX_350,NV_ARCH_40}, |
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285 {DEVICE_NVIDIA_G70_GEFORCE_7300,NV_ARCH_40}, |
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286 {DEVICE_NVIDIA_GEFORCE_7300_GS,NV_ARCH_40}, |
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287 {DEVICE_NVIDIA_G70_GEFORCE_7600,NV_ARCH_40}, |
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288 {DEVICE_NVIDIA_G70_GEFORCE_76002,NV_ARCH_40}, |
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289 {DEVICE_NVIDIA_GEFORCE_7600_GS,NV_ARCH_40}, |
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290 {DEVICE_NVIDIA_G70_GEFORCE_GO,NV_ARCH_40}, |
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291 {DEVICE_NVIDIA_QUADRO_FX_560,NV_ARCH_40}, |
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292 {DEVICE_NVIDIA_G70_GEFORCE_7800,NV_ARCH_40}, |
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293 {DEVICE_NVIDIA_G70_GEFORCE_78002,NV_ARCH_40}, |
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294 {DEVICE_NVIDIA_G70_GEFORCE_78003,NV_ARCH_40}, |
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295 {DEVICE_NVIDIA_G70_GEFORCE_78004,NV_ARCH_40}, |
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296 {DEVICE_NVIDIA_G70_GEFORCE_78005,NV_ARCH_40}, |
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297 {DEVICE_NVIDIA_GEFORCE_GO_7800,NV_ARCH_40}, |
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298 {DEVICE_NVIDIA_GEFORCE_7900_GTX,NV_ARCH_40}, |
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299 {DEVICE_NVIDIA_GEFORCE_7900_GT,NV_ARCH_40}, |
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300 {DEVICE_NVIDIA_GEFORCE_7900_GS,NV_ARCH_40}, |
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301 {DEVICE_NVIDIA_GEFORCE_GO_7900,NV_ARCH_40}, |
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302 {DEVICE_NVIDIA_GEFORCE_GO_79002,NV_ARCH_40}, |
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303 {DEVICE_NVIDIA_GE_FORCE_GO,NV_ARCH_40}, |
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304 {DEVICE_NVIDIA_G70GL_QUADRO_FX4500,NV_ARCH_40}, |
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305 {DEVICE_NVIDIA_G71_QUADRO_FX,NV_ARCH_40}, |
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306 {DEVICE_NVIDIA_G71_QUADRO_FX2,NV_ARCH_40} |
22850 | 307 }; |
308 | |
309 | |
310 static int find_chip(unsigned chip_id){ | |
311 unsigned i; | |
312 for(i = 0;i < sizeof(nvidia_card_ids)/sizeof(struct nvidia_cards);i++) | |
313 { | |
314 if(chip_id == nvidia_card_ids[i].chip_id)return i; | |
315 } | |
316 return -1; | |
317 } | |
318 | |
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319 static int nv_probe(int verbose, int force){ |
22850 | 320 pciinfo_t lst[MAX_PCI_DEVICES]; |
321 unsigned i,num_pci; | |
322 int err; | |
323 | |
324 if (force) | |
325 printf("[nvidia_vid]: warning: forcing not supported yet!\n"); | |
326 err = pci_scan(lst,&num_pci); | |
327 if(err){ | |
328 printf("[nvidia_vid] Error occurred during pci scan: %s\n",strerror(err)); | |
329 return err; | |
330 } | |
331 else { | |
332 err = ENXIO; | |
333 for(i=0; i < num_pci; i++){ | |
334 if(lst[i].vendor == VENDOR_NVIDIA2 || lst[i].vendor == VENDOR_NVIDIA){ | |
335 int idx; | |
336 const char *dname; | |
337 idx = find_chip(lst[i].device); | |
338 if(idx == -1) | |
339 continue; | |
340 dname = pci_device_name(lst[i].vendor, lst[i].device); | |
341 dname = dname ? dname : "Unknown chip"; | |
342 printf("[nvidia_vid] Found chip: %s\n", dname); | |
343 if ((lst[i].command & PCI_COMMAND_IO) == 0){ | |
344 printf("[nvidia_vid] Device is disabled, ignoring\n"); | |
345 continue; | |
346 } | |
347 nvidia_cap.device_id = lst[i].device; | |
348 err = 0; | |
349 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); | |
350 break; | |
351 } | |
352 } | |
353 } | |
354 if(err && verbose) printf("[nvidia_vid] Can't find chip\n"); | |
355 return err; | |
356 } | |
357 | |
358 | |
359 | |
360 | |
361 /* | |
362 * PCI-Memory IO access macros. | |
363 */ | |
364 | |
365 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") | |
366 | |
367 #undef VID_WR08 | |
368 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) | |
369 #undef VID_RD08 | |
370 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) | |
371 | |
372 #undef VID_WR32 | |
373 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=val; }) | |
374 #undef VID_RD32 | |
375 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) | |
376 | |
377 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) | |
378 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) | |
379 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) | |
380 | |
381 | |
382 | |
383 | |
384 | |
385 | |
386 struct rivatv_chip { | |
387 volatile uint32_t *PMC; /* general control */ | |
388 volatile uint32_t *PME; /* multimedia port */ | |
389 volatile uint32_t *PFB; /* framebuffer control */ | |
390 volatile uint32_t *PVIDEO; /* overlay control */ | |
391 volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ | |
392 volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ | |
393 volatile uint32_t *PRAMIN; /* instance memory */ | |
394 volatile uint32_t *PRAMHT; /* hash table */ | |
395 volatile uint32_t *PRAMFC; /* fifo context table */ | |
396 volatile uint32_t *PRAMRO; /* fifo runout table */ | |
397 volatile uint32_t *PFIFO; /* fifo control region */ | |
398 volatile uint32_t *FIFO; /* fifo channels (USER) */ | |
399 volatile uint32_t *PGRAPH; /* graphics engine */ | |
400 | |
401 unsigned long fbsize; /* framebuffer size */ | |
402 int arch; /* compatible NV_ARCH_XX define */ | |
403 int realarch; /* real architecture */ | |
404 void (* lock) (struct rivatv_chip *, int); | |
405 }; | |
406 typedef struct rivatv_chip rivatv_chip; | |
407 | |
408 | |
409 struct rivatv_info { | |
410 unsigned int use_colorkey; | |
411 unsigned int colorkey; /* saved xv colorkey*/ | |
412 unsigned int vidixcolorkey; /*currently used colorkey*/ | |
413 unsigned int depth; | |
414 unsigned int format; | |
415 unsigned int pitch; | |
416 unsigned int width,height; | |
417 unsigned int d_width,d_height; /*scaled width && height*/ | |
418 unsigned int wx,wy; /*window x && y*/ | |
419 unsigned int screen_x; /*screen width*/ | |
420 unsigned int screen_y; /*screen height*/ | |
421 unsigned long buffer_size; /* size of the image buffer */ | |
422 struct rivatv_chip chip; /* NV architecture structure */ | |
423 void* video_base; /* virtual address of control region */ | |
424 void* control_base; /* virtual address of fb region */ | |
425 void* picture_base; /* direct pointer to video picture */ | |
426 unsigned long picture_offset; /* offset of video picture in frame buffer */ | |
427 // struct rivatv_dma dma; /* DMA structure */ | |
428 unsigned int cur_frame; | |
429 unsigned int num_frames; /* number of buffers */ | |
430 int bps; /* bytes per line */ | |
431 }; | |
432 typedef struct rivatv_info rivatv_info; | |
433 | |
434 //framebuffer size funcs | |
435 static unsigned long rivatv_fbsize_nv03 (struct rivatv_chip *chip){ | |
436 if (VID_RD32 (chip->PFB, 0) & 0x00000020) { | |
437 if (((VID_RD32 (chip->PMC, 0) & 0xF0) == 0x20) | |
438 && ((VID_RD32 (chip->PMC, 0) & 0x0F) >= 0x02)) { | |
439 /* SDRAM 128 ZX. */ | |
440 return ((1 << (VID_RD32 (chip->PFB, 0) & 0x03)) * 1024 * 1024); | |
441 } | |
442 else { | |
443 return 1024 * 1024 * 8; | |
444 } | |
445 } | |
446 else { | |
447 /* SGRAM 128. */ | |
448 switch (VID_RD32(chip->PFB, 0) & 0x00000003) { | |
449 case 0: | |
450 return 1024 * 1024 * 8; | |
451 break; | |
452 case 2: | |
453 return 1024 * 1024 * 4; | |
454 break; | |
455 default: | |
456 return 1024 * 1024 * 2; | |
457 break; | |
458 } | |
459 } | |
460 } | |
461 static unsigned long rivatv_fbsize_nv04 (struct rivatv_chip *chip){ | |
462 if (VID_RD32 (chip->PFB, 0) & 0x00000100) { | |
463 return ((VID_RD32 (chip->PFB, 0) >> 12) & 0x0F) * 1024 * 1024 * 2 | |
464 + 1024 * 1024 * 2; | |
465 } else { | |
466 switch (VID_RD32 (chip->PFB, 0) & 0x00000003) { | |
467 case 0: | |
468 return 1024 * 1024 * 32; | |
469 break; | |
470 case 1: | |
471 return 1024 * 1024 * 4; | |
472 break; | |
473 case 2: | |
474 return 1024 * 1024 * 8; | |
475 break; | |
476 case 3: | |
477 default: | |
478 return 1024 * 1024 * 16; | |
479 break; | |
480 } | |
481 } | |
482 } | |
483 | |
484 static unsigned long rivatv_fbsize_nv10 (struct rivatv_chip *chip){ | |
485 return VID_RD32 (chip->PFB, 0x20C) & 0xFFF00000; | |
486 } | |
487 | |
488 //lock funcs | |
489 static void rivatv_lock_nv03 (struct rivatv_chip *chip, int LockUnlock){ | |
490 VID_WR08 (chip->PVIO, 0x3C4, 0x06); | |
491 VID_WR08 (chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57); | |
492 } | |
493 | |
494 static void rivatv_lock_nv04 (struct rivatv_chip *chip, int LockUnlock){ | |
495 VID_WR08 (chip->PCIO, 0x3C4, 0x06); | |
496 VID_WR08 (chip->PCIO, 0x3C5, LockUnlock ? 0x99 : 0x57); | |
497 VID_WR08 (chip->PCIO, 0x3D4, 0x1F); | |
498 VID_WR08 (chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57); | |
499 } | |
500 | |
501 | |
502 | |
503 | |
504 /* Enable PFB (Framebuffer), PVIDEO (Overlay unit) and PME (Mediaport) if neccessary. */ | |
505 static void rivatv_enable_PMEDIA (struct rivatv_info *info){ | |
506 uint32_t reg; | |
507 | |
508 /* switch off interrupts once for a while */ | |
509 // VID_WR32 (info->chip.PME, 0x200140, 0x00); | |
510 // VID_WR32 (info->chip.PMC, 0x000140, 0x00); | |
511 | |
512 reg = VID_RD32 (info->chip.PMC, 0x000200); | |
513 | |
514 /* NV3 (0x10100010): NV03_PMC_ENABLE_PMEDIA, NV03_PMC_ENABLE_PFB, NV03_PMC_ENABLE_PVIDEO */ | |
515 | |
516 if ((reg & 0x10100010) != 0x10100010) { | |
517 printf("PVIDEO and PFB disabled, enabling...\n"); | |
518 VID_OR32 (info->chip.PMC, 0x000200, 0x10100010); | |
519 } | |
520 | |
521 /* save the current colorkey */ | |
522 switch (info->chip.arch ) { | |
523 case NV_ARCH_10: | |
524 case NV_ARCH_20: | |
525 case NV_ARCH_30: | |
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526 case NV_ARCH_40: |
22850 | 527 /* NV_PVIDEO_COLOR_KEY */ |
528 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0xB00); | |
529 break; | |
530 case NV_ARCH_03: | |
531 case NV_ARCH_04: | |
532 /* NV_PVIDEO_KEY */ | |
533 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0x240); | |
534 break; | |
535 } | |
536 | |
537 | |
538 /* re-enable interrupts again */ | |
539 // VID_WR32 (info->chip.PMC, 0x000140, 0x01); | |
540 // VID_WR32 (info->chip.PME, 0x200140, 0x01); | |
541 } | |
542 | |
543 /* Stop overlay video. */ | |
544 static void rivatv_overlay_stop (struct rivatv_info *info) { | |
545 switch (info->chip.arch ) { | |
546 case NV_ARCH_10: | |
547 case NV_ARCH_20: | |
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548 case NV_ARCH_30: |
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549 case NV_ARCH_40: |
22850 | 550 /* NV_PVIDEO_COLOR_KEY */ |
551 /* Xv-Extension-Hack: Restore previously saved value. */ | |
552 VID_WR32 (info->chip.PVIDEO, 0xB00, info->colorkey); | |
553 /* NV_PVIDEO_STOP */ | |
554 VID_OR32 (info->chip.PVIDEO, 0x704, 0x11); | |
555 /* NV_PVIDEO_BUFFER */ | |
556 VID_AND32 (info->chip.PVIDEO, 0x700, ~0x11); | |
557 /* NV_PVIDEO_INTR_EN_BUFFER */ | |
558 // VID_AND32 (info->chip.PVIDEO, 0x140, ~0x11); | |
559 break; | |
560 case NV_ARCH_03: | |
561 case NV_ARCH_04: | |
562 /* NV_PVIDEO_KEY */ | |
563 VID_WR32 (info->chip.PVIDEO, 0x240, info->colorkey); | |
564 /* NV_PVIDEO_OVERLAY_VIDEO_OFF */ | |
565 VID_AND32 (info->chip.PVIDEO, 0x244, ~0x01); | |
566 /* NV_PVIDEO_INTR_EN_0_NOTIFY */ | |
567 // VID_AND32 (info->chip.PVIDEO, 0x140, ~0x01); | |
568 /* NV_PVIDEO_OE_STATE */ | |
569 VID_WR32 (info->chip.PVIDEO, 0x224, 0); | |
570 /* NV_PVIDEO_SU_STATE */ | |
571 VID_WR32 (info->chip.PVIDEO, 0x228, 0); | |
572 /* NV_PVIDEO_RM_STATE */ | |
573 VID_WR32 (info->chip.PVIDEO, 0x22C, 0); | |
574 break; | |
575 } | |
576 } | |
577 | |
578 /* Get pan offset of the physical screen. */ | |
579 static uint32_t rivatv_overlay_pan (struct rivatv_info *info){ | |
580 uint32_t pan; | |
581 info->chip.lock (&info->chip, 0); | |
582 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0D); | |
583 pan = VID_RD08 (info->chip.PCIO, 0x3D5); | |
584 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0C); | |
585 pan |= VID_RD08 (info->chip.PCIO, 0x3D5) << 8; | |
586 VID_WR08 (info->chip.PCIO, 0x3D4, 0x19); | |
587 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x1F) << 16; | |
588 VID_WR08 (info->chip.PCIO, 0x3D4, 0x2D); | |
589 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x60) << 16; | |
590 return pan << 2; | |
591 } | |
592 | |
593 /* Compute and set colorkey depending on the colour depth. */ | |
594 static void rivatv_overlay_colorkey (rivatv_info* info, unsigned int chromakey){ | |
595 uint32_t r, g, b, key = 0; | |
596 | |
597 r = (chromakey & 0x00FF0000) >> 16; | |
598 g = (chromakey & 0x0000FF00) >> 8; | |
599 b = chromakey & 0x000000FF; | |
600 switch (info->depth) { | |
601 case 15: | |
602 key = ((r >> 3) << 10) | ((g >> 3) << 5) | ((b >> 3)); | |
603 #ifndef WIN32 | |
604 key = key | 0x00008000; | |
605 #endif | |
606 break; | |
607 case 16: // XXX unchecked | |
608 key = ((r >> 3) << 11) | ((g >> 2) << 5) | ((b >> 3)); | |
609 #ifndef WIN32 | |
610 key = key | 0x00008000; | |
611 #endif | |
612 break; | |
613 case 24: // XXX unchecked, maybe swap order of masking - FIXME Can the card be in 24 bit mode anyway? | |
614 key = (chromakey & 0x00FFFFFF) | 0x00800000; | |
615 break; | |
616 case 32: | |
617 key = chromakey; | |
618 #ifndef WIN32 | |
619 key = key | 0x80000000; | |
620 #endif | |
621 break; | |
622 } | |
623 //printf("[nvidia_vid] depth=%d %08X \n", info->depth, chromakey); | |
624 switch (info->chip.arch) { | |
625 case NV_ARCH_10: | |
626 case NV_ARCH_20: | |
627 case NV_ARCH_30: | |
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628 case NV_ARCH_40: |
22850 | 629 VID_WR32 (info->chip.PVIDEO, 0xB00, key); |
630 break; | |
631 case NV_ARCH_03: | |
632 case NV_ARCH_04: | |
633 VID_WR32 (info->chip.PVIDEO, 0x240, key); | |
634 break; | |
635 } | |
636 } | |
637 | |
638 static void nv_getscreenproperties(struct rivatv_info *info){ | |
639 uint32_t bpp=0,x; | |
640 info->chip.lock(&info->chip, 0); | |
641 /*get screen depth*/ | |
642 VID_WR08(info->chip.PCIO, 0x03D4,0x28); | |
643 bpp = VID_RD08(info->chip.PCIO,0x03D5)&0x3; | |
644 if((bpp == 2) && (VID_RD32(info->chip.PVIDEO,0x600) & 0x00001000) == 0x0)info->depth=15; | |
645 else info->depth = 0x04 << bpp; | |
646 /*get screen width*/ | |
647 VID_WR08(info->chip.PCIO, 0x03D4, 0x1); | |
648 info->screen_x = (1 + VID_RD08(info->chip.PCIO, 0x3D5)) * 8; | |
649 /*get screen height*/ | |
650 /* get first 8 bits in VT_DISPLAY_END*/ | |
651 VID_WR08(info->chip.PCIO, 0x03D4, 0x12); | |
652 info->screen_y = VID_RD08(info->chip.PCIO,0x03D5); | |
653 VID_WR08(info->chip.PCIO,0x03D4,0x07); | |
654 /* get 9th bit in CRTC_OVERFLOW*/ | |
655 info->screen_y |= (VID_RD08(info->chip.PCIO,0x03D5) &0x02)<<7; | |
656 /* and the 10th in CRTC_OVERFLOW*/ | |
657 info->screen_y |=(VID_RD08(info->chip.PCIO,0x03D5) &0x40)<<3; | |
658 ++info->screen_y; | |
659 | |
660 /* NV_PCRTC_OFFSET */ | |
661 VID_WR08 (info->chip.PCIO, 0x3D4, 0x13); | |
662 x = VID_RD08 (info->chip.PCIO, 0x3D5); | |
663 /* NV_PCRTC_REPAINT0_OFFSET_10_8 */ | |
664 VID_WR08 (info->chip.PCIO, 0x3D4, 0x19); | |
665 x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0xE0) << 3; | |
666 /* NV_PCRTC_EXTRA_OFFSET_11 */ | |
667 VID_WR08 (info->chip.PCIO, 0x3D4, 0x25); | |
668 x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x20) << 6; x <<= 3; | |
669 info->bps = x * bpp; | |
670 } | |
671 | |
672 | |
673 | |
674 | |
675 /* Start overlay video. */ | |
676 static void rivatv_overlay_start (struct rivatv_info *info,int bufno){ | |
677 uint32_t base, size, offset, xscale, yscale, pan; | |
678 uint32_t value; | |
679 int x=info->wx, y=info->wy; | |
680 int lwidth=info->d_width, lheight=info->d_height; | |
681 | |
682 size = info->buffer_size; | |
683 base = info->picture_offset; | |
684 offset = bufno*size; | |
685 /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/ | |
686 nv_getscreenproperties(info); | |
687 | |
688 if(info->depth){ | |
689 /* get pan offset of the physical screen */ | |
690 pan = rivatv_overlay_pan (info); | |
691 /* adjust window position depending on the pan offset */ | |
692 if (info->bps != 0) | |
693 { | |
694 x = info->wx - (pan % info->bps) * 8 / info->depth; | |
695 y = info->wy - (pan / info->bps); | |
696 } | |
697 } else { | |
698 // we can't adjust the window position correctly in textmode | |
699 // setting y to 8 seems to work ok, though | |
700 if(info->chip.arch < NV_ARCH_10 && y < 8) y = 8; | |
701 } | |
702 | |
703 /* adjust negative output window variables */ | |
704 if (x < 0) { | |
705 lwidth = info->d_width + x; | |
706 offset += (-x * info->width / info->d_width) << 1; | |
707 // offset += (-window->x * port->vld_width / window->width) << 1; | |
708 x = 0; | |
709 } | |
710 if (y < 0) { | |
711 lheight = info->d_height + y; | |
712 offset += (-y * info->height / info->d_height * info->width) << 1; | |
713 // offset += (-window->y * port->vld_height / window->height * port->org_width) << 1; | |
714 y = 0; | |
715 } | |
716 | |
717 switch (info->chip.arch) { | |
718 case NV_ARCH_10: | |
719 case NV_ARCH_20: | |
720 case NV_ARCH_30: | |
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721 case NV_ARCH_40: |
22850 | 722 |
723 /* NV_PVIDEO_BASE */ | |
724 VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base + offset); | |
725 //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base); | |
726 /* NV_PVIDEO_LIMIT */ | |
727 VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + offset + size - 1); | |
728 //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1); | |
729 | |
730 /* extra code for NV20 && NV30 architectures */ | |
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731 if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30 || info->chip.arch == NV_ARCH_40) { |
22850 | 732 VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base + offset); |
733 //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base); | |
734 VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + offset + size - 1); | |
735 //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1); | |
736 } | |
737 | |
738 /* NV_PVIDEO_LUMINANCE */ | |
739 VID_WR32 (info->chip.PVIDEO, 0x910 + 0, eq.lum); | |
740 //VID_WR32 (info->chip.PVIDEO, 0x910 + 4, 0x00001000); | |
741 /* NV_PVIDEO_CHROMINANCE */ | |
742 VID_WR32 (info->chip.PVIDEO, 0x918 + 0, eq.chrom); | |
743 //VID_WR32 (info->chip.PVIDEO, 0x918 + 4, 0x00001000); | |
744 | |
745 /* NV_PVIDEO_OFFSET */ | |
746 VID_WR32 (info->chip.PVIDEO, 0x920 + 0, 0x0); | |
747 //VID_WR32 (info->chip.PVIDEO, 0x920 + 4, offset + pitch); | |
748 /* NV_PVIDEO_SIZE_IN */ | |
749 VID_WR32 (info->chip.PVIDEO, 0x928 + 0, ((info->height) << 16) | info->width); | |
750 //VID_WR32 (info->chip.PVIDEO, 0x928 + 4, ((port->org_height/2) << 16) | port->org_width); | |
751 /* NV_PVIDEO_POINT_IN */ | |
752 VID_WR32 (info->chip.PVIDEO, 0x930 + 0, 0x00000000); | |
753 //VID_WR32 (info->chip.PVIDEO, 0x930 + 4, 0x00000000); | |
754 /* NV_PVIDEO_DS_DX_RATIO */ | |
755 VID_WR32 (info->chip.PVIDEO, 0x938 + 0, (info->width << 20) / info->d_width); | |
756 //VID_WR32 (info->chip.PVIDEO, 0x938 + 4, (port->org_width << 20) / window->width); | |
757 /* NV_PVIDEO_DT_DY_RATIO */ | |
758 VID_WR32 (info->chip.PVIDEO, 0x940 + 0, ((info->height) << 20) / info->d_height); | |
759 //VID_WR32 (info->chip.PVIDEO, 0x940 + 4, ((port->org_height/2) << 20) / window->height); | |
760 | |
761 /* NV_PVIDEO_POINT_OUT */ | |
762 VID_WR32 (info->chip.PVIDEO, 0x948 + 0, ((y + 0) << 16) | x); | |
763 //VID_WR32 (info->chip.PVIDEO, 0x948 + 4, ((y + 0) << 16) | x); | |
764 /* NV_PVIDEO_SIZE_OUT */ | |
765 VID_WR32 (info->chip.PVIDEO, 0x950 + 0, (lheight << 16) | lwidth); | |
766 //VID_WR32 (info->chip.PVIDEO, 0x950 + 4, (height << 16) | width); | |
767 | |
768 /* NV_PVIDEO_FORMAT */ | |
769 value = info->pitch; | |
770 if(info->use_colorkey)value |= 1 << 20; | |
771 if(info->format == IMGFMT_YUY2)value |= 1 << 16; | |
772 VID_WR32 (info->chip.PVIDEO, 0x958 + 0, value); | |
773 //VID_WR32 (info->chip.PVIDEO, 0x958 + 4, (pitch << 1) | 0x00100000); | |
774 | |
775 /* NV_PVIDEO_INTR_EN_BUFFER */ | |
776 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01/*0x11*/); | |
777 /* NV_PVIDEO_STOP */ | |
778 VID_WR32 (info->chip.PVIDEO, 0x704,0x0); | |
779 /* NV_PVIDEO_BUFFER */ | |
780 VID_WR32 (info->chip.PVIDEO, 0x700, 0x01/*0x11*/); | |
781 break; | |
782 | |
783 case NV_ARCH_03: | |
784 case NV_ARCH_04: | |
785 | |
786 | |
787 /* NV_PVIDEO_OE_STATE */ | |
788 VID_WR32 (info->chip.PVIDEO, 0x224, 0); | |
789 /* NV_PVIDEO_SU_STATE */ | |
790 VID_WR32 (info->chip.PVIDEO, 0x228, 0); | |
791 /* NV_PVIDEO_RM_STATE */ | |
792 VID_WR32 (info->chip.PVIDEO, 0x22C, 0); | |
793 | |
794 /* NV_PVIDEO_BUFF0_START_ADDRESS */ | |
795 VID_WR32 (info->chip.PVIDEO, 0x20C + 0, base + offset + 0); | |
796 VID_WR32 (info->chip.PVIDEO, 0x20C + 4, base + offset + 0); | |
797 /* NV_PVIDEO_BUFF0_PITCH_LENGTH */ | |
798 VID_WR32 (info->chip.PVIDEO, 0x214 + 0, info->pitch); | |
799 VID_WR32 (info->chip.PVIDEO, 0x214 + 4, info->pitch); | |
800 | |
801 /* NV_PVIDEO_WINDOW_START */ | |
802 VID_WR32 (info->chip.PVIDEO, 0x230, (y << 16) | x); | |
803 /* NV_PVIDEO_WINDOW_SIZE */ | |
804 VID_WR32 (info->chip.PVIDEO, 0x234, (lheight << 16) | lwidth); | |
805 /* NV_PVIDEO_STEP_SIZE */ | |
806 yscale = ((info->height - 1) << 11) / (info->d_height - 1); | |
807 xscale = ((info->width - 1) << 11) / (info->d_width - 1); | |
808 VID_WR32 (info->chip.PVIDEO, 0x200, (yscale << 16) | xscale); | |
809 | |
810 /* NV_PVIDEO_RED_CSC_OFFSET */ | |
811 VID_WR32 (info->chip.PVIDEO, 0x280, eq.red_off); | |
812 /* NV_PVIDEO_GREEN_CSC_OFFSET */ | |
813 VID_WR32 (info->chip.PVIDEO, 0x284, eq.green_off); | |
814 /* NV_PVIDEO_BLUE_CSC_OFFSET */ | |
815 VID_WR32 (info->chip.PVIDEO, 0x288, eq.blue_off); | |
816 /* NV_PVIDEO_CSC_ADJUST */ | |
817 VID_WR32 (info->chip.PVIDEO, 0x28C, 0x00000); /* No colour correction! */ | |
818 | |
819 /* NV_PVIDEO_CONTROL_Y (BLUR_ON, LINE_HALF) */ | |
820 VID_WR32 (info->chip.PVIDEO, 0x204, 0x001); | |
821 /* NV_PVIDEO_CONTROL_X (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */ | |
822 VID_WR32 (info->chip.PVIDEO, 0x208, 0x111); /*directx overlay 0x110 */ | |
823 | |
824 /* NV_PVIDEO_FIFO_BURST_LENGTH */ | |
825 VID_WR32 (info->chip.PVIDEO, 0x23C, 0x03); | |
826 /* NV_PVIDEO_FIFO_THRES_SIZE */ | |
827 VID_WR32 (info->chip.PVIDEO, 0x238, 0x38); /*windows uses 0x40*/ | |
828 | |
829 /* NV_PVIDEO_BUFF0_OFFSET */ | |
830 VID_WR32 (info->chip.PVIDEO, 0x21C + 0, 0); | |
831 VID_WR32 (info->chip.PVIDEO, 0x21C + 4, 0); | |
832 | |
833 /* NV_PVIDEO_INTR_EN_0_NOTIFY_ENABLED */ | |
834 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01); | |
835 | |
836 /* NV_PVIDEO_OVERLAY (KEY_ON, VIDEO_ON, FORMAT_CCIR) */ | |
837 value = 0x1; /*video on*/ | |
838 if(info->format==IMGFMT_YUY2)value |= 0x100; | |
839 if(info->use_colorkey)value |=0x10; | |
840 VID_WR32 (info->chip.PVIDEO, 0x244, value); | |
841 | |
842 /* NV_PVIDEO_SU_STATE */ | |
843 VID_XOR32 (info->chip.PVIDEO, 0x228, 1 << 16); | |
844 break; | |
845 } | |
846 /*set colorkey*/ | |
847 rivatv_overlay_colorkey(info,info->vidixcolorkey); | |
848 | |
849 } | |
850 | |
851 | |
852 | |
853 | |
854 | |
855 | |
856 | |
857 static rivatv_info* info; | |
858 | |
859 | |
860 | |
861 | |
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862 static int nv_init(void){ |
22850 | 863 int mtrr; |
864 info = calloc(1,sizeof(rivatv_info)); | |
865 info->control_base = map_phys_mem(pci_info.base0, 0x00C00000 + 0x00008000); | |
866 info->chip.arch = nvidia_card_ids[find_chip(pci_info.device)].arch; | |
867 printf("[nvidia_vid] arch %x register base %p\n",info->chip.arch,info->control_base); | |
868 info->chip.PFIFO = (uint32_t *) (info->control_base + 0x00002000); | |
869 info->chip.FIFO = (uint32_t *) (info->control_base + 0x00800000); | |
870 info->chip.PMC = (uint32_t *) (info->control_base + 0x00000000); | |
871 info->chip.PFB = (uint32_t *) (info->control_base + 0x00100000); | |
872 info->chip.PME = (uint32_t *) (info->control_base + 0x00000000); | |
873 info->chip.PCIO = (uint8_t *) (info->control_base + 0x00601000); | |
874 info->chip.PVIO = (uint8_t *) (info->control_base + 0x000C0000); | |
875 info->chip.PGRAPH = (uint32_t *) (info->control_base + 0x00400000); | |
876 /* setup chip specific functions */ | |
877 switch (info->chip.arch) { | |
878 case NV_ARCH_03: | |
879 info->chip.lock = rivatv_lock_nv03; | |
880 info->chip.fbsize = rivatv_fbsize_nv03 (&info->chip); | |
881 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); | |
882 break; | |
883 case NV_ARCH_04: | |
884 info->chip.lock = rivatv_lock_nv04; | |
885 info->chip.fbsize = rivatv_fbsize_nv04 (&info->chip); | |
886 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); | |
887 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); | |
888 break; | |
889 case NV_ARCH_10: | |
890 case NV_ARCH_20: | |
891 case NV_ARCH_30: | |
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892 case NV_ARCH_40: |
22850 | 893 info->chip.lock = rivatv_lock_nv04; |
894 info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip); | |
895 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); | |
896 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000); | |
897 break; | |
898 } | |
899 switch (info->chip.arch) { | |
900 case NV_ARCH_03: | |
901 { | |
902 /* This maps framebuffer @6MB, thus 2MB are left for video. */ | |
903 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
904 /* This may trash your screen for resolutions greater than 1024x768, sorry. */ | |
905 info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1); | |
906 info->picture_base = info->video_base + info->picture_offset; | |
907 info->chip.PRAMIN = (uint32_t *) (info->video_base + 0x00C00000); | |
908 break; | |
909 } | |
910 case NV_ARCH_04: | |
911 case NV_ARCH_10: | |
912 case NV_ARCH_20: | |
913 case NV_ARCH_30: | |
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914 case NV_ARCH_40: |
22850 | 915 { |
916 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
917 info->picture_offset = info->chip.fbsize - NV04_BES_SIZE; | |
918 if(info->chip.fbsize > 16*1024*1024) | |
919 info->picture_offset -= NV04_BES_SIZE; | |
920 // info->picture_base = (unsigned long)map_phys_mem(pci_info.base1+info->picture_offset,NV04_BES_SIZE); | |
921 info->picture_base = info->video_base + info->picture_offset; | |
922 break; | |
923 } | |
924 } | |
925 | |
926 printf("[nvidia_vid] detected memory size %u MB\n",(uint32_t)(info->chip.fbsize /1024/1024)); | |
927 | |
928 if ((mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB))!= 0) | |
929 printf("[nvidia_vid] unable to setup MTRR: %s\n", strerror(mtrr)); | |
930 else | |
931 printf("[nvidia_vid] MTRR set up\n"); | |
932 | |
933 nv_getscreenproperties(info); | |
934 if(!info->depth)printf("[nvidia_vid] text mode: %ux%u\n",info->screen_x,info->screen_y); | |
935 else printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x,info->screen_y, info->depth); | |
936 | |
937 | |
938 rivatv_enable_PMEDIA(info); | |
939 info->cur_frame = 0; | |
940 info->use_colorkey = 0; | |
941 | |
942 eq.lum = 0x00001000; | |
943 eq.chrom = 0x00001000; | |
944 memset(&eq.vals, 0, sizeof(vidix_video_eq_t)); | |
945 eq.vals.cap = VEQ_CAP_BRIGHTNESS; | |
946 if (info->chip.arch > NV_ARCH_04) | |
947 eq.vals.cap |= VEQ_CAP_CONTRAST | VEQ_CAP_SATURATION | VEQ_CAP_HUE; | |
948 eq.red_off = 0x69; | |
949 eq.green_off = 0x3e; | |
950 eq.blue_off = 0x89; | |
951 return 0; | |
952 } | |
953 | |
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954 static void nv_destroy(void){ |
22850 | 955 unmap_phys_mem(info->control_base ,0x00C00000 + 0x00008000); |
956 unmap_phys_mem(info->video_base, info->chip.fbsize); | |
957 free(info); | |
958 } | |
959 | |
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960 static int nv_get_caps(vidix_capability_t *to){ |
22850 | 961 memcpy(to, &nvidia_cap, sizeof(vidix_capability_t)); |
962 return 0; | |
963 } | |
964 | |
965 inline static int is_supported_fourcc(uint32_t fourcc) | |
966 { | |
967 if (fourcc == IMGFMT_UYVY || fourcc == IMGFMT_YUY2) | |
968 return 1; | |
969 else | |
970 return 0; | |
971 } | |
972 | |
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973 static int nv_query_fourcc(vidix_fourcc_t *to){ |
22850 | 974 if(is_supported_fourcc(to->fourcc)){ |
975 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
976 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
977 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
978 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
979 VID_DEPTH_32BPP; | |
980 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; | |
981 return 0; | |
982 } | |
983 else to->depth = to->flags = 0; | |
984 return ENOSYS; | |
985 } | |
986 | |
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987 static int nv_config_playback(vidix_playback_t *vinfo){ |
22850 | 988 uint32_t i; |
989 printf("called %s\n", __FUNCTION__); | |
990 if (! is_supported_fourcc(vinfo->fourcc)) | |
991 return ENOSYS; | |
992 | |
993 info->width = vinfo->src.w; | |
994 info->height = vinfo->src.h; | |
995 | |
996 info->d_width = vinfo->dest.w; | |
997 info->d_height = vinfo->dest.h; | |
998 info->wx = vinfo->dest.x; | |
999 info->wy = vinfo->dest.y; | |
1000 info->format = vinfo->fourcc; | |
1001 | |
1002 printf("[nvidia_vid] setting up a %dx%d-%dx%d video window (src %dx%d), format 0x%X\n", | |
1003 info->d_width, info->d_height, info->wx, info->wy, info->width, info->height, vinfo->fourcc); | |
1004 | |
1005 | |
1006 vinfo->dga_addr=info->picture_base; | |
1007 | |
1008 switch (vinfo->fourcc) | |
1009 { | |
1010 case IMGFMT_YUY2: | |
1011 case IMGFMT_UYVY: | |
1012 | |
1013 vinfo->dest.pitch.y = 64; | |
1014 vinfo->dest.pitch.u = 0; | |
1015 vinfo->dest.pitch.v = 0; | |
1016 | |
1017 vinfo->offset.y = 0; | |
1018 vinfo->offset.v = 0; | |
1019 vinfo->offset.u = 0; | |
1020 info->pitch = ((info->width << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1); | |
1021 vinfo->frame_size = info->pitch * info->height; | |
1022 break; | |
1023 } | |
1024 info->buffer_size = vinfo->frame_size; | |
1025 info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; | |
1026 if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; | |
1027 // vinfo->num_frames = 1; | |
1028 // printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); | |
1029 for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; | |
1030 return 0; | |
1031 } | |
1032 | |
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1033 static int nv_playback_on(void){ |
22850 | 1034 rivatv_overlay_start(info,info->cur_frame); |
1035 return 0; | |
1036 } | |
1037 | |
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1038 static int nv_playback_off(void){ |
22850 | 1039 rivatv_overlay_stop(info); |
1040 return 0; | |
1041 } | |
1042 | |
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1043 static int nv_set_gkeys( const vidix_grkey_t * grkey){ |
22850 | 1044 if (grkey->ckey.op == CKEY_FALSE) |
1045 { | |
1046 info->use_colorkey = 0; | |
1047 printf("[nvidia_vid] colorkeying disabled\n"); | |
1048 } | |
1049 else { | |
1050 info->use_colorkey = 1; | |
1051 info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); | |
1052 printf("[nvidia_vid] set colorkey 0x%x\n",info->vidixcolorkey); | |
1053 } | |
1054 if(info->d_width && info->d_height)rivatv_overlay_start(info,0); | |
1055 return 0; | |
1056 } | |
1057 | |
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1058 static int nv_frame_sel(unsigned int frame){ |
22850 | 1059 // printf("selecting buffer %d\n", frame); |
1060 rivatv_overlay_start(info, frame); | |
1061 if (info->num_frames >= 1) | |
1062 info->cur_frame = frame/*(frame+1)%info->num_frames*/; | |
1063 return 0; | |
1064 } | |
1065 | |
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1066 static int nv_set_eq(const vidix_video_eq_t *eq_parm) { |
22850 | 1067 double angle; |
1068 int16_t chrom_cos, chrom_sin; | |
1069 if (eq_parm->cap & VEQ_CAP_BRIGHTNESS) | |
1070 eq.vals.brightness = eq_parm->brightness; | |
1071 if (eq_parm->cap & VEQ_CAP_CONTRAST) | |
1072 eq.vals.contrast = eq_parm->contrast; | |
1073 if (eq_parm->cap & VEQ_CAP_SATURATION) | |
1074 eq.vals.saturation = eq_parm->saturation; | |
1075 if (eq_parm->cap & VEQ_CAP_HUE) | |
1076 eq.vals.hue = eq_parm->hue; | |
1077 eq.lum = (((eq.vals.brightness * 512 + 500) / 1000) << 16) | | |
1078 ((((eq.vals.contrast + 1000) * 8191 + 1000) / 2000) & 0xffff); | |
1079 angle = (double)eq.vals.hue / 1000.0 * 3.1415927; | |
1080 chrom_cos = ((eq.vals.saturation + 1000) * 8191 * cos(angle) + 1000) / 2000; | |
1081 chrom_sin = ((eq.vals.saturation + 1000) * 8191 * sin(angle) + 1000) / 2000; | |
1082 eq.chrom = chrom_sin << 16 | chrom_cos; | |
1083 eq.red_off = 0x69 - eq.vals.brightness * 62 / 1000; | |
1084 eq.green_off = 0x3e + eq.vals.brightness * 62 / 1000; | |
1085 eq.blue_off = 0x89 - eq.vals.brightness * 62 / 1000; | |
1086 return 0; | |
1087 } | |
1088 | |
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1089 static int nv_get_eq(vidix_video_eq_t *eq_parm) { |
22850 | 1090 memcpy(eq_parm, &eq.vals, sizeof(vidix_video_eq_t)); |
1091 return 0; | |
1092 } | |
1093 | |
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1094 VDXDriver nvidia_drv = { |
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1095 "nvidia", |
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1096 NULL, |
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1097 .probe = nv_probe, |
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1098 .get_caps = nv_get_caps, |
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1099 .query_fourcc = nv_query_fourcc, |
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1100 .init = nv_init, |
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1101 .destroy = nv_destroy, |
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1102 .config_playback = nv_config_playback, |
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1103 .playback_on = nv_playback_on, |
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1104 .playback_off = nv_playback_off, |
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1105 .frame_sel = nv_frame_sel, |
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1106 .get_eq = nv_get_eq, |
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1107 .set_eq = nv_set_eq, |
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1108 .set_gkey = nv_set_gkeys, |
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1109 }; |