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comparison drivers/radeon/radeon_vid.c @ 2917:3dd4e8a45d0d

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double buffering. But problems are still there
author nick
date Thu, 15 Nov 2001 17:29:52 +0000
parents f46c5556f1e6
children 49bcb6176569
comparison
equal deleted inserted replaced
2916:5ecae3e4db37 2917:3dd4e8a45d0d
9 * This software has been released under the terms of the GNU Public 9 * This software has been released under the terms of the GNU Public
10 * license. See http://www.gnu.org/copyleft/gpl.html for details. 10 * license. See http://www.gnu.org/copyleft/gpl.html for details.
11 * 11 *
12 * This file is partly based on mga_vid and sis_vid stuff from 12 * This file is partly based on mga_vid and sis_vid stuff from
13 * mplayer's package. 13 * mplayer's package.
14 * Also here was used code from CVS of GATOS project and X11 trees.
14 */ 15 */
15 16
16 /* 17 /*
17 It's entirely possible this major conflicts with something else 18 It's entirely possible this major conflicts with something else
18 mknod /dev/radeon_vid c 178 0 19 mknod /dev/radeon_vid c 178 0
22 TODO: 23 TODO:
23 OV0_COLOUR_CNTL brightness saturation 24 OV0_COLOUR_CNTL brightness saturation
24 SCALER_GAMMA_SEL_BRIGHT gamma correction ??? 25 SCALER_GAMMA_SEL_BRIGHT gamma correction ???
25 OV0_GRAPHICS_KEY_CLR color key 26 OV0_GRAPHICS_KEY_CLR color key
26 OV0_AUTO_FLIP_CNTL 27 OV0_AUTO_FLIP_CNTL
27 OV0_DEINTERLACE_PATTERN
28 OV0_FILTER_CNTL 28 OV0_FILTER_CNTL
29 OV0_VIDEO_KEY_CLR 29 OV0_VIDEO_KEY_CLR
30 OV0_KEY_CNTL 30 OV0_KEY_CNTL
31 31
32 BPP should be known 32 BPP should be known
218 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); 218 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
219 while(!(INREG(OV0_REG_LOAD_CNTL)&REG_LD_CTL_LOCK_READBACK)); 219 while(!(INREG(OV0_REG_LOAD_CNTL)&REG_LD_CTL_LOCK_READBACK));
220 220
221 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); 221 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD);
222 222
223 OUTREG(OV0_DEINTERLACE_PATTERN,0xAAAAA); 223 OUTREG(OV0_DEINTERLACE_PATTERN,0xAAAAAAAA);
224 224
225 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); 225 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
226 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); 226 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
227 227
228 OUTREG(OV0_H_INC, besr.h_inc); 228 OUTREG(OV0_H_INC, besr.h_inc);
310 ,(uint32_t)config->y_org 310 ,(uint32_t)config->y_org
311 ,(uint32_t)config->dest_width 311 ,(uint32_t)config->dest_width
312 ,(uint32_t)config->dest_height 312 ,(uint32_t)config->dest_height
313 ,(uint32_t)config->frame_size 313 ,(uint32_t)config->frame_size
314 ,(uint32_t)config->num_frames); 314 ,(uint32_t)config->num_frames);
315 315 radeon_vid_stop_video();
316 config->num_frames = 1; /* FIXME: should be 6 later */
317 switch(config->format) 316 switch(config->format)
318 { 317 {
319 case IMGFMT_RGB15: 318 case IMGFMT_RGB15:
320 case IMGFMT_BGR15: 319 case IMGFMT_BGR15:
321 case IMGFMT_RGB16: 320 case IMGFMT_RGB16:
339 } 338 }
340 339
341 pitch = ((XXX_WIDTH << 1) + 15) & ~15; 340 pitch = ((XXX_WIDTH << 1) + 15) & ~15;
342 besr.fourcc = config->format; 341 besr.fourcc = config->format;
343 342
344 besr.v_inc = (config->src_height << 20) / (config->dest_height<<4); 343 besr.v_inc = (config->src_height << 20) / (config->dest_height);
345 besr.h_inc = (config->src_width << 12) / (config->dest_width<<4); 344 besr.h_inc = (config->src_width << 12) / (config->dest_width);
346 besr.step_by = 1; 345 besr.step_by = 1;
347 346
348 while(besr.h_inc >= (2 << 12)) { 347 while(besr.h_inc >= (2 << 12)) {
349 besr.step_by++; 348 besr.step_by++;
350 besr.h_inc >>= 1; 349 besr.h_inc >>= 1;
372 371
373 tmp = (XXX_SRC_Y & 0x0000ffff) + 0x00018000; 372 tmp = (XXX_SRC_Y & 0x0000ffff) + 0x00018000;
374 besr.p1_v_accum_init = ((tmp << 4) & 0x03ff8000) | 0x00000001; 373 besr.p1_v_accum_init = ((tmp << 4) & 0x03ff8000) | 0x00000001;
375 374
376 left = 0; /*(XXX_SRC_X >> 16) & 7;*/ 375 left = 0; /*(XXX_SRC_X >> 16) & 7;*/
377 besr.h_inc |= ((besr.h_inc >> 1) << 16); 376 besr.h_inc |= ((besr.h_inc/* >> 1*/) << 16);
378 besr.step_by |= (besr.step_by << 8); 377 besr.step_by |= (besr.step_by << 8);
379 besr.y_x_start = (config->x_org + 8) | (config->y_org << 16); 378 besr.y_x_start = (config->x_org + 8) | (config->y_org << 16);
380 besr.y_x_end = ((config->x_org + config->dest_width) + 8) | ((config->y_org + config->dest_height) << 16); 379 besr.y_x_end = ((config->x_org + config->dest_width) + 8) | ((config->y_org + config->dest_height) << 16);
381 besr.p1_blank_lines_at_top = 0x00000fff | ((config->src_height - 1) << 16); 380 besr.p1_blank_lines_at_top = 0x00000fff | ((config->src_height - 1) << 16);
382 besr.vid_buf_pitch0_value = pitch; 381 besr.vid_buf_pitch0_value = pitch;
389 return 0; 388 return 0;
390 } 389 }
391 390
392 static void radeon_vid_frame_sel(int frame) 391 static void radeon_vid_frame_sel(int frame)
393 { 392 {
394 /* TODO ASAP */ 393 uint32_t off;
394 switch(frame)
395 {
396 default:
397 case 0: off = besr.vid_buf0_base_adrs; break;
398 case 1: off = besr.vid_buf1_base_adrs; break;
399 case 2: off = besr.vid_buf2_base_adrs; break;
400 case 3: off = besr.vid_buf3_base_adrs; break;
401 case 4: off = besr.vid_buf4_base_adrs; break;
402 case 5: off = besr.vid_buf5_base_adrs; break;
403 }
404 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
405 while(!(INREG(OV0_REG_LOAD_CNTL)&REG_LD_CTL_LOCK_READBACK));
406 OUTREG(OV0_VID_BUF0_BASE_ADRS, off);
407 OUTREG(OV0_REG_LOAD_CNTL, 0);
408
395 } 409 }
396 410
397 static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) 411 static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
398 { 412 {
399 int frame; 413 int frame;