2870
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1 /*
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2 *
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3 * radeon_vid.c
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4 *
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5 * Copyright (C) 2001 Nick Kurshev
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6 *
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7 * BES YUV Framebuffer driver for Radeon cards
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8 *
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9 * This software has been released under the terms of the GNU Public
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10 * license. See http://www.gnu.org/copyleft/gpl.html for details.
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11 *
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12 * This file is partly based on mga_vid and sis_vid stuff from
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13 * mplayer's package.
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2917
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14 * Also here was used code from CVS of GATOS project and X11 trees.
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2870
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15 */
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16
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17 /*
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18 It's entirely possible this major conflicts with something else
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19 mknod /dev/radeon_vid c 178 0
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20 */
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21
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22 /*
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23 TODO:
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24 OV0_COLOUR_CNTL brightness saturation
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25 SCALER_GAMMA_SEL_BRIGHT gamma correction ???
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26 OV0_GRAPHICS_KEY_CLR color key
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27 OV0_AUTO_FLIP_CNTL
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28 OV0_FILTER_CNTL
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29 OV0_VIDEO_KEY_CLR
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30 OV0_KEY_CNTL
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31
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32 BPP should be known
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33 */
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34
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35 #include <linux/config.h>
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36 #include <linux/version.h>
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37 #include <linux/module.h>
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38 #include <linux/types.h>
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39 #include <linux/kernel.h>
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40 #include <linux/sched.h>
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41 #include <linux/mm.h>
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42 #include <linux/string.h>
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43 #include <linux/errno.h>
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44 #include <linux/slab.h>
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45 #include <linux/pci.h>
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46 #include <linux/ioport.h>
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47 #include <linux/init.h>
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48
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49 #include "radeon_vid.h"
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50 #include "radeon.h"
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51
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52 #ifdef CONFIG_MTRR
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53 #include <asm/mtrr.h>
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54 #endif
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55
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56 #include <asm/uaccess.h>
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57 #include <asm/system.h>
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58 #include <asm/io.h>
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59
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60 #define TRUE 1
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61 #define FALSE 0
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62
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63 #define RADEON_VID_MAJOR 178
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64
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65
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66 MODULE_AUTHOR("Nick Kurshev <nickols_k@mail.ru>");
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67 MODULE_DESCRIPTION("Accelerated YUV BES driver for Radeons");
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68 MODULE_LICENSE("GPL");
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69
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70
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71 typedef struct bes_registers_s
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72 {
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73 /* base address of yuv framebuffer */
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74 uint32_t yuv_base;
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75 uint32_t fourcc;
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76 /* YUV BES registers */
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77 uint32_t reg_load_cntl;
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78 uint32_t h_inc;
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79 uint32_t step_by;
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80 uint32_t y_x_start;
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81 uint32_t y_x_end;
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82 uint32_t v_inc;
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83 uint32_t p1_blank_lines_at_top;
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84 uint32_t vid_buf_pitch0_value;
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85 uint32_t p1_x_start_end;
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86 uint32_t p2_x_start_end;
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87 uint32_t p3_x_start_end;
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88 uint32_t vid_buf0_base_adrs;
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89 /* These ones are for auto flip: maybe in the future */
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90 uint32_t vid_buf1_base_adrs;
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91 uint32_t vid_buf2_base_adrs;
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92 uint32_t vid_buf3_base_adrs;
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93 uint32_t vid_buf4_base_adrs;
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94 uint32_t vid_buf5_base_adrs;
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95
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96 uint32_t p1_v_accum_init;
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97 uint32_t p1_h_accum_init;
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98 uint32_t p23_h_accum_init;
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99 uint32_t scale_cntl;
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100 uint32_t exclusive_horz;
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101 uint32_t auto_flip_cntl;
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102 uint32_t filter_cntl;
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103 uint32_t colour_cntl;
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104 uint32_t graphics_key_msk;
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105 uint32_t graphics_key_clr;
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106 uint32_t key_cntl;
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107 uint32_t test;
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108 } bes_registers_t;
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109
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110 typedef struct video_registers_s
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111 {
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112 uint32_t name;
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113 uint32_t value;
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114 }video_registers_t;
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115
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116 static bes_registers_t besr;
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117 static video_registers_t vregs[] =
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118 {
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119 { OV0_REG_LOAD_CNTL, 0 },
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120 { OV0_H_INC, 0 },
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121 { OV0_STEP_BY, 0 },
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122 { OV0_Y_X_START, 0 },
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123 { OV0_Y_X_END, 0 },
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124 { OV0_V_INC, 0 },
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125 { OV0_P1_BLANK_LINES_AT_TOP, 0 },
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126 { OV0_VID_BUF_PITCH0_VALUE, 0 },
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127 { OV0_P1_X_START_END, 0 },
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128 { OV0_P2_X_START_END, 0 },
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129 { OV0_P3_X_START_END, 0 },
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130 { OV0_VID_BUF0_BASE_ADRS, 0 },
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131 { OV0_VID_BUF1_BASE_ADRS, 0 },
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132 { OV0_VID_BUF2_BASE_ADRS, 0 },
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133 { OV0_VID_BUF3_BASE_ADRS, 0 },
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134 { OV0_VID_BUF4_BASE_ADRS, 0 },
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135 { OV0_VID_BUF5_BASE_ADRS, 0 },
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136 { OV0_P1_V_ACCUM_INIT, 0 },
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137 { OV0_P1_H_ACCUM_INIT, 0 },
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138 { OV0_P23_H_ACCUM_INIT, 0 },
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139 { OV0_SCALE_CNTL, 0 },
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140 { OV0_EXCLUSIVE_HORZ, 0 },
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141 { OV0_AUTO_FLIP_CNTL, 0 },
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142 { OV0_FILTER_CNTL, 0 },
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143 { OV0_COLOUR_CNTL, 0 },
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144 { OV0_GRAPHICS_KEY_MSK, 0 },
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145 { OV0_GRAPHICS_KEY_CLR, 0 },
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146 { OV0_KEY_CNTL, 0 },
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147 { OV0_TEST, 0 }
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148 };
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149
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150 static uint32_t radeon_vid_in_use = 0;
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151 static uint32_t vid_src_ready = 0;
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152 static uint32_t vid_overlay_on = 0;
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153
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154 static uint8_t *radeon_mmio_base = 0;
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155 static uint32_t radeon_mem_base = 0;
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156 #define RADEON_SRC_BASE 0ULL /* this driver uses all video memory */
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157
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158 static uint32_t radeon_ram_size = 0;
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159
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160 //static struct video_window radeon_win;
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161 static mga_vid_config_t radeon_config;
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162
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163 #define DEBUG 1
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164 #if DEBUG
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165 #define RTRACE printk
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166 #else
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167 #define RTRACE(...) ((void)0)
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168 #endif
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169
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170
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171 /*
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172 * IO macros
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173 */
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174
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175 #define INREG8(addr) readb((radeon_mmio_base)+addr)
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176 #define OUTREG8(addr,val) writeb(val, (radeon_mmio_base)+addr)
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177 #define INREG(addr) readl((radeon_mmio_base)+addr)
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178 #define OUTREG(addr,val) writel(val, (radeon_mmio_base)+addr)
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179
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180 static void radeon_vid_save_state( void )
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181 {
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182 size_t i;
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183 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++)
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184 vregs[i].value = INREG(vregs[i].name);
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185 }
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186
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187 static void radeon_vid_restore_state( void )
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188 {
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189 size_t i;
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190 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++)
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191 OUTREG(vregs[i].name,vregs[i].value);
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192 }
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193
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194 static void radeon_vid_stop_video( void )
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195 {
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196 if(vid_src_ready == 1)
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197 {
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198 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET);
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199 OUTREG(OV0_EXCLUSIVE_HORZ, 0);
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200 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */
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201 OUTREG(OV0_FILTER_CNTL, 0x0000000f);
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202 /*
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203 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) |
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204 (saturation << 8) |
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205 (saturation << 16));
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206 OUTREG(OV0_GRAPHICS_KEY_MSK, (1 << depth) - 1);
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207 OUTREG(OV0_GRAPHICS_KEY_CLR, colorKey);
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208 */
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209 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE);
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210 OUTREG(OV0_TEST, 0);
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211 }
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212 vid_src_ready = 0;
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213 }
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214
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215 static void radeon_vid_display_video( void )
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216 {
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217 int bes_flags;
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218 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
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219 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK));
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220
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221 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD);
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222
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2917
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223 OUTREG(OV0_DEINTERLACE_PATTERN,0xAAAAAAAA);
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2870
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224
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225 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
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226 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
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227
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228 OUTREG(OV0_H_INC, besr.h_inc);
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229 OUTREG(OV0_STEP_BY, besr.step_by);
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230 OUTREG(OV0_Y_X_START, besr.y_x_start);
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231 OUTREG(OV0_Y_X_END, besr.y_x_end);
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232 OUTREG(OV0_V_INC, besr.v_inc);
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233 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top);
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234 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value);
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235 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end);
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236 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end);
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237 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end);
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238 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs);
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239 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs);
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240 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs);
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241 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs);
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242 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs);
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243 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf5_base_adrs);
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244 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init);
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245 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init);
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246 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init);
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247
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248 bes_flags = SCALER_ENABLE |
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249 SCALER_DOUBLE_BUFFER |
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250 SCALER_ADAPTIVE_DEINT |
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251 SCALER_SMART_SWITCH |
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252 SCALER_HORZ_PICK_NEAREST;
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253 switch(besr.fourcc)
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254 {
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255 case IMGFMT_RGB15:
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256 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break;
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257 case IMGFMT_RGB16:
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258 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break;
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259 case IMGFMT_RGB24:
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260 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break;
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261 case IMGFMT_RGB32:
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262 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break;
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263
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264 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break;
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265 case IMGFMT_IYUV: bes_flags |= SCALER_SOURCE_YUV12; break;
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266 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break;
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267
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268 case IMGFMT_YV12:
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269 case IMGFMT_I420:
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270 case IMGFMT_YUY2:
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271 default: bes_flags |= SCALER_SOURCE_VYUY422; break;
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272 }
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273 OUTREG(OV0_SCALE_CNTL, bes_flags);
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274 /*
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275 TODO:
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276 brightness: -64 : +63
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277 saturation: 0 : 31
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278 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) |
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279 (saturation << 8) |
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280 (saturation << 16));
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281 OUTREG(OV0_GRAPHICS_KEY_CLR, colkey_red | colkey_green << 8 | colkey_blue << 16);
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282
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283 */
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284 OUTREG(OV0_REG_LOAD_CNTL, 0);
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285 }
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286
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287 static void radeon_vid_start_video( void )
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288 {
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289 if(vid_src_ready == 0) radeon_vid_display_video();
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290 vid_src_ready = 1;
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291 }
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292
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293 #define XXX_SRC_X 0
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294 #define XXX_SRC_Y 0
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295
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296 #define XXX_WIDTH config->dest_width
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297 #define XXX_HEIGHT config->dest_height
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298
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299 static int radeon_vid_init_video( mga_vid_config_t *config )
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300 {
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301 uint32_t tmp,left,src_w,pitch;
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302
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303 RTRACE("radeon_vid: usr_config: version = %x card=%x ram=%x src(%xx%x) dest(%x:%xx%x:%x) frame_size=%x num_frames=%x\n"
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304 ,(uint32_t)config->version
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305 ,(uint32_t)config->card_type
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306 ,(uint32_t)config->ram_size
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307 ,(uint32_t)config->src_width
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308 ,(uint32_t)config->src_height
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309 ,(uint32_t)config->x_org
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310 ,(uint32_t)config->y_org
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311 ,(uint32_t)config->dest_width
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312 ,(uint32_t)config->dest_height
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313 ,(uint32_t)config->frame_size
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314 ,(uint32_t)config->num_frames);
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315 radeon_vid_stop_video();
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316 switch(config->format)
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317 {
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318 case IMGFMT_RGB15:
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319 case IMGFMT_BGR15:
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320 case IMGFMT_RGB16:
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321 case IMGFMT_BGR16:
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322 case IMGFMT_RGB24:
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323 case IMGFMT_BGR24:
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324 case IMGFMT_RGB32:
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325 case IMGFMT_BGR32:
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326
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327 case IMGFMT_YVU9:
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328 case IMGFMT_IYUV:
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329 case IMGFMT_UYVY:
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330
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331 case IMGFMT_YV12:
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332 case IMGFMT_I420:
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333 case IMGFMT_YUY2:
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334 break;
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335 default:
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336 printk( "radeon_vid: Unsupported pixel format: 0x%X\n",config->format);
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337 return -1;
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338 }
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339
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340 pitch = ((XXX_WIDTH << 1) + 15) & ~15;
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341 besr.fourcc = config->format;
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342
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343 besr.v_inc = (config->src_height << 20) / (config->dest_height);
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344 besr.h_inc = (config->src_width << 12) / (config->dest_width);
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345 besr.step_by = 1;
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346
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347 while(besr.h_inc >= (2 << 12)) {
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348 besr.step_by++;
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349 besr.h_inc >>= 1;
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350 }
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351
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352 RTRACE("radeon_vid: BES: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by);
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353 /* keep everything in 16.16 */
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354
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355 besr.vid_buf0_base_adrs = RADEON_SRC_BASE; /* I guess that offset 0 is o'k */
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356 /* besr.vid_buf0_base_adrs += (((XXX_SRC_X >> 16) & ~7) << 1)&0xfffffff0;*/
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357 RTRACE("radeon_vid: BES: vid_buf0_basey=%x\n",besr.vid_buf0_base_adrs);
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358 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs + config->frame_size;
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359 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs;
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360 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs + config->frame_size;
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361 besr.vid_buf4_base_adrs = besr.vid_buf0_base_adrs;
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362 besr.vid_buf5_base_adrs = besr.vid_buf0_base_adrs + config->frame_size;
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363
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364 tmp = (XXX_SRC_X & 0x0003ffff) + 0x00028000 + (besr.h_inc << 3);
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365 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) |
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366 ((tmp << 12) & 0xf0000000);
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367
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368 tmp = ((XXX_SRC_X >> 1) & 0x0001ffff) + 0x00028000 + (besr.h_inc << 2);
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369 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) |
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370 ((tmp << 12) & 0x70000000);
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371
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372 tmp = (XXX_SRC_Y & 0x0000ffff) + 0x00018000;
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373 besr.p1_v_accum_init = ((tmp << 4) & 0x03ff8000) | 0x00000001;
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374
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375 left = 0; /*(XXX_SRC_X >> 16) & 7;*/
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376 besr.h_inc |= ((besr.h_inc/* >> 1*/) << 16);
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377 besr.step_by |= (besr.step_by << 8);
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378 besr.y_x_start = (config->x_org + 8) | (config->y_org << 16);
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379 besr.y_x_end = ((config->x_org + config->dest_width) + 8) | ((config->y_org + config->dest_height) << 16);
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380 besr.p1_blank_lines_at_top = 0x00000fff | ((config->src_height - 1) << 16);
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381 besr.vid_buf_pitch0_value = pitch;
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382 RTRACE("radeon_vid: BES: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n"
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383 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value);
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384 besr.p1_x_start_end = (config->src_width + left - 1) | (left << 16);
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385 left >>= 1; src_w=config->src_width >> 1;
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386 besr.p2_x_start_end = (src_w + left - 1) | (left << 16);
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387 besr.p3_x_start_end = besr.p2_x_start_end;
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388 return 0;
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389 }
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390
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391 static void radeon_vid_frame_sel(int frame)
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392 {
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2917
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393 uint32_t off;
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394 switch(frame)
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395 {
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396 default:
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397 case 0: off = besr.vid_buf0_base_adrs; break;
|
|
398 case 1: off = besr.vid_buf1_base_adrs; break;
|
|
399 case 2: off = besr.vid_buf2_base_adrs; break;
|
|
400 case 3: off = besr.vid_buf3_base_adrs; break;
|
|
401 case 4: off = besr.vid_buf4_base_adrs; break;
|
|
402 case 5: off = besr.vid_buf5_base_adrs; break;
|
|
403 }
|
|
404 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
|
|
405 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK));
|
|
406 OUTREG(OV0_VID_BUF0_BASE_ADRS, off);
|
|
407 OUTREG(OV0_REG_LOAD_CNTL, 0);
|
|
408
|
2870
|
409 }
|
|
410
|
|
411 static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
|
|
412 {
|
|
413 int frame;
|
|
414
|
|
415 switch(cmd)
|
|
416 {
|
|
417 case MGA_VID_CONFIG:
|
|
418 RTRACE( "radeon_mmio_base = %p\n",radeon_mmio_base);
|
|
419 RTRACE( "radeon_mem_base = %08x\n",radeon_mem_base);
|
|
420 RTRACE( "radeon_vid: Received configuration\n");
|
|
421
|
|
422 if(copy_from_user(&radeon_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t)))
|
|
423 {
|
|
424 printk( "radeon_vid: failed copy from userspace\n");
|
|
425 return(-EFAULT);
|
|
426 }
|
|
427 if(radeon_config.version != MGA_VID_VERSION){
|
|
428 printk( "radeon_vid: incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,radeon_config.version);
|
|
429 return(-EFAULT);
|
|
430 }
|
|
431
|
|
432 if(radeon_config.frame_size==0 || radeon_config.frame_size>1024*768*2){
|
|
433 printk( "radeon_vid: illegal frame_size: %d\n",radeon_config.frame_size);
|
|
434 return(-EFAULT);
|
|
435 }
|
|
436
|
|
437 if(radeon_config.num_frames<1 || radeon_config.num_frames>4){
|
|
438 printk( "radeon_vid: illegal num_frames: %d\n",radeon_config.num_frames);
|
|
439 return(-EFAULT);
|
|
440 }
|
|
441
|
|
442 /* FIXME: Fake of G400 ;) or would be better G200 ??? */
|
|
443 radeon_config.card_type = 0;
|
|
444 radeon_config.ram_size = radeon_ram_size;
|
|
445
|
|
446 if (copy_to_user((mga_vid_config_t *) arg, &radeon_config, sizeof(mga_vid_config_t)))
|
|
447 {
|
|
448 printk( "radeon_vid: failed copy to userspace\n");
|
|
449 return(-EFAULT);
|
|
450 }
|
|
451 return radeon_vid_init_video(&radeon_config);
|
|
452 break;
|
|
453
|
|
454 case MGA_VID_ON:
|
|
455 RTRACE( "radeon_vid: Video ON (ioctl)\n");
|
|
456 vid_src_ready = 1;
|
|
457 if(vid_overlay_on) radeon_vid_start_video();
|
|
458 break;
|
|
459
|
|
460 case MGA_VID_OFF:
|
|
461 RTRACE( "radeon_vid: Video OFF (ioctl)\n");
|
|
462 radeon_vid_stop_video();
|
|
463 break;
|
|
464
|
|
465 case MGA_VID_FSEL:
|
|
466 if(copy_from_user(&frame,(int *) arg,sizeof(int)))
|
|
467 {
|
|
468 printk("radeon_vid: FSEL failed copy from userspace\n");
|
|
469 return(-EFAULT);
|
|
470 }
|
|
471 radeon_vid_frame_sel(frame);
|
|
472 break;
|
|
473
|
|
474 default:
|
|
475 printk( "radeon_vid: Invalid ioctl\n");
|
|
476 return (-EINVAL);
|
|
477 }
|
|
478
|
|
479 return 0;
|
|
480 }
|
|
481
|
|
482 struct ati_card_id_s
|
|
483 {
|
|
484 int id;
|
|
485 char name[17];
|
|
486 }ati_card_ids[]=
|
|
487 {
|
|
488 { PCI_DEVICE_ID_RADEON_QD, "Radeon QD " },
|
|
489 { PCI_DEVICE_ID_RADEON_QE, "Radeon QE " },
|
|
490 { PCI_DEVICE_ID_RADEON_QF, "Radeon QF " },
|
|
491 { PCI_DEVICE_ID_RADEON_QG, "Radeon QG " },
|
|
492 { PCI_DEVICE_ID_RADEON_QY, "Radeon VE QY " },
|
|
493 { PCI_DEVICE_ID_RADEON_QZ, "Radeon VE QZ " },
|
|
494 { PCI_DEVICE_ID_RADEON_LY, "Radeon M6 LY " },
|
|
495 { PCI_DEVICE_ID_RADEON_LZ, "Radeon M6 LZ " },
|
|
496 { PCI_DEVICE_ID_RADEON_LW, "Radeon M7 LW " },
|
|
497 { PCI_DEVICE_ID_R200_QL, "Radeon2 8500 QL " },
|
|
498 { PCI_DEVICE_ID_RV200_QW, "Radeon2 7500 QW " }
|
|
499 };
|
|
500
|
|
501 static int radeon_vid_config_card(void)
|
|
502 {
|
|
503 struct pci_dev *dev = NULL;
|
|
504 size_t i;
|
|
505
|
|
506 for(i=0;i<sizeof(ati_card_ids)/sizeof(struct ati_card_id_s);i++)
|
|
507 if((dev=pci_find_device(PCI_VENDOR_ID_ATI, ati_card_ids[i].id, NULL)))
|
|
508 break;
|
|
509 if(dev)
|
|
510 printk("radeon_vid: Found %s\n",ati_card_ids[i].name);
|
|
511 else
|
|
512 {
|
|
513 printk("radeon_vid: No supported cards found\n");
|
|
514 return FALSE;
|
|
515 }
|
|
516
|
|
517 radeon_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RADEON_REGSIZE);
|
|
518 radeon_mem_base = dev->resource[0].start;
|
|
519
|
|
520 RTRACE( "radeon_vid: MMIO at 0x%p\n", radeon_mmio_base);
|
|
521 RTRACE( "radeon_vid: Frame Buffer at 0x%08x\n", radeon_mem_base);
|
|
522
|
|
523 radeon_ram_size = pci_resource_len(dev, 0)/0x100000;
|
|
524
|
|
525 return TRUE;
|
|
526 }
|
|
527
|
|
528
|
|
529 static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos)
|
|
530 {
|
|
531 return -EINVAL;
|
|
532 }
|
|
533
|
|
534 static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
|
|
535 {
|
|
536 return -EINVAL;
|
|
537 }
|
|
538
|
|
539 static int radeon_vid_mmap(struct file *file, struct vm_area_struct *vma)
|
|
540 {
|
|
541
|
|
542 RTRACE( "radeon_vid: mapping video memory into userspace\n");
|
|
543 if(remap_page_range(vma->vm_start, radeon_mem_base + RADEON_SRC_BASE,
|
|
544 vma->vm_end - vma->vm_start, vma->vm_page_prot))
|
|
545 {
|
|
546 printk( "radeon_vid: error mapping video memory\n");
|
|
547 return(-EAGAIN);
|
|
548 }
|
|
549
|
|
550 return(0);
|
|
551 }
|
|
552
|
|
553 static int radeon_vid_release(struct inode *inode, struct file *file)
|
|
554 {
|
|
555 //Close the window just in case
|
|
556 vid_src_ready = 0;
|
|
557 radeon_vid_in_use = 0;
|
|
558 radeon_vid_stop_video();
|
|
559
|
|
560 MOD_DEC_USE_COUNT;
|
|
561 return 0;
|
|
562 }
|
|
563
|
|
564 static long long radeon_vid_lseek(struct file *file, long long offset, int origin)
|
|
565 {
|
|
566 return -ESPIPE;
|
|
567 }
|
|
568
|
|
569 static int radeon_vid_open(struct inode *inode, struct file *file)
|
|
570 {
|
|
571 int minor = MINOR(inode->i_rdev);
|
|
572
|
|
573 if(minor != 0)
|
|
574 return(-ENXIO);
|
|
575
|
|
576 if(radeon_vid_in_use == 1)
|
|
577 return(-EBUSY);
|
|
578
|
|
579 radeon_vid_in_use = 1;
|
|
580 MOD_INC_USE_COUNT;
|
|
581 return(0);
|
|
582 }
|
|
583
|
|
584 #if LINUX_VERSION_CODE >= 0x020400
|
|
585 static struct file_operations radeon_vid_fops =
|
|
586 {
|
|
587 llseek: radeon_vid_lseek,
|
|
588 read: radeon_vid_read,
|
|
589 write: radeon_vid_write,
|
|
590 ioctl: radeon_vid_ioctl,
|
|
591 mmap: radeon_vid_mmap,
|
|
592 open: radeon_vid_open,
|
|
593 release: radeon_vid_release
|
|
594 };
|
|
595 #else
|
|
596 static struct file_operations radeon_vid_fops =
|
|
597 {
|
|
598 radeon_vid_lseek,
|
|
599 radeon_vid_read,
|
|
600 radeon_vid_write,
|
|
601 NULL,
|
|
602 NULL,
|
|
603 radeon_vid_ioctl,
|
|
604 radeon_vid_mmap,
|
|
605 radeon_vid_open,
|
|
606 NULL,
|
|
607 radeon_vid_release
|
|
608 };
|
|
609 #endif
|
|
610
|
|
611 /*
|
|
612 * Main Initialization Function
|
|
613 */
|
|
614
|
|
615
|
|
616 static int radeon_vid_initialize(void)
|
|
617 {
|
|
618 radeon_vid_in_use = 0;
|
|
619
|
|
620 RTRACE( "Radeon BES YUV Video interface v0.01 (c) Nick Kurshev\n");
|
|
621 if(register_chrdev(RADEON_VID_MAJOR, "radeon_vid", &radeon_vid_fops))
|
|
622 {
|
|
623 printk( "radeon_vid: unable to get major: %d\n", RADEON_VID_MAJOR);
|
|
624 return -EIO;
|
|
625 }
|
|
626
|
|
627 if (!radeon_vid_config_card())
|
|
628 {
|
|
629 printk("radeon_vid: can't configure this card\n");
|
|
630 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid");
|
|
631 return -EINVAL;
|
|
632 }
|
|
633 radeon_vid_save_state();
|
|
634 return(0);
|
|
635 }
|
|
636
|
|
637 int init_module(void)
|
|
638 {
|
|
639 return radeon_vid_initialize();
|
|
640 }
|
|
641
|
|
642 void cleanup_module(void)
|
|
643 {
|
|
644 radeon_vid_restore_state();
|
|
645 if(radeon_mmio_base)
|
|
646 iounmap(radeon_mmio_base);
|
|
647
|
|
648 RTRACE( "radeon_vid: Cleaning up module\n");
|
|
649 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid");
|
|
650 }
|
|
651
|