comparison drivers/radeon/radeon_vid.c @ 3250:61b1441c0f8c

More configurable stuff
author nick
date Sat, 01 Dec 2001 17:57:49 +0000
parents 7cec2396bde3
children e714f1e4ab27
comparison
equal deleted inserted replaced
3249:49a0d462dffe 3250:61b1441c0f8c
12 * This file is partly based on mga_vid and sis_vid stuff from 12 * This file is partly based on mga_vid and sis_vid stuff from
13 * mplayer's package. 13 * mplayer's package.
14 * Also here was used code from CVS of GATOS project and X11 trees. 14 * Also here was used code from CVS of GATOS project and X11 trees.
15 */ 15 */
16 16
17 #define RADEON_VID_VERSION "1.0.0" 17 #define RADEON_VID_VERSION "1.0.1"
18 18
19 /* 19 /*
20 It's entirely possible this major conflicts with something else 20 It's entirely possible this major conflicts with something else
21 mknod /dev/radeon_vid c 178 0 21 mknod /dev/radeon_vid c 178 0
22 or 22 or
27 ----------------------------------------------------------- 27 -----------------------------------------------------------
28 TODO: 28 TODO:
29 Highest priority: fbvid.h compatibility 29 Highest priority: fbvid.h compatibility
30 High priority: RGB/BGR 2-32, YVU9, IF09 support 30 High priority: RGB/BGR 2-32, YVU9, IF09 support
31 Middle priority: 31 Middle priority:
32 OV0_COLOUR_CNTL brightness saturation
33 SCALER_GAMMA_SEL_BRIGHT gamma correction ??? 32 SCALER_GAMMA_SEL_BRIGHT gamma correction ???
34 OV0_GRAPHICS_KEY_CLR color key
35 OV0_AUTO_FLIP_CNTL 33 OV0_AUTO_FLIP_CNTL
36 OV0_FILTER_CNTL 34 OV0_FILTER_CNTL
37 OV0_VIDEO_KEY_CLR 35 OV0_VIDEO_KEY_CLR
38 OV0_KEY_CNTL 36 OV0_KEY_CNTL
39 Low priority: CLPL, IYU1, IYU2, UYNV, CYUV 37 Low priority: CLPL, IYU1, IYU2, UYNV, CYUV
128 uint32_t p23_h_accum_init; 126 uint32_t p23_h_accum_init;
129 uint32_t scale_cntl; 127 uint32_t scale_cntl;
130 uint32_t exclusive_horz; 128 uint32_t exclusive_horz;
131 uint32_t auto_flip_cntl; 129 uint32_t auto_flip_cntl;
132 uint32_t filter_cntl; 130 uint32_t filter_cntl;
131 uint32_t graphics_key_msk;
132 uint32_t key_cntl;
133 uint32_t test;
134 /* Configurable stuff */
135 int double_buff;
133 int brightness; 136 int brightness;
134 int saturation; 137 int saturation;
135 uint32_t graphics_key_msk;
136 uint32_t graphics_key_clr; 138 uint32_t graphics_key_clr;
137 uint32_t key_cntl; 139 int deinterlace_on;
138 uint32_t test; 140 uint32_t deinterlace_pattern;
139 } bes_registers_t; 141 } bes_registers_t;
140 142
141 typedef struct video_registers_s 143 typedef struct video_registers_s
142 { 144 {
143 uint32_t name; 145 uint32_t name;
185 static uint32_t radeon_vid_in_use = 0; 187 static uint32_t radeon_vid_in_use = 0;
186 188
187 static uint8_t *radeon_mmio_base = 0; 189 static uint8_t *radeon_mmio_base = 0;
188 static uint32_t radeon_mem_base = 0; 190 static uint32_t radeon_mem_base = 0;
189 static int32_t radeon_overlay_off = 0; 191 static int32_t radeon_overlay_off = 0;
190 static int radeon_double_buff=1;
191 static uint32_t radeon_ram_size = 0; 192 static uint32_t radeon_ram_size = 0;
192 193
193 static mga_vid_config_t radeon_config; 194 static mga_vid_config_t radeon_config;
194 195
195 #undef DEBUG 196 #undef DEBUG
274 { 275 {
275 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); 276 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET);
276 OUTREG(OV0_EXCLUSIVE_HORZ, 0); 277 OUTREG(OV0_EXCLUSIVE_HORZ, 0);
277 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ 278 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */
278 OUTREG(OV0_FILTER_CNTL, 0x0000000f); 279 OUTREG(OV0_FILTER_CNTL, 0x0000000f);
279 /*
280 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) |
281 (saturation << 8) |
282 (saturation << 16));
283 OUTREG(OV0_GRAPHICS_KEY_MSK, (1 << depth) - 1);
284 OUTREG(OV0_GRAPHICS_KEY_CLR, colorKey);
285 */
286 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); 280 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE);
287 OUTREG(OV0_TEST, 0); 281 OUTREG(OV0_TEST, 0);
288 } 282 }
289 283
290 static void radeon_vid_display_video( void ) 284 static void radeon_vid_display_video( void )
301 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); 295 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
302 while(!(INREG(OV0_REG_LOAD_CNTL)&REG_LD_CTL_LOCK_READBACK)); 296 while(!(INREG(OV0_REG_LOAD_CNTL)&REG_LD_CTL_LOCK_READBACK));
303 297
304 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); 298 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD);
305 299
306 OUTREG(OV0_DEINTERLACE_PATTERN,0x900AAAAA); 300 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern);
307 301
308 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); 302 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
309 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); 303 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
310 304
311 OUTREG(OV0_H_INC, besr.h_inc); 305 OUTREG(OV0_H_INC, besr.h_inc);
333 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); 327 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init);
334 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); 328 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init);
335 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); 329 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init);
336 330
337 bes_flags = SCALER_ENABLE | 331 bes_flags = SCALER_ENABLE |
338 SCALER_ADAPTIVE_DEINT |
339 SCALER_SMART_SWITCH | 332 SCALER_SMART_SWITCH |
340 SCALER_HORZ_PICK_NEAREST; 333 SCALER_HORZ_PICK_NEAREST;
341 if(radeon_double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; 334 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER;
335 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT;
342 #ifdef RAGE128 336 #ifdef RAGE128
343 bes_flags |= SCALER_BURST_PER_PLANE; 337 bes_flags |= SCALER_BURST_PER_PLANE;
344 #endif 338 #endif
345 switch(besr.fourcc) 339 switch(besr.fourcc)
346 { 340 {
364 case IMGFMT_YUY2: 358 case IMGFMT_YUY2:
365 default: bes_flags |= SCALER_SOURCE_VYUY422; break; 359 default: bes_flags |= SCALER_SOURCE_VYUY422; break;
366 } 360 }
367 RTRACE(RVID_MSG"OV0: SCALER=%x\n",bes_flags); 361 RTRACE(RVID_MSG"OV0: SCALER=%x\n",bes_flags);
368 OUTREG(OV0_SCALE_CNTL, bes_flags); 362 OUTREG(OV0_SCALE_CNTL, bes_flags);
369 /*
370 TODO:
371 brightness: -64 : +63
372 saturation: 0 : 31
373 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) |
374 (saturation << 8) |
375 (saturation << 16));
376 OUTREG(OV0_GRAPHICS_KEY_CLR, colkey_red | colkey_green << 8 | colkey_blue << 16);
377
378 */
379 OUTREG(OV0_REG_LOAD_CNTL, 0); 363 OUTREG(OV0_REG_LOAD_CNTL, 0);
380 } 364 }
381 365
382 #define XXX_SRC_X 0 366 #define XXX_SRC_X 0
383 #define XXX_SRC_Y 0 367 #define XXX_SRC_Y 0
548 } 532 }
549 533
550 static void radeon_vid_frame_sel(int frame) 534 static void radeon_vid_frame_sel(int frame)
551 { 535 {
552 uint32_t off0,off1,off2; 536 uint32_t off0,off1,off2;
553 if(!radeon_double_buff) return; 537 if(!besr.double_buff) return;
554 if(frame%2) 538 if(frame%2)
555 { 539 {
556 off0 = besr.vid_buf3_base_adrs; 540 off0 = besr.vid_buf3_base_adrs;
557 off1 = besr.vid_buf4_base_adrs; 541 off1 = besr.vid_buf4_base_adrs;
558 off2 = besr.vid_buf5_base_adrs; 542 off2 = besr.vid_buf5_base_adrs;
569 OUTREG(OV0_VID_BUF1_BASE_ADRS, off1); 553 OUTREG(OV0_VID_BUF1_BASE_ADRS, off1);
570 OUTREG(OV0_VID_BUF2_BASE_ADRS, off2); 554 OUTREG(OV0_VID_BUF2_BASE_ADRS, off2);
571 OUTREG(OV0_REG_LOAD_CNTL, 0); 555 OUTREG(OV0_REG_LOAD_CNTL, 0);
572 } 556 }
573 557
558 static void radeon_vid_make_default(void)
559 {
560 besr.deinterlace_pattern = 0x900AAAAA;
561 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern);
562 besr.deinterlace_on=1;
563 besr.double_buff=1;
564 }
565
566
574 static void radeon_vid_preset(void) 567 static void radeon_vid_preset(void)
575 { 568 {
576 unsigned tmp; 569 unsigned tmp;
577 tmp = INREG(OV0_COLOUR_CNTL); 570 tmp = INREG(OV0_COLOUR_CNTL);
578 besr.saturation = (tmp>>8)&0x1f; 571 besr.saturation = (tmp>>8)&0x1f;
579 besr.brightness = tmp & 0x7f; 572 besr.brightness = tmp & 0x7f;
573 besr.graphics_key_clr = INREG(OV0_GRAPHICS_KEY_CLR);
574 besr.deinterlace_pattern = INREG(OV0_DEINTERLACE_PATTERN);
580 } 575 }
581 576
582 static int video_on = 0; 577 static int video_on = 0;
583 578
584 static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) 579 static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
775 } 770 }
776 771
777 #define PARAM_BRIGHTNESS "brightness=" 772 #define PARAM_BRIGHTNESS "brightness="
778 #define PARAM_SATURATION "saturation=" 773 #define PARAM_SATURATION "saturation="
779 #define PARAM_DOUBLE_BUFF "double_buff=" 774 #define PARAM_DOUBLE_BUFF "double_buff="
775 #define PARAM_COLOUR_KEY "colour_key="
776 #define PARAM_DEINTERLACE "deinterlace="
777 #define PARAM_DEINTERLACE_PATTERN "deinterlace_pattern="
780 778
781 static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) 779 static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos)
782 { 780 {
783 unsigned len,saturation; 781 unsigned len,saturation;
784 long brightness; 782 long brightness;
785 brightness = besr.brightness; 783 brightness = besr.brightness;
786 saturation = besr.saturation; 784 saturation = besr.saturation;
787 len = 0; 785 len = 0;
788 len += sprintf(&buf[len],"Chip: %s\n",ati_card_ids[detected_chip].name); 786 len += sprintf(&buf[len],"Chip: %s\n",ati_card_ids[detected_chip].name);
789 len += sprintf(&buf[len],"Memory: %p:%x\n",radeon_mem_base,radeon_ram_size*0x100000); 787 len += sprintf(&buf[len],"Memory: %p:%x\n",radeon_mem_base,radeon_ram_size*0x100000);
790 len += sprintf(&buf[len],"MMIO: %p\n",radeon_mmio_base); 788 len += sprintf(&buf[len],"MMIO: %p\n\n",radeon_mmio_base);
791 len += sprintf(&buf[len],"Configurable stuff:\n"); 789 len += sprintf(&buf[len],"Configurable stuff:\n");
792 len += sprintf(&buf[len],PARAM_DOUBLE_BUFF"%s\n",radeon_double_buff?"on":"off"); 790 len += sprintf(&buf[len],"~~~~~~~~~~~~~~~~~~~\n");
791 len += sprintf(&buf[len],PARAM_DOUBLE_BUFF"%s\n",besr.double_buff?"on":"off");
793 len += sprintf(&buf[len],PARAM_BRIGHTNESS"%i\n",brightness); 792 len += sprintf(&buf[len],PARAM_BRIGHTNESS"%i\n",brightness);
794 len += sprintf(&buf[len],PARAM_SATURATION"%u\n",saturation); 793 len += sprintf(&buf[len],PARAM_SATURATION"%u\n",saturation);
794 len += sprintf(&buf[len],PARAM_COLOUR_KEY"%X\n",besr.graphics_key_clr);
795 len += sprintf(&buf[len],PARAM_DEINTERLACE"%s\n",besr.deinterlace_on?"on":"off");
796 len += sprintf(&buf[len],PARAM_DEINTERLACE_PATTERN"%X\n",besr.deinterlace_pattern);
795 return len; 797 return len;
796 } 798 }
797 799
798 static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) 800 static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
799 { 801 {
801 { 803 {
802 long brightness; 804 long brightness;
803 brightness=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10); 805 brightness=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10);
804 if(brightness >= -64 && brightness <= 63) 806 if(brightness >= -64 && brightness <= 63)
805 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) | 807 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) |
806 (besr.saturation << 8) | 808 (besr.saturation << 8) |
807 (besr.saturation << 16)); 809 (besr.saturation << 16));
808 } 810 }
809 else 811 else
810 if(memcmp(buf,PARAM_SATURATION,min(count,strlen(PARAM_SATURATION))) == 0) 812 if(memcmp(buf,PARAM_SATURATION,min(count,strlen(PARAM_SATURATION))) == 0)
811 { 813 {
812 long saturation; 814 long saturation;
813 saturation=simple_strtol(&buf[strlen(PARAM_SATURATION)],NULL,10); 815 saturation=simple_strtol(&buf[strlen(PARAM_SATURATION)],NULL,10);
814 if(saturation >= 0 && saturation <= 31) 816 if(saturation >= 0 && saturation <= 31)
815 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | 817 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) |
816 (saturation << 8) | 818 (saturation << 8) |
817 (saturation << 16)); 819 (saturation << 16));
818 } 820 }
819 else 821 else
820 if(memcmp(buf,PARAM_DOUBLE_BUFF,min(count,strlen(PARAM_DOUBLE_BUFF))) == 0) 822 if(memcmp(buf,PARAM_DOUBLE_BUFF,min(count,strlen(PARAM_DOUBLE_BUFF))) == 0)
821 { 823 {
822 if(memcmp(&buf[strlen(PARAM_DOUBLE_BUFF)],"on",2) == 0) radeon_double_buff = 1; 824 if(memcmp(&buf[strlen(PARAM_DOUBLE_BUFF)],"on",2) == 0) besr.double_buff = 1;
823 else radeon_double_buff = 0; 825 else besr.double_buff = 0;
826 }
827 else
828 if(memcmp(buf,PARAM_COLOUR_KEY,min(count,strlen(PARAM_COLOUR_KEY))) == 0)
829 {
830 long ckey;
831 ckey=simple_strtol(&buf[strlen(PARAM_COLOUR_KEY)],NULL,16);
832 OUTREG(OV0_GRAPHICS_KEY_CLR, ckey);
833 }
834 else
835 if(memcmp(buf,PARAM_DEINTERLACE,min(count,strlen(PARAM_DEINTERLACE))) == 0)
836 {
837 if(memcmp(&buf[strlen(PARAM_DEINTERLACE)],"on",2) == 0) besr.deinterlace_on = 1;
838 else besr.deinterlace_on = 0;
839 }
840 else
841 if(memcmp(buf,PARAM_DEINTERLACE_PATTERN,min(count,strlen(PARAM_DEINTERLACE_PATTERN))) == 0)
842 {
843 long dpat;
844 dpat=simple_strtol(&buf[strlen(PARAM_DEINTERLACE_PATTERN)],NULL,16);
845 OUTREG(OV0_DEINTERLACE_PATTERN, dpat);
824 } 846 }
825 radeon_vid_preset(); 847 radeon_vid_preset();
826 return count; 848 return count;
827 } 849 }
828 850
920 printk(RVID_MSG"can't configure this card\n"); 942 printk(RVID_MSG"can't configure this card\n");
921 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); 943 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid");
922 return -EINVAL; 944 return -EINVAL;
923 } 945 }
924 radeon_vid_save_state(); 946 radeon_vid_save_state();
947 radeon_vid_make_default();
925 radeon_vid_preset(); 948 radeon_vid_preset();
926 return(0); 949 return(0);
927 } 950 }
928 951
929 int init_module(void) 952 int init_module(void)