Mercurial > mplayer.hg
comparison vidix/drivers/radeon_vid.c @ 4611:7b793875a640
Get(Set) deinterlacing
author | nick |
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date | Sat, 09 Feb 2002 15:14:48 +0000 |
parents | e9928913a61d |
children | a093bb34b723 |
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4610:eb8ffbcd0b73 | 4611:7b793875a640 |
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780 radeon_fifo_wait(15); | 780 radeon_fifo_wait(15); |
781 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); | 781 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); |
782 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | 782 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); |
783 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | 783 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); |
784 | 784 |
785 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | 785 if(besr.deinterlace_on) OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); |
786 #ifdef RAGE128 | 786 #ifdef RAGE128 |
787 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | | 787 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | |
788 (besr.saturation << 8) | | 788 (besr.saturation << 8) | |
789 (besr.saturation << 16)); | 789 (besr.saturation << 16)); |
790 #endif | 790 #endif |
1221 itu_space); | 1221 itu_space); |
1222 #endif | 1222 #endif |
1223 return 0; | 1223 return 0; |
1224 } | 1224 } |
1225 | 1225 |
1226 int vixPlaybackSetDeint( const vidix_deinterlace_t * info) | |
1227 { | |
1228 unsigned sflg; | |
1229 switch(info->flags) | |
1230 { | |
1231 default: | |
1232 case CFG_NON_INTERLACED: | |
1233 besr.deinterlace_on = 0; | |
1234 break; | |
1235 case CFG_EVEN_ODD_INTERLACING: | |
1236 case CFG_INTERLACED: | |
1237 besr.deinterlace_on = 1; | |
1238 besr.deinterlace_pattern = 0x900AAAAA; | |
1239 break; | |
1240 case CFG_ODD_EVEN_INTERLACING: | |
1241 besr.deinterlace_on = 1; | |
1242 besr.deinterlace_pattern = 0x00055555; | |
1243 break; | |
1244 case CFG_UNIQUE_INTERLACING: | |
1245 besr.deinterlace_on = 1; | |
1246 besr.deinterlace_pattern = info->deinterlace_pattern; | |
1247 break; | |
1248 } | |
1249 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1250 radeon_engine_idle(); | |
1251 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1252 radeon_fifo_wait(15); | |
1253 sflg = INREG(OV0_SCALE_CNTL); | |
1254 if(besr.deinterlace_on) | |
1255 { | |
1256 OUTREG(OV0_SCALE_CNTL,sflg | SCALER_ADAPTIVE_DEINT); | |
1257 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
1258 } | |
1259 else OUTREG(OV0_SCALE_CNTL,sflg & (~SCALER_ADAPTIVE_DEINT)); | |
1260 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
1261 return 0; | |
1262 } | |
1263 | |
1264 int vixPlaybackGetDeint( vidix_deinterlace_t * info) | |
1265 { | |
1266 if(!besr.deinterlace_on) info->flags = CFG_NON_INTERLACED; | |
1267 else | |
1268 { | |
1269 info->flags = CFG_UNIQUE_INTERLACING; | |
1270 info->deinterlace_pattern = besr.deinterlace_pattern; | |
1271 } | |
1272 return 0; | |
1273 } |