Mercurial > mplayer.hg
annotate vidix/drivers/radeon_vid.c @ 4611:7b793875a640
Get(Set) deinterlacing
author | nick |
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date | Sat, 09 Feb 2002 15:14:48 +0000 |
parents | e9928913a61d |
children | a093bb34b723 |
rev | line source |
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3996 | 1 /* |
2 radeon_vid - VIDIX based video driver for Radeon and Rage128 chips | |
4030 | 3 Copyrights 2002 Nick Kurshev. This file is based on sources from |
4 GATOS (gatos.sf.net) and X11 (www.xfree86.org) | |
5 Licence: GPL | |
3996 | 6 */ |
7 | |
8 #include <errno.h> | |
9 #include <stdio.h> | |
10 #include <stdlib.h> | |
11 #include <string.h> | |
12 #include <math.h> | |
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stdint.h replaced by inttypes.h (used more frequently in the sources)
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13 #include <inttypes.h> |
4201 | 14 #include "../../libdha/pci_ids.h" |
15 #include "../../libdha/pci_names.h" | |
3996 | 16 #include "../vidix.h" |
17 #include "../fourcc.h" | |
18 #include "../../libdha/libdha.h" | |
19 #include "radeon.h" | |
20 | |
21 #ifdef RAGE128 | |
22 #define RADEON_MSG "Rage128_vid:" | |
23 #define X_ADJUST 0 | |
24 #else | |
25 #define RADEON_MSG "Radeon_vid:" | |
26 #define X_ADJUST 8 | |
27 #ifndef RADEON | |
28 #define RADEON | |
29 #endif | |
30 #endif | |
31 | |
4030 | 32 static int __verbose = 0; |
4015 | 33 |
3996 | 34 typedef struct bes_registers_s |
35 { | |
36 /* base address of yuv framebuffer */ | |
37 uint32_t yuv_base; | |
38 uint32_t fourcc; | |
39 uint32_t dest_bpp; | |
40 /* YUV BES registers */ | |
41 uint32_t reg_load_cntl; | |
42 uint32_t h_inc; | |
43 uint32_t step_by; | |
44 uint32_t y_x_start; | |
45 uint32_t y_x_end; | |
46 uint32_t v_inc; | |
47 uint32_t p1_blank_lines_at_top; | |
48 uint32_t p23_blank_lines_at_top; | |
49 uint32_t vid_buf_pitch0_value; | |
50 uint32_t vid_buf_pitch1_value; | |
51 uint32_t p1_x_start_end; | |
52 uint32_t p2_x_start_end; | |
53 uint32_t p3_x_start_end; | |
54 uint32_t base_addr; | |
55 uint32_t vid_buf0_base_adrs; | |
56 uint32_t vid_buf1_base_adrs; | |
57 uint32_t vid_buf2_base_adrs; | |
58 uint32_t vid_buf3_base_adrs; | |
59 uint32_t vid_buf4_base_adrs; | |
60 uint32_t vid_buf5_base_adrs; | |
61 | |
62 uint32_t p1_v_accum_init; | |
63 uint32_t p1_h_accum_init; | |
64 uint32_t p23_v_accum_init; | |
65 uint32_t p23_h_accum_init; | |
66 uint32_t scale_cntl; | |
67 uint32_t exclusive_horz; | |
68 uint32_t auto_flip_cntl; | |
69 uint32_t filter_cntl; | |
70 uint32_t key_cntl; | |
71 uint32_t test; | |
72 /* Configurable stuff */ | |
73 int double_buff; | |
74 | |
75 int brightness; | |
76 int saturation; | |
77 | |
78 int ckey_on; | |
79 uint32_t graphics_key_clr; | |
80 uint32_t graphics_key_msk; | |
81 | |
82 int deinterlace_on; | |
83 uint32_t deinterlace_pattern; | |
84 | |
85 } bes_registers_t; | |
86 | |
87 typedef struct video_registers_s | |
88 { | |
89 const char * sname; | |
90 uint32_t name; | |
91 uint32_t value; | |
92 }video_registers_t; | |
93 | |
94 static bes_registers_t besr; | |
95 #ifndef RAGE128 | |
96 static int IsR200=0; | |
97 #endif | |
98 #define DECLARE_VREG(name) { #name, name, 0 } | |
99 static video_registers_t vregs[] = | |
100 { | |
101 DECLARE_VREG(VIDEOMUX_CNTL), | |
102 DECLARE_VREG(VIPPAD_MASK), | |
103 DECLARE_VREG(VIPPAD1_A), | |
104 DECLARE_VREG(VIPPAD1_EN), | |
105 DECLARE_VREG(VIPPAD1_Y), | |
106 DECLARE_VREG(OV0_Y_X_START), | |
107 DECLARE_VREG(OV0_Y_X_END), | |
108 DECLARE_VREG(OV0_PIPELINE_CNTL), | |
109 DECLARE_VREG(OV0_EXCLUSIVE_HORZ), | |
110 DECLARE_VREG(OV0_EXCLUSIVE_VERT), | |
111 DECLARE_VREG(OV0_REG_LOAD_CNTL), | |
112 DECLARE_VREG(OV0_SCALE_CNTL), | |
113 DECLARE_VREG(OV0_V_INC), | |
114 DECLARE_VREG(OV0_P1_V_ACCUM_INIT), | |
115 DECLARE_VREG(OV0_P23_V_ACCUM_INIT), | |
116 DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), | |
117 DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), | |
118 #ifdef RADEON | |
119 DECLARE_VREG(OV0_BASE_ADDR), | |
120 #endif | |
121 DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), | |
122 DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), | |
123 DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), | |
124 DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), | |
125 DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), | |
126 DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), | |
127 DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), | |
128 DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), | |
129 DECLARE_VREG(OV0_AUTO_FLIP_CNTL), | |
130 DECLARE_VREG(OV0_DEINTERLACE_PATTERN), | |
131 DECLARE_VREG(OV0_SUBMIT_HISTORY), | |
132 DECLARE_VREG(OV0_H_INC), | |
133 DECLARE_VREG(OV0_STEP_BY), | |
134 DECLARE_VREG(OV0_P1_H_ACCUM_INIT), | |
135 DECLARE_VREG(OV0_P23_H_ACCUM_INIT), | |
136 DECLARE_VREG(OV0_P1_X_START_END), | |
137 DECLARE_VREG(OV0_P2_X_START_END), | |
138 DECLARE_VREG(OV0_P3_X_START_END), | |
139 DECLARE_VREG(OV0_FILTER_CNTL), | |
140 DECLARE_VREG(OV0_FOUR_TAP_COEF_0), | |
141 DECLARE_VREG(OV0_FOUR_TAP_COEF_1), | |
142 DECLARE_VREG(OV0_FOUR_TAP_COEF_2), | |
143 DECLARE_VREG(OV0_FOUR_TAP_COEF_3), | |
144 DECLARE_VREG(OV0_FOUR_TAP_COEF_4), | |
145 DECLARE_VREG(OV0_FLAG_CNTL), | |
146 #ifdef RAGE128 | |
147 DECLARE_VREG(OV0_COLOUR_CNTL), | |
148 #else | |
149 DECLARE_VREG(OV0_SLICE_CNTL), | |
150 #endif | |
151 DECLARE_VREG(OV0_VID_KEY_CLR), | |
152 DECLARE_VREG(OV0_VID_KEY_MSK), | |
153 DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), | |
154 DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), | |
155 DECLARE_VREG(OV0_KEY_CNTL), | |
156 DECLARE_VREG(OV0_TEST), | |
157 DECLARE_VREG(OV0_LIN_TRANS_A), | |
158 DECLARE_VREG(OV0_LIN_TRANS_B), | |
159 DECLARE_VREG(OV0_LIN_TRANS_C), | |
160 DECLARE_VREG(OV0_LIN_TRANS_D), | |
161 DECLARE_VREG(OV0_LIN_TRANS_E), | |
162 DECLARE_VREG(OV0_LIN_TRANS_F), | |
163 DECLARE_VREG(OV0_GAMMA_0_F), | |
164 DECLARE_VREG(OV0_GAMMA_10_1F), | |
165 DECLARE_VREG(OV0_GAMMA_20_3F), | |
166 DECLARE_VREG(OV0_GAMMA_40_7F), | |
167 DECLARE_VREG(OV0_GAMMA_380_3BF), | |
168 DECLARE_VREG(OV0_GAMMA_3C0_3FF), | |
169 DECLARE_VREG(SUBPIC_CNTL), | |
170 DECLARE_VREG(SUBPIC_DEFCOLCON), | |
171 DECLARE_VREG(SUBPIC_Y_X_START), | |
172 DECLARE_VREG(SUBPIC_Y_X_END), | |
173 DECLARE_VREG(SUBPIC_V_INC), | |
174 DECLARE_VREG(SUBPIC_H_INC), | |
175 DECLARE_VREG(SUBPIC_BUF0_OFFSET), | |
176 DECLARE_VREG(SUBPIC_BUF1_OFFSET), | |
177 DECLARE_VREG(SUBPIC_LC0_OFFSET), | |
178 DECLARE_VREG(SUBPIC_LC1_OFFSET), | |
179 DECLARE_VREG(SUBPIC_PITCH), | |
180 DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), | |
181 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), | |
182 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), | |
183 DECLARE_VREG(SUBPIC_PALETTE_INDEX), | |
184 DECLARE_VREG(SUBPIC_PALETTE_DATA), | |
185 DECLARE_VREG(SUBPIC_H_ACCUM_INIT), | |
186 DECLARE_VREG(SUBPIC_V_ACCUM_INIT), | |
187 DECLARE_VREG(IDCT_RUNS), | |
188 DECLARE_VREG(IDCT_LEVELS), | |
189 DECLARE_VREG(IDCT_AUTH_CONTROL), | |
190 DECLARE_VREG(IDCT_AUTH), | |
191 DECLARE_VREG(IDCT_CONTROL) | |
192 }; | |
4030 | 193 |
3996 | 194 static void * radeon_mmio_base = 0; |
195 static void * radeon_mem_base = 0; | |
196 static int32_t radeon_overlay_off = 0; | |
197 static uint32_t radeon_ram_size = 0; | |
198 | |
4012 | 199 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) |
200 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
201 | |
202 #define INREG8(addr) GETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr) | |
203 #define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr,val) | |
204 #define INREG(addr) GETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr) | |
205 #define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,val) | |
3996 | 206 #define OUTREGP(addr,val,mask) \ |
207 do { \ | |
208 unsigned int _tmp = INREG(addr); \ | |
209 _tmp &= (mask); \ | |
210 _tmp |= (val); \ | |
211 OUTREG(addr, _tmp); \ | |
212 } while (0) | |
213 | |
214 static uint32_t radeon_vid_get_dbpp( void ) | |
215 { | |
216 uint32_t dbpp,retval; | |
217 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; | |
218 switch(dbpp) | |
219 { | |
220 case DST_8BPP: retval = 8; break; | |
221 case DST_15BPP: retval = 15; break; | |
222 case DST_16BPP: retval = 16; break; | |
223 case DST_24BPP: retval = 24; break; | |
224 default: retval=32; break; | |
225 } | |
226 return retval; | |
227 } | |
228 | |
229 static int radeon_is_dbl_scan( void ) | |
230 { | |
231 return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; | |
232 } | |
233 | |
234 static int radeon_is_interlace( void ) | |
235 { | |
236 return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; | |
237 } | |
238 | |
239 static __inline__ void radeon_engine_flush ( void ) | |
240 { | |
241 int i; | |
242 | |
243 /* initiate flush */ | |
244 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, | |
245 ~RB2D_DC_FLUSH_ALL); | |
246 | |
247 for (i=0; i < 2000000; i++) { | |
248 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) | |
249 break; | |
250 } | |
251 } | |
252 | |
253 | |
254 static __inline__ void _radeon_fifo_wait (unsigned entries) | |
255 { | |
256 int i; | |
257 | |
258 for (i=0; i<2000000; i++) | |
259 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) | |
260 return; | |
261 } | |
262 | |
263 | |
264 static __inline__ void _radeon_engine_idle ( void ) | |
265 { | |
266 int i; | |
267 | |
268 /* ensure FIFO is empty before waiting for idle */ | |
269 _radeon_fifo_wait (64); | |
270 | |
271 for (i=0; i<2000000; i++) { | |
272 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { | |
273 radeon_engine_flush (); | |
274 return; | |
275 } | |
276 } | |
277 } | |
278 | |
279 #define radeon_engine_idle() _radeon_engine_idle() | |
280 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) | |
281 | |
282 | |
283 #ifndef RAGE128 | |
284 /* Reference color space transform data */ | |
285 typedef struct tagREF_TRANSFORM | |
286 { | |
287 float RefLuma; | |
288 float RefRCb; | |
289 float RefRCr; | |
290 float RefGCb; | |
291 float RefGCr; | |
292 float RefBCb; | |
293 float RefBCr; | |
294 } REF_TRANSFORM; | |
295 | |
296 /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ | |
297 REF_TRANSFORM trans[2] = | |
298 { | |
299 {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ | |
300 {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ | |
301 }; | |
302 /**************************************************************************** | |
303 * SetTransform * | |
304 * Function: Calculates and sets color space transform from supplied * | |
305 * reference transform, gamma, brightness, contrast, hue and * | |
306 * saturation. * | |
307 * Inputs: bright - brightness * | |
308 * cont - contrast * | |
309 * sat - saturation * | |
310 * hue - hue * | |
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311 * red_intensity - intense of red component * |
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312 * green_intensity - intense of green component * |
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313 * blue_intensity - intense of blue component * |
3996 | 314 * ref - index to the table of refernce transforms * |
315 * Outputs: NONE * | |
316 ****************************************************************************/ | |
317 | |
318 static void radeon_set_transform(float bright, float cont, float sat, | |
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319 float hue, float red_intensity, |
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320 float green_intensity,float blue_intensity, |
4284 | 321 unsigned ref) |
3996 | 322 { |
323 float OvHueSin, OvHueCos; | |
324 float CAdjLuma, CAdjOff; | |
4284 | 325 float RedAdj,GreenAdj,BlueAdj; |
3996 | 326 float CAdjRCb, CAdjRCr; |
327 float CAdjGCb, CAdjGCr; | |
328 float CAdjBCb, CAdjBCr; | |
329 float OvLuma, OvROff, OvGOff, OvBOff; | |
330 float OvRCb, OvRCr; | |
331 float OvGCb, OvGCr; | |
332 float OvBCb, OvBCr; | |
333 float Loff = 64.0; | |
334 float Coff = 512.0f; | |
335 | |
336 uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; | |
337 uint32_t dwOvRCb, dwOvRCr; | |
338 uint32_t dwOvGCb, dwOvGCr; | |
339 uint32_t dwOvBCb, dwOvBCr; | |
340 | |
341 if (ref >= 2) return; | |
342 | |
343 OvHueSin = sin((double)hue); | |
344 OvHueCos = cos((double)hue); | |
345 | |
346 CAdjLuma = cont * trans[ref].RefLuma; | |
347 CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; | |
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348 RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0; |
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349 GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0; |
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350 BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0; |
3996 | 351 |
352 CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; | |
353 CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; | |
354 CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); | |
355 CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); | |
356 CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; | |
357 CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; | |
358 | |
359 #if 0 /* default constants */ | |
360 CAdjLuma = 1.16455078125; | |
361 | |
362 CAdjRCb = 0.0; | |
363 CAdjRCr = 1.59619140625; | |
364 CAdjGCb = -0.39111328125; | |
365 CAdjGCr = -0.8125; | |
366 CAdjBCb = 2.01708984375; | |
367 CAdjBCr = 0; | |
368 #endif | |
369 OvLuma = CAdjLuma; | |
370 OvRCb = CAdjRCb; | |
371 OvRCr = CAdjRCr; | |
372 OvGCb = CAdjGCb; | |
373 OvGCr = CAdjGCr; | |
374 OvBCb = CAdjBCb; | |
375 OvBCr = CAdjBCr; | |
4284 | 376 OvROff = RedAdj + CAdjOff - |
3996 | 377 OvLuma * Loff - (OvRCb + OvRCr) * Coff; |
4284 | 378 OvGOff = GreenAdj + CAdjOff - |
3996 | 379 OvLuma * Loff - (OvGCb + OvGCr) * Coff; |
4284 | 380 OvBOff = BlueAdj + CAdjOff - |
3996 | 381 OvLuma * Loff - (OvBCb + OvBCr) * Coff; |
382 #if 0 /* default constants */ | |
383 OvROff = -888.5; | |
384 OvGOff = 545; | |
385 OvBOff = -1104; | |
386 #endif | |
387 | |
388 dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; | |
389 dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; | |
390 dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; | |
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391 /* Whatever docs say about R200 having 3.8 format instead of 3.11 |
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392 as in Radeon is a lie */ |
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393 #if 0 |
3996 | 394 if(!IsR200) |
395 { | |
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396 #endif |
3996 | 397 dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; |
398 dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; | |
399 dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; | |
400 dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; | |
401 dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; | |
402 dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; | |
403 dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; | |
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404 #if 0 |
3996 | 405 } |
406 else | |
407 { | |
408 dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; | |
409 dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; | |
410 dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; | |
411 dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; | |
412 dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; | |
413 dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; | |
414 dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; | |
415 } | |
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416 #endif |
3996 | 417 OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); |
418 OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); | |
419 OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); | |
420 OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); | |
421 OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); | |
422 OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); | |
423 } | |
424 | |
425 /* Gamma curve definition */ | |
426 typedef struct | |
427 { | |
428 unsigned int gammaReg; | |
429 unsigned int gammaSlope; | |
430 unsigned int gammaOffset; | |
431 }GAMMA_SETTINGS; | |
432 | |
433 /* Recommended gamma curve parameters */ | |
434 GAMMA_SETTINGS r200_def_gamma[18] = | |
435 { | |
436 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
437 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
438 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
439 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
440 {OV0_GAMMA_80_BF, 0x100, 0x0100}, | |
441 {OV0_GAMMA_C0_FF, 0x100, 0x0100}, | |
442 {OV0_GAMMA_100_13F, 0x100, 0x0200}, | |
443 {OV0_GAMMA_140_17F, 0x100, 0x0200}, | |
444 {OV0_GAMMA_180_1BF, 0x100, 0x0300}, | |
445 {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, | |
446 {OV0_GAMMA_200_23F, 0x100, 0x0400}, | |
447 {OV0_GAMMA_240_27F, 0x100, 0x0400}, | |
448 {OV0_GAMMA_280_2BF, 0x100, 0x0500}, | |
449 {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, | |
450 {OV0_GAMMA_300_33F, 0x100, 0x0600}, | |
451 {OV0_GAMMA_340_37F, 0x100, 0x0600}, | |
452 {OV0_GAMMA_380_3BF, 0x100, 0x0700}, | |
453 {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} | |
454 }; | |
455 | |
456 GAMMA_SETTINGS r100_def_gamma[6] = | |
457 { | |
458 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
459 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
460 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
461 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
462 {OV0_GAMMA_380_3BF, 0x100, 0x0100}, | |
463 {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} | |
464 }; | |
465 | |
466 static void make_default_gamma_correction( void ) | |
467 { | |
468 size_t i; | |
469 if(!IsR200){ | |
470 OUTREG(OV0_LIN_TRANS_A, 0x12A00000); | |
471 OUTREG(OV0_LIN_TRANS_B, 0x199018FE); | |
472 OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); | |
473 OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); | |
474 OUTREG(OV0_LIN_TRANS_E, 0x12A02050); | |
475 OUTREG(OV0_LIN_TRANS_F, 0x0000174E); | |
476 for(i=0; i<6; i++){ | |
477 OUTREG(r100_def_gamma[i].gammaReg, | |
478 (r100_def_gamma[i].gammaSlope<<16) | | |
479 r100_def_gamma[i].gammaOffset); | |
480 } | |
481 } | |
482 else{ | |
483 OUTREG(OV0_LIN_TRANS_A, 0x12a00000); | |
484 OUTREG(OV0_LIN_TRANS_B, 0x1990190e); | |
485 OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); | |
486 OUTREG(OV0_LIN_TRANS_D, 0xf3000442); | |
487 OUTREG(OV0_LIN_TRANS_E, 0x12a02040); | |
488 OUTREG(OV0_LIN_TRANS_F, 0x175f); | |
489 | |
490 /* Default Gamma, | |
491 Of 18 segments for gamma cure, all segments in R200 are programmable, | |
492 while only lower 4 and upper 2 segments are programmable in Radeon*/ | |
493 for(i=0; i<18; i++){ | |
494 OUTREG(r200_def_gamma[i].gammaReg, | |
495 (r200_def_gamma[i].gammaSlope<<16) | | |
496 r200_def_gamma[i].gammaOffset); | |
497 } | |
498 } | |
499 } | |
500 #endif | |
501 | |
502 static void radeon_vid_make_default(void) | |
503 { | |
504 #ifdef RAGE128 | |
505 OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brihgtness and saturation for Rage128 */ | |
506 #else | |
507 make_default_gamma_correction(); | |
508 #endif | |
509 besr.deinterlace_pattern = 0x900AAAAA; | |
510 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
511 besr.deinterlace_on=1; | |
512 besr.double_buff=1; | |
513 } | |
514 | |
515 | |
516 unsigned vixGetVersion( void ) { return VIDIX_VERSION; } | |
517 | |
4107 | 518 static unsigned short ati_card_ids[] = |
3996 | 519 { |
520 #ifdef RAGE128 | |
521 /* | |
522 This driver should be compatible with Rage128 (pro) chips. | |
523 (include adaptive deinterlacing!!!). | |
524 Moreover: the same logic can be used with Mach64 chips. | |
525 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
526 but they are incompatible by i/o ports. So if enthusiasts will want | |
527 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
528 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
529 fourccs (422 and 420 formats only). | |
530 */ | |
531 /* Rage128 Pro GL */ | |
4107 | 532 DEVICE_ATI_RAGE_128_PA_PRO, |
533 DEVICE_ATI_RAGE_128_PB_PRO, | |
534 DEVICE_ATI_RAGE_128_PC_PRO, | |
535 DEVICE_ATI_RAGE_128_PD_PRO, | |
536 DEVICE_ATI_RAGE_128_PE_PRO, | |
537 DEVICE_ATI_RAGE_128_PF_PRO, | |
3996 | 538 /* Rage128 Pro VR */ |
4107 | 539 DEVICE_ATI_RAGE_128_PG_PRO, |
540 DEVICE_ATI_RAGE_128_PH_PRO, | |
541 DEVICE_ATI_RAGE_128_PI_PRO, | |
542 DEVICE_ATI_RAGE_128_PJ_PRO, | |
543 DEVICE_ATI_RAGE_128_PK_PRO, | |
544 DEVICE_ATI_RAGE_128_PL_PRO, | |
545 DEVICE_ATI_RAGE_128_PM_PRO, | |
546 DEVICE_ATI_RAGE_128_PN_PRO, | |
547 DEVICE_ATI_RAGE_128_PO_PRO, | |
548 DEVICE_ATI_RAGE_128_PP_PRO, | |
549 DEVICE_ATI_RAGE_128_PQ_PRO, | |
550 DEVICE_ATI_RAGE_128_PR_PRO, | |
551 DEVICE_ATI_RAGE_128_PS_PRO, | |
552 DEVICE_ATI_RAGE_128_PT_PRO, | |
553 DEVICE_ATI_RAGE_128_PU_PRO, | |
554 DEVICE_ATI_RAGE_128_PV_PRO, | |
555 DEVICE_ATI_RAGE_128_PW_PRO, | |
556 DEVICE_ATI_RAGE_128_PX_PRO, | |
3996 | 557 /* Rage128 GL */ |
4107 | 558 DEVICE_ATI_RAGE_128_RE_SG, |
559 DEVICE_ATI_RAGE_128_RF_SG, | |
560 DEVICE_ATI_RAGE_128_RG, | |
561 DEVICE_ATI_RAGE_128_RK_VR, | |
562 DEVICE_ATI_RAGE_128_RL_VR, | |
563 DEVICE_ATI_RAGE_128_SE_4X, | |
564 DEVICE_ATI_RAGE_128_SF_4X, | |
565 DEVICE_ATI_RAGE_128_SG_4X, | |
566 DEVICE_ATI_RAGE_128_4X, | |
567 DEVICE_ATI_RAGE_128_SK_4X, | |
568 DEVICE_ATI_RAGE_128_SL_4X, | |
569 DEVICE_ATI_RAGE_128_SM_4X, | |
570 DEVICE_ATI_RAGE_128_4X2, | |
571 DEVICE_ATI_RAGE_128_PRO, | |
572 DEVICE_ATI_RAGE_128_PRO2, | |
573 DEVICE_ATI_RAGE_128_PRO3 | |
3996 | 574 #else |
575 /* Radeons (indeed: Rage 256 Pro ;) */ | |
4107 | 576 DEVICE_ATI_RADEON_8500_DV, |
577 DEVICE_ATI_RADEON_MOBILITY_M6, | |
578 DEVICE_ATI_RADEON_MOBILITY_M62, | |
579 DEVICE_ATI_RADEON_MOBILITY_M63, | |
580 DEVICE_ATI_RADEON_QD, | |
581 DEVICE_ATI_RADEON_QE, | |
582 DEVICE_ATI_RADEON_QF, | |
583 DEVICE_ATI_RADEON_QG, | |
584 DEVICE_ATI_RADEON_QL, | |
585 DEVICE_ATI_RADEON_QW, | |
586 DEVICE_ATI_RADEON_VE_QY, | |
587 DEVICE_ATI_RADEON_VE_QZ | |
3996 | 588 #endif |
589 }; | |
590 | |
591 static int find_chip(unsigned chip_id) | |
592 { | |
593 unsigned i; | |
4107 | 594 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) |
3996 | 595 { |
4107 | 596 if(chip_id == ati_card_ids[i]) return i; |
3996 | 597 } |
598 return -1; | |
599 } | |
600 | |
601 pciinfo_t pci_info; | |
602 static int probed=0; | |
603 | |
604 vidix_capability_t def_cap = | |
605 { | |
606 #ifdef RAGE128 | |
607 "BES driver for rage128 cards", | |
608 #else | |
609 "BES driver for radeon cards", | |
610 #endif | |
4327 | 611 "Nick Kurshev", |
3996 | 612 TYPE_OUTPUT | TYPE_FX, |
4191 | 613 { 0, 0, 0, 0 }, |
4282 | 614 2048, |
615 2048, | |
3996 | 616 4, |
617 4, | |
618 -1, | |
4264 | 619 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, |
4134 | 620 VENDOR_ATI, |
3996 | 621 0, |
622 { 0, 0, 0, 0} | |
623 }; | |
624 | |
625 | |
4191 | 626 int vixProbe( int verbose,int force ) |
3996 | 627 { |
628 pciinfo_t lst[MAX_PCI_DEVICES]; | |
629 unsigned i,num_pci; | |
630 int err; | |
4030 | 631 __verbose = verbose; |
3996 | 632 err = pci_scan(lst,&num_pci); |
633 if(err) | |
634 { | |
635 printf(RADEON_MSG" Error occured during pci scan: %s\n",strerror(err)); | |
636 return err; | |
637 } | |
638 else | |
639 { | |
640 err = ENXIO; | |
641 for(i=0;i<num_pci;i++) | |
642 { | |
4107 | 643 if(lst[i].vendor == VENDOR_ATI) |
3996 | 644 { |
645 int idx; | |
4191 | 646 const char *dname; |
3996 | 647 idx = find_chip(lst[i].device); |
4191 | 648 if(idx == -1 && force == PROBE_NORMAL) continue; |
649 dname = pci_device_name(VENDOR_ATI,lst[i].device); | |
650 dname = dname ? dname : "Unknown chip"; | |
651 printf(RADEON_MSG" Found chip: %s\n",dname); | |
3996 | 652 #ifndef RAGE128 |
4191 | 653 if(idx != -1) |
654 if(ati_card_ids[idx] == DEVICE_ATI_RADEON_QL || | |
655 ati_card_ids[idx] == DEVICE_ATI_RADEON_8500_DV || | |
656 ati_card_ids[idx] == DEVICE_ATI_RADEON_QW) IsR200 = 1; | |
3996 | 657 #endif |
4193 | 658 if(force > PROBE_NORMAL) |
659 { | |
660 printf(RADEON_MSG" Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); | |
661 if(idx == -1) | |
662 #ifdef RAGE128 | |
4373 | 663 printf(RADEON_MSG" Assuming it as Rage128\n"); |
4193 | 664 #else |
4373 | 665 printf(RADEON_MSG" Assuming it as Radeon1\n"); |
4193 | 666 #endif |
667 } | |
4191 | 668 def_cap.device_id = lst[i].device; |
3996 | 669 err = 0; |
670 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); | |
671 probed=1; | |
672 break; | |
673 } | |
674 } | |
675 } | |
676 if(err && verbose) printf(RADEON_MSG" Can't find chip\n"); | |
677 return err; | |
678 } | |
679 | |
680 int vixInit( void ) | |
681 { | |
4477 | 682 int err; |
4012 | 683 if(!probed) |
684 { | |
685 printf(RADEON_MSG" Driver was not probed but is being initializing\n"); | |
686 return EINTR; | |
687 } | |
688 if((radeon_mmio_base = map_phys_mem(pci_info.base2,0xFFFF))==(void *)-1) return ENOMEM; | |
3996 | 689 radeon_ram_size = INREG(CONFIG_MEMSIZE); |
690 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ | |
691 radeon_ram_size &= CONFIG_MEMSIZE_MASK; | |
692 if((radeon_mem_base = map_phys_mem(pci_info.base0,radeon_ram_size))==(void *)-1) return ENOMEM; | |
4070
b61ba6c256dd
Minor interface changes: color and video keys are moved out from playback configuring
nick
parents:
4038
diff
changeset
|
693 memset(&besr,0,sizeof(bes_registers_t)); |
3996 | 694 radeon_vid_make_default(); |
695 printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); | |
4477 | 696 err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB); |
697 if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n"); | |
3996 | 698 return 0; |
699 } | |
700 | |
701 void vixDestroy( void ) | |
702 { | |
703 unmap_phys_mem(radeon_mem_base,radeon_ram_size); | |
704 unmap_phys_mem(radeon_mmio_base,0x7FFF); | |
705 } | |
706 | |
707 int vixGetCapability(vidix_capability_t *to) | |
708 { | |
709 memcpy(to,&def_cap,sizeof(vidix_capability_t)); | |
710 return 0; | |
711 } | |
712 | |
713 uint32_t supported_fourcc[] = | |
714 { | |
715 IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV, | |
4455 | 716 IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU, |
4429 | 717 IMGFMT_RGB15, IMGFMT_BGR15, |
4416 | 718 IMGFMT_RGB16, IMGFMT_BGR16, |
719 IMGFMT_RGB32, IMGFMT_BGR32 | |
3996 | 720 }; |
721 | |
722 __inline__ static int is_supported_fourcc(uint32_t fourcc) | |
723 { | |
724 unsigned i; | |
725 for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++) | |
726 { | |
727 if(fourcc==supported_fourcc[i]) return 1; | |
728 } | |
729 return 0; | |
730 } | |
731 | |
732 int vixQueryFourcc(vidix_fourcc_t *to) | |
733 { | |
734 if(is_supported_fourcc(to->fourcc)) | |
735 { | |
736 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
737 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
738 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
739 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
740 VID_DEPTH_32BPP; | |
741 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK; | |
742 return 0; | |
743 } | |
4015 | 744 else to->depth = to->flags = 0; |
3996 | 745 return ENOSYS; |
746 } | |
747 | |
748 static void radeon_vid_dump_regs( void ) | |
749 { | |
750 size_t i; | |
4015 | 751 printf(RADEON_MSG"*** Begin of DRIVER variables dump ***\n"); |
752 printf(RADEON_MSG"radeon_mmio_base=%p\n",radeon_mmio_base); | |
753 printf(RADEON_MSG"radeon_mem_base=%p\n",radeon_mem_base); | |
754 printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off); | |
755 printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size); | |
756 printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n"); | |
3996 | 757 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) |
4015 | 758 printf(RADEON_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); |
759 printf(RADEON_MSG"*** End of OV0 registers dump ***\n"); | |
3996 | 760 } |
761 | |
762 static void radeon_vid_stop_video( void ) | |
763 { | |
764 radeon_engine_idle(); | |
765 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
766 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
767 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
768 OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); | |
769 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); | |
770 OUTREG(OV0_TEST, 0); | |
771 } | |
772 | |
773 static void radeon_vid_display_video( void ) | |
774 { | |
775 int bes_flags; | |
776 radeon_fifo_wait(2); | |
777 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
778 radeon_engine_idle(); | |
779 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
780 radeon_fifo_wait(15); | |
781 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); | |
782 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
783 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
784 | |
4611 | 785 if(besr.deinterlace_on) OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); |
3996 | 786 #ifdef RAGE128 |
787 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | | |
788 (besr.saturation << 8) | | |
789 (besr.saturation << 16)); | |
790 #endif | |
791 radeon_fifo_wait(2); | |
792 if(besr.ckey_on) | |
793 { | |
794 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); | |
795 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
796 OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_EQ|VIDEO_KEY_FN_FALSE|CMP_MIX_OR); | |
797 } | |
798 else | |
799 { | |
800 OUTREG(OV0_GRAPHICS_KEY_MSK, 0ULL); | |
801 OUTREG(OV0_GRAPHICS_KEY_CLR, 0ULL); | |
802 OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_NE); | |
803 } | |
804 | |
805 OUTREG(OV0_H_INC, besr.h_inc); | |
806 OUTREG(OV0_STEP_BY, besr.step_by); | |
807 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
808 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
809 OUTREG(OV0_V_INC, besr.v_inc); | |
810 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
811 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); | |
812 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); | |
813 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); | |
814 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); | |
815 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
816 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
817 #ifdef RADEON | |
818 OUTREG(OV0_BASE_ADDR, besr.base_addr); | |
819 #endif | |
820 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs); | |
821 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs); | |
822 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs); | |
823 radeon_fifo_wait(9); | |
824 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs); | |
825 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs); | |
826 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf5_base_adrs); | |
827 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); | |
828 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
829 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
830 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); | |
831 | |
832 bes_flags = SCALER_ENABLE | | |
833 SCALER_SMART_SWITCH | | |
834 #ifdef RADEON | |
835 SCALER_HORZ_PICK_NEAREST; | |
836 #else | |
837 SCALER_Y2R_TEMP | | |
838 SCALER_PIX_EXPAND; | |
839 #endif | |
840 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; | |
841 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
842 #ifdef RAGE128 | |
843 bes_flags |= SCALER_BURST_PER_PLANE; | |
844 #endif | |
845 switch(besr.fourcc) | |
846 { | |
847 case IMGFMT_RGB15: | |
848 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
4429 | 849 case IMGFMT_RGB16: |
3996 | 850 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; |
4416 | 851 /* |
3996 | 852 case IMGFMT_RGB24: |
853 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
4416 | 854 */ |
3996 | 855 case IMGFMT_RGB32: |
856 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
857 /* 4:1:0*/ | |
858 case IMGFMT_IF09: | |
859 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; | |
860 /* 4:2:0 */ | |
861 case IMGFMT_IYUV: | |
862 case IMGFMT_I420: | |
863 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; | |
864 break; | |
865 /* 4:2:2 */ | |
4455 | 866 case IMGFMT_YVYU: |
3996 | 867 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; |
868 case IMGFMT_YUY2: | |
869 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
870 } | |
871 OUTREG(OV0_SCALE_CNTL, bes_flags); | |
872 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
4030 | 873 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 874 } |
875 | |
4456 | 876 static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) |
4009 | 877 { |
4456 | 878 unsigned pitch,spy,spv,spu; |
879 spy = spv = spu = 0; | |
880 switch(spitch->y) | |
881 { | |
882 case 16: | |
883 case 32: | |
884 case 64: | |
885 case 128: | |
886 case 256: spy = spitch->y; break; | |
887 default: break; | |
888 } | |
889 switch(spitch->u) | |
890 { | |
891 case 16: | |
892 case 32: | |
893 case 64: | |
894 case 128: | |
895 case 256: spu = spitch->u; break; | |
896 default: break; | |
897 } | |
898 switch(spitch->v) | |
899 { | |
900 case 16: | |
901 case 32: | |
902 case 64: | |
903 case 128: | |
904 case 256: spv = spitch->v; break; | |
905 default: break; | |
906 } | |
4009 | 907 switch(fourcc) |
908 { | |
909 /* 4:2:0 */ | |
910 case IMGFMT_IYUV: | |
911 case IMGFMT_YV12: | |
4456 | 912 case IMGFMT_I420: |
913 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; | |
914 else pitch = 32; | |
915 break; | |
916 default: | |
917 if(spy >= 16) pitch = spy; | |
918 else pitch = 16; | |
919 break; | |
4009 | 920 } |
921 return pitch; | |
922 } | |
923 | |
3996 | 924 static int radeon_vid_init_video( vidix_playback_t *config ) |
925 { | |
926 uint32_t tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top; | |
4571 | 927 int is_420,is_rgb32,is_rgb,best_pitch,mpitch; |
3996 | 928 radeon_vid_stop_video(); |
929 left = config->src.x << 16; | |
930 top = config->src.y << 16; | |
931 src_h = config->src.h; | |
932 src_w = config->src.w; | |
4571 | 933 is_420 = is_rgb32 = is_rgb = 0; |
3996 | 934 if(config->fourcc == IMGFMT_YV12 || |
935 config->fourcc == IMGFMT_I420 || | |
936 config->fourcc == IMGFMT_IYUV) is_420 = 1; | |
4416 | 937 if(config->fourcc == IMGFMT_RGB32 || |
938 config->fourcc == IMGFMT_BGR32) is_rgb32 = 1; | |
4571 | 939 if(config->fourcc == IMGFMT_RGB32 || |
940 config->fourcc == IMGFMT_BGR32 || | |
941 config->fourcc == IMGFMT_RGB24 || | |
942 config->fourcc == IMGFMT_BGR24 || | |
943 config->fourcc == IMGFMT_RGB16 || | |
944 config->fourcc == IMGFMT_BGR16 || | |
945 config->fourcc == IMGFMT_RGB15 || | |
946 config->fourcc == IMGFMT_BGR15) is_rgb = 1; | |
4456 | 947 best_pitch = radeon_query_pitch(config->fourcc,&config->src.pitch); |
4415 | 948 mpitch = best_pitch-1; |
3996 | 949 switch(config->fourcc) |
950 { | |
951 /* 4:2:0 */ | |
952 case IMGFMT_IYUV: | |
953 case IMGFMT_YV12: | |
4415 | 954 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; |
4015 | 955 config->dest.pitch.y = |
956 config->dest.pitch.u = | |
4415 | 957 config->dest.pitch.v = best_pitch; |
3996 | 958 break; |
4416 | 959 /* RGB 4:4:4:4 */ |
960 case IMGFMT_RGB32: | |
961 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; | |
962 config->dest.pitch.y = | |
963 config->dest.pitch.u = | |
964 config->dest.pitch.v = best_pitch; | |
965 break; | |
3996 | 966 /* 4:2:2 */ |
4455 | 967 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ |
4415 | 968 pitch = ((src_w*2) + mpitch) & ~mpitch; |
3996 | 969 config->dest.pitch.y = |
970 config->dest.pitch.u = | |
4415 | 971 config->dest.pitch.v = best_pitch; |
3996 | 972 break; |
973 } | |
974 dest_w = config->dest.w; | |
975 dest_h = config->dest.h; | |
976 if(radeon_is_dbl_scan()) dest_h *= 2; | |
977 else | |
978 if(radeon_is_interlace()) dest_h /= 2; | |
979 besr.dest_bpp = radeon_vid_get_dbpp(); | |
980 besr.fourcc = config->fourcc; | |
981 besr.v_inc = (src_h << 20) / dest_h; | |
982 h_inc = (src_w << 12) / dest_w; | |
983 step_by = 1; | |
984 while(h_inc >= (2 << 12)) { | |
985 step_by++; | |
986 h_inc >>= 1; | |
987 } | |
988 | |
989 /* keep everything in 16.16 */ | |
4015 | 990 besr.base_addr = INREG(DISPLAY_BASE_ADDR); |
3996 | 991 if(is_420) |
992 { | |
993 uint32_t d1line,d2line,d3line; | |
994 d1line = top*pitch; | |
995 d2line = src_h*pitch+(d1line>>1); | |
996 d3line = d2line+((src_h*pitch)>>2); | |
997 d1line += (left >> 16) & ~15; | |
998 d2line += (left >> 17) & ~15; | |
999 d3line += (left >> 17) & ~15; | |
1000 config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK; | |
4015 | 1001 config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; |
1002 config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; | |
3996 | 1003 besr.vid_buf0_base_adrs=(radeon_overlay_off+config->offset.y); |
4015 | 1004 besr.vid_buf1_base_adrs=(radeon_overlay_off+config->offset.v)|VIF_BUF1_PITCH_SEL; |
1005 besr.vid_buf2_base_adrs=(radeon_overlay_off+config->offset.u)|VIF_BUF2_PITCH_SEL; | |
3996 | 1006 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) |
1007 { | |
1008 uint32_t tmp; | |
1009 tmp = config->offset.u; | |
1010 config->offset.u = config->offset.v; | |
1011 config->offset.v = tmp; | |
1012 } | |
4414 | 1013 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; |
1014 besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs+config->frame_size; | |
1015 besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs+config->frame_size; | |
3996 | 1016 } |
1017 else | |
1018 { | |
1019 besr.vid_buf0_base_adrs = radeon_overlay_off; | |
1020 config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; | |
1021 besr.vid_buf0_base_adrs += config->offset.y; | |
4414 | 1022 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; |
3996 | 1023 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs; |
4415 | 1024 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; |
4414 | 1025 besr.vid_buf4_base_adrs = besr.vid_buf0_base_adrs; |
1026 besr.vid_buf5_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; | |
3996 | 1027 } |
1028 config->offsets[0] = 0; | |
1029 config->offsets[1] = config->frame_size; | |
1030 | |
1031 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); | |
1032 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1033 ((tmp << 12) & 0xf0000000); | |
1034 | |
1035 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); | |
1036 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1037 ((tmp << 12) & 0x70000000); | |
1038 tmp = (top & 0x0000ffff) + 0x00018000; | |
1039 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) | |
1040 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
1041 | |
1042 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
1043 besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) | |
1044 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; | |
1045 | |
1046 leftUV = (left >> 17) & 15; | |
1047 left = (left >> 16) & 15; | |
4571 | 1048 if(is_rgb && !is_rgb32) h_inc<<=1; |
4416 | 1049 if(is_rgb32) |
4571 | 1050 besr.h_inc = (h_inc >> 1) | ((h_inc >> 1) << 16); |
4416 | 1051 else |
1052 besr.h_inc = h_inc | ((h_inc >> 1) << 16); | |
3996 | 1053 besr.step_by = step_by | (step_by << 8); |
1054 besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16); | |
1055 besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16); | |
1056 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
1057 if(is_420) | |
1058 { | |
1059 src_h = (src_h + 1) >> 1; | |
1060 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
1061 } | |
1062 else besr.p23_blank_lines_at_top = 0; | |
1063 besr.vid_buf_pitch0_value = pitch; | |
1064 besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch; | |
1065 besr.p1_x_start_end = (src_w+left-1)|(left<<16); | |
1066 src_w>>=1; | |
1067 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
1068 besr.p3_x_start_end = besr.p2_x_start_end; | |
1069 return 0; | |
1070 } | |
1071 | |
4009 | 1072 static void radeon_compute_framesize(vidix_playback_t *info) |
1073 { | |
1074 unsigned pitch,awidth; | |
4456 | 1075 pitch = radeon_query_pitch(info->fourcc,&info->src.pitch); |
4033 | 1076 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); |
1077 switch(info->fourcc) | |
1078 { | |
1079 case IMGFMT_I420: | |
1080 case IMGFMT_YV12: | |
1081 case IMGFMT_IYUV: | |
1082 info->frame_size = awidth*info->src.h+(awidth*info->src.h)/2; | |
1083 break; | |
4429 | 1084 case IMGFMT_RGB32: |
1085 case IMGFMT_BGR32: | |
1086 info->frame_size = awidth*info->src.h*4; | |
1087 break; | |
1088 /* YUY2 YVYU, RGB15, RGB16 */ | |
4033 | 1089 default: info->frame_size = awidth*info->src.h*2; |
1090 break; | |
1091 } | |
4009 | 1092 } |
1093 | |
3996 | 1094 int vixConfigPlayback(vidix_playback_t *info) |
1095 { | |
1096 if(!is_supported_fourcc(info->fourcc)) return ENOSYS; | |
1097 if(info->num_frames>2) info->num_frames=2; | |
4009 | 1098 radeon_compute_framesize(info); |
3996 | 1099 radeon_overlay_off = radeon_ram_size - info->frame_size*info->num_frames; |
1100 radeon_overlay_off &= 0xffff0000; | |
1101 if(radeon_overlay_off < 0) return EINVAL; | |
1102 info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off; | |
1103 radeon_vid_init_video(info); | |
1104 return 0; | |
1105 } | |
1106 | |
1107 int vixPlaybackOn( void ) | |
1108 { | |
1109 radeon_vid_display_video(); | |
1110 return 0; | |
1111 } | |
1112 | |
1113 int vixPlaybackOff( void ) | |
1114 { | |
1115 radeon_vid_stop_video(); | |
1116 return 0; | |
1117 } | |
1118 | |
4033 | 1119 int vixPlaybackFrameSelect(unsigned frame) |
3996 | 1120 { |
4412 | 1121 uint32_t off[6]; |
1122 /* | |
1123 buf3-5 always should point onto second buffer for better | |
1124 deinterlacing and TV-in | |
1125 */ | |
3996 | 1126 if(frame%2) |
1127 { | |
4412 | 1128 off[0] = besr.vid_buf3_base_adrs; |
1129 off[1] = besr.vid_buf4_base_adrs; | |
1130 off[2] = besr.vid_buf5_base_adrs; | |
1131 off[3] = besr.vid_buf0_base_adrs; | |
1132 off[4] = besr.vid_buf1_base_adrs; | |
1133 off[5] = besr.vid_buf2_base_adrs; | |
3996 | 1134 } |
1135 else | |
1136 { | |
4412 | 1137 off[0] = besr.vid_buf0_base_adrs; |
1138 off[1] = besr.vid_buf1_base_adrs; | |
1139 off[2] = besr.vid_buf2_base_adrs; | |
1140 off[3] = besr.vid_buf3_base_adrs; | |
1141 off[4] = besr.vid_buf4_base_adrs; | |
1142 off[5] = besr.vid_buf5_base_adrs; | |
3996 | 1143 } |
1144 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1145 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
4412 | 1146 OUTREG(OV0_VID_BUF0_BASE_ADRS, off[0]); |
1147 OUTREG(OV0_VID_BUF1_BASE_ADRS, off[1]); | |
1148 OUTREG(OV0_VID_BUF2_BASE_ADRS, off[2]); | |
4413 | 1149 OUTREG(OV0_VID_BUF3_BASE_ADRS, off[3]); |
1150 OUTREG(OV0_VID_BUF4_BASE_ADRS, off[4]); | |
1151 OUTREG(OV0_VID_BUF5_BASE_ADRS, off[5]); | |
3996 | 1152 OUTREG(OV0_REG_LOAD_CNTL, 0); |
4030 | 1153 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1154 return 0; |
1155 } | |
1156 | |
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1157 vidix_video_eq_t equal = |
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1158 { |
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1159 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION |
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1160 #ifndef RAGE128 |
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1161 | VEQ_CAP_CONTRAST | VEQ_CAP_HUE | VEQ_CAP_RGB_INTENSITY |
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1162 #endif |
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1163 , |
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1164 0, 0, 0, 0, 0, 0, 0, 0 }; |
3996 | 1165 |
1166 int vixPlaybackGetEq( vidix_video_eq_t * eq) | |
1167 { | |
1168 memcpy(eq,&equal,sizeof(vidix_video_eq_t)); | |
1169 return 0; | |
1170 } | |
1171 | |
4229 | 1172 #ifndef RAGE128 |
1173 #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) | |
1174 #define RTFBrightness(a) (((a)*1.0)/2000.0) | |
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1175 #define RTFIntensity(a) (((a)*1.0)/2000.0) |
4229 | 1176 #define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) |
1177 #define RTFHue(a) (((a)*3.1416)/1000.0) | |
1178 #define RTFCheckParam(a) {if((a)<-1000) (a)=-1000; if((a)>1000) (a)=1000;} | |
1179 #endif | |
1180 | |
3996 | 1181 int vixPlaybackSetEq( const vidix_video_eq_t * eq) |
1182 { | |
1183 #ifdef RAGE128 | |
1184 int br,sat; | |
4229 | 1185 #else |
1186 int itu_space; | |
3996 | 1187 #endif |
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1188 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; |
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1189 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; |
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1190 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; |
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1191 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; |
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1192 if(eq->cap & VEQ_CAP_RGB_INTENSITY) |
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1193 { |
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1194 equal.red_intensity = eq->red_intensity; |
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1195 equal.green_intensity = eq->green_intensity; |
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1196 equal.blue_intensity = eq->blue_intensity; |
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1197 } |
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1198 equal.flags = eq->flags; |
3996 | 1199 #ifdef RAGE128 |
1200 br = equal.brightness * 64 / 1000; | |
4229 | 1201 if(br < -64) br = -64; if(br > 63) br = 63; |
4230 | 1202 sat = (equal.saturation + 1000) * 16 / 1000; |
4229 | 1203 if(sat < 0) sat = 0; if(sat > 31) sat = 31; |
3996 | 1204 OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); |
1205 #else | |
4229 | 1206 itu_space = equal.flags == VEQ_FLG_ITU_R_BT_709 ? 1 : 0; |
1207 RTFCheckParam(equal.brightness); | |
1208 RTFCheckParam(equal.saturation); | |
1209 RTFCheckParam(equal.contrast); | |
1210 RTFCheckParam(equal.hue); | |
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1211 RTFCheckParam(equal.red_intensity); |
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1212 RTFCheckParam(equal.green_intensity); |
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1213 RTFCheckParam(equal.blue_intensity); |
4229 | 1214 radeon_set_transform(RTFBrightness(equal.brightness), |
1215 RTFContrast(equal.contrast), | |
1216 RTFSaturation(equal.saturation), | |
1217 RTFHue(equal.hue), | |
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1218 RTFIntensity(equal.red_intensity), |
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1219 RTFIntensity(equal.green_intensity), |
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1220 RTFIntensity(equal.blue_intensity), |
4229 | 1221 itu_space); |
3996 | 1222 #endif |
1223 return 0; | |
1224 } | |
1225 | |
4611 | 1226 int vixPlaybackSetDeint( const vidix_deinterlace_t * info) |
1227 { | |
1228 unsigned sflg; | |
1229 switch(info->flags) | |
1230 { | |
1231 default: | |
1232 case CFG_NON_INTERLACED: | |
1233 besr.deinterlace_on = 0; | |
1234 break; | |
1235 case CFG_EVEN_ODD_INTERLACING: | |
1236 case CFG_INTERLACED: | |
1237 besr.deinterlace_on = 1; | |
1238 besr.deinterlace_pattern = 0x900AAAAA; | |
1239 break; | |
1240 case CFG_ODD_EVEN_INTERLACING: | |
1241 besr.deinterlace_on = 1; | |
1242 besr.deinterlace_pattern = 0x00055555; | |
1243 break; | |
1244 case CFG_UNIQUE_INTERLACING: | |
1245 besr.deinterlace_on = 1; | |
1246 besr.deinterlace_pattern = info->deinterlace_pattern; | |
1247 break; | |
1248 } | |
1249 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1250 radeon_engine_idle(); | |
1251 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1252 radeon_fifo_wait(15); | |
1253 sflg = INREG(OV0_SCALE_CNTL); | |
1254 if(besr.deinterlace_on) | |
1255 { | |
1256 OUTREG(OV0_SCALE_CNTL,sflg | SCALER_ADAPTIVE_DEINT); | |
1257 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
1258 } | |
1259 else OUTREG(OV0_SCALE_CNTL,sflg & (~SCALER_ADAPTIVE_DEINT)); | |
1260 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
1261 return 0; | |
1262 } | |
1263 | |
1264 int vixPlaybackGetDeint( vidix_deinterlace_t * info) | |
1265 { | |
1266 if(!besr.deinterlace_on) info->flags = CFG_NON_INTERLACED; | |
1267 else | |
1268 { | |
1269 info->flags = CFG_UNIQUE_INTERLACING; | |
1270 info->deinterlace_pattern = besr.deinterlace_pattern; | |
1271 } | |
1272 return 0; | |
1273 } |