Mercurial > mplayer.hg
annotate vidix/drivers/radeon_vid.c @ 4264:689531ade0fb
added FLAG_EQUALIZER
author | alex |
---|---|
date | Sat, 19 Jan 2002 18:41:50 +0000 |
parents | 7444f7901ae2 |
children | ae7d42d7b286 |
rev | line source |
---|---|
3996 | 1 /* |
2 radeon_vid - VIDIX based video driver for Radeon and Rage128 chips | |
4030 | 3 Copyrights 2002 Nick Kurshev. This file is based on sources from |
4 GATOS (gatos.sf.net) and X11 (www.xfree86.org) | |
5 Licence: GPL | |
3996 | 6 */ |
7 | |
8 #include <errno.h> | |
9 #include <stdio.h> | |
10 #include <stdlib.h> | |
11 #include <string.h> | |
12 #include <math.h> | |
4003
92c59012249d
stdint.h replaced by inttypes.h (used more frequently in the sources)
pl
parents:
3996
diff
changeset
|
13 #include <inttypes.h> |
4201 | 14 #include "../../libdha/pci_ids.h" |
15 #include "../../libdha/pci_names.h" | |
3996 | 16 #include "../vidix.h" |
17 #include "../fourcc.h" | |
18 #include "../../libdha/libdha.h" | |
19 #include "radeon.h" | |
20 | |
21 #ifdef RAGE128 | |
22 #define RADEON_MSG "Rage128_vid:" | |
23 #define X_ADJUST 0 | |
24 #else | |
25 #define RADEON_MSG "Radeon_vid:" | |
26 #define X_ADJUST 8 | |
27 #ifndef RADEON | |
28 #define RADEON | |
29 #endif | |
30 #endif | |
31 | |
4030 | 32 static int __verbose = 0; |
4015 | 33 |
3996 | 34 typedef struct bes_registers_s |
35 { | |
36 /* base address of yuv framebuffer */ | |
37 uint32_t yuv_base; | |
38 uint32_t fourcc; | |
39 uint32_t dest_bpp; | |
40 /* YUV BES registers */ | |
41 uint32_t reg_load_cntl; | |
42 uint32_t h_inc; | |
43 uint32_t step_by; | |
44 uint32_t y_x_start; | |
45 uint32_t y_x_end; | |
46 uint32_t v_inc; | |
47 uint32_t p1_blank_lines_at_top; | |
48 uint32_t p23_blank_lines_at_top; | |
49 uint32_t vid_buf_pitch0_value; | |
50 uint32_t vid_buf_pitch1_value; | |
51 uint32_t p1_x_start_end; | |
52 uint32_t p2_x_start_end; | |
53 uint32_t p3_x_start_end; | |
54 uint32_t base_addr; | |
55 uint32_t vid_buf0_base_adrs; | |
56 /* These ones are for auto flip: maybe in the future */ | |
57 uint32_t vid_buf1_base_adrs; | |
58 uint32_t vid_buf2_base_adrs; | |
59 uint32_t vid_buf3_base_adrs; | |
60 uint32_t vid_buf4_base_adrs; | |
61 uint32_t vid_buf5_base_adrs; | |
62 | |
63 uint32_t p1_v_accum_init; | |
64 uint32_t p1_h_accum_init; | |
65 uint32_t p23_v_accum_init; | |
66 uint32_t p23_h_accum_init; | |
67 uint32_t scale_cntl; | |
68 uint32_t exclusive_horz; | |
69 uint32_t auto_flip_cntl; | |
70 uint32_t filter_cntl; | |
71 uint32_t key_cntl; | |
72 uint32_t test; | |
73 /* Configurable stuff */ | |
74 int double_buff; | |
75 | |
76 int brightness; | |
77 int saturation; | |
78 | |
79 int ckey_on; | |
80 uint32_t graphics_key_clr; | |
81 uint32_t graphics_key_msk; | |
82 | |
83 int deinterlace_on; | |
84 uint32_t deinterlace_pattern; | |
85 | |
86 } bes_registers_t; | |
87 | |
88 typedef struct video_registers_s | |
89 { | |
90 const char * sname; | |
91 uint32_t name; | |
92 uint32_t value; | |
93 }video_registers_t; | |
94 | |
95 static bes_registers_t besr; | |
96 #ifndef RAGE128 | |
97 static int IsR200=0; | |
98 #endif | |
99 #define DECLARE_VREG(name) { #name, name, 0 } | |
100 static video_registers_t vregs[] = | |
101 { | |
102 DECLARE_VREG(VIDEOMUX_CNTL), | |
103 DECLARE_VREG(VIPPAD_MASK), | |
104 DECLARE_VREG(VIPPAD1_A), | |
105 DECLARE_VREG(VIPPAD1_EN), | |
106 DECLARE_VREG(VIPPAD1_Y), | |
107 DECLARE_VREG(OV0_Y_X_START), | |
108 DECLARE_VREG(OV0_Y_X_END), | |
109 DECLARE_VREG(OV0_PIPELINE_CNTL), | |
110 DECLARE_VREG(OV0_EXCLUSIVE_HORZ), | |
111 DECLARE_VREG(OV0_EXCLUSIVE_VERT), | |
112 DECLARE_VREG(OV0_REG_LOAD_CNTL), | |
113 DECLARE_VREG(OV0_SCALE_CNTL), | |
114 DECLARE_VREG(OV0_V_INC), | |
115 DECLARE_VREG(OV0_P1_V_ACCUM_INIT), | |
116 DECLARE_VREG(OV0_P23_V_ACCUM_INIT), | |
117 DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), | |
118 DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), | |
119 #ifdef RADEON | |
120 DECLARE_VREG(OV0_BASE_ADDR), | |
121 #endif | |
122 DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), | |
123 DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), | |
124 DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), | |
125 DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), | |
126 DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), | |
127 DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), | |
128 DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), | |
129 DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), | |
130 DECLARE_VREG(OV0_AUTO_FLIP_CNTL), | |
131 DECLARE_VREG(OV0_DEINTERLACE_PATTERN), | |
132 DECLARE_VREG(OV0_SUBMIT_HISTORY), | |
133 DECLARE_VREG(OV0_H_INC), | |
134 DECLARE_VREG(OV0_STEP_BY), | |
135 DECLARE_VREG(OV0_P1_H_ACCUM_INIT), | |
136 DECLARE_VREG(OV0_P23_H_ACCUM_INIT), | |
137 DECLARE_VREG(OV0_P1_X_START_END), | |
138 DECLARE_VREG(OV0_P2_X_START_END), | |
139 DECLARE_VREG(OV0_P3_X_START_END), | |
140 DECLARE_VREG(OV0_FILTER_CNTL), | |
141 DECLARE_VREG(OV0_FOUR_TAP_COEF_0), | |
142 DECLARE_VREG(OV0_FOUR_TAP_COEF_1), | |
143 DECLARE_VREG(OV0_FOUR_TAP_COEF_2), | |
144 DECLARE_VREG(OV0_FOUR_TAP_COEF_3), | |
145 DECLARE_VREG(OV0_FOUR_TAP_COEF_4), | |
146 DECLARE_VREG(OV0_FLAG_CNTL), | |
147 #ifdef RAGE128 | |
148 DECLARE_VREG(OV0_COLOUR_CNTL), | |
149 #else | |
150 DECLARE_VREG(OV0_SLICE_CNTL), | |
151 #endif | |
152 DECLARE_VREG(OV0_VID_KEY_CLR), | |
153 DECLARE_VREG(OV0_VID_KEY_MSK), | |
154 DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), | |
155 DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), | |
156 DECLARE_VREG(OV0_KEY_CNTL), | |
157 DECLARE_VREG(OV0_TEST), | |
158 DECLARE_VREG(OV0_LIN_TRANS_A), | |
159 DECLARE_VREG(OV0_LIN_TRANS_B), | |
160 DECLARE_VREG(OV0_LIN_TRANS_C), | |
161 DECLARE_VREG(OV0_LIN_TRANS_D), | |
162 DECLARE_VREG(OV0_LIN_TRANS_E), | |
163 DECLARE_VREG(OV0_LIN_TRANS_F), | |
164 DECLARE_VREG(OV0_GAMMA_0_F), | |
165 DECLARE_VREG(OV0_GAMMA_10_1F), | |
166 DECLARE_VREG(OV0_GAMMA_20_3F), | |
167 DECLARE_VREG(OV0_GAMMA_40_7F), | |
168 DECLARE_VREG(OV0_GAMMA_380_3BF), | |
169 DECLARE_VREG(OV0_GAMMA_3C0_3FF), | |
170 DECLARE_VREG(SUBPIC_CNTL), | |
171 DECLARE_VREG(SUBPIC_DEFCOLCON), | |
172 DECLARE_VREG(SUBPIC_Y_X_START), | |
173 DECLARE_VREG(SUBPIC_Y_X_END), | |
174 DECLARE_VREG(SUBPIC_V_INC), | |
175 DECLARE_VREG(SUBPIC_H_INC), | |
176 DECLARE_VREG(SUBPIC_BUF0_OFFSET), | |
177 DECLARE_VREG(SUBPIC_BUF1_OFFSET), | |
178 DECLARE_VREG(SUBPIC_LC0_OFFSET), | |
179 DECLARE_VREG(SUBPIC_LC1_OFFSET), | |
180 DECLARE_VREG(SUBPIC_PITCH), | |
181 DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), | |
182 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), | |
183 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), | |
184 DECLARE_VREG(SUBPIC_PALETTE_INDEX), | |
185 DECLARE_VREG(SUBPIC_PALETTE_DATA), | |
186 DECLARE_VREG(SUBPIC_H_ACCUM_INIT), | |
187 DECLARE_VREG(SUBPIC_V_ACCUM_INIT), | |
188 DECLARE_VREG(IDCT_RUNS), | |
189 DECLARE_VREG(IDCT_LEVELS), | |
190 DECLARE_VREG(IDCT_AUTH_CONTROL), | |
191 DECLARE_VREG(IDCT_AUTH), | |
192 DECLARE_VREG(IDCT_CONTROL) | |
193 }; | |
4030 | 194 |
3996 | 195 static void * radeon_mmio_base = 0; |
196 static void * radeon_mem_base = 0; | |
197 static int32_t radeon_overlay_off = 0; | |
198 static uint32_t radeon_ram_size = 0; | |
199 | |
4012 | 200 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) |
201 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
202 | |
203 #define INREG8(addr) GETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr) | |
204 #define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr,val) | |
205 #define INREG(addr) GETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr) | |
206 #define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,val) | |
3996 | 207 #define OUTREGP(addr,val,mask) \ |
208 do { \ | |
209 unsigned int _tmp = INREG(addr); \ | |
210 _tmp &= (mask); \ | |
211 _tmp |= (val); \ | |
212 OUTREG(addr, _tmp); \ | |
213 } while (0) | |
214 | |
215 static uint32_t radeon_vid_get_dbpp( void ) | |
216 { | |
217 uint32_t dbpp,retval; | |
218 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; | |
219 switch(dbpp) | |
220 { | |
221 case DST_8BPP: retval = 8; break; | |
222 case DST_15BPP: retval = 15; break; | |
223 case DST_16BPP: retval = 16; break; | |
224 case DST_24BPP: retval = 24; break; | |
225 default: retval=32; break; | |
226 } | |
227 return retval; | |
228 } | |
229 | |
230 static int radeon_is_dbl_scan( void ) | |
231 { | |
232 return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; | |
233 } | |
234 | |
235 static int radeon_is_interlace( void ) | |
236 { | |
237 return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; | |
238 } | |
239 | |
240 static __inline__ void radeon_engine_flush ( void ) | |
241 { | |
242 int i; | |
243 | |
244 /* initiate flush */ | |
245 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, | |
246 ~RB2D_DC_FLUSH_ALL); | |
247 | |
248 for (i=0; i < 2000000; i++) { | |
249 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) | |
250 break; | |
251 } | |
252 } | |
253 | |
254 | |
255 static __inline__ void _radeon_fifo_wait (unsigned entries) | |
256 { | |
257 int i; | |
258 | |
259 for (i=0; i<2000000; i++) | |
260 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) | |
261 return; | |
262 } | |
263 | |
264 | |
265 static __inline__ void _radeon_engine_idle ( void ) | |
266 { | |
267 int i; | |
268 | |
269 /* ensure FIFO is empty before waiting for idle */ | |
270 _radeon_fifo_wait (64); | |
271 | |
272 for (i=0; i<2000000; i++) { | |
273 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { | |
274 radeon_engine_flush (); | |
275 return; | |
276 } | |
277 } | |
278 } | |
279 | |
280 #define radeon_engine_idle() _radeon_engine_idle() | |
281 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) | |
282 | |
283 | |
284 #ifndef RAGE128 | |
285 /* Reference color space transform data */ | |
286 typedef struct tagREF_TRANSFORM | |
287 { | |
288 float RefLuma; | |
289 float RefRCb; | |
290 float RefRCr; | |
291 float RefGCb; | |
292 float RefGCr; | |
293 float RefBCb; | |
294 float RefBCr; | |
295 } REF_TRANSFORM; | |
296 | |
297 /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ | |
298 REF_TRANSFORM trans[2] = | |
299 { | |
300 {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ | |
301 {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ | |
302 }; | |
303 /**************************************************************************** | |
304 * SetTransform * | |
305 * Function: Calculates and sets color space transform from supplied * | |
306 * reference transform, gamma, brightness, contrast, hue and * | |
307 * saturation. * | |
308 * Inputs: bright - brightness * | |
309 * cont - contrast * | |
310 * sat - saturation * | |
311 * hue - hue * | |
312 * ref - index to the table of refernce transforms * | |
313 * Outputs: NONE * | |
314 ****************************************************************************/ | |
315 | |
316 static void radeon_set_transform(float bright, float cont, float sat, | |
317 float hue, unsigned ref) | |
318 { | |
319 float OvHueSin, OvHueCos; | |
320 float CAdjLuma, CAdjOff; | |
321 float CAdjRCb, CAdjRCr; | |
322 float CAdjGCb, CAdjGCr; | |
323 float CAdjBCb, CAdjBCr; | |
324 float OvLuma, OvROff, OvGOff, OvBOff; | |
325 float OvRCb, OvRCr; | |
326 float OvGCb, OvGCr; | |
327 float OvBCb, OvBCr; | |
328 float Loff = 64.0; | |
329 float Coff = 512.0f; | |
330 | |
331 uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; | |
332 uint32_t dwOvRCb, dwOvRCr; | |
333 uint32_t dwOvGCb, dwOvGCr; | |
334 uint32_t dwOvBCb, dwOvBCr; | |
335 | |
336 if (ref >= 2) return; | |
337 | |
338 OvHueSin = sin((double)hue); | |
339 OvHueCos = cos((double)hue); | |
340 | |
341 CAdjLuma = cont * trans[ref].RefLuma; | |
342 CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; | |
343 | |
344 CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; | |
345 CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; | |
346 CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); | |
347 CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); | |
348 CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; | |
349 CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; | |
350 | |
351 #if 0 /* default constants */ | |
352 CAdjLuma = 1.16455078125; | |
353 | |
354 CAdjRCb = 0.0; | |
355 CAdjRCr = 1.59619140625; | |
356 CAdjGCb = -0.39111328125; | |
357 CAdjGCr = -0.8125; | |
358 CAdjBCb = 2.01708984375; | |
359 CAdjBCr = 0; | |
360 #endif | |
361 OvLuma = CAdjLuma; | |
362 OvRCb = CAdjRCb; | |
363 OvRCr = CAdjRCr; | |
364 OvGCb = CAdjGCb; | |
365 OvGCr = CAdjGCr; | |
366 OvBCb = CAdjBCb; | |
367 OvBCr = CAdjBCr; | |
368 OvROff = CAdjOff - | |
369 OvLuma * Loff - (OvRCb + OvRCr) * Coff; | |
370 OvGOff = CAdjOff - | |
371 OvLuma * Loff - (OvGCb + OvGCr) * Coff; | |
372 OvBOff = CAdjOff - | |
373 OvLuma * Loff - (OvBCb + OvBCr) * Coff; | |
374 #if 0 /* default constants */ | |
375 OvROff = -888.5; | |
376 OvGOff = 545; | |
377 OvBOff = -1104; | |
378 #endif | |
379 | |
380 dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; | |
381 dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; | |
382 dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; | |
383 if(!IsR200) | |
384 { | |
385 dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; | |
386 dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; | |
387 dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; | |
388 dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; | |
389 dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; | |
390 dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; | |
391 dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; | |
392 } | |
393 else | |
394 { | |
395 dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; | |
396 dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; | |
397 dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; | |
398 dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; | |
399 dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; | |
400 dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; | |
401 dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; | |
402 } | |
403 | |
404 OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); | |
405 OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); | |
406 OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); | |
407 OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); | |
408 OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); | |
409 OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); | |
410 } | |
411 | |
412 /* Gamma curve definition */ | |
413 typedef struct | |
414 { | |
415 unsigned int gammaReg; | |
416 unsigned int gammaSlope; | |
417 unsigned int gammaOffset; | |
418 }GAMMA_SETTINGS; | |
419 | |
420 /* Recommended gamma curve parameters */ | |
421 GAMMA_SETTINGS r200_def_gamma[18] = | |
422 { | |
423 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
424 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
425 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
426 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
427 {OV0_GAMMA_80_BF, 0x100, 0x0100}, | |
428 {OV0_GAMMA_C0_FF, 0x100, 0x0100}, | |
429 {OV0_GAMMA_100_13F, 0x100, 0x0200}, | |
430 {OV0_GAMMA_140_17F, 0x100, 0x0200}, | |
431 {OV0_GAMMA_180_1BF, 0x100, 0x0300}, | |
432 {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, | |
433 {OV0_GAMMA_200_23F, 0x100, 0x0400}, | |
434 {OV0_GAMMA_240_27F, 0x100, 0x0400}, | |
435 {OV0_GAMMA_280_2BF, 0x100, 0x0500}, | |
436 {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, | |
437 {OV0_GAMMA_300_33F, 0x100, 0x0600}, | |
438 {OV0_GAMMA_340_37F, 0x100, 0x0600}, | |
439 {OV0_GAMMA_380_3BF, 0x100, 0x0700}, | |
440 {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} | |
441 }; | |
442 | |
443 GAMMA_SETTINGS r100_def_gamma[6] = | |
444 { | |
445 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
446 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
447 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
448 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
449 {OV0_GAMMA_380_3BF, 0x100, 0x0100}, | |
450 {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} | |
451 }; | |
452 | |
453 static void make_default_gamma_correction( void ) | |
454 { | |
455 size_t i; | |
456 if(!IsR200){ | |
457 OUTREG(OV0_LIN_TRANS_A, 0x12A00000); | |
458 OUTREG(OV0_LIN_TRANS_B, 0x199018FE); | |
459 OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); | |
460 OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); | |
461 OUTREG(OV0_LIN_TRANS_E, 0x12A02050); | |
462 OUTREG(OV0_LIN_TRANS_F, 0x0000174E); | |
463 for(i=0; i<6; i++){ | |
464 OUTREG(r100_def_gamma[i].gammaReg, | |
465 (r100_def_gamma[i].gammaSlope<<16) | | |
466 r100_def_gamma[i].gammaOffset); | |
467 } | |
468 } | |
469 else{ | |
470 OUTREG(OV0_LIN_TRANS_A, 0x12a00000); | |
471 OUTREG(OV0_LIN_TRANS_B, 0x1990190e); | |
472 OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); | |
473 OUTREG(OV0_LIN_TRANS_D, 0xf3000442); | |
474 OUTREG(OV0_LIN_TRANS_E, 0x12a02040); | |
475 OUTREG(OV0_LIN_TRANS_F, 0x175f); | |
476 | |
477 /* Default Gamma, | |
478 Of 18 segments for gamma cure, all segments in R200 are programmable, | |
479 while only lower 4 and upper 2 segments are programmable in Radeon*/ | |
480 for(i=0; i<18; i++){ | |
481 OUTREG(r200_def_gamma[i].gammaReg, | |
482 (r200_def_gamma[i].gammaSlope<<16) | | |
483 r200_def_gamma[i].gammaOffset); | |
484 } | |
485 } | |
486 } | |
487 #endif | |
488 | |
489 static void radeon_vid_make_default(void) | |
490 { | |
491 #ifdef RAGE128 | |
492 OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brihgtness and saturation for Rage128 */ | |
493 #else | |
494 make_default_gamma_correction(); | |
495 #endif | |
496 besr.deinterlace_pattern = 0x900AAAAA; | |
497 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
498 besr.deinterlace_on=1; | |
499 besr.double_buff=1; | |
500 } | |
501 | |
502 | |
503 unsigned vixGetVersion( void ) { return VIDIX_VERSION; } | |
504 | |
4107 | 505 static unsigned short ati_card_ids[] = |
3996 | 506 { |
507 #ifdef RAGE128 | |
508 /* | |
509 This driver should be compatible with Rage128 (pro) chips. | |
510 (include adaptive deinterlacing!!!). | |
511 Moreover: the same logic can be used with Mach64 chips. | |
512 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
513 but they are incompatible by i/o ports. So if enthusiasts will want | |
514 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
515 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
516 fourccs (422 and 420 formats only). | |
517 */ | |
518 /* Rage128 Pro GL */ | |
4107 | 519 DEVICE_ATI_RAGE_128_PA_PRO, |
520 DEVICE_ATI_RAGE_128_PB_PRO, | |
521 DEVICE_ATI_RAGE_128_PC_PRO, | |
522 DEVICE_ATI_RAGE_128_PD_PRO, | |
523 DEVICE_ATI_RAGE_128_PE_PRO, | |
524 DEVICE_ATI_RAGE_128_PF_PRO, | |
3996 | 525 /* Rage128 Pro VR */ |
4107 | 526 DEVICE_ATI_RAGE_128_PG_PRO, |
527 DEVICE_ATI_RAGE_128_PH_PRO, | |
528 DEVICE_ATI_RAGE_128_PI_PRO, | |
529 DEVICE_ATI_RAGE_128_PJ_PRO, | |
530 DEVICE_ATI_RAGE_128_PK_PRO, | |
531 DEVICE_ATI_RAGE_128_PL_PRO, | |
532 DEVICE_ATI_RAGE_128_PM_PRO, | |
533 DEVICE_ATI_RAGE_128_PN_PRO, | |
534 DEVICE_ATI_RAGE_128_PO_PRO, | |
535 DEVICE_ATI_RAGE_128_PP_PRO, | |
536 DEVICE_ATI_RAGE_128_PQ_PRO, | |
537 DEVICE_ATI_RAGE_128_PR_PRO, | |
538 DEVICE_ATI_RAGE_128_PS_PRO, | |
539 DEVICE_ATI_RAGE_128_PT_PRO, | |
540 DEVICE_ATI_RAGE_128_PU_PRO, | |
541 DEVICE_ATI_RAGE_128_PV_PRO, | |
542 DEVICE_ATI_RAGE_128_PW_PRO, | |
543 DEVICE_ATI_RAGE_128_PX_PRO, | |
3996 | 544 /* Rage128 GL */ |
4107 | 545 DEVICE_ATI_RAGE_128_RE_SG, |
546 DEVICE_ATI_RAGE_128_RF_SG, | |
547 DEVICE_ATI_RAGE_128_RG, | |
548 DEVICE_ATI_RAGE_128_RK_VR, | |
549 DEVICE_ATI_RAGE_128_RL_VR, | |
550 DEVICE_ATI_RAGE_128_SE_4X, | |
551 DEVICE_ATI_RAGE_128_SF_4X, | |
552 DEVICE_ATI_RAGE_128_SG_4X, | |
553 DEVICE_ATI_RAGE_128_4X, | |
554 DEVICE_ATI_RAGE_128_SK_4X, | |
555 DEVICE_ATI_RAGE_128_SL_4X, | |
556 DEVICE_ATI_RAGE_128_SM_4X, | |
557 DEVICE_ATI_RAGE_128_4X2, | |
558 DEVICE_ATI_RAGE_128_PRO, | |
559 DEVICE_ATI_RAGE_128_PRO2, | |
560 DEVICE_ATI_RAGE_128_PRO3 | |
3996 | 561 #else |
562 /* Radeons (indeed: Rage 256 Pro ;) */ | |
4107 | 563 DEVICE_ATI_RADEON_8500_DV, |
564 DEVICE_ATI_RADEON_MOBILITY_M6, | |
565 DEVICE_ATI_RADEON_MOBILITY_M62, | |
566 DEVICE_ATI_RADEON_MOBILITY_M63, | |
567 DEVICE_ATI_RADEON_QD, | |
568 DEVICE_ATI_RADEON_QE, | |
569 DEVICE_ATI_RADEON_QF, | |
570 DEVICE_ATI_RADEON_QG, | |
571 DEVICE_ATI_RADEON_QL, | |
572 DEVICE_ATI_RADEON_QW, | |
573 DEVICE_ATI_RADEON_VE_QY, | |
574 DEVICE_ATI_RADEON_VE_QZ | |
3996 | 575 #endif |
576 }; | |
577 | |
578 static int find_chip(unsigned chip_id) | |
579 { | |
580 unsigned i; | |
4107 | 581 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) |
3996 | 582 { |
4107 | 583 if(chip_id == ati_card_ids[i]) return i; |
3996 | 584 } |
585 return -1; | |
586 } | |
587 | |
588 pciinfo_t pci_info; | |
589 static int probed=0; | |
590 | |
591 vidix_capability_t def_cap = | |
592 { | |
593 #ifdef RAGE128 | |
594 "BES driver for rage128 cards", | |
595 #else | |
596 "BES driver for radeon cards", | |
597 #endif | |
598 TYPE_OUTPUT | TYPE_FX, | |
4191 | 599 { 0, 0, 0, 0 }, |
3996 | 600 1024, |
601 768, | |
602 4, | |
603 4, | |
604 -1, | |
4264 | 605 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, |
4134 | 606 VENDOR_ATI, |
3996 | 607 0, |
608 { 0, 0, 0, 0} | |
609 }; | |
610 | |
611 | |
4191 | 612 int vixProbe( int verbose,int force ) |
3996 | 613 { |
614 pciinfo_t lst[MAX_PCI_DEVICES]; | |
615 unsigned i,num_pci; | |
616 int err; | |
4030 | 617 __verbose = verbose; |
3996 | 618 err = pci_scan(lst,&num_pci); |
619 if(err) | |
620 { | |
621 printf(RADEON_MSG" Error occured during pci scan: %s\n",strerror(err)); | |
622 return err; | |
623 } | |
624 else | |
625 { | |
626 err = ENXIO; | |
627 for(i=0;i<num_pci;i++) | |
628 { | |
4107 | 629 if(lst[i].vendor == VENDOR_ATI) |
3996 | 630 { |
631 int idx; | |
4191 | 632 const char *dname; |
3996 | 633 idx = find_chip(lst[i].device); |
4191 | 634 if(idx == -1 && force == PROBE_NORMAL) continue; |
635 dname = pci_device_name(VENDOR_ATI,lst[i].device); | |
636 dname = dname ? dname : "Unknown chip"; | |
637 printf(RADEON_MSG" Found chip: %s\n",dname); | |
3996 | 638 #ifndef RAGE128 |
4191 | 639 if(idx != -1) |
640 if(ati_card_ids[idx] == DEVICE_ATI_RADEON_QL || | |
641 ati_card_ids[idx] == DEVICE_ATI_RADEON_8500_DV || | |
642 ati_card_ids[idx] == DEVICE_ATI_RADEON_QW) IsR200 = 1; | |
3996 | 643 #endif |
4193 | 644 if(force > PROBE_NORMAL) |
645 { | |
646 printf(RADEON_MSG" Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); | |
647 if(idx == -1) | |
648 printf(RADEON_MSG" Assuming it as %s\n", | |
649 #ifdef RAGE128 | |
650 "Rage128" | |
651 #else | |
652 "Radeon1" | |
653 #endif | |
654 ); | |
655 } | |
4191 | 656 def_cap.device_id = lst[i].device; |
3996 | 657 err = 0; |
658 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); | |
659 probed=1; | |
660 break; | |
661 } | |
662 } | |
663 } | |
664 if(err && verbose) printf(RADEON_MSG" Can't find chip\n"); | |
665 return err; | |
666 } | |
667 | |
668 int vixInit( void ) | |
669 { | |
4012 | 670 if(!probed) |
671 { | |
672 printf(RADEON_MSG" Driver was not probed but is being initializing\n"); | |
673 return EINTR; | |
674 } | |
675 if((radeon_mmio_base = map_phys_mem(pci_info.base2,0xFFFF))==(void *)-1) return ENOMEM; | |
3996 | 676 radeon_ram_size = INREG(CONFIG_MEMSIZE); |
677 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ | |
678 radeon_ram_size &= CONFIG_MEMSIZE_MASK; | |
679 if((radeon_mem_base = map_phys_mem(pci_info.base0,radeon_ram_size))==(void *)-1) return ENOMEM; | |
4070
b61ba6c256dd
Minor interface changes: color and video keys are moved out from playback configuring
nick
parents:
4038
diff
changeset
|
680 memset(&besr,0,sizeof(bes_registers_t)); |
3996 | 681 radeon_vid_make_default(); |
682 printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); | |
683 return 0; | |
684 } | |
685 | |
686 void vixDestroy( void ) | |
687 { | |
688 unmap_phys_mem(radeon_mem_base,radeon_ram_size); | |
689 unmap_phys_mem(radeon_mmio_base,0x7FFF); | |
690 } | |
691 | |
692 int vixGetCapability(vidix_capability_t *to) | |
693 { | |
694 memcpy(to,&def_cap,sizeof(vidix_capability_t)); | |
695 return 0; | |
696 } | |
697 | |
698 uint32_t supported_fourcc[] = | |
699 { | |
700 IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV, | |
701 IMGFMT_UYVY, IMGFMT_YUY2 | |
702 }; | |
703 | |
704 __inline__ static int is_supported_fourcc(uint32_t fourcc) | |
705 { | |
706 unsigned i; | |
707 for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++) | |
708 { | |
709 if(fourcc==supported_fourcc[i]) return 1; | |
710 } | |
711 return 0; | |
712 } | |
713 | |
714 int vixQueryFourcc(vidix_fourcc_t *to) | |
715 { | |
716 if(is_supported_fourcc(to->fourcc)) | |
717 { | |
718 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
719 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
720 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
721 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
722 VID_DEPTH_32BPP; | |
723 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK; | |
724 return 0; | |
725 } | |
4015 | 726 else to->depth = to->flags = 0; |
3996 | 727 return ENOSYS; |
728 } | |
729 | |
730 static void radeon_vid_dump_regs( void ) | |
731 { | |
732 size_t i; | |
4015 | 733 printf(RADEON_MSG"*** Begin of DRIVER variables dump ***\n"); |
734 printf(RADEON_MSG"radeon_mmio_base=%p\n",radeon_mmio_base); | |
735 printf(RADEON_MSG"radeon_mem_base=%p\n",radeon_mem_base); | |
736 printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off); | |
737 printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size); | |
738 printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n"); | |
3996 | 739 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) |
4015 | 740 printf(RADEON_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); |
741 printf(RADEON_MSG"*** End of OV0 registers dump ***\n"); | |
3996 | 742 } |
743 | |
744 static void radeon_vid_stop_video( void ) | |
745 { | |
746 radeon_engine_idle(); | |
747 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
748 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
749 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
750 OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); | |
751 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); | |
752 OUTREG(OV0_TEST, 0); | |
753 } | |
754 | |
755 static void radeon_vid_display_video( void ) | |
756 { | |
757 int bes_flags; | |
758 radeon_fifo_wait(2); | |
759 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
760 radeon_engine_idle(); | |
761 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
762 radeon_fifo_wait(15); | |
763 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); | |
764 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
765 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
766 | |
767 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
768 #ifdef RAGE128 | |
769 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | | |
770 (besr.saturation << 8) | | |
771 (besr.saturation << 16)); | |
772 #endif | |
773 radeon_fifo_wait(2); | |
774 if(besr.ckey_on) | |
775 { | |
776 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); | |
777 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
778 OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_EQ|VIDEO_KEY_FN_FALSE|CMP_MIX_OR); | |
779 } | |
780 else | |
781 { | |
782 OUTREG(OV0_GRAPHICS_KEY_MSK, 0ULL); | |
783 OUTREG(OV0_GRAPHICS_KEY_CLR, 0ULL); | |
784 OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_NE); | |
785 } | |
786 | |
787 OUTREG(OV0_H_INC, besr.h_inc); | |
788 OUTREG(OV0_STEP_BY, besr.step_by); | |
789 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
790 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
791 OUTREG(OV0_V_INC, besr.v_inc); | |
792 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
793 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); | |
794 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); | |
795 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); | |
796 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); | |
797 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
798 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
799 #ifdef RADEON | |
800 OUTREG(OV0_BASE_ADDR, besr.base_addr); | |
801 #endif | |
802 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs); | |
803 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs); | |
804 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs); | |
805 radeon_fifo_wait(9); | |
806 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs); | |
807 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs); | |
808 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf5_base_adrs); | |
809 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); | |
810 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
811 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
812 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); | |
813 | |
814 bes_flags = SCALER_ENABLE | | |
815 SCALER_SMART_SWITCH | | |
816 #ifdef RADEON | |
817 SCALER_HORZ_PICK_NEAREST; | |
818 #else | |
819 SCALER_Y2R_TEMP | | |
820 SCALER_PIX_EXPAND; | |
821 #endif | |
822 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; | |
823 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
824 #ifdef RAGE128 | |
825 bes_flags |= SCALER_BURST_PER_PLANE; | |
826 #endif | |
827 switch(besr.fourcc) | |
828 { | |
829 case IMGFMT_RGB15: | |
830 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
831 case IMGFMT_RGB16: | |
832 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; | |
833 case IMGFMT_RGB24: | |
834 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
835 case IMGFMT_RGB32: | |
836 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
837 /* 4:1:0*/ | |
838 case IMGFMT_IF09: | |
839 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; | |
840 /* 4:2:0 */ | |
841 case IMGFMT_IYUV: | |
842 case IMGFMT_I420: | |
843 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; | |
844 break; | |
845 /* 4:2:2 */ | |
846 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; | |
847 case IMGFMT_YUY2: | |
848 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
849 } | |
850 OUTREG(OV0_SCALE_CNTL, bes_flags); | |
851 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
4030 | 852 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 853 } |
854 | |
4009 | 855 static unsigned radeon_query_pitch(unsigned fourcc) |
856 { | |
857 unsigned pitch; | |
858 switch(fourcc) | |
859 { | |
860 /* 4:2:0 */ | |
861 case IMGFMT_IYUV: | |
862 case IMGFMT_YV12: | |
863 case IMGFMT_I420: pitch = 32; break; | |
864 default: pitch = 16; break; | |
865 } | |
866 return pitch; | |
867 } | |
868 | |
3996 | 869 static int radeon_vid_init_video( vidix_playback_t *config ) |
870 { | |
871 uint32_t tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top; | |
872 int is_420; | |
873 radeon_vid_stop_video(); | |
874 left = config->src.x << 16; | |
875 top = config->src.y << 16; | |
876 src_h = config->src.h; | |
877 src_w = config->src.w; | |
878 is_420 = 0; | |
879 if(config->fourcc == IMGFMT_YV12 || | |
880 config->fourcc == IMGFMT_I420 || | |
881 config->fourcc == IMGFMT_IYUV) is_420 = 1; | |
882 switch(config->fourcc) | |
883 { | |
884 /* 4:2:0 */ | |
885 case IMGFMT_IYUV: | |
886 case IMGFMT_YV12: | |
887 case IMGFMT_I420: pitch = (src_w + 31) & ~31; | |
4015 | 888 config->dest.pitch.y = |
889 config->dest.pitch.u = | |
3996 | 890 config->dest.pitch.v = 32; |
891 break; | |
892 /* 4:2:2 */ | |
893 default: | |
894 case IMGFMT_UYVY: | |
895 case IMGFMT_YUY2: | |
896 pitch = ((src_w*2) + 15) & ~15; | |
897 config->dest.pitch.y = | |
898 config->dest.pitch.u = | |
899 config->dest.pitch.v = 16; | |
900 break; | |
901 } | |
902 dest_w = config->dest.w; | |
903 dest_h = config->dest.h; | |
904 if(radeon_is_dbl_scan()) dest_h *= 2; | |
905 else | |
906 if(radeon_is_interlace()) dest_h /= 2; | |
907 besr.dest_bpp = radeon_vid_get_dbpp(); | |
908 besr.fourcc = config->fourcc; | |
909 besr.v_inc = (src_h << 20) / dest_h; | |
910 h_inc = (src_w << 12) / dest_w; | |
911 step_by = 1; | |
912 | |
913 while(h_inc >= (2 << 12)) { | |
914 step_by++; | |
915 h_inc >>= 1; | |
916 } | |
917 | |
918 /* keep everything in 16.16 */ | |
4015 | 919 besr.base_addr = INREG(DISPLAY_BASE_ADDR); |
3996 | 920 if(is_420) |
921 { | |
922 uint32_t d1line,d2line,d3line; | |
923 d1line = top*pitch; | |
924 d2line = src_h*pitch+(d1line>>1); | |
925 d3line = d2line+((src_h*pitch)>>2); | |
926 d1line += (left >> 16) & ~15; | |
927 d2line += (left >> 17) & ~15; | |
928 d3line += (left >> 17) & ~15; | |
929 config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK; | |
4015 | 930 config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; |
931 config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; | |
3996 | 932 besr.vid_buf0_base_adrs=(radeon_overlay_off+config->offset.y); |
4015 | 933 besr.vid_buf1_base_adrs=(radeon_overlay_off+config->offset.v)|VIF_BUF1_PITCH_SEL; |
934 besr.vid_buf2_base_adrs=(radeon_overlay_off+config->offset.u)|VIF_BUF2_PITCH_SEL; | |
3996 | 935 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) |
936 { | |
937 uint32_t tmp; | |
938 tmp = besr.vid_buf1_base_adrs; | |
939 besr.vid_buf1_base_adrs = besr.vid_buf2_base_adrs; | |
940 besr.vid_buf2_base_adrs = tmp; | |
941 tmp = config->offset.u; | |
942 config->offset.u = config->offset.v; | |
943 config->offset.v = tmp; | |
944 } | |
945 } | |
946 else | |
947 { | |
948 besr.vid_buf0_base_adrs = radeon_overlay_off; | |
949 config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; | |
950 besr.vid_buf0_base_adrs += config->offset.y; | |
951 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs; | |
952 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs; | |
953 } | |
954 config->offsets[0] = 0; | |
955 config->offsets[1] = config->frame_size; | |
956 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; | |
957 besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs+config->frame_size; | |
958 besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs+config->frame_size; | |
959 | |
960 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); | |
961 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
962 ((tmp << 12) & 0xf0000000); | |
963 | |
964 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); | |
965 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
966 ((tmp << 12) & 0x70000000); | |
967 tmp = (top & 0x0000ffff) + 0x00018000; | |
968 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) | |
969 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
970 | |
971 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
972 besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) | |
973 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; | |
974 | |
975 leftUV = (left >> 17) & 15; | |
976 left = (left >> 16) & 15; | |
977 besr.h_inc = h_inc | ((h_inc >> 1) << 16); | |
978 besr.step_by = step_by | (step_by << 8); | |
979 besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16); | |
980 besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16); | |
981 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
982 if(is_420) | |
983 { | |
984 src_h = (src_h + 1) >> 1; | |
985 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
986 } | |
987 else besr.p23_blank_lines_at_top = 0; | |
988 besr.vid_buf_pitch0_value = pitch; | |
989 besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch; | |
990 besr.p1_x_start_end = (src_w+left-1)|(left<<16); | |
991 src_w>>=1; | |
992 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
993 besr.p3_x_start_end = besr.p2_x_start_end; | |
994 return 0; | |
995 } | |
996 | |
4009 | 997 static void radeon_compute_framesize(vidix_playback_t *info) |
998 { | |
999 unsigned pitch,awidth; | |
1000 pitch = radeon_query_pitch(info->fourcc); | |
4033 | 1001 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); |
1002 switch(info->fourcc) | |
1003 { | |
1004 case IMGFMT_I420: | |
1005 case IMGFMT_YV12: | |
1006 case IMGFMT_IYUV: | |
1007 info->frame_size = awidth*info->src.h+(awidth*info->src.h)/2; | |
1008 break; | |
1009 default: info->frame_size = awidth*info->src.h*2; | |
1010 break; | |
1011 } | |
4009 | 1012 } |
1013 | |
3996 | 1014 int vixConfigPlayback(vidix_playback_t *info) |
1015 { | |
1016 if(!is_supported_fourcc(info->fourcc)) return ENOSYS; | |
1017 if(info->num_frames>2) info->num_frames=2; | |
4009 | 1018 radeon_compute_framesize(info); |
3996 | 1019 radeon_overlay_off = radeon_ram_size - info->frame_size*info->num_frames; |
1020 radeon_overlay_off &= 0xffff0000; | |
1021 if(radeon_overlay_off < 0) return EINVAL; | |
1022 info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off; | |
1023 radeon_vid_init_video(info); | |
1024 return 0; | |
1025 } | |
1026 | |
1027 int vixPlaybackOn( void ) | |
1028 { | |
1029 radeon_vid_display_video(); | |
1030 return 0; | |
1031 } | |
1032 | |
1033 int vixPlaybackOff( void ) | |
1034 { | |
1035 radeon_vid_stop_video(); | |
1036 return 0; | |
1037 } | |
1038 | |
4033 | 1039 int vixPlaybackFrameSelect(unsigned frame) |
3996 | 1040 { |
1041 uint32_t off0,off1,off2; | |
1042 /* if(!besr.double_buff) return; */ | |
1043 if(frame%2) | |
1044 { | |
1045 off0 = besr.vid_buf3_base_adrs; | |
1046 off1 = besr.vid_buf4_base_adrs; | |
1047 off2 = besr.vid_buf5_base_adrs; | |
1048 } | |
1049 else | |
1050 { | |
1051 off0 = besr.vid_buf0_base_adrs; | |
1052 off1 = besr.vid_buf1_base_adrs; | |
1053 off2 = besr.vid_buf2_base_adrs; | |
1054 } | |
1055 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1056 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1057 OUTREG(OV0_VID_BUF0_BASE_ADRS, off0); | |
1058 OUTREG(OV0_VID_BUF1_BASE_ADRS, off1); | |
1059 OUTREG(OV0_VID_BUF2_BASE_ADRS, off2); | |
1060 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
4030 | 1061 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1062 return 0; |
1063 } | |
1064 | |
4191 | 1065 vidix_video_eq_t equal = { 0, 0, 0, 0, 0, 0, 0, 0 }; |
3996 | 1066 |
1067 int vixPlaybackGetEq( vidix_video_eq_t * eq) | |
1068 { | |
1069 memcpy(eq,&equal,sizeof(vidix_video_eq_t)); | |
1070 return 0; | |
1071 } | |
1072 | |
4229 | 1073 #ifndef RAGE128 |
1074 #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) | |
1075 #define RTFBrightness(a) (((a)*1.0)/2000.0) | |
1076 #define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) | |
1077 #define RTFHue(a) (((a)*3.1416)/1000.0) | |
1078 #define RTFCheckParam(a) {if((a)<-1000) (a)=-1000; if((a)>1000) (a)=1000;} | |
1079 #endif | |
1080 | |
3996 | 1081 int vixPlaybackSetEq( const vidix_video_eq_t * eq) |
1082 { | |
1083 #ifdef RAGE128 | |
1084 int br,sat; | |
4229 | 1085 #else |
1086 int itu_space; | |
3996 | 1087 #endif |
1088 memcpy(&equal,eq,sizeof(vidix_video_eq_t)); | |
1089 #ifdef RAGE128 | |
1090 br = equal.brightness * 64 / 1000; | |
4229 | 1091 if(br < -64) br = -64; if(br > 63) br = 63; |
4230 | 1092 sat = (equal.saturation + 1000) * 16 / 1000; |
4229 | 1093 if(sat < 0) sat = 0; if(sat > 31) sat = 31; |
3996 | 1094 OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); |
1095 #else | |
4229 | 1096 itu_space = equal.flags == VEQ_FLG_ITU_R_BT_709 ? 1 : 0; |
1097 RTFCheckParam(equal.brightness); | |
1098 RTFCheckParam(equal.saturation); | |
1099 RTFCheckParam(equal.contrast); | |
1100 RTFCheckParam(equal.hue); | |
1101 radeon_set_transform(RTFBrightness(equal.brightness), | |
1102 RTFContrast(equal.contrast), | |
1103 RTFSaturation(equal.saturation), | |
1104 RTFHue(equal.hue), | |
1105 itu_space); | |
3996 | 1106 #endif |
1107 return 0; | |
1108 } | |
1109 |