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comparison vidix/mga_vid.c @ 22850:9a1e26fef45b

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Move driver files directly into the vidix directory.
author diego
date Sun, 01 Apr 2007 00:02:43 +0000
parents
children 77def5093daf
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22849:bddb09395c3e 22850:9a1e26fef45b
1 /*
2 Matrox MGA driver
3
4 ported to VIDIX by Alex Beregszaszi
5
6 YUY2 support (see config.format) added by A'rpi/ESP-team
7 double buffering added by A'rpi/ESP-team
8
9 Brightness/contrast support by Nick Kurshev/Dariush Pietrzak (eyck) and me
10
11 TODO:
12 * fix memory size detection (current reading pci userconfig isn't
13 working as requested - returns the max avail. ram on arch?)
14 * translate all non-english comments to english
15 */
16
17 /*
18 * Original copyright:
19 *
20 * mga_vid.c
21 *
22 * Copyright (C) 1999 Aaron Holtzman
23 *
24 * Module skeleton based on gutted agpgart module by Jeff Hartmann
25 * <slicer@ionet.net>
26 *
27 * Matrox MGA G200/G400 YUV Video Interface module Version 0.1.0
28 *
29 * BES == Back End Scaler
30 *
31 * This software has been released under the terms of the GNU Public
32 * license. See http://www.gnu.org/copyleft/gpl.html for details.
33 */
34
35 //#define CRTC2
36
37 // Set this value, if autodetection fails! (video ram size in megabytes)
38 //#define MGA_MEMORY_SIZE 16
39
40 /* No irq support in userspace implemented yet, do not enable this! */
41 /* disable irq */
42 #undef MGA_ALLOW_IRQ
43
44 #define MGA_VSYNC_POS 2
45
46 #undef MGA_PCICONFIG_MEMDETECT
47
48 #define MGA_DEFAULT_FRAMES 4
49
50 #include <errno.h>
51 #include <stdio.h>
52 #include <stdlib.h>
53 #include <string.h>
54 #include <math.h>
55 #include <inttypes.h>
56
57 #include "vidix.h"
58 #include "fourcc.h"
59 #include "../libdha/libdha.h"
60 #include "../libdha/pci_ids.h"
61 #include "../libdha/pci_names.h"
62
63 #ifdef __MINGW32__
64 #define ENOTSUP 134
65 #endif
66
67 #if !defined(ENOTSUP) && defined(EOPNOTSUPP)
68 #define ENOTSUP EOPNOTSUPP
69 #endif
70
71 /* from radeon_vid */
72 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ))))
73 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL
74
75 #define readb(addr) GETREG(uint8_t,(uint32_t)(addr),0)
76 #define writeb(val,addr) SETREG(uint8_t,(uint32_t)(addr),0,val)
77 #define readl(addr) GETREG(uint32_t,(uint32_t)(addr),0)
78 #define writel(val,addr) SETREG(uint32_t,(uint32_t)(addr),0,val)
79
80 static int mga_verbose = 0;
81
82 /* for device detection */
83 static int probed = 0;
84 static pciinfo_t pci_info;
85
86 /* internal booleans */
87 static int mga_vid_in_use = 0;
88 static int is_g400 = 0;
89 static int vid_src_ready = 0;
90 static int vid_overlay_on = 0;
91
92 /* mapped physical addresses */
93 static uint8_t *mga_mmio_base = 0;
94 static uint8_t *mga_mem_base = 0;
95
96 static int mga_src_base = 0; /* YUV buffer position in video memory */
97
98 static uint32_t mga_ram_size = 0; /* how much megabytes videoram we have */
99
100 /* Graphic keys */
101 static vidix_grkey_t mga_grkey;
102
103 static int colkey_saved = 0;
104 static int colkey_on = 0;
105 static unsigned char colkey_color[4];
106 static unsigned char colkey_mask[4];
107
108 /* for IRQ */
109 static int mga_irq = -1;
110
111 static int mga_next_frame = 0;
112
113 static vidix_capability_t mga_cap =
114 {
115 "Matrox MGA G200/G4x0/G5x0 YUV Video",
116 "Aaron Holtzman, Arpad Gereoffy, Alex Beregszaszi, Nick Kurshev",
117 TYPE_OUTPUT,
118 { 0, 0, 0, 0 },
119 2048,
120 2048,
121 4,
122 4,
123 -1,
124 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER,
125 VENDOR_MATROX,
126 -1, /* will be set in vixProbe */
127 { 0, 0, 0, 0}
128 };
129
130 /* MATROX BES registers */
131 typedef struct bes_registers_s
132 {
133 //BES Control
134 uint32_t besctl;
135 //BES Global control
136 uint32_t besglobctl;
137 //Luma control (brightness and contrast)
138 uint32_t beslumactl;
139 //Line pitch
140 uint32_t bespitch;
141
142 //Buffer A-1 Chroma 3 plane org
143 uint32_t besa1c3org;
144 //Buffer A-1 Chroma org
145 uint32_t besa1corg;
146 //Buffer A-1 Luma org
147 uint32_t besa1org;
148
149 //Buffer A-2 Chroma 3 plane org
150 uint32_t besa2c3org;
151 //Buffer A-2 Chroma org
152 uint32_t besa2corg;
153 //Buffer A-2 Luma org
154 uint32_t besa2org;
155
156 //Buffer B-1 Chroma 3 plane org
157 uint32_t besb1c3org;
158 //Buffer B-1 Chroma org
159 uint32_t besb1corg;
160 //Buffer B-1 Luma org
161 uint32_t besb1org;
162
163 //Buffer B-2 Chroma 3 plane org
164 uint32_t besb2c3org;
165 //Buffer B-2 Chroma org
166 uint32_t besb2corg;
167 //Buffer B-2 Luma org
168 uint32_t besb2org;
169
170 //BES Horizontal coord
171 uint32_t beshcoord;
172 //BES Horizontal inverse scaling [5.14]
173 uint32_t beshiscal;
174 //BES Horizontal source start [10.14] (for scaling)
175 uint32_t beshsrcst;
176 //BES Horizontal source ending [10.14] (for scaling)
177 uint32_t beshsrcend;
178 //BES Horizontal source last
179 uint32_t beshsrclst;
180
181
182 //BES Vertical coord
183 uint32_t besvcoord;
184 //BES Vertical inverse scaling [5.14]
185 uint32_t besviscal;
186 //BES Field 1 vertical source last position
187 uint32_t besv1srclst;
188 //BES Field 1 weight start
189 uint32_t besv1wght;
190 //BES Field 2 vertical source last position
191 uint32_t besv2srclst;
192 //BES Field 2 weight start
193 uint32_t besv2wght;
194
195 } bes_registers_t;
196 static bes_registers_t regs;
197
198 #ifdef CRTC2
199 typedef struct crtc2_registers_s
200 {
201 uint32_t c2ctl;
202 uint32_t c2datactl;
203 uint32_t c2misc;
204 uint32_t c2hparam;
205 uint32_t c2hsync;
206 uint32_t c2offset;
207 uint32_t c2pl2startadd0;
208 uint32_t c2pl2startadd1;
209 uint32_t c2pl3startadd0;
210 uint32_t c2pl3startadd1;
211 uint32_t c2preload;
212 uint32_t c2spicstartadd0;
213 uint32_t c2spicstartadd1;
214 uint32_t c2startadd0;
215 uint32_t c2startadd1;
216 uint32_t c2subpiclut;
217 uint32_t c2vcount;
218 uint32_t c2vparam;
219 uint32_t c2vsync;
220 } crtc2_registers_t;
221 static crtc2_registers_t cregs;
222 #endif
223
224 //All register offsets are converted to word aligned offsets (32 bit)
225 //because we want all our register accesses to be 32 bits
226 #define VCOUNT 0x1e20
227
228 #define PALWTADD 0x3c00 // Index register for X_DATAREG port
229 #define X_DATAREG 0x3c0a
230
231 #define XMULCTRL 0x19
232 #define BPP_8 0x00
233 #define BPP_15 0x01
234 #define BPP_16 0x02
235 #define BPP_24 0x03
236 #define BPP_32_DIR 0x04
237 #define BPP_32_PAL 0x07
238
239 #define XCOLMSK 0x40
240 #define X_COLKEY 0x42
241 #define XKEYOPMODE 0x51
242 #define XCOLMSK0RED 0x52
243 #define XCOLMSK0GREEN 0x53
244 #define XCOLMSK0BLUE 0x54
245 #define XCOLKEY0RED 0x55
246 #define XCOLKEY0GREEN 0x56
247 #define XCOLKEY0BLUE 0x57
248
249 #ifdef CRTC2
250 /*CRTC2 registers*/
251 #define XMISCCTRL 0x1e
252 #define C2CTL 0x3c10
253 #define C2DATACTL 0x3c4c
254 #define C2MISC 0x3c44
255 #define C2HPARAM 0x3c14
256 #define C2HSYNC 0x3c18
257 #define C2OFFSET 0x3c40
258 #define C2PL2STARTADD0 0x3c30 // like BESA1CORG
259 #define C2PL2STARTADD1 0x3c34 // like BESA2CORG
260 #define C2PL3STARTADD0 0x3c38 // like BESA1C3ORG
261 #define C2PL3STARTADD1 0x3c3c // like BESA2C3ORG
262 #define C2PRELOAD 0x3c24
263 #define C2SPICSTARTADD0 0x3c54
264 #define C2SPICSTARTADD1 0x3c58
265 #define C2STARTADD0 0x3c28 // like BESA1ORG
266 #define C2STARTADD1 0x3c2c // like BESA2ORG
267 #define C2SUBPICLUT 0x3c50
268 #define C2VCOUNT 0x3c48
269 #define C2VPARAM 0x3c1c
270 #define C2VSYNC 0x3c20
271 #endif /* CRTC2 */
272
273 // Backend Scaler registers
274 #define BESCTL 0x3d20
275 #define BESGLOBCTL 0x3dc0
276 #define BESLUMACTL 0x3d40
277 #define BESPITCH 0x3d24
278
279 #define BESA1C3ORG 0x3d60
280 #define BESA1CORG 0x3d10
281 #define BESA1ORG 0x3d00
282
283 #define BESA2C3ORG 0x3d64
284 #define BESA2CORG 0x3d14
285 #define BESA2ORG 0x3d04
286
287 #define BESB1C3ORG 0x3d68
288 #define BESB1CORG 0x3d18
289 #define BESB1ORG 0x3d08
290
291 #define BESB2C3ORG 0x3d6C
292 #define BESB2CORG 0x3d1C
293 #define BESB2ORG 0x3d0C
294
295 #define BESHCOORD 0x3d28
296 #define BESHISCAL 0x3d30
297 #define BESHSRCEND 0x3d3C
298 #define BESHSRCLST 0x3d50
299 #define BESHSRCST 0x3d38
300 #define BESV1WGHT 0x3d48
301 #define BESV2WGHT 0x3d4c
302 #define BESV1SRCLST 0x3d54
303 #define BESV2SRCLST 0x3d58
304 #define BESVISCAL 0x3d34
305 #define BESVCOORD 0x3d2c
306 #define BESSTATUS 0x3dc4
307
308 #define CRTCX 0x1fd4
309 #define CRTCD 0x1fd5
310 #define IEN 0x1e1c
311 #define ICLEAR 0x1e18
312 #define STATUS 0x1e14
313
314
315 #ifdef CRTC2
316 static void crtc2_frame_sel(int frame)
317 {
318 switch(frame) {
319 case 0:
320 cregs.c2pl2startadd0=regs.besa1corg;
321 cregs.c2pl3startadd0=regs.besa1c3org;
322 cregs.c2startadd0=regs.besa1org;
323 break;
324 case 1:
325 cregs.c2pl2startadd0=regs.besa2corg;
326 cregs.c2pl3startadd0=regs.besa2c3org;
327 cregs.c2startadd0=regs.besa2org;
328 break;
329 case 2:
330 cregs.c2pl2startadd0=regs.besb1corg;
331 cregs.c2pl3startadd0=regs.besb1c3org;
332 cregs.c2startadd0=regs.besb1org;
333 break;
334 case 3:
335 cregs.c2pl2startadd0=regs.besb2corg;
336 cregs.c2pl3startadd0=regs.besb2c3org;
337 cregs.c2startadd0=regs.besb2org;
338 break;
339 }
340 writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0);
341 writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0);
342 writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0);
343 }
344 #endif
345
346 int vixPlaybackFrameSelect(unsigned int frame)
347 {
348 mga_next_frame = frame;
349 if (mga_verbose>1) printf("[mga] frameselect: %d\n", mga_next_frame);
350 #if MGA_ALLOW_IRQ
351 if (mga_irq == -1)
352 #endif
353 {
354 //we don't need the vcount protection as we're only hitting
355 //one register (and it doesn't seem to be double buffered)
356 regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25);
357 writel( regs.besctl, mga_mmio_base + BESCTL );
358
359 // writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16),
360 writel( regs.besglobctl + (MGA_VSYNC_POS<<16),
361 mga_mmio_base + BESGLOBCTL);
362 #ifdef CRTC2
363 crtc2_frame_sel(mga_next_frame);
364 #endif
365 }
366
367 return(0);
368 }
369
370
371 static void mga_vid_write_regs(int restore)
372 {
373 //Make sure internal registers don't get updated until we're done
374 writel( (readl(mga_mmio_base + VCOUNT)-1)<<16,
375 mga_mmio_base + BESGLOBCTL);
376
377 // color or coordinate keying
378
379 if(restore && colkey_saved){
380 // restore it
381 colkey_saved=0;
382
383 // printf("[mga] Restoring colorkey (ON: %d %02X:%02X:%02X)\n",
384 // colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]);
385
386 // Set color key registers:
387 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
388 writeb( colkey_on, mga_mmio_base + X_DATAREG);
389
390 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD);
391 writeb( colkey_color[0], mga_mmio_base + X_DATAREG);
392 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD);
393 writeb( colkey_color[1], mga_mmio_base + X_DATAREG);
394 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD);
395 writeb( colkey_color[2], mga_mmio_base + X_DATAREG);
396 writeb( X_COLKEY, mga_mmio_base + PALWTADD);
397 writeb( colkey_color[3], mga_mmio_base + X_DATAREG);
398
399 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD);
400 writeb( colkey_mask[0], mga_mmio_base + X_DATAREG);
401 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD);
402 writeb( colkey_mask[1], mga_mmio_base + X_DATAREG);
403 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD);
404 writeb( colkey_mask[2], mga_mmio_base + X_DATAREG);
405 writeb( XCOLMSK, mga_mmio_base + PALWTADD);
406 writeb( colkey_mask[3], mga_mmio_base + X_DATAREG);
407
408 } else if(!colkey_saved){
409 // save it
410 colkey_saved=1;
411 // Get color key registers:
412 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
413 colkey_on=(unsigned char)readb(mga_mmio_base + X_DATAREG) & 1;
414
415 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD);
416 colkey_color[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
417 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD);
418 colkey_color[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
419 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD);
420 colkey_color[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
421 writeb( X_COLKEY, mga_mmio_base + PALWTADD);
422 colkey_color[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
423
424 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD);
425 colkey_mask[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
426 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD);
427 colkey_mask[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
428 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD);
429 colkey_mask[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
430 writeb( XCOLMSK, mga_mmio_base + PALWTADD);
431 colkey_mask[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
432
433 // printf("[mga] Saved colorkey (ON: %d %02X:%02X:%02X)\n",
434 // colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]);
435
436 }
437
438 if(!restore){
439 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
440 writeb( mga_grkey.ckey.op == CKEY_TRUE, mga_mmio_base + X_DATAREG);
441 if ( mga_grkey.ckey.op == CKEY_TRUE )
442 {
443 uint32_t r=0, g=0, b=0;
444
445 writeb( XMULCTRL, mga_mmio_base + PALWTADD);
446 switch (readb (mga_mmio_base + X_DATAREG))
447 {
448 case BPP_8:
449 /* Need to look up the color index, just using
450 color 0 for now. */
451 break;
452
453 case BPP_15:
454 r = mga_grkey.ckey.red >> 3;
455 g = mga_grkey.ckey.green >> 3;
456 b = mga_grkey.ckey.blue >> 3;
457 break;
458
459 case BPP_16:
460 r = mga_grkey.ckey.red >> 3;
461 g = mga_grkey.ckey.green >> 2;
462 b = mga_grkey.ckey.blue >> 3;
463 break;
464
465 case BPP_24:
466 case BPP_32_DIR:
467 case BPP_32_PAL:
468 r = mga_grkey.ckey.red;
469 g = mga_grkey.ckey.green;
470 b = mga_grkey.ckey.blue;
471 break;
472 }
473
474 // Enable colorkeying
475 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
476 writeb( 1, mga_mmio_base + X_DATAREG);
477
478 // Disable color keying on alpha channel
479 writeb( XCOLMSK, mga_mmio_base + PALWTADD);
480 writeb( 0x00, mga_mmio_base + X_DATAREG);
481 writeb( X_COLKEY, mga_mmio_base + PALWTADD);
482 writeb( 0x00, mga_mmio_base + X_DATAREG);
483
484
485 // Set up color key registers
486 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD);
487 writeb( r, mga_mmio_base + X_DATAREG);
488 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD);
489 writeb( g, mga_mmio_base + X_DATAREG);
490 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD);
491 writeb( b, mga_mmio_base + X_DATAREG);
492
493 // Set up color key mask registers
494 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD);
495 writeb( 0xff, mga_mmio_base + X_DATAREG);
496 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD);
497 writeb( 0xff, mga_mmio_base + X_DATAREG);
498 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD);
499 writeb( 0xff, mga_mmio_base + X_DATAREG);
500 }
501 else
502 {
503 // Disable colorkeying
504 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
505 writeb( 0, mga_mmio_base + X_DATAREG);
506 }
507 }
508
509 // Backend Scaler
510 writel( regs.besctl, mga_mmio_base + BESCTL);
511 if(is_g400)
512 writel( regs.beslumactl, mga_mmio_base + BESLUMACTL);
513 writel( regs.bespitch, mga_mmio_base + BESPITCH);
514
515 writel( regs.besa1org, mga_mmio_base + BESA1ORG);
516 writel( regs.besa1corg, mga_mmio_base + BESA1CORG);
517 writel( regs.besa2org, mga_mmio_base + BESA2ORG);
518 writel( regs.besa2corg, mga_mmio_base + BESA2CORG);
519 writel( regs.besb1org, mga_mmio_base + BESB1ORG);
520 writel( regs.besb1corg, mga_mmio_base + BESB1CORG);
521 writel( regs.besb2org, mga_mmio_base + BESB2ORG);
522 writel( regs.besb2corg, mga_mmio_base + BESB2CORG);
523 if(is_g400)
524 {
525 writel( regs.besa1c3org, mga_mmio_base + BESA1C3ORG);
526 writel( regs.besa2c3org, mga_mmio_base + BESA2C3ORG);
527 writel( regs.besb1c3org, mga_mmio_base + BESB1C3ORG);
528 writel( regs.besb2c3org, mga_mmio_base + BESB2C3ORG);
529 }
530
531 writel( regs.beshcoord, mga_mmio_base + BESHCOORD);
532 writel( regs.beshiscal, mga_mmio_base + BESHISCAL);
533 writel( regs.beshsrcst, mga_mmio_base + BESHSRCST);
534 writel( regs.beshsrcend, mga_mmio_base + BESHSRCEND);
535 writel( regs.beshsrclst, mga_mmio_base + BESHSRCLST);
536
537 writel( regs.besvcoord, mga_mmio_base + BESVCOORD);
538 writel( regs.besviscal, mga_mmio_base + BESVISCAL);
539
540 writel( regs.besv1srclst, mga_mmio_base + BESV1SRCLST);
541 writel( regs.besv1wght, mga_mmio_base + BESV1WGHT);
542 writel( regs.besv2srclst, mga_mmio_base + BESV2SRCLST);
543 writel( regs.besv2wght, mga_mmio_base + BESV2WGHT);
544
545 //update the registers somewhere between 1 and 2 frames from now.
546 writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16),
547 mga_mmio_base + BESGLOBCTL);
548
549 if (mga_verbose > 1)
550 {
551 printf("[mga] wrote BES registers\n");
552 printf("[mga] BESCTL = 0x%08x\n",
553 readl(mga_mmio_base + BESCTL));
554 printf("[mga] BESGLOBCTL = 0x%08x\n",
555 readl(mga_mmio_base + BESGLOBCTL));
556 printf("[mga] BESSTATUS= 0x%08x\n",
557 readl(mga_mmio_base + BESSTATUS));
558 }
559 #ifdef CRTC2
560 // printf("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL));
561 // printf("c2misc:0x%08x\n",readl(mga_mmio_base + C2MISC));
562 // printf("c2ctl:0x%08x c2datactl:0x%08x\n",cregs.c2ctl,cregs.c2datactl);
563
564 // writel(cregs.c2ctl, mga_mmio_base + C2CTL);
565
566 writel(((readl(mga_mmio_base + C2CTL) & ~0x03e00000) + (cregs.c2ctl & 0x03e00000)), mga_mmio_base + C2CTL);
567 writel(((readl(mga_mmio_base + C2DATACTL) & ~0x000000ff) + (cregs.c2datactl & 0x000000ff)), mga_mmio_base + C2DATACTL);
568 // ctrc2
569 // disable CRTC2 acording to specs
570 // writel(cregs.c2ctl & 0xfffffff0, mga_mmio_base + C2CTL);
571 // je to treba ???
572 // writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0xa2, mga_mmio_base + XMISCCTRL); // MAFC - mfcsel & vdoutsel
573 // writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0x92, mga_mmio_base + XMISCCTRL);
574 // writeb((readb(mga_mmio_base + XMISCCTRL) & ~0xe9) + 0xa2, mga_mmio_base + XMISCCTRL);
575 // writel(cregs.c2datactl, mga_mmio_base + C2DATACTL);
576 // writel(cregs.c2hparam, mga_mmio_base + C2HPARAM);
577 // writel(cregs.c2hsync, mga_mmio_base + C2HSYNC);
578 // writel(cregs.c2vparam, mga_mmio_base + C2VPARAM);
579 // writel(cregs.c2vsync, mga_mmio_base + C2VSYNC);
580 writel(cregs.c2misc, mga_mmio_base + C2MISC);
581
582 if (mga_verbose > 1) printf("[mga] c2offset = %d\n",cregs.c2offset);
583
584 writel(cregs.c2offset, mga_mmio_base + C2OFFSET);
585 writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0);
586 // writel(cregs.c2startadd1, mga_mmio_base + C2STARTADD1);
587 writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0);
588 // writel(cregs.c2pl2startadd1, mga_mmio_base + C2PL2STARTADD1);
589 writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0);
590 // writel(cregs.c2pl3startadd1, mga_mmio_base + C2PL3STARTADD1);
591 writel(cregs.c2spicstartadd0, mga_mmio_base + C2SPICSTARTADD0);
592 // writel(cregs.c2spicstartadd1, mga_mmio_base + C2SPICSTARTADD1);
593 // writel(cregs.c2subpiclut, mga_mmio_base + C2SUBPICLUT);
594 // writel(cregs.c2preload, mga_mmio_base + C2PRELOAD);
595 // finaly enable everything
596 // writel(cregs.c2ctl, mga_mmio_base + C2CTL);
597 // printf("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL));
598 // printf("c2misc:0x%08x\n", readl(mga_mmio_base + C2MISC));
599 #endif
600 }
601
602 #ifdef MGA_ALLOW_IRQ
603 static void enable_irq(){
604 long int cc;
605
606 cc = readl(mga_mmio_base + IEN);
607 // printf("*** !!! IRQREG = %d\n", (int)(cc&0xff));
608
609 writeb( 0x11, mga_mmio_base + CRTCX);
610
611 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */
612 writeb(0x00, mga_mmio_base + CRTCD ); /* enable on */
613 writeb(0x10, mga_mmio_base + CRTCD ); /* clear = 1 */
614
615 writel( regs.besglobctl , mga_mmio_base + BESGLOBCTL);
616
617 return;
618 }
619
620 static void disable_irq()
621 {
622 writeb( 0x11, mga_mmio_base + CRTCX);
623 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */
624
625 return;
626 }
627
628 void mga_handle_irq(int irq, void *dev_id/*, struct pt_regs *pregs*/) {
629 // static int frame=0;
630 // static int counter=0;
631 long int cc;
632 // if ( ! mga_enabled_flag ) return;
633
634 // printf("vcount = %d\n",readl(mga_mmio_base + VCOUNT));
635
636 //printf("mga_interrupt #%d\n", irq);
637
638 if ( irq != -1 ) {
639
640 cc = readl(mga_mmio_base + STATUS);
641 if ( ! (cc & 0x10) ) return; /* vsyncpen */
642 // debug_irqcnt++;
643 }
644
645 // if ( debug_irqignore ) {
646 // debug_irqignore = 0;
647
648
649 /*
650 if ( mga_conf_deinterlace ) {
651 if ( mga_first_field ) {
652 // printf("mga_interrupt first field\n");
653 if ( syncfb_interrupt() )
654 mga_first_field = 0;
655 } else {
656 // printf("mga_interrupt second field\n");
657 mga_select_buffer( mga_current_field | 2 );
658 mga_first_field = 1;
659 }
660 } else {
661 syncfb_interrupt();
662 }
663 */
664
665 // frame=(frame+1)&1;
666 regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25);
667 writel( regs.besctl, mga_mmio_base + BESCTL );
668
669 #ifdef CRTC2
670 // sem pridat vyber obrazku !!!!
671 crtc2_frame_sel(mga_next_frame);
672 #endif
673
674 #if 0
675 ++counter;
676 if(!(counter&63)){
677 printf("mga irq counter = %d\n",counter);
678 }
679 #endif
680
681 // } else {
682 // debug_irqignore = 1;
683 // }
684
685 if ( irq != -1 ) {
686 writeb( 0x11, mga_mmio_base + CRTCX);
687 writeb( 0, mga_mmio_base + CRTCD );
688 writeb( 0x10, mga_mmio_base + CRTCD );
689 }
690
691 // writel( regs.besglobctl, mga_mmio_base + BESGLOBCTL);
692
693
694 return;
695
696 }
697 #endif /* MGA_ALLOW_IRQ */
698
699 int vixConfigPlayback(vidix_playback_t *config)
700 {
701 unsigned int i;
702 int x, y, sw, sh, dw, dh;
703 int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights;
704 #ifdef CRTC2
705 #define right_margin 0
706 #define left_margin 18
707 #define hsync_len 46
708 #define lower_margin 10
709 #define vsync_len 4
710 #define upper_margin 39
711
712 unsigned int hdispend = (config->src.w + 31) & ~31;
713 unsigned int hsyncstart = hdispend + (right_margin & ~7);
714 unsigned int hsyncend = hsyncstart + (hsync_len & ~7);
715 unsigned int htotal = hsyncend + (left_margin & ~7);
716 unsigned int vdispend = config->src.h;
717 unsigned int vsyncstart = vdispend + lower_margin;
718 unsigned int vsyncend = vsyncstart + vsync_len;
719 unsigned int vtotal = vsyncend + upper_margin;
720 #endif
721
722 if ((config->num_frames < 1) || (config->num_frames > 4))
723 {
724 printf("[mga] illegal num_frames: %d, setting to %d\n",
725 config->num_frames, MGA_DEFAULT_FRAMES);
726 config->num_frames = MGA_DEFAULT_FRAMES;
727 }
728
729 x = config->dest.x;
730 y = config->dest.y;
731 sw = config->src.w;
732 sh = config->src.h;
733 dw = config->dest.w;
734 dh = config->dest.h;
735
736 config->dest.pitch.y=32;
737 config->dest.pitch.u=config->dest.pitch.v=32;
738
739 if (mga_verbose) printf("[mga] Setting up a %dx%d-%dx%d video window (src %dx%d) format %X\n",
740 dw, dh, x, y, sw, sh, config->fourcc);
741
742 if ((sw < 4) || (sh < 4) || (dw < 4) || (dh < 4))
743 {
744 printf("[mga] Invalid src/dest dimensions\n");
745 return(EINVAL);
746 }
747
748 //FIXME check that window is valid and inside desktop
749
750 // printf("[mga] vcount = %d\n", readl(mga_mmio_base + VCOUNT));
751
752 sw+=sw&1;
753 switch(config->fourcc)
754 {
755 case IMGFMT_I420:
756 case IMGFMT_IYUV:
757 case IMGFMT_YV12:
758 sh+=sh&1;
759 config->frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2;
760 break;
761 case IMGFMT_YUY2:
762 case IMGFMT_UYVY:
763 config->frame_size = ((sw + 31) & ~31) * sh * 2;
764 break;
765 default:
766 printf("[mga] Unsupported pixel format: %x\n", config->fourcc);
767 return(ENOTSUP);
768 }
769
770 config->offsets[0] = 0;
771 // config->offsets[1] = config->frame_size;
772 // config->offsets[2] = 2*config->frame_size;
773 // config->offsets[3] = 3*config->frame_size;
774 for (i = 1; i < config->num_frames+1; i++)
775 config->offsets[i] = i*config->frame_size;
776
777 config->offset.y=0;
778 if(config->fourcc == IMGFMT_I420 || config->fourcc == IMGFMT_IYUV)
779 {
780 config->offset.u=((sw + 31) & ~31) * sh;
781 config->offset.v=config->offset.u+((sw + 31) & ~31) * sh /4;
782 }
783 else {
784 config->offset.v=((sw + 31) & ~31) * sh;
785 config->offset.u=config->offset.v+((sw + 31) & ~31) * sh /4;
786 }
787
788 //FIXME figure out a better way to allocate memory on card
789 //allocate 2 megs
790 //mga_src_base = mga_mem_base + (MGA_VIDMEM_SIZE-2) * 0x100000;
791 //mga_src_base = (MGA_VIDMEM_SIZE-3) * 0x100000;
792
793 mga_src_base = (mga_ram_size*0x100000-config->num_frames*config->frame_size);
794 if (mga_src_base < 0)
795 {
796 printf("[mga] not enough memory for frames!\n");
797 return(EFAULT);
798 }
799 mga_src_base &= (~0xFFFF); /* 64k boundary */
800 if (mga_verbose > 1) printf("[mga] YUV buffer base: %#x\n", mga_src_base);
801
802 config->dga_addr = mga_mem_base + mga_src_base;
803
804 /* for G200 set Interleaved UV planes */
805 if (!is_g400)
806 config->flags = VID_PLAY_INTERLEAVED_UV | INTERLEAVING_UV;
807
808 //Setup the BES registers for a three plane 4:2:0 video source
809
810 regs.besglobctl = 0;
811
812 switch(config->fourcc)
813 {
814 case IMGFMT_YV12:
815 case IMGFMT_I420:
816 case IMGFMT_IYUV:
817 regs.besctl = 1 // BES enabled
818 + (0<<6) // even start polarity
819 + (1<<10) // x filtering enabled
820 + (1<<11) // y filtering enabled
821 + (1<<16) // chroma upsampling
822 + (1<<17) // 4:2:0 mode
823 + (1<<18); // dither enabled
824 #if 0
825 if(is_g400)
826 {
827 //zoom disabled, zoom filter disabled, 420 3 plane format, proc amp
828 //disabled, rgb mode disabled
829 regs.besglobctl = (1<<5);
830 }
831 else
832 {
833 //zoom disabled, zoom filter disabled, Cb samples in 0246, Cr
834 //in 1357, BES register update on besvcnt
835 regs.besglobctl = 0;
836 }
837 #endif
838 break;
839
840 case IMGFMT_YUY2:
841 regs.besctl = 1 // BES enabled
842 + (0<<6) // even start polarity
843 + (1<<10) // x filtering enabled
844 + (1<<11) // y filtering enabled
845 + (1<<16) // chroma upsampling
846 + (0<<17) // 4:2:2 mode
847 + (1<<18); // dither enabled
848
849 regs.besglobctl = 0; // YUY2 format selected
850 break;
851
852 case IMGFMT_UYVY:
853 regs.besctl = 1 // BES enabled
854 + (0<<6) // even start polarity
855 + (1<<10) // x filtering enabled
856 + (1<<11) // y filtering enabled
857 + (1<<16) // chroma upsampling
858 + (0<<17) // 4:2:2 mode
859 + (1<<18); // dither enabled
860
861 regs.besglobctl = 1<<6; // UYVY format selected
862 break;
863
864 }
865
866 //Disable contrast and brightness control
867 regs.besglobctl |= (1<<5) + (1<<7);
868 regs.beslumactl = (0x7f << 16) + (0x80<<0);
869 regs.beslumactl = 0x80<<0;
870
871 //Setup destination window boundaries
872 besleft = x > 0 ? x : 0;
873 bestop = y > 0 ? y : 0;
874 regs.beshcoord = (besleft<<16) + (x + dw-1);
875 regs.besvcoord = (bestop<<16) + (y + dh-1);
876
877 //Setup source dimensions
878 regs.beshsrclst = (sw - 1) << 16;
879 regs.bespitch = (sw + 31) & ~31 ;
880
881 //Setup horizontal scaling
882 ifactor = ((sw-1)<<14)/(dw-1);
883 ofsleft = besleft - x;
884
885 regs.beshiscal = ifactor<<2;
886 regs.beshsrcst = (ofsleft*ifactor)<<2;
887 regs.beshsrcend = regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2);
888
889 //Setup vertical scaling
890 ifactor = ((sh-1)<<14)/(dh-1);
891 ofstop = bestop - y;
892
893 regs.besviscal = ifactor<<2;
894
895 baseadrofs = ((ofstop*regs.besviscal)>>16)*regs.bespitch;
896 //frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2;
897 regs.besa1org = (uint32_t) mga_src_base + baseadrofs;
898 regs.besa2org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size;
899 regs.besb1org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size;
900 regs.besb2org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size;
901
902 if(config->fourcc==IMGFMT_YV12
903 ||config->fourcc==IMGFMT_IYUV
904 ||config->fourcc==IMGFMT_I420
905 ){
906 // planar YUV frames:
907 if (is_g400)
908 baseadrofs = (((ofstop*regs.besviscal)/4)>>16)*regs.bespitch;
909 else
910 baseadrofs = (((ofstop*regs.besviscal)/2)>>16)*regs.bespitch;
911
912 if(config->fourcc==IMGFMT_YV12){
913 regs.besa1corg = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ;
914 regs.besa2corg = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh;
915 regs.besb1corg = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh;
916 regs.besb2corg = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh;
917 regs.besa1c3org = regs.besa1corg + ((regs.bespitch * sh) / 4);
918 regs.besa2c3org = regs.besa2corg + ((regs.bespitch * sh) / 4);
919 regs.besb1c3org = regs.besb1corg + ((regs.bespitch * sh) / 4);
920 regs.besb2c3org = regs.besb2corg + ((regs.bespitch * sh) / 4);
921 } else {
922 regs.besa1c3org = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ;
923 regs.besa2c3org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh;
924 regs.besb1c3org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh;
925 regs.besb2c3org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh;
926 regs.besa1corg = regs.besa1c3org + ((regs.bespitch * sh) / 4);
927 regs.besa2corg = regs.besa2c3org + ((regs.bespitch * sh) / 4);
928 regs.besb1corg = regs.besb1c3org + ((regs.bespitch * sh) / 4);
929 regs.besb2corg = regs.besb2c3org + ((regs.bespitch * sh) / 4);
930 }
931
932 }
933
934 weight = ofstop * (regs.besviscal >> 2);
935 weights = weight < 0 ? 1 : 0;
936 regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2);
937 regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF);
938
939 #ifdef CRTC2
940 // pridat hlavni registry - tj. casovani ...
941
942
943 switch(config->fourcc){
944 case IMGFMT_YV12:
945 case IMGFMT_I420:
946 case IMGFMT_IYUV:
947 cregs.c2ctl = 1 // CRTC2 enabled
948 + (1<<1) // external clock
949 + (0<<2) // external clock
950 + (1<<3) // pixel clock enable - not needed ???
951 + (0<<4) // high prioryty req
952 + (1<<5) // high prioryty req
953 + (0<<6) // high prioryty req
954 + (1<<8) // high prioryty req max
955 + (0<<9) // high prioryty req max
956 + (0<<10) // high prioryty req max
957 + (0<<20) // CRTC1 to DAC
958 + (1<<21) // 420 mode
959 + (1<<22) // 420 mode
960 + (1<<23) // 420 mode
961 + (0<<24) // single chroma line for 420 mode - need to be corrected
962 + (0<<25) /*/ interlace mode - need to be corrected*/
963 + (0<<26) // field legth polariry
964 + (0<<27) // field identification polariry
965 + (1<<28) // VIDRST detection mode
966 + (0<<29) // VIDRST detection mode
967 + (1<<30) // Horizontal counter preload
968 + (1<<31) // Vertical counter preload
969 ;
970 cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode
971 + (1<<1) // Y filter enable
972 + (1<<2) // CbCr filter enable
973 + (0<<3) // subpicture enable (disabled)
974 + (0<<4) // NTSC enable (disabled - PAL)
975 + (0<<5) // C2 static subpicture enable (disabled)
976 + (0<<6) // C2 subpicture offset division (disabled)
977 + (0<<7) // 422 subformat selection !
978 /* + (0<<8) // 15 bpp high alpha
979 + (0<<9) // 15 bpp high alpha
980 + (0<<10) // 15 bpp high alpha
981 + (0<<11) // 15 bpp high alpha
982 + (0<<12) // 15 bpp high alpha
983 + (0<<13) // 15 bpp high alpha
984 + (0<<14) // 15 bpp high alpha
985 + (0<<15) // 15 bpp high alpha
986 + (0<<16) // 15 bpp low alpha
987 + (0<<17) // 15 bpp low alpha
988 + (0<<18) // 15 bpp low alpha
989 + (0<<19) // 15 bpp low alpha
990 + (0<<20) // 15 bpp low alpha
991 + (0<<21) // 15 bpp low alpha
992 + (0<<22) // 15 bpp low alpha
993 + (0<<23) // 15 bpp low alpha
994 + (0<<24) // static subpicture key
995 + (0<<25) // static subpicture key
996 + (0<<26) // static subpicture key
997 + (0<<27) // static subpicture key
998 + (0<<28) // static subpicture key
999 */ ;
1000 break;
1001
1002 case IMGFMT_YUY2:
1003 cregs.c2ctl = 1 // CRTC2 enabled
1004 + (1<<1) // external clock
1005 + (0<<2) // external clock
1006 + (1<<3) // pixel clock enable - not needed ???
1007 + (0<<4) // high prioryty req - acc to spec
1008 + (1<<5) // high prioryty req
1009 + (0<<6) // high prioryty req
1010 // 7 reserved
1011 + (1<<8) // high prioryty req max
1012 + (0<<9) // high prioryty req max
1013 + (0<<10) // high prioryty req max
1014 // 11-19 reserved
1015 + (0<<20) // CRTC1 to DAC
1016 + (1<<21) // 422 mode
1017 + (0<<22) // 422 mode
1018 + (1<<23) // 422 mode
1019 + (0<<24) // single chroma line for 420 mode - need to be corrected
1020 + (0<<25) /*/ interlace mode - need to be corrected*/
1021 + (0<<26) // field legth polariry
1022 + (0<<27) // field identification polariry
1023 + (1<<28) // VIDRST detection mode
1024 + (0<<29) // VIDRST detection mode
1025 + (1<<30) // Horizontal counter preload
1026 + (1<<31) // Vertical counter preload
1027 ;
1028 cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode
1029 + (1<<1) // Y filter enable
1030 + (1<<2) // CbCr filter enable
1031 + (0<<3) // subpicture enable (disabled)
1032 + (0<<4) // NTSC enable (disabled - PAL)
1033 + (0<<5) // C2 static subpicture enable (disabled)
1034 + (0<<6) // C2 subpicture offset division (disabled)
1035 + (0<<7) // 422 subformat selection !
1036 /* + (0<<8) // 15 bpp high alpha
1037 + (0<<9) // 15 bpp high alpha
1038 + (0<<10) // 15 bpp high alpha
1039 + (0<<11) // 15 bpp high alpha
1040 + (0<<12) // 15 bpp high alpha
1041 + (0<<13) // 15 bpp high alpha
1042 + (0<<14) // 15 bpp high alpha
1043 + (0<<15) // 15 bpp high alpha
1044 + (0<<16) // 15 bpp low alpha
1045 + (0<<17) // 15 bpp low alpha
1046 + (0<<18) // 15 bpp low alpha
1047 + (0<<19) // 15 bpp low alpha
1048 + (0<<20) // 15 bpp low alpha
1049 + (0<<21) // 15 bpp low alpha
1050 + (0<<22) // 15 bpp low alpha
1051 + (0<<23) // 15 bpp low alpha
1052 + (0<<24) // static subpicture key
1053 + (0<<25) // static subpicture key
1054 + (0<<26) // static subpicture key
1055 + (0<<27) // static subpicture key
1056 + (0<<28) // static subpicture key
1057 */ ;
1058 break;
1059
1060 case IMGFMT_UYVY:
1061 cregs.c2ctl = 1 // CRTC2 enabled
1062 + (1<<1) // external clock
1063 + (0<<2) // external clock
1064 + (1<<3) // pixel clock enable - not needed ???
1065 + (0<<4) // high prioryty req
1066 + (1<<5) // high prioryty req
1067 + (0<<6) // high prioryty req
1068 + (1<<8) // high prioryty req max
1069 + (0<<9) // high prioryty req max
1070 + (0<<10) // high prioryty req max
1071 + (0<<20) // CRTC1 to DAC
1072 + (1<<21) // 422 mode
1073 + (0<<22) // 422 mode
1074 + (1<<23) // 422 mode
1075 + (1<<24) // single chroma line for 420 mode - need to be corrected
1076 + (1<<25) /*/ interlace mode - need to be corrected*/
1077 + (0<<26) // field legth polariry
1078 + (0<<27) // field identification polariry
1079 + (1<<28) // VIDRST detection mode
1080 + (0<<29) // VIDRST detection mode
1081 + (1<<30) // Horizontal counter preload
1082 + (1<<31) // Vertical counter preload
1083 ;
1084 cregs.c2datactl = 0 // enable dither - propably not needed, we are already in YUV mode
1085 + (1<<1) // Y filter enable
1086 + (1<<2) // CbCr filter enable
1087 + (0<<3) // subpicture enable (disabled)
1088 + (0<<4) // NTSC enable (disabled - PAL)
1089 + (0<<5) // C2 static subpicture enable (disabled)
1090 + (0<<6) // C2 subpicture offset division (disabled)
1091 + (1<<7) // 422 subformat selection !
1092 /* + (0<<8) // 15 bpp high alpha
1093 + (0<<9) // 15 bpp high alpha
1094 + (0<<10) // 15 bpp high alpha
1095 + (0<<11) // 15 bpp high alpha
1096 + (0<<12) // 15 bpp high alpha
1097 + (0<<13) // 15 bpp high alpha
1098 + (0<<14) // 15 bpp high alpha
1099 + (0<<15) // 15 bpp high alpha
1100 + (0<<16) // 15 bpp low alpha
1101 + (0<<17) // 15 bpp low alpha
1102 + (0<<18) // 15 bpp low alpha
1103 + (0<<19) // 15 bpp low alpha
1104 + (0<<20) // 15 bpp low alpha
1105 + (0<<21) // 15 bpp low alpha
1106 + (0<<22) // 15 bpp low alpha
1107 + (0<<23) // 15 bpp low alpha
1108 + (0<<24) // static subpicture key
1109 + (0<<25) // static subpicture key
1110 + (0<<26) // static subpicture key
1111 + (0<<27) // static subpicture key
1112 + (0<<28) // static subpicture key
1113 */ ;
1114 break;
1115 }
1116
1117 cregs.c2hparam=((hdispend - 8) << 16) | (htotal - 8);
1118 cregs.c2hsync=((hsyncend - 8) << 16) | (hsyncstart - 8);
1119
1120 cregs.c2misc=0 // CRTCV2 656 togg f0
1121 +(0<<1) // CRTCV2 656 togg f0
1122 +(0<<2) // CRTCV2 656 togg f0
1123 +(0<<4) // CRTCV2 656 togg f1
1124 +(0<<5) // CRTCV2 656 togg f1
1125 +(0<<6) // CRTCV2 656 togg f1
1126 +(0<<8) // Hsync active high
1127 +(0<<9) // Vsync active high
1128 // 16-27 c2vlinecomp - nevim co tam dat
1129 ;
1130 cregs.c2offset=(regs.bespitch << 1);
1131
1132 cregs.c2pl2startadd0=regs.besa1corg;
1133 // cregs.c2pl2startadd1=regs.besa2corg;
1134 cregs.c2pl3startadd0=regs.besa1c3org;
1135 // cregs.c2pl3startadd1=regs.besa2c3org;
1136
1137 cregs.c2preload=(vsyncstart << 16) | (hsyncstart); // from
1138
1139 cregs.c2spicstartadd0=0; // not used
1140 // cregs.c2spicstartadd1=0; // not used
1141
1142 cregs.c2startadd0=regs.besa1org;
1143 // cregs.c2startadd1=regs.besa2org;
1144
1145 cregs.c2subpiclut=0; //not used
1146
1147 cregs.c2vparam=((vdispend - 1) << 16) | (vtotal - 1);
1148 cregs.c2vsync=((vsyncend - 1) << 16) | (vsyncstart - 1);
1149 #endif /* CRTC2 */
1150
1151 mga_vid_write_regs(0);
1152 return(0);
1153 }
1154
1155 int vixPlaybackOn(void)
1156 {
1157 if (mga_verbose) printf("[mga] playback on\n");
1158
1159 vid_src_ready = 1;
1160 if(vid_overlay_on)
1161 {
1162 regs.besctl |= 1;
1163 mga_vid_write_regs(0);
1164 }
1165 #ifdef MGA_ALLOW_IRQ
1166 if (mga_irq != -1)
1167 enable_irq();
1168 #endif
1169 mga_next_frame=0;
1170
1171 return(0);
1172 }
1173
1174 int vixPlaybackOff(void)
1175 {
1176 if (mga_verbose) printf("[mga] playback off\n");
1177
1178 vid_src_ready = 0;
1179 #ifdef MGA_ALLOW_IRQ
1180 if (mga_irq != -1)
1181 disable_irq();
1182 #endif
1183 regs.besctl &= ~1;
1184 regs.besglobctl &= ~(1<<6); /* UYVY format selected */
1185 mga_vid_write_regs(0);
1186
1187 return(0);
1188 }
1189
1190 int vixProbe(int verbose,int force)
1191 {
1192 pciinfo_t lst[MAX_PCI_DEVICES];
1193 unsigned int i, num_pci;
1194 int err;
1195
1196 if (verbose) printf("[mga] probe\n");
1197
1198 mga_verbose = verbose;
1199
1200 is_g400 = -1;
1201
1202 err = pci_scan(lst, &num_pci);
1203 if (err)
1204 {
1205 printf("[mga] Error occurred during pci scan: %s\n", strerror(err));
1206 return(err);
1207 }
1208
1209 if (mga_verbose)
1210 printf("[mga] found %d pci devices\n", num_pci);
1211
1212 for (i = 0; i < num_pci; i++)
1213 {
1214 if (mga_verbose > 1)
1215 printf("[mga] pci[%d] vendor: %d device: %d\n",
1216 i, lst[i].vendor, lst[i].device);
1217 if (lst[i].vendor == VENDOR_MATROX)
1218 {
1219 if ((lst[i].command & PCI_COMMAND_IO) == 0)
1220 {
1221 printf("[mga] Device is disabled, ignoring\n");
1222 continue;
1223 }
1224 switch(lst[i].device)
1225 {
1226 case DEVICE_MATROX_MGA_G550_AGP:
1227 printf("[mga] Found MGA G550\n");
1228 is_g400 = 1;
1229 goto card_found;
1230 case DEVICE_MATROX_MGA_G400_AGP:
1231 printf("[mga] Found MGA G400/G450\n");
1232 is_g400 = 1;
1233 goto card_found;
1234 case DEVICE_MATROX_MGA_G200_AGP:
1235 printf("[mga] Found MGA G200 AGP\n");
1236 is_g400 = 0;
1237 goto card_found;
1238 case DEVICE_MATROX_MGA_G200:
1239 printf("[mga] Found MGA G200 PCI\n");
1240 is_g400 = 0;
1241 goto card_found;
1242 }
1243 }
1244 }
1245
1246 if (is_g400 == -1)
1247 {
1248 if (verbose) printf("[mga] Can't find chip\n");
1249 return(ENXIO);
1250 }
1251
1252 card_found:
1253 probed = 1;
1254 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));
1255
1256 mga_cap.device_id = pci_info.device; /* set device id in capabilites */
1257
1258 return(0);
1259 }
1260
1261 int vixInit(void)
1262 {
1263 unsigned int card_option = 0;
1264 int err;
1265
1266 if (mga_verbose) printf("[mga] init\n");
1267
1268 mga_vid_in_use = 0;
1269
1270 printf("Matrox MGA G200/G400/G450 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n");
1271 #ifdef CRCT2
1272 printf("Driver compiled with TV-out (second-head) support\n");
1273 #endif
1274
1275 if (!probed)
1276 {
1277 printf("[mga] driver was not probed but is being initializing\n");
1278 return(EINTR);
1279 }
1280
1281 #ifdef MGA_PCICONFIG_MEMDETECT
1282 pci_config_read(pci_info.bus, pci_info.card, pci_info.func,
1283 0x40, 4, &card_option);
1284 if (mga_verbose > 1) printf("[mga] OPTION word: 0x%08X mem: 0x%02X %s\n", card_option,
1285 (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM");
1286 #endif
1287
1288 if (mga_ram_size)
1289 {
1290 printf("[mga] RAMSIZE forced to %d MB\n", mga_ram_size);
1291 }
1292 else
1293 {
1294 #ifdef MGA_MEMORY_SIZE
1295 mga_ram_size = MGA_MEMORY_SIZE;
1296 printf("[mga] hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size);
1297 #else
1298 if (is_g400)
1299 {
1300 switch((card_option>>10)&0x17)
1301 {
1302 // SDRAM:
1303 case 0x00:
1304 case 0x04: mga_ram_size = 16; break;
1305 case 0x03: mga_ram_size = 32; break;
1306 // SGRAM:
1307 case 0x10:
1308 case 0x14: mga_ram_size = 32; break;
1309 case 0x11:
1310 case 0x12: mga_ram_size = 16; break;
1311 default:
1312 mga_ram_size = 16;
1313 printf("[mga] Couldn't detect RAMSIZE, assuming 16MB!\n");
1314 }
1315 }
1316 else
1317 {
1318 switch((card_option>>10)&0x17)
1319 {
1320 // case 0x10:
1321 // case 0x13: mga_ram_size = 8; break;
1322 default: mga_ram_size = 8;
1323 }
1324 }
1325
1326 #if 0
1327 // printf("List resources -----------\n");
1328 for(temp=0;temp<DEVICE_COUNT_RESOURCE;temp++){
1329 struct resource *res=&pci_dev->resource[temp];
1330 if(res->flags){
1331 int size=(1+res->end-res->start)>>20;
1332 printf("res %d: start: 0x%X end: 0x%X (%d MB) flags=0x%X\n",temp,res->start,res->end,size,res->flags);
1333 if(res->flags&(IORESOURCE_MEM|IORESOURCE_PREFETCH)){
1334 if(size>mga_ram_size && size<=64) mga_ram_size=size;
1335 }
1336 }
1337 }
1338 #endif
1339
1340 printf("[mga] detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size);
1341 #endif
1342 }
1343
1344 if (mga_ram_size)
1345 {
1346 if ((mga_ram_size < 4) || (mga_ram_size > 64))
1347 {
1348 printf("[mga] invalid RAMSIZE: %d MB\n", mga_ram_size);
1349 return(EINVAL);
1350 }
1351 }
1352
1353 if (mga_verbose > 1) printf("[mga] hardware addresses: mmio: %#x, framebuffer: %#x\n",
1354 pci_info.base1, pci_info.base0);
1355
1356 mga_mmio_base = map_phys_mem(pci_info.base1,0x4000);
1357 mga_mem_base = map_phys_mem(pci_info.base0,mga_ram_size*1024*1024);
1358
1359 if (mga_verbose > 1) printf("[mga] MMIO at %p, IRQ: %d, framebuffer: %p\n",
1360 mga_mmio_base, mga_irq, mga_mem_base);
1361 err = mtrr_set_type(pci_info.base0,mga_ram_size*1024*1024,MTRR_TYPE_WRCOMB);
1362 if(!err) printf("[mga] Set write-combining type of video memory\n");
1363 #ifdef MGA_ALLOW_IRQ
1364 if (mga_irq != -1)
1365 {
1366 int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq);
1367 if (tmp)
1368 {
1369 printf("syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp);
1370 mga_irq=-1;
1371 }
1372 else
1373 {
1374 printf("syncfb (mga): registered irq %d\n", mga_irq);
1375 }
1376 }
1377 else
1378 {
1379 printf("syncfb (mga): No valid irq was found\n");
1380 mga_irq=-1;
1381 }
1382 #else
1383 printf("syncfb (mga): IRQ disabled in mga_vid.c\n");
1384 mga_irq=-1;
1385 #endif
1386
1387 return(0);
1388 }
1389
1390 void vixDestroy(void)
1391 {
1392 if (mga_verbose) printf("[mga] destroy\n");
1393
1394 /* FIXME turn off BES */
1395 vid_src_ready = 0;
1396 regs.besctl &= ~1;
1397 regs.besglobctl &= ~(1<<6); // UYVY format selected
1398 // mga_config.colkey_on=0; //!!!
1399 mga_vid_write_regs(1);
1400 mga_vid_in_use = 0;
1401
1402 #ifdef MGA_ALLOW_IRQ
1403 if (mga_irq != -1)
1404 free_irq(mga_irq, &mga_irq);
1405 #endif
1406
1407 if (mga_mmio_base)
1408 unmap_phys_mem(mga_mmio_base, 0x4000);
1409 if (mga_mem_base)
1410 unmap_phys_mem(mga_mem_base, mga_ram_size);
1411 return;
1412 }
1413
1414 int vixQueryFourcc(vidix_fourcc_t *to)
1415 {
1416 if (mga_verbose) printf("[mga] query fourcc (%x)\n", to->fourcc);
1417
1418 switch(to->fourcc)
1419 {
1420 case IMGFMT_YV12:
1421 case IMGFMT_IYUV:
1422 case IMGFMT_I420:
1423 case IMGFMT_YUY2:
1424 case IMGFMT_UYVY:
1425 break;
1426 default:
1427 to->depth = to->flags = 0;
1428 return(ENOTSUP);
1429 }
1430
1431 to->depth = VID_DEPTH_12BPP |
1432 VID_DEPTH_15BPP | VID_DEPTH_16BPP |
1433 VID_DEPTH_24BPP | VID_DEPTH_32BPP;
1434 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
1435 return(0);
1436 }
1437
1438 unsigned int vixGetVersion(void)
1439 {
1440 return(VIDIX_VERSION);
1441 }
1442
1443 int vixGetCapability(vidix_capability_t *to)
1444 {
1445 memcpy(to, &mga_cap, sizeof(vidix_capability_t));
1446 return(0);
1447 }
1448
1449 int vixGetGrKeys(vidix_grkey_t *grkey)
1450 {
1451 memcpy(grkey, &mga_grkey, sizeof(vidix_grkey_t));
1452 return(0);
1453 }
1454
1455 int vixSetGrKeys(const vidix_grkey_t *grkey)
1456 {
1457 memcpy(&mga_grkey, grkey, sizeof(vidix_grkey_t));
1458 mga_vid_write_regs(0);
1459 return(0);
1460 }
1461
1462 int vixPlaybackSetEq( const vidix_video_eq_t * eq)
1463 {
1464 /* contrast and brightness control isn't supported on G200 - alex */
1465 if (!is_g400)
1466 {
1467 if (mga_verbose) printf("[mga] equalizer isn't supported with G200\n");
1468 return(ENOTSUP);
1469 }
1470
1471 // only brightness&contrast are supported:
1472 if(!(eq->cap & (VEQ_CAP_BRIGHTNESS|VEQ_CAP_CONTRAST)))
1473 return(ENOTSUP);
1474
1475 //regs.beslumactl = readl(mga_mmio_base + BESLUMACTL);
1476 // printf("LUMA = %08X \n",regs.beslumactl);
1477 if (eq->cap & VEQ_CAP_BRIGHTNESS) {
1478 regs.beslumactl &= 0xFFFF;
1479 regs.beslumactl |= (eq->brightness*255/2000)<<16;
1480 }
1481 if (eq->cap & VEQ_CAP_CONTRAST) {
1482 regs.beslumactl &= 0xFFFF0000;
1483 regs.beslumactl |= (128+eq->contrast*255/2000)&0xFFFF;
1484 }
1485 writel(regs.beslumactl,mga_mmio_base + BESLUMACTL);
1486
1487 return(0);
1488 }
1489
1490 int vixPlaybackGetEq( vidix_video_eq_t * eq)
1491 {
1492 /* contrast and brightness control isn't supported on G200 - alex */
1493 if (!is_g400)
1494 {
1495 if (mga_verbose) printf("[mga] equalizer isn't supported with G200\n");
1496 return(ENOTSUP);
1497 }
1498
1499 // regs.beslumactl = readl(mga_mmio_base + BESLUMACTL);
1500
1501 eq->brightness = (signed short int)(regs.beslumactl >> 16) * 1000 / 128;
1502 eq->contrast = (signed short int)(regs.beslumactl & 0xFFFF) * 1000 / 128 - 1000;
1503 eq->cap = VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST;
1504
1505 printf("MGA GET_EQ: br=%d c=%d \n",eq->brightness,eq->contrast);
1506
1507 return(0);
1508 }