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comparison vidix/nvidia_vid.c @ 22850:9a1e26fef45b

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Move driver files directly into the vidix directory.
author diego
date Sun, 01 Apr 2007 00:02:43 +0000
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children 77def5093daf
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22849:bddb09395c3e 22850:9a1e26fef45b
1 /*
2 nvidia_vid - VIDIX based video driver for NVIDIA chips
3 Copyrights 2003 - 2004 Sascha Sommer. This file is based on sources from
4 RIVATV (rivatv.sf.net)
5 Licence: GPL
6 WARNING: THIS DRIVER IS IN BETA STAGE
7
8 multi buffer support and TNT2 fixes by Dmitry Baryshkov
9 */
10
11
12 #include <errno.h>
13 #include <stdio.h>
14 #include <stdlib.h>
15 #include <string.h>
16 #include <math.h>
17 #include <inttypes.h>
18 #include <unistd.h>
19
20
21 #include "vidix.h"
22 #include "fourcc.h"
23 #include "../libdha/libdha.h"
24 #include "../libdha/pci_ids.h"
25 #include "../libdha/pci_names.h"
26 #include "../config.h"
27 #include "../libavutil/common.h"
28 #include "../mpbswap.h"
29
30
31 pciinfo_t pci_info;
32
33
34 #define MAX_FRAMES 3
35 #define NV04_BES_SIZE 1024*2000*4
36
37
38 static vidix_capability_t nvidia_cap = {
39 "NVIDIA RIVA OVERLAY DRIVER",
40 "Sascha Sommer <saschasommer@freenet.de>",
41 TYPE_OUTPUT,
42 { 0, 0, 0, 0 },
43 2046,
44 2046,
45 4,
46 4,
47 -1,
48 FLAG_UPSCALER|FLAG_DOWNSCALER,
49 VENDOR_NVIDIA2,
50 -1,
51 { 0, 0, 0, 0 }
52 };
53
54
55 unsigned int vixGetVersion(void){
56 return(VIDIX_VERSION);
57 }
58
59
60 #define NV_ARCH_03 0x03
61 #define NV_ARCH_04 0x04
62 #define NV_ARCH_10 0x10
63 #define NV_ARCH_20 0x20
64 #define NV_ARCH_30 0x30
65
66 // since no useful information whatsoever is passed
67 // to the equalizer functions we need this
68 static struct {
69 uint32_t lum; // luminance (brightness + contrast)
70 uint32_t chrom; // chrominance (saturation + hue)
71 uint8_t red_off; // for NV03/NV04
72 uint8_t green_off;
73 uint8_t blue_off;
74 vidix_video_eq_t vals;
75 } eq;
76
77 struct nvidia_cards {
78 unsigned short chip_id;
79 unsigned short arch;
80 };
81
82
83 static struct nvidia_cards nvidia_card_ids[] = {
84 /*NV03*/
85 {DEVICE_NVIDIA2_RIVA128, NV_ARCH_03},
86 {DEVICE_NVIDIA2_RIVA128ZX,NV_ARCH_03},
87 /*NV04*/
88 {DEVICE_NVIDIA_NV4_RIVA_TNT,NV_ARCH_04},
89 {DEVICE_NVIDIA_NV5_RIVA_TNT2,NV_ARCH_04},
90 {DEVICE_NVIDIA_NV5_RIVA_TNT22,NV_ARCH_04},
91 {DEVICE_NVIDIA_NV5_RIVA_TNT23,NV_ARCH_04},
92 {DEVICE_NVIDIA_NV5_RIVA_TNT24,NV_ARCH_04},
93 {DEVICE_NVIDIA_NV6_VANTA,NV_ARCH_04},
94 {DEVICE_NVIDIA_RIVA_TNT2_MODEL,NV_ARCH_04},
95 {DEVICE_NVIDIA_NV6_VANTA2,NV_ARCH_04},
96 {DEVICE_NVIDIA_NV6_VANTA3,NV_ARCH_04},
97 {DEVICE_NVIDIA_NV5_RIVA_TNT25,NV_ARCH_04},
98 {DEVICE_NVIDIA2_TNT,NV_ARCH_04},
99 {DEVICE_NVIDIA2_TNT2,NV_ARCH_04},
100 {DEVICE_NVIDIA2_VTNT2,NV_ARCH_04},
101 {DEVICE_NVIDIA2_UTNT2 ,NV_ARCH_04},
102 {DEVICE_NVIDIA2_ITNT2,NV_ARCH_04},
103 /*NV10*/
104 {DEVICE_NVIDIA_NV10_GEFORCE_256,NV_ARCH_10},
105 {DEVICE_NVIDIA_NV10_GEFORCE_2562,NV_ARCH_10},
106 {DEVICE_NVIDIA_NV11_GEFORCE2_MX,NV_ARCH_10},
107 {DEVICE_NVIDIA_NV11_GEFORCE2_MX2,NV_ARCH_10},
108 {DEVICE_NVIDIA_NV11_GEFORCE2_GO,NV_ARCH_10},
109 {DEVICE_NVIDIA_NV11_GEFORCE2_MXR ,NV_ARCH_10},
110 {DEVICE_NVIDIA_NV15_GEFORCE2_GTS,NV_ARCH_10},
111 {DEVICE_NVIDIA_NV15_GEFORCE2_TI,NV_ARCH_10},
112 {DEVICE_NVIDIA_NV15_GEFORCE2_ULTRA,NV_ARCH_10},
113 {DEVICE_NVIDIA_NV17_GEFORCE4_MX460,NV_ARCH_10},
114 {DEVICE_NVIDIA_NV17_GEFORCE4_MX440,NV_ARCH_10},
115 {DEVICE_NVIDIA_NV17_GEFORCE4_MX420,NV_ARCH_10},
116 {DEVICE_NVIDIA_NV17_GEFORCE4_440,NV_ARCH_10},
117 {DEVICE_NVIDIA_NV17_GEFORCE4_420,NV_ARCH_10},
118 {DEVICE_NVIDIA_NV17_GEFORCE4_4202,NV_ARCH_10},
119 {DEVICE_NVIDIA_NV17_GEFORCE4_4402,NV_ARCH_10},
120 {DEVICE_NVIDIA_NV18_GEFORCE4_MX440,NV_ARCH_10},
121 {DEVICE_NVIDIA_NV15_GEFORCE2,NV_ARCH_10},
122 /*NV20*/
123 {DEVICE_NVIDIA_NV20_GEFORCE3,NV_ARCH_20},
124 {DEVICE_NVIDIA_NV20_GEFORCE3_TI200,NV_ARCH_20},
125 {DEVICE_NVIDIA_NV20_GEFORCE3_TI500,NV_ARCH_20},
126 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4600,NV_ARCH_20},
127 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4400,NV_ARCH_20},
128 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4200,NV_ARCH_20},
129 {DEVICE_NVIDIA_QUADRO4_900XGL,NV_ARCH_20},
130 {DEVICE_NVIDIA_QUADRO4_750XGL,NV_ARCH_20},
131 {DEVICE_NVIDIA_QUADRO4_700XGL,NV_ARCH_20},
132 {DEVICE_NVIDIA_NV28_GEFORCE4_TI,NV_ARCH_20},
133 {DEVICE_NVIDIA_NV28_GEFORCE4_TI2,NV_ARCH_20},
134 {DEVICE_NVIDIA_NV28_GEFORCE4_TI3,NV_ARCH_20},
135 {DEVICE_NVIDIA_NV28_GEFORCE4_TI4,NV_ARCH_20},
136 {DEVICE_NVIDIA_NV28GL_QUADRO4_980,NV_ARCH_20},
137 {DEVICE_NVIDIA_NV28GL_QUADRO4_780,NV_ARCH_20},
138 /*NV30*/
139 {DEVICE_NVIDIA_NV30_GEFORCE_FX,NV_ARCH_30},
140 {DEVICE_NVIDIA_NV30_GEFORCE_FX2,NV_ARCH_30},
141 {DEVICE_NVIDIA_NV30_GEFORCE_FX3,NV_ARCH_30},
142 {DEVICE_NVIDIA_NV30GL_QUADRO_FX,NV_ARCH_30},
143 {DEVICE_NVIDIA_NV30GL_QUADRO_FX2,NV_ARCH_30},
144 {DEVICE_NVIDIA_NV31_GEFORCE_FX,NV_ARCH_30},
145 {DEVICE_NVIDIA_NV31_GEFORCE_FX2,NV_ARCH_30},
146 {DEVICE_NVIDIA_NV34_GEFORCE_FX,NV_ARCH_30},
147 {DEVICE_NVIDIA_NV34_GEFORCE_FX2,NV_ARCH_30},
148 {DEVICE_NVIDIA_NV34_GEFORCE_FX3,NV_ARCH_30},
149 {DEVICE_NVIDIA_NV34M_GEFORCE_FX,NV_ARCH_30},
150 {DEVICE_NVIDIA_NV34GL_QUADRO_FX,NV_ARCH_30},
151 {DEVICE_NVIDIA_NV35_GEFORCE_FX,NV_ARCH_30},
152 {DEVICE_NVIDIA_NV35_GEFORCE_FX2,NV_ARCH_30},
153 {DEVICE_NVIDIA_NV35GL_QUADRO_FX,NV_ARCH_30},
154 {DEVICE_NVIDIA_NV36_GEFORCE_FX,NV_ARCH_30},
155 };
156
157
158 static int find_chip(unsigned chip_id){
159 unsigned i;
160 for(i = 0;i < sizeof(nvidia_card_ids)/sizeof(struct nvidia_cards);i++)
161 {
162 if(chip_id == nvidia_card_ids[i].chip_id)return i;
163 }
164 return -1;
165 }
166
167 int vixProbe(int verbose, int force){
168 pciinfo_t lst[MAX_PCI_DEVICES];
169 unsigned i,num_pci;
170 int err;
171
172 if (force)
173 printf("[nvidia_vid]: warning: forcing not supported yet!\n");
174 err = pci_scan(lst,&num_pci);
175 if(err){
176 printf("[nvidia_vid] Error occurred during pci scan: %s\n",strerror(err));
177 return err;
178 }
179 else {
180 err = ENXIO;
181 for(i=0; i < num_pci; i++){
182 if(lst[i].vendor == VENDOR_NVIDIA2 || lst[i].vendor == VENDOR_NVIDIA){
183 int idx;
184 const char *dname;
185 idx = find_chip(lst[i].device);
186 if(idx == -1)
187 continue;
188 dname = pci_device_name(lst[i].vendor, lst[i].device);
189 dname = dname ? dname : "Unknown chip";
190 printf("[nvidia_vid] Found chip: %s\n", dname);
191 if ((lst[i].command & PCI_COMMAND_IO) == 0){
192 printf("[nvidia_vid] Device is disabled, ignoring\n");
193 continue;
194 }
195 nvidia_cap.device_id = lst[i].device;
196 err = 0;
197 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));
198 break;
199 }
200 }
201 }
202 if(err && verbose) printf("[nvidia_vid] Can't find chip\n");
203 return err;
204 }
205
206
207
208
209 /*
210 * PCI-Memory IO access macros.
211 */
212
213 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory")
214
215 #undef VID_WR08
216 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); })
217 #undef VID_RD08
218 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; })
219
220 #undef VID_WR32
221 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=val; })
222 #undef VID_RD32
223 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; })
224
225 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val))
226 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val))
227 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val))
228
229
230
231
232
233
234 struct rivatv_chip {
235 volatile uint32_t *PMC; /* general control */
236 volatile uint32_t *PME; /* multimedia port */
237 volatile uint32_t *PFB; /* framebuffer control */
238 volatile uint32_t *PVIDEO; /* overlay control */
239 volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */
240 volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */
241 volatile uint32_t *PRAMIN; /* instance memory */
242 volatile uint32_t *PRAMHT; /* hash table */
243 volatile uint32_t *PRAMFC; /* fifo context table */
244 volatile uint32_t *PRAMRO; /* fifo runout table */
245 volatile uint32_t *PFIFO; /* fifo control region */
246 volatile uint32_t *FIFO; /* fifo channels (USER) */
247 volatile uint32_t *PGRAPH; /* graphics engine */
248
249 unsigned long fbsize; /* framebuffer size */
250 int arch; /* compatible NV_ARCH_XX define */
251 int realarch; /* real architecture */
252 void (* lock) (struct rivatv_chip *, int);
253 };
254 typedef struct rivatv_chip rivatv_chip;
255
256
257 struct rivatv_info {
258 unsigned int use_colorkey;
259 unsigned int colorkey; /* saved xv colorkey*/
260 unsigned int vidixcolorkey; /*currently used colorkey*/
261 unsigned int depth;
262 unsigned int format;
263 unsigned int pitch;
264 unsigned int width,height;
265 unsigned int d_width,d_height; /*scaled width && height*/
266 unsigned int wx,wy; /*window x && y*/
267 unsigned int screen_x; /*screen width*/
268 unsigned int screen_y; /*screen height*/
269 unsigned long buffer_size; /* size of the image buffer */
270 struct rivatv_chip chip; /* NV architecture structure */
271 void* video_base; /* virtual address of control region */
272 void* control_base; /* virtual address of fb region */
273 void* picture_base; /* direct pointer to video picture */
274 unsigned long picture_offset; /* offset of video picture in frame buffer */
275 // struct rivatv_dma dma; /* DMA structure */
276 unsigned int cur_frame;
277 unsigned int num_frames; /* number of buffers */
278 int bps; /* bytes per line */
279 };
280 typedef struct rivatv_info rivatv_info;
281
282 //framebuffer size funcs
283 static unsigned long rivatv_fbsize_nv03 (struct rivatv_chip *chip){
284 if (VID_RD32 (chip->PFB, 0) & 0x00000020) {
285 if (((VID_RD32 (chip->PMC, 0) & 0xF0) == 0x20)
286 && ((VID_RD32 (chip->PMC, 0) & 0x0F) >= 0x02)) {
287 /* SDRAM 128 ZX. */
288 return ((1 << (VID_RD32 (chip->PFB, 0) & 0x03)) * 1024 * 1024);
289 }
290 else {
291 return 1024 * 1024 * 8;
292 }
293 }
294 else {
295 /* SGRAM 128. */
296 switch (VID_RD32(chip->PFB, 0) & 0x00000003) {
297 case 0:
298 return 1024 * 1024 * 8;
299 break;
300 case 2:
301 return 1024 * 1024 * 4;
302 break;
303 default:
304 return 1024 * 1024 * 2;
305 break;
306 }
307 }
308 }
309 static unsigned long rivatv_fbsize_nv04 (struct rivatv_chip *chip){
310 if (VID_RD32 (chip->PFB, 0) & 0x00000100) {
311 return ((VID_RD32 (chip->PFB, 0) >> 12) & 0x0F) * 1024 * 1024 * 2
312 + 1024 * 1024 * 2;
313 } else {
314 switch (VID_RD32 (chip->PFB, 0) & 0x00000003) {
315 case 0:
316 return 1024 * 1024 * 32;
317 break;
318 case 1:
319 return 1024 * 1024 * 4;
320 break;
321 case 2:
322 return 1024 * 1024 * 8;
323 break;
324 case 3:
325 default:
326 return 1024 * 1024 * 16;
327 break;
328 }
329 }
330 }
331
332 static unsigned long rivatv_fbsize_nv10 (struct rivatv_chip *chip){
333 return VID_RD32 (chip->PFB, 0x20C) & 0xFFF00000;
334 }
335
336 //lock funcs
337 static void rivatv_lock_nv03 (struct rivatv_chip *chip, int LockUnlock){
338 VID_WR08 (chip->PVIO, 0x3C4, 0x06);
339 VID_WR08 (chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57);
340 }
341
342 static void rivatv_lock_nv04 (struct rivatv_chip *chip, int LockUnlock){
343 VID_WR08 (chip->PCIO, 0x3C4, 0x06);
344 VID_WR08 (chip->PCIO, 0x3C5, LockUnlock ? 0x99 : 0x57);
345 VID_WR08 (chip->PCIO, 0x3D4, 0x1F);
346 VID_WR08 (chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57);
347 }
348
349
350
351
352 /* Enable PFB (Framebuffer), PVIDEO (Overlay unit) and PME (Mediaport) if neccessary. */
353 static void rivatv_enable_PMEDIA (struct rivatv_info *info){
354 uint32_t reg;
355
356 /* switch off interrupts once for a while */
357 // VID_WR32 (info->chip.PME, 0x200140, 0x00);
358 // VID_WR32 (info->chip.PMC, 0x000140, 0x00);
359
360 reg = VID_RD32 (info->chip.PMC, 0x000200);
361
362 /* NV3 (0x10100010): NV03_PMC_ENABLE_PMEDIA, NV03_PMC_ENABLE_PFB, NV03_PMC_ENABLE_PVIDEO */
363
364 if ((reg & 0x10100010) != 0x10100010) {
365 printf("PVIDEO and PFB disabled, enabling...\n");
366 VID_OR32 (info->chip.PMC, 0x000200, 0x10100010);
367 }
368
369 /* save the current colorkey */
370 switch (info->chip.arch ) {
371 case NV_ARCH_10:
372 case NV_ARCH_20:
373 case NV_ARCH_30:
374 /* NV_PVIDEO_COLOR_KEY */
375 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0xB00);
376 break;
377 case NV_ARCH_03:
378 case NV_ARCH_04:
379 /* NV_PVIDEO_KEY */
380 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0x240);
381 break;
382 }
383
384
385 /* re-enable interrupts again */
386 // VID_WR32 (info->chip.PMC, 0x000140, 0x01);
387 // VID_WR32 (info->chip.PME, 0x200140, 0x01);
388 }
389
390 /* Stop overlay video. */
391 static void rivatv_overlay_stop (struct rivatv_info *info) {
392 switch (info->chip.arch ) {
393 case NV_ARCH_10:
394 case NV_ARCH_20:
395 case NV_ARCH_30:
396 /* NV_PVIDEO_COLOR_KEY */
397 /* Xv-Extension-Hack: Restore previously saved value. */
398 VID_WR32 (info->chip.PVIDEO, 0xB00, info->colorkey);
399 /* NV_PVIDEO_STOP */
400 VID_OR32 (info->chip.PVIDEO, 0x704, 0x11);
401 /* NV_PVIDEO_BUFFER */
402 VID_AND32 (info->chip.PVIDEO, 0x700, ~0x11);
403 /* NV_PVIDEO_INTR_EN_BUFFER */
404 // VID_AND32 (info->chip.PVIDEO, 0x140, ~0x11);
405 break;
406 case NV_ARCH_03:
407 case NV_ARCH_04:
408 /* NV_PVIDEO_KEY */
409 VID_WR32 (info->chip.PVIDEO, 0x240, info->colorkey);
410 /* NV_PVIDEO_OVERLAY_VIDEO_OFF */
411 VID_AND32 (info->chip.PVIDEO, 0x244, ~0x01);
412 /* NV_PVIDEO_INTR_EN_0_NOTIFY */
413 // VID_AND32 (info->chip.PVIDEO, 0x140, ~0x01);
414 /* NV_PVIDEO_OE_STATE */
415 VID_WR32 (info->chip.PVIDEO, 0x224, 0);
416 /* NV_PVIDEO_SU_STATE */
417 VID_WR32 (info->chip.PVIDEO, 0x228, 0);
418 /* NV_PVIDEO_RM_STATE */
419 VID_WR32 (info->chip.PVIDEO, 0x22C, 0);
420 break;
421 }
422 }
423
424 /* Get pan offset of the physical screen. */
425 static uint32_t rivatv_overlay_pan (struct rivatv_info *info){
426 uint32_t pan;
427 info->chip.lock (&info->chip, 0);
428 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0D);
429 pan = VID_RD08 (info->chip.PCIO, 0x3D5);
430 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0C);
431 pan |= VID_RD08 (info->chip.PCIO, 0x3D5) << 8;
432 VID_WR08 (info->chip.PCIO, 0x3D4, 0x19);
433 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x1F) << 16;
434 VID_WR08 (info->chip.PCIO, 0x3D4, 0x2D);
435 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x60) << 16;
436 return pan << 2;
437 }
438
439 /* Compute and set colorkey depending on the colour depth. */
440 static void rivatv_overlay_colorkey (rivatv_info* info, unsigned int chromakey){
441 uint32_t r, g, b, key = 0;
442
443 r = (chromakey & 0x00FF0000) >> 16;
444 g = (chromakey & 0x0000FF00) >> 8;
445 b = chromakey & 0x000000FF;
446 switch (info->depth) {
447 case 15:
448 key = ((r >> 3) << 10) | ((g >> 3) << 5) | ((b >> 3));
449 #ifndef WIN32
450 key = key | 0x00008000;
451 #endif
452 break;
453 case 16: // XXX unchecked
454 key = ((r >> 3) << 11) | ((g >> 2) << 5) | ((b >> 3));
455 #ifndef WIN32
456 key = key | 0x00008000;
457 #endif
458 break;
459 case 24: // XXX unchecked, maybe swap order of masking - FIXME Can the card be in 24 bit mode anyway?
460 key = (chromakey & 0x00FFFFFF) | 0x00800000;
461 break;
462 case 32:
463 key = chromakey;
464 #ifndef WIN32
465 key = key | 0x80000000;
466 #endif
467 break;
468 }
469 //printf("[nvidia_vid] depth=%d %08X \n", info->depth, chromakey);
470 switch (info->chip.arch) {
471 case NV_ARCH_10:
472 case NV_ARCH_20:
473 case NV_ARCH_30:
474 VID_WR32 (info->chip.PVIDEO, 0xB00, key);
475 break;
476 case NV_ARCH_03:
477 case NV_ARCH_04:
478 VID_WR32 (info->chip.PVIDEO, 0x240, key);
479 break;
480 }
481 }
482
483 static void nv_getscreenproperties(struct rivatv_info *info){
484 uint32_t bpp=0,x;
485 info->chip.lock(&info->chip, 0);
486 /*get screen depth*/
487 VID_WR08(info->chip.PCIO, 0x03D4,0x28);
488 bpp = VID_RD08(info->chip.PCIO,0x03D5)&0x3;
489 if((bpp == 2) && (VID_RD32(info->chip.PVIDEO,0x600) & 0x00001000) == 0x0)info->depth=15;
490 else info->depth = 0x04 << bpp;
491 /*get screen width*/
492 VID_WR08(info->chip.PCIO, 0x03D4, 0x1);
493 info->screen_x = (1 + VID_RD08(info->chip.PCIO, 0x3D5)) * 8;
494 /*get screen height*/
495 /* get first 8 bits in VT_DISPLAY_END*/
496 VID_WR08(info->chip.PCIO, 0x03D4, 0x12);
497 info->screen_y = VID_RD08(info->chip.PCIO,0x03D5);
498 VID_WR08(info->chip.PCIO,0x03D4,0x07);
499 /* get 9th bit in CRTC_OVERFLOW*/
500 info->screen_y |= (VID_RD08(info->chip.PCIO,0x03D5) &0x02)<<7;
501 /* and the 10th in CRTC_OVERFLOW*/
502 info->screen_y |=(VID_RD08(info->chip.PCIO,0x03D5) &0x40)<<3;
503 ++info->screen_y;
504
505 /* NV_PCRTC_OFFSET */
506 VID_WR08 (info->chip.PCIO, 0x3D4, 0x13);
507 x = VID_RD08 (info->chip.PCIO, 0x3D5);
508 /* NV_PCRTC_REPAINT0_OFFSET_10_8 */
509 VID_WR08 (info->chip.PCIO, 0x3D4, 0x19);
510 x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0xE0) << 3;
511 /* NV_PCRTC_EXTRA_OFFSET_11 */
512 VID_WR08 (info->chip.PCIO, 0x3D4, 0x25);
513 x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x20) << 6; x <<= 3;
514 info->bps = x * bpp;
515 }
516
517
518
519
520 /* Start overlay video. */
521 static void rivatv_overlay_start (struct rivatv_info *info,int bufno){
522 uint32_t base, size, offset, xscale, yscale, pan;
523 uint32_t value;
524 int x=info->wx, y=info->wy;
525 int lwidth=info->d_width, lheight=info->d_height;
526
527 size = info->buffer_size;
528 base = info->picture_offset;
529 offset = bufno*size;
530 /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/
531 nv_getscreenproperties(info);
532
533 if(info->depth){
534 /* get pan offset of the physical screen */
535 pan = rivatv_overlay_pan (info);
536 /* adjust window position depending on the pan offset */
537 if (info->bps != 0)
538 {
539 x = info->wx - (pan % info->bps) * 8 / info->depth;
540 y = info->wy - (pan / info->bps);
541 }
542 } else {
543 // we can't adjust the window position correctly in textmode
544 // setting y to 8 seems to work ok, though
545 if(info->chip.arch < NV_ARCH_10 && y < 8) y = 8;
546 }
547
548 /* adjust negative output window variables */
549 if (x < 0) {
550 lwidth = info->d_width + x;
551 offset += (-x * info->width / info->d_width) << 1;
552 // offset += (-window->x * port->vld_width / window->width) << 1;
553 x = 0;
554 }
555 if (y < 0) {
556 lheight = info->d_height + y;
557 offset += (-y * info->height / info->d_height * info->width) << 1;
558 // offset += (-window->y * port->vld_height / window->height * port->org_width) << 1;
559 y = 0;
560 }
561
562 switch (info->chip.arch) {
563 case NV_ARCH_10:
564 case NV_ARCH_20:
565 case NV_ARCH_30:
566
567 /* NV_PVIDEO_BASE */
568 VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base + offset);
569 //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base);
570 /* NV_PVIDEO_LIMIT */
571 VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + offset + size - 1);
572 //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1);
573
574 /* extra code for NV20 && NV30 architectures */
575 if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30) {
576 VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base + offset);
577 //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base);
578 VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + offset + size - 1);
579 //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1);
580 }
581
582 /* NV_PVIDEO_LUMINANCE */
583 VID_WR32 (info->chip.PVIDEO, 0x910 + 0, eq.lum);
584 //VID_WR32 (info->chip.PVIDEO, 0x910 + 4, 0x00001000);
585 /* NV_PVIDEO_CHROMINANCE */
586 VID_WR32 (info->chip.PVIDEO, 0x918 + 0, eq.chrom);
587 //VID_WR32 (info->chip.PVIDEO, 0x918 + 4, 0x00001000);
588
589 /* NV_PVIDEO_OFFSET */
590 VID_WR32 (info->chip.PVIDEO, 0x920 + 0, 0x0);
591 //VID_WR32 (info->chip.PVIDEO, 0x920 + 4, offset + pitch);
592 /* NV_PVIDEO_SIZE_IN */
593 VID_WR32 (info->chip.PVIDEO, 0x928 + 0, ((info->height) << 16) | info->width);
594 //VID_WR32 (info->chip.PVIDEO, 0x928 + 4, ((port->org_height/2) << 16) | port->org_width);
595 /* NV_PVIDEO_POINT_IN */
596 VID_WR32 (info->chip.PVIDEO, 0x930 + 0, 0x00000000);
597 //VID_WR32 (info->chip.PVIDEO, 0x930 + 4, 0x00000000);
598 /* NV_PVIDEO_DS_DX_RATIO */
599 VID_WR32 (info->chip.PVIDEO, 0x938 + 0, (info->width << 20) / info->d_width);
600 //VID_WR32 (info->chip.PVIDEO, 0x938 + 4, (port->org_width << 20) / window->width);
601 /* NV_PVIDEO_DT_DY_RATIO */
602 VID_WR32 (info->chip.PVIDEO, 0x940 + 0, ((info->height) << 20) / info->d_height);
603 //VID_WR32 (info->chip.PVIDEO, 0x940 + 4, ((port->org_height/2) << 20) / window->height);
604
605 /* NV_PVIDEO_POINT_OUT */
606 VID_WR32 (info->chip.PVIDEO, 0x948 + 0, ((y + 0) << 16) | x);
607 //VID_WR32 (info->chip.PVIDEO, 0x948 + 4, ((y + 0) << 16) | x);
608 /* NV_PVIDEO_SIZE_OUT */
609 VID_WR32 (info->chip.PVIDEO, 0x950 + 0, (lheight << 16) | lwidth);
610 //VID_WR32 (info->chip.PVIDEO, 0x950 + 4, (height << 16) | width);
611
612 /* NV_PVIDEO_FORMAT */
613 value = info->pitch;
614 if(info->use_colorkey)value |= 1 << 20;
615 if(info->format == IMGFMT_YUY2)value |= 1 << 16;
616 VID_WR32 (info->chip.PVIDEO, 0x958 + 0, value);
617 //VID_WR32 (info->chip.PVIDEO, 0x958 + 4, (pitch << 1) | 0x00100000);
618
619 /* NV_PVIDEO_INTR_EN_BUFFER */
620 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01/*0x11*/);
621 /* NV_PVIDEO_STOP */
622 VID_WR32 (info->chip.PVIDEO, 0x704,0x0);
623 /* NV_PVIDEO_BUFFER */
624 VID_WR32 (info->chip.PVIDEO, 0x700, 0x01/*0x11*/);
625 break;
626
627 case NV_ARCH_03:
628 case NV_ARCH_04:
629
630
631 /* NV_PVIDEO_OE_STATE */
632 VID_WR32 (info->chip.PVIDEO, 0x224, 0);
633 /* NV_PVIDEO_SU_STATE */
634 VID_WR32 (info->chip.PVIDEO, 0x228, 0);
635 /* NV_PVIDEO_RM_STATE */
636 VID_WR32 (info->chip.PVIDEO, 0x22C, 0);
637
638 /* NV_PVIDEO_BUFF0_START_ADDRESS */
639 VID_WR32 (info->chip.PVIDEO, 0x20C + 0, base + offset + 0);
640 VID_WR32 (info->chip.PVIDEO, 0x20C + 4, base + offset + 0);
641 /* NV_PVIDEO_BUFF0_PITCH_LENGTH */
642 VID_WR32 (info->chip.PVIDEO, 0x214 + 0, info->pitch);
643 VID_WR32 (info->chip.PVIDEO, 0x214 + 4, info->pitch);
644
645 /* NV_PVIDEO_WINDOW_START */
646 VID_WR32 (info->chip.PVIDEO, 0x230, (y << 16) | x);
647 /* NV_PVIDEO_WINDOW_SIZE */
648 VID_WR32 (info->chip.PVIDEO, 0x234, (lheight << 16) | lwidth);
649 /* NV_PVIDEO_STEP_SIZE */
650 yscale = ((info->height - 1) << 11) / (info->d_height - 1);
651 xscale = ((info->width - 1) << 11) / (info->d_width - 1);
652 VID_WR32 (info->chip.PVIDEO, 0x200, (yscale << 16) | xscale);
653
654 /* NV_PVIDEO_RED_CSC_OFFSET */
655 VID_WR32 (info->chip.PVIDEO, 0x280, eq.red_off);
656 /* NV_PVIDEO_GREEN_CSC_OFFSET */
657 VID_WR32 (info->chip.PVIDEO, 0x284, eq.green_off);
658 /* NV_PVIDEO_BLUE_CSC_OFFSET */
659 VID_WR32 (info->chip.PVIDEO, 0x288, eq.blue_off);
660 /* NV_PVIDEO_CSC_ADJUST */
661 VID_WR32 (info->chip.PVIDEO, 0x28C, 0x00000); /* No colour correction! */
662
663 /* NV_PVIDEO_CONTROL_Y (BLUR_ON, LINE_HALF) */
664 VID_WR32 (info->chip.PVIDEO, 0x204, 0x001);
665 /* NV_PVIDEO_CONTROL_X (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */
666 VID_WR32 (info->chip.PVIDEO, 0x208, 0x111); /*directx overlay 0x110 */
667
668 /* NV_PVIDEO_FIFO_BURST_LENGTH */
669 VID_WR32 (info->chip.PVIDEO, 0x23C, 0x03);
670 /* NV_PVIDEO_FIFO_THRES_SIZE */
671 VID_WR32 (info->chip.PVIDEO, 0x238, 0x38); /*windows uses 0x40*/
672
673 /* NV_PVIDEO_BUFF0_OFFSET */
674 VID_WR32 (info->chip.PVIDEO, 0x21C + 0, 0);
675 VID_WR32 (info->chip.PVIDEO, 0x21C + 4, 0);
676
677 /* NV_PVIDEO_INTR_EN_0_NOTIFY_ENABLED */
678 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01);
679
680 /* NV_PVIDEO_OVERLAY (KEY_ON, VIDEO_ON, FORMAT_CCIR) */
681 value = 0x1; /*video on*/
682 if(info->format==IMGFMT_YUY2)value |= 0x100;
683 if(info->use_colorkey)value |=0x10;
684 VID_WR32 (info->chip.PVIDEO, 0x244, value);
685
686 /* NV_PVIDEO_SU_STATE */
687 VID_XOR32 (info->chip.PVIDEO, 0x228, 1 << 16);
688 break;
689 }
690 /*set colorkey*/
691 rivatv_overlay_colorkey(info,info->vidixcolorkey);
692
693 }
694
695
696
697
698
699
700
701 static rivatv_info* info;
702
703
704
705
706 int vixInit(void){
707 int mtrr;
708 info = calloc(1,sizeof(rivatv_info));
709 info->control_base = map_phys_mem(pci_info.base0, 0x00C00000 + 0x00008000);
710 info->chip.arch = nvidia_card_ids[find_chip(pci_info.device)].arch;
711 printf("[nvidia_vid] arch %x register base %p\n",info->chip.arch,info->control_base);
712 info->chip.PFIFO = (uint32_t *) (info->control_base + 0x00002000);
713 info->chip.FIFO = (uint32_t *) (info->control_base + 0x00800000);
714 info->chip.PMC = (uint32_t *) (info->control_base + 0x00000000);
715 info->chip.PFB = (uint32_t *) (info->control_base + 0x00100000);
716 info->chip.PME = (uint32_t *) (info->control_base + 0x00000000);
717 info->chip.PCIO = (uint8_t *) (info->control_base + 0x00601000);
718 info->chip.PVIO = (uint8_t *) (info->control_base + 0x000C0000);
719 info->chip.PGRAPH = (uint32_t *) (info->control_base + 0x00400000);
720 /* setup chip specific functions */
721 switch (info->chip.arch) {
722 case NV_ARCH_03:
723 info->chip.lock = rivatv_lock_nv03;
724 info->chip.fbsize = rivatv_fbsize_nv03 (&info->chip);
725 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000);
726 break;
727 case NV_ARCH_04:
728 info->chip.lock = rivatv_lock_nv04;
729 info->chip.fbsize = rivatv_fbsize_nv04 (&info->chip);
730 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000);
731 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000);
732 break;
733 case NV_ARCH_10:
734 case NV_ARCH_20:
735 case NV_ARCH_30:
736 info->chip.lock = rivatv_lock_nv04;
737 info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip);
738 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000);
739 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000);
740 break;
741 }
742 switch (info->chip.arch) {
743 case NV_ARCH_03:
744 {
745 /* This maps framebuffer @6MB, thus 2MB are left for video. */
746 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize);
747 /* This may trash your screen for resolutions greater than 1024x768, sorry. */
748 info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1);
749 info->picture_base = info->video_base + info->picture_offset;
750 info->chip.PRAMIN = (uint32_t *) (info->video_base + 0x00C00000);
751 break;
752 }
753 case NV_ARCH_04:
754 case NV_ARCH_10:
755 case NV_ARCH_20:
756 case NV_ARCH_30:
757 {
758 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize);
759 info->picture_offset = info->chip.fbsize - NV04_BES_SIZE;
760 if(info->chip.fbsize > 16*1024*1024)
761 info->picture_offset -= NV04_BES_SIZE;
762 // info->picture_base = (unsigned long)map_phys_mem(pci_info.base1+info->picture_offset,NV04_BES_SIZE);
763 info->picture_base = info->video_base + info->picture_offset;
764 break;
765 }
766 }
767
768 printf("[nvidia_vid] detected memory size %u MB\n",(uint32_t)(info->chip.fbsize /1024/1024));
769
770 if ((mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB))!= 0)
771 printf("[nvidia_vid] unable to setup MTRR: %s\n", strerror(mtrr));
772 else
773 printf("[nvidia_vid] MTRR set up\n");
774
775 nv_getscreenproperties(info);
776 if(!info->depth)printf("[nvidia_vid] text mode: %ux%u\n",info->screen_x,info->screen_y);
777 else printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x,info->screen_y, info->depth);
778
779
780 rivatv_enable_PMEDIA(info);
781 info->cur_frame = 0;
782 info->use_colorkey = 0;
783
784 eq.lum = 0x00001000;
785 eq.chrom = 0x00001000;
786 memset(&eq.vals, 0, sizeof(vidix_video_eq_t));
787 eq.vals.cap = VEQ_CAP_BRIGHTNESS;
788 if (info->chip.arch > NV_ARCH_04)
789 eq.vals.cap |= VEQ_CAP_CONTRAST | VEQ_CAP_SATURATION | VEQ_CAP_HUE;
790 eq.red_off = 0x69;
791 eq.green_off = 0x3e;
792 eq.blue_off = 0x89;
793 return 0;
794 }
795
796 void vixDestroy(void){
797 unmap_phys_mem(info->control_base ,0x00C00000 + 0x00008000);
798 unmap_phys_mem(info->video_base, info->chip.fbsize);
799 free(info);
800 }
801
802 int vixGetCapability(vidix_capability_t *to){
803 memcpy(to, &nvidia_cap, sizeof(vidix_capability_t));
804 return 0;
805 }
806
807 inline static int is_supported_fourcc(uint32_t fourcc)
808 {
809 if (fourcc == IMGFMT_UYVY || fourcc == IMGFMT_YUY2)
810 return 1;
811 else
812 return 0;
813 }
814
815 int vixQueryFourcc(vidix_fourcc_t *to){
816 if(is_supported_fourcc(to->fourcc)){
817 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP |
818 VID_DEPTH_4BPP | VID_DEPTH_8BPP |
819 VID_DEPTH_12BPP| VID_DEPTH_15BPP|
820 VID_DEPTH_16BPP| VID_DEPTH_24BPP|
821 VID_DEPTH_32BPP;
822 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
823 return 0;
824 }
825 else to->depth = to->flags = 0;
826 return ENOSYS;
827 }
828
829 int vixConfigPlayback(vidix_playback_t *vinfo){
830 uint32_t i;
831 printf("called %s\n", __FUNCTION__);
832 if (! is_supported_fourcc(vinfo->fourcc))
833 return ENOSYS;
834
835 info->width = vinfo->src.w;
836 info->height = vinfo->src.h;
837
838 info->d_width = vinfo->dest.w;
839 info->d_height = vinfo->dest.h;
840 info->wx = vinfo->dest.x;
841 info->wy = vinfo->dest.y;
842 info->format = vinfo->fourcc;
843
844 printf("[nvidia_vid] setting up a %dx%d-%dx%d video window (src %dx%d), format 0x%X\n",
845 info->d_width, info->d_height, info->wx, info->wy, info->width, info->height, vinfo->fourcc);
846
847
848 vinfo->dga_addr=info->picture_base;
849
850 switch (vinfo->fourcc)
851 {
852 case IMGFMT_YUY2:
853 case IMGFMT_UYVY:
854
855 vinfo->dest.pitch.y = 64;
856 vinfo->dest.pitch.u = 0;
857 vinfo->dest.pitch.v = 0;
858
859 vinfo->offset.y = 0;
860 vinfo->offset.v = 0;
861 vinfo->offset.u = 0;
862 info->pitch = ((info->width << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1);
863 vinfo->frame_size = info->pitch * info->height;
864 break;
865 }
866 info->buffer_size = vinfo->frame_size;
867 info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size;
868 if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES;
869 // vinfo->num_frames = 1;
870 // printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames);
871 for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i;
872 return 0;
873 }
874
875 int vixPlaybackOn(void){
876 rivatv_overlay_start(info,info->cur_frame);
877 return 0;
878 }
879
880 int vixPlaybackOff(void){
881 rivatv_overlay_stop(info);
882 return 0;
883 }
884
885 int vixSetGrKeys( const vidix_grkey_t * grkey){
886 if (grkey->ckey.op == CKEY_FALSE)
887 {
888 info->use_colorkey = 0;
889 printf("[nvidia_vid] colorkeying disabled\n");
890 }
891 else {
892 info->use_colorkey = 1;
893 info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue);
894 printf("[nvidia_vid] set colorkey 0x%x\n",info->vidixcolorkey);
895 }
896 if(info->d_width && info->d_height)rivatv_overlay_start(info,0);
897 return 0;
898 }
899
900 int vixPlaybackFrameSelect(unsigned int frame){
901 // printf("selecting buffer %d\n", frame);
902 rivatv_overlay_start(info, frame);
903 if (info->num_frames >= 1)
904 info->cur_frame = frame/*(frame+1)%info->num_frames*/;
905 return 0;
906 }
907
908 int vixPlaybackSetEq(const vidix_video_eq_t *eq_parm) {
909 double angle;
910 int16_t chrom_cos, chrom_sin;
911 if (eq_parm->cap & VEQ_CAP_BRIGHTNESS)
912 eq.vals.brightness = eq_parm->brightness;
913 if (eq_parm->cap & VEQ_CAP_CONTRAST)
914 eq.vals.contrast = eq_parm->contrast;
915 if (eq_parm->cap & VEQ_CAP_SATURATION)
916 eq.vals.saturation = eq_parm->saturation;
917 if (eq_parm->cap & VEQ_CAP_HUE)
918 eq.vals.hue = eq_parm->hue;
919 eq.lum = (((eq.vals.brightness * 512 + 500) / 1000) << 16) |
920 ((((eq.vals.contrast + 1000) * 8191 + 1000) / 2000) & 0xffff);
921 angle = (double)eq.vals.hue / 1000.0 * 3.1415927;
922 chrom_cos = ((eq.vals.saturation + 1000) * 8191 * cos(angle) + 1000) / 2000;
923 chrom_sin = ((eq.vals.saturation + 1000) * 8191 * sin(angle) + 1000) / 2000;
924 eq.chrom = chrom_sin << 16 | chrom_cos;
925 eq.red_off = 0x69 - eq.vals.brightness * 62 / 1000;
926 eq.green_off = 0x3e + eq.vals.brightness * 62 / 1000;
927 eq.blue_off = 0x89 - eq.vals.brightness * 62 / 1000;
928 return 0;
929 }
930
931 int vixPlaybackGetEq(vidix_video_eq_t *eq_parm) {
932 memcpy(eq_parm, &eq.vals, sizeof(vidix_video_eq_t));
933 return 0;
934 }
935