Mercurial > mplayer.hg

comparison vidix/radeon_vid.c @ 22850:9a1e26fef45b

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Move driver files directly into the vidix directory.
author diego
date Sun, 01 Apr 2007 00:02:43 +0000
parents
children 77def5093daf
comparison
equal deleted inserted replaced
22849:bddb09395c3e 22850:9a1e26fef45b
1 /*
2 radeon_vid - VIDIX based video driver for Radeon and Rage128 chips
3 Copyrights 2002 Nick Kurshev. This file is based on sources from
4 GATOS (gatos.sf.net) and X11 (www.xfree86.org)
5 Licence: GPL
6
7 31.12.2002 added support for fglrx drivers by Marcel Naziri (zwobbl@zwobbl.de)
8 6.04.2004 fixes to allow compiling vidix without X11 (broken in original patch)
9 PPC support by Alex Beregszaszi
10 */
11
12 #include <errno.h>
13 #include <stdio.h>
14 #include <stdlib.h>
15 #include <string.h>
16 #include <math.h>
17 #include <inttypes.h>
18
19 #include "../config.h"
20 #include "../libavutil/common.h"
21 #include "../mpbswap.h"
22 #include "../libdha/pci_ids.h"
23 #include "../libdha/pci_names.h"
24 #include "vidix.h"
25 #include "fourcc.h"
26 #include "../libdha/libdha.h"
27 #include "radeon.h"
28
29 #ifdef HAVE_X11
30 #include <X11/Xlib.h>
31 #endif
32
33 #ifdef RAGE128
34 #define RADEON_MSG "[rage128]"
35 #define X_ADJUST 0
36 #else
37 #define RADEON_MSG "[radeon]"
38 #define X_ADJUST (is_shift_required ? 8 : 0)
39 #ifndef RADEON
40 #define RADEON
41 #endif
42 #endif
43
44 static int __verbose = 0;
45 #ifdef RADEON
46 static int is_shift_required = 0;
47 #endif
48
49 typedef struct bes_registers_s
50 {
51 /* base address of yuv framebuffer */
52 uint32_t yuv_base;
53 uint32_t fourcc;
54 uint32_t dest_bpp;
55 /* YUV BES registers */
56 uint32_t reg_load_cntl;
57 uint32_t h_inc;
58 uint32_t step_by;
59 uint32_t y_x_start;
60 uint32_t y_x_end;
61 uint32_t v_inc;
62 uint32_t p1_blank_lines_at_top;
63 uint32_t p23_blank_lines_at_top;
64 uint32_t vid_buf_pitch0_value;
65 uint32_t vid_buf_pitch1_value;
66 uint32_t p1_x_start_end;
67 uint32_t p2_x_start_end;
68 uint32_t p3_x_start_end;
69 uint32_t base_addr;
70 uint32_t vid_buf_base_adrs_y[VID_PLAY_MAXFRAMES];
71 uint32_t vid_buf_base_adrs_u[VID_PLAY_MAXFRAMES];
72 uint32_t vid_buf_base_adrs_v[VID_PLAY_MAXFRAMES];
73 uint32_t vid_nbufs;
74
75 uint32_t p1_v_accum_init;
76 uint32_t p1_h_accum_init;
77 uint32_t p23_v_accum_init;
78 uint32_t p23_h_accum_init;
79 uint32_t scale_cntl;
80 uint32_t exclusive_horz;
81 uint32_t auto_flip_cntl;
82 uint32_t filter_cntl;
83 uint32_t key_cntl;
84 uint32_t test;
85 /* Configurable stuff */
86 int double_buff;
87
88 int brightness;
89 int saturation;
90
91 int ckey_on;
92 uint32_t graphics_key_clr;
93 uint32_t graphics_key_msk;
94 uint32_t ckey_cntl;
95
96 int deinterlace_on;
97 uint32_t deinterlace_pattern;
98
99 } bes_registers_t;
100
101 typedef struct video_registers_s
102 {
103 const char * sname;
104 uint32_t name;
105 uint32_t value;
106 }video_registers_t;
107
108 static bes_registers_t besr;
109 #ifndef RAGE128
110 static int RadeonFamily=100;
111 #endif
112 #define DECLARE_VREG(name) { #name, name, 0 }
113 static video_registers_t vregs[] =
114 {
115 DECLARE_VREG(VIDEOMUX_CNTL),
116 DECLARE_VREG(VIPPAD_MASK),
117 DECLARE_VREG(VIPPAD1_A),
118 DECLARE_VREG(VIPPAD1_EN),
119 DECLARE_VREG(VIPPAD1_Y),
120 DECLARE_VREG(OV0_Y_X_START),
121 DECLARE_VREG(OV0_Y_X_END),
122 DECLARE_VREG(OV0_PIPELINE_CNTL),
123 DECLARE_VREG(OV0_EXCLUSIVE_HORZ),
124 DECLARE_VREG(OV0_EXCLUSIVE_VERT),
125 DECLARE_VREG(OV0_REG_LOAD_CNTL),
126 DECLARE_VREG(OV0_SCALE_CNTL),
127 DECLARE_VREG(OV0_V_INC),
128 DECLARE_VREG(OV0_P1_V_ACCUM_INIT),
129 DECLARE_VREG(OV0_P23_V_ACCUM_INIT),
130 DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP),
131 DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP),
132 #ifdef RADEON
133 DECLARE_VREG(OV0_BASE_ADDR),
134 #endif
135 DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS),
136 DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS),
137 DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS),
138 DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS),
139 DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS),
140 DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS),
141 DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE),
142 DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE),
143 DECLARE_VREG(OV0_AUTO_FLIP_CNTL),
144 DECLARE_VREG(OV0_DEINTERLACE_PATTERN),
145 DECLARE_VREG(OV0_SUBMIT_HISTORY),
146 DECLARE_VREG(OV0_H_INC),
147 DECLARE_VREG(OV0_STEP_BY),
148 DECLARE_VREG(OV0_P1_H_ACCUM_INIT),
149 DECLARE_VREG(OV0_P23_H_ACCUM_INIT),
150 DECLARE_VREG(OV0_P1_X_START_END),
151 DECLARE_VREG(OV0_P2_X_START_END),
152 DECLARE_VREG(OV0_P3_X_START_END),
153 DECLARE_VREG(OV0_FILTER_CNTL),
154 DECLARE_VREG(OV0_FOUR_TAP_COEF_0),
155 DECLARE_VREG(OV0_FOUR_TAP_COEF_1),
156 DECLARE_VREG(OV0_FOUR_TAP_COEF_2),
157 DECLARE_VREG(OV0_FOUR_TAP_COEF_3),
158 DECLARE_VREG(OV0_FOUR_TAP_COEF_4),
159 DECLARE_VREG(OV0_FLAG_CNTL),
160 #ifdef RAGE128
161 DECLARE_VREG(OV0_COLOUR_CNTL),
162 #else
163 DECLARE_VREG(OV0_SLICE_CNTL),
164 #endif
165 DECLARE_VREG(OV0_VID_KEY_CLR),
166 DECLARE_VREG(OV0_VID_KEY_MSK),
167 DECLARE_VREG(OV0_GRAPHICS_KEY_CLR),
168 DECLARE_VREG(OV0_GRAPHICS_KEY_MSK),
169 DECLARE_VREG(OV0_KEY_CNTL),
170 DECLARE_VREG(OV0_TEST),
171 DECLARE_VREG(OV0_LIN_TRANS_A),
172 DECLARE_VREG(OV0_LIN_TRANS_B),
173 DECLARE_VREG(OV0_LIN_TRANS_C),
174 DECLARE_VREG(OV0_LIN_TRANS_D),
175 DECLARE_VREG(OV0_LIN_TRANS_E),
176 DECLARE_VREG(OV0_LIN_TRANS_F),
177 DECLARE_VREG(OV0_GAMMA_0_F),
178 DECLARE_VREG(OV0_GAMMA_10_1F),
179 DECLARE_VREG(OV0_GAMMA_20_3F),
180 DECLARE_VREG(OV0_GAMMA_40_7F),
181 DECLARE_VREG(OV0_GAMMA_380_3BF),
182 DECLARE_VREG(OV0_GAMMA_3C0_3FF),
183 DECLARE_VREG(SUBPIC_CNTL),
184 DECLARE_VREG(SUBPIC_DEFCOLCON),
185 DECLARE_VREG(SUBPIC_Y_X_START),
186 DECLARE_VREG(SUBPIC_Y_X_END),
187 DECLARE_VREG(SUBPIC_V_INC),
188 DECLARE_VREG(SUBPIC_H_INC),
189 DECLARE_VREG(SUBPIC_BUF0_OFFSET),
190 DECLARE_VREG(SUBPIC_BUF1_OFFSET),
191 DECLARE_VREG(SUBPIC_LC0_OFFSET),
192 DECLARE_VREG(SUBPIC_LC1_OFFSET),
193 DECLARE_VREG(SUBPIC_PITCH),
194 DECLARE_VREG(SUBPIC_BTN_HLI_COLCON),
195 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START),
196 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END),
197 DECLARE_VREG(SUBPIC_PALETTE_INDEX),
198 DECLARE_VREG(SUBPIC_PALETTE_DATA),
199 DECLARE_VREG(SUBPIC_H_ACCUM_INIT),
200 DECLARE_VREG(SUBPIC_V_ACCUM_INIT),
201 DECLARE_VREG(IDCT_RUNS),
202 DECLARE_VREG(IDCT_LEVELS),
203 DECLARE_VREG(IDCT_AUTH_CONTROL),
204 DECLARE_VREG(IDCT_AUTH),
205 DECLARE_VREG(IDCT_CONTROL),
206 DECLARE_VREG(CONFIG_CNTL)
207 };
208
209 #ifdef HAVE_X11
210 static uint32_t firegl_shift = 0;
211 #endif
212 static void * radeon_mmio_base = 0;
213 static void * radeon_mem_base = 0;
214 static int32_t radeon_overlay_off = 0;
215 static uint32_t radeon_ram_size = 0;
216 /* Restore on exit */
217 static uint32_t SAVED_OV0_GRAPHICS_KEY_CLR = 0;
218 static uint32_t SAVED_OV0_GRAPHICS_KEY_MSK = 0;
219 static uint32_t SAVED_OV0_VID_KEY_CLR = 0;
220 static uint32_t SAVED_OV0_VID_KEY_MSK = 0;
221 static uint32_t SAVED_OV0_KEY_CNTL = 0;
222 #ifdef WORDS_BIGENDIAN
223 static uint32_t SAVED_CONFIG_CNTL = 0;
224 #if defined(RAGE128)
225 #define APER_0_BIG_ENDIAN_16BPP_SWAP (1<<0)
226 #define APER_0_BIG_ENDIAN_32BPP_SWAP (2<<0)
227 #else
228 #define RADEON_SURFACE_CNTL 0x0b00
229 #define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)
230 #define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)
231 #endif
232 #endif
233
234 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ))))
235 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL
236
237 #define INREG8(addr) GETREG(uint8_t,(uint8_t*)(radeon_mmio_base),addr)
238 #define OUTREG8(addr,val) SETREG(uint8_t,(uint8_t*)(radeon_mmio_base),addr,val)
239
240 static inline uint32_t INREG (uint32_t addr) {
241 uint32_t tmp = GETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr);
242 return le2me_32(tmp);
243 }
244 //#define OUTREG(addr,val) SETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr,val)
245 #define OUTREG(addr,val) SETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr,le2me_32(val))
246 #define OUTREGP(addr,val,mask) \
247 do { \
248 unsigned int _tmp = INREG(addr); \
249 _tmp &= (mask); \
250 _tmp |= (val); \
251 OUTREG(addr, _tmp); \
252 } while (0)
253
254 static __inline__ uint32_t INPLL(uint32_t addr)
255 {
256 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f);
257 return (INREG(CLOCK_CNTL_DATA));
258 }
259
260 #define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \
261 OUTREG(CLOCK_CNTL_DATA, val)
262 #define OUTPLLP(addr,val,mask) \
263 do { \
264 unsigned int _tmp = INPLL(addr); \
265 _tmp &= (mask); \
266 _tmp |= (val); \
267 OUTPLL(addr, _tmp); \
268 } while (0)
269
270 static uint32_t radeon_vid_get_dbpp( void )
271 {
272 uint32_t dbpp,retval;
273 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF;
274 switch(dbpp)
275 {
276 case DST_8BPP: retval = 8; break;
277 case DST_15BPP: retval = 15; break;
278 case DST_16BPP: retval = 16; break;
279 case DST_24BPP: retval = 24; break;
280 default: retval=32; break;
281 }
282 return retval;
283 }
284
285 static int radeon_is_dbl_scan( void )
286 {
287 return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN;
288 }
289
290 static int radeon_is_interlace( void )
291 {
292 return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN;
293 }
294
295 static uint32_t radeon_get_xres( void )
296 {
297 /* FIXME: currently we extract that from CRTC!!!*/
298 uint32_t xres,h_total;
299 h_total = INREG(CRTC_H_TOTAL_DISP);
300 xres = (h_total >> 16) & 0xffff;
301 return (xres + 1)*8;
302 }
303
304 static uint32_t radeon_get_yres( void )
305 {
306 /* FIXME: currently we extract that from CRTC!!!*/
307 uint32_t yres,v_total;
308 v_total = INREG(CRTC_V_TOTAL_DISP);
309 yres = (v_total >> 16) & 0xffff;
310 return yres + 1;
311 }
312
313 /* get flat panel x resolution*/
314 static uint32_t radeon_get_fp_xres( void ){
315 uint32_t xres=(INREG(FP_HORZ_STRETCH)&0x00fff000)>>16;
316 xres=(xres+1)*8;
317 return xres;
318 }
319
320 /* get flat panel y resolution*/
321 static uint32_t radeon_get_fp_yres( void ){
322 uint32_t yres=(INREG(FP_VERT_STRETCH)&0x00fff000)>>12;
323 return yres+1;
324 }
325
326 static void radeon_wait_vsync(void)
327 {
328 int i;
329
330 OUTREG(GEN_INT_STATUS, VSYNC_INT_AK);
331 for (i = 0; i < 2000000; i++)
332 {
333 if (INREG(GEN_INT_STATUS) & VSYNC_INT) break;
334 }
335 }
336
337 #ifdef RAGE128
338 static void _radeon_engine_idle(void);
339 static void _radeon_fifo_wait(unsigned);
340 #define radeon_engine_idle() _radeon_engine_idle()
341 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries)
342 /* Flush all dirty data in the Pixel Cache to memory. */
343 static __inline__ void radeon_engine_flush ( void )
344 {
345 unsigned i;
346
347 OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL);
348 for (i = 0; i < 2000000; i++) {
349 if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break;
350 }
351 }
352
353 /* Reset graphics card to known state. */
354 static void radeon_engine_reset( void )
355 {
356 uint32_t clock_cntl_index;
357 uint32_t mclk_cntl;
358 uint32_t gen_reset_cntl;
359
360 radeon_engine_flush();
361
362 clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
363 mclk_cntl = INPLL(MCLK_CNTL);
364
365 OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP);
366
367 gen_reset_cntl = INREG(GEN_RESET_CNTL);
368
369 OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
370 INREG(GEN_RESET_CNTL);
371 OUTREG(GEN_RESET_CNTL,
372 gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI));
373 INREG(GEN_RESET_CNTL);
374
375 OUTPLL(MCLK_CNTL, mclk_cntl);
376 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
377 OUTREG(GEN_RESET_CNTL, gen_reset_cntl);
378 }
379 #else
380
381 static __inline__ void radeon_engine_flush ( void )
382 {
383 int i;
384
385 /* initiate flush */
386 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
387 ~RB2D_DC_FLUSH_ALL);
388
389 for (i=0; i < 2000000; i++) {
390 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
391 break;
392 }
393 }
394
395 static void _radeon_engine_idle(void);
396 static void _radeon_fifo_wait(unsigned);
397 #define radeon_engine_idle() _radeon_engine_idle()
398 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries)
399
400 static void radeon_engine_reset( void )
401 {
402 uint32_t clock_cntl_index, mclk_cntl, rbbm_soft_reset;
403
404 radeon_engine_flush ();
405
406 clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
407 mclk_cntl = INPLL(MCLK_CNTL);
408
409 OUTPLL(MCLK_CNTL, (mclk_cntl |
410 FORCEON_MCLKA |
411 FORCEON_MCLKB |
412 FORCEON_YCLKA |
413 FORCEON_YCLKB |
414 FORCEON_MC |
415 FORCEON_AIC));
416 rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
417
418 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
419 SOFT_RESET_CP |
420 SOFT_RESET_HI |
421 SOFT_RESET_SE |
422 SOFT_RESET_RE |
423 SOFT_RESET_PP |
424 SOFT_RESET_E2 |
425 SOFT_RESET_RB |
426 SOFT_RESET_HDP);
427 INREG(RBBM_SOFT_RESET);
428 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (uint32_t)
429 ~(SOFT_RESET_CP |
430 SOFT_RESET_HI |
431 SOFT_RESET_SE |
432 SOFT_RESET_RE |
433 SOFT_RESET_PP |
434 SOFT_RESET_E2 |
435 SOFT_RESET_RB |
436 SOFT_RESET_HDP));
437 INREG(RBBM_SOFT_RESET);
438
439 OUTPLL(MCLK_CNTL, mclk_cntl);
440 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
441 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
442
443 return;
444 }
445 #endif
446 static void radeon_engine_restore( void )
447 {
448 #ifndef RAGE128
449 int pitch64;
450 uint32_t xres,yres,bpp;
451 radeon_fifo_wait(1);
452 xres = radeon_get_xres();
453 yres = radeon_get_yres();
454 bpp = radeon_vid_get_dbpp();
455 /* turn of all automatic flushing - we'll do it all */
456 OUTREG(RB2D_DSTCACHE_MODE, 0);
457
458 pitch64 = ((xres * (bpp / 8) + 0x3f)) >> 6;
459
460 radeon_fifo_wait(1);
461 OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) |
462 (pitch64 << 22));
463
464 radeon_fifo_wait(1);
465 #if defined(WORDS_BIGENDIAN)
466 #ifdef RADEON
467 OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
468 #endif
469 #else
470 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
471 #endif
472
473 radeon_fifo_wait(1);
474 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX
475 | DEFAULT_SC_BOTTOM_MAX));
476 radeon_fifo_wait(1);
477 OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL)
478 | GMC_BRUSH_SOLID_COLOR
479 | GMC_SRC_DATATYPE_COLOR));
480
481 radeon_fifo_wait(7);
482 OUTREG(DST_LINE_START, 0);
483 OUTREG(DST_LINE_END, 0);
484 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
485 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
486 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
487 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
488 OUTREG(DP_WRITE_MASK, 0xffffffff);
489
490 radeon_engine_idle();
491 #endif
492 }
493 #ifdef RAGE128
494 static void _radeon_fifo_wait (unsigned entries)
495 {
496 unsigned i;
497
498 for(;;)
499 {
500 for (i=0; i<2000000; i++)
501 if ((INREG(GUI_STAT) & GUI_FIFOCNT_MASK) >= entries)
502 return;
503 radeon_engine_reset();
504 radeon_engine_restore();
505 }
506 }
507
508 static void _radeon_engine_idle ( void )
509 {
510 unsigned i;
511
512 /* ensure FIFO is empty before waiting for idle */
513 radeon_fifo_wait (64);
514 for(;;)
515 {
516 for (i=0; i<2000000; i++) {
517 if ((INREG(GUI_STAT) & GUI_ACTIVE) == 0) {
518 radeon_engine_flush ();
519 return;
520 }
521 }
522 radeon_engine_reset();
523 radeon_engine_restore();
524 }
525 }
526 #else
527 static void _radeon_fifo_wait (unsigned entries)
528 {
529 unsigned i;
530
531 for(;;)
532 {
533 for (i=0; i<2000000; i++)
534 if ((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries)
535 return;
536 radeon_engine_reset();
537 radeon_engine_restore();
538 }
539 }
540 static void _radeon_engine_idle ( void )
541 {
542 int i;
543
544 /* ensure FIFO is empty before waiting for idle */
545 radeon_fifo_wait (64);
546 for(;;)
547 {
548 for (i=0; i<2000000; i++) {
549 if (((INREG(RBBM_STATUS) & RBBM_ACTIVE)) == 0) {
550 radeon_engine_flush ();
551 return;
552 }
553 }
554 radeon_engine_reset();
555 radeon_engine_restore();
556 }
557 }
558 #endif
559
560 #ifndef RAGE128
561 /* Reference color space transform data */
562 typedef struct tagREF_TRANSFORM
563 {
564 float RefLuma;
565 float RefRCb;
566 float RefRCr;
567 float RefGCb;
568 float RefGCr;
569 float RefBCb;
570 float RefBCr;
571 } REF_TRANSFORM;
572
573 /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */
574 REF_TRANSFORM trans[2] =
575 {
576 {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */
577 {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */
578 };
579 /****************************************************************************
580 * SetTransform *
581 * Function: Calculates and sets color space transform from supplied *
582 * reference transform, gamma, brightness, contrast, hue and *
583 * saturation. *
584 * Inputs: bright - brightness *
585 * cont - contrast *
586 * sat - saturation *
587 * hue - hue *
588 * red_intensity - intense of red component *
589 * green_intensity - intense of green component *
590 * blue_intensity - intense of blue component *
591 * ref - index to the table of refernce transforms *
592 * Outputs: NONE *
593 ****************************************************************************/
594
595 static void radeon_set_transform(float bright, float cont, float sat,
596 float hue, float red_intensity,
597 float green_intensity,float blue_intensity,
598 unsigned ref)
599 {
600 float OvHueSin, OvHueCos;
601 float CAdjLuma, CAdjOff;
602 float RedAdj,GreenAdj,BlueAdj;
603 float CAdjRCb, CAdjRCr;
604 float CAdjGCb, CAdjGCr;
605 float CAdjBCb, CAdjBCr;
606 float OvLuma, OvROff, OvGOff, OvBOff;
607 float OvRCb, OvRCr;
608 float OvGCb, OvGCr;
609 float OvBCb, OvBCr;
610 float Loff = 64.0;
611 float Coff = 512.0f;
612
613 uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff;
614 uint32_t dwOvRCb, dwOvRCr;
615 uint32_t dwOvGCb, dwOvGCr;
616 uint32_t dwOvBCb, dwOvBCr;
617
618 if (ref >= 2) return;
619
620 OvHueSin = sin((double)hue);
621 OvHueCos = cos((double)hue);
622
623 CAdjLuma = cont * trans[ref].RefLuma;
624 CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0;
625 RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0;
626 GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0;
627 BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0;
628
629 CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr;
630 CAdjRCr = sat * OvHueCos * trans[ref].RefRCr;
631 CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr);
632 CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr);
633 CAdjBCb = sat * OvHueCos * trans[ref].RefBCb;
634 CAdjBCr = sat * OvHueSin * trans[ref].RefBCb;
635
636 #if 0 /* default constants */
637 CAdjLuma = 1.16455078125;
638
639 CAdjRCb = 0.0;
640 CAdjRCr = 1.59619140625;
641 CAdjGCb = -0.39111328125;
642 CAdjGCr = -0.8125;
643 CAdjBCb = 2.01708984375;
644 CAdjBCr = 0;
645 #endif
646 OvLuma = CAdjLuma;
647 OvRCb = CAdjRCb;
648 OvRCr = CAdjRCr;
649 OvGCb = CAdjGCb;
650 OvGCr = CAdjGCr;
651 OvBCb = CAdjBCb;
652 OvBCr = CAdjBCr;
653 OvROff = RedAdj + CAdjOff -
654 OvLuma * Loff - (OvRCb + OvRCr) * Coff;
655 OvGOff = GreenAdj + CAdjOff -
656 OvLuma * Loff - (OvGCb + OvGCr) * Coff;
657 OvBOff = BlueAdj + CAdjOff -
658 OvLuma * Loff - (OvBCb + OvBCr) * Coff;
659 #if 0 /* default constants */
660 OvROff = -888.5;
661 OvGOff = 545;
662 OvBOff = -1104;
663 #endif
664
665 dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff;
666 dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff;
667 dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff;
668 /* Whatever docs say about R200 having 3.8 format instead of 3.11
669 as in Radeon is a lie */
670 #if 0
671 if(RadeonFamily == 100)
672 {
673 #endif
674 dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17;
675 dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1;
676 dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17;
677 dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1;
678 dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17;
679 dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1;
680 dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17;
681 #if 0
682 }
683 else
684 {
685 dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20;
686 dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4;
687 dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20;
688 dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4;
689 dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20;
690 dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4;
691 dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20;
692 }
693 #endif
694 OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma);
695 OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr);
696 OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma);
697 OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr);
698 OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma);
699 OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr);
700 }
701
702 /* Gamma curve definition */
703 typedef struct
704 {
705 unsigned int gammaReg;
706 unsigned int gammaSlope;
707 unsigned int gammaOffset;
708 }GAMMA_SETTINGS;
709
710 /* Recommended gamma curve parameters */
711 GAMMA_SETTINGS r200_def_gamma[18] =
712 {
713 {OV0_GAMMA_0_F, 0x100, 0x0000},
714 {OV0_GAMMA_10_1F, 0x100, 0x0020},
715 {OV0_GAMMA_20_3F, 0x100, 0x0040},
716 {OV0_GAMMA_40_7F, 0x100, 0x0080},
717 {OV0_GAMMA_80_BF, 0x100, 0x0100},
718 {OV0_GAMMA_C0_FF, 0x100, 0x0100},
719 {OV0_GAMMA_100_13F, 0x100, 0x0200},
720 {OV0_GAMMA_140_17F, 0x100, 0x0200},
721 {OV0_GAMMA_180_1BF, 0x100, 0x0300},
722 {OV0_GAMMA_1C0_1FF, 0x100, 0x0300},
723 {OV0_GAMMA_200_23F, 0x100, 0x0400},
724 {OV0_GAMMA_240_27F, 0x100, 0x0400},
725 {OV0_GAMMA_280_2BF, 0x100, 0x0500},
726 {OV0_GAMMA_2C0_2FF, 0x100, 0x0500},
727 {OV0_GAMMA_300_33F, 0x100, 0x0600},
728 {OV0_GAMMA_340_37F, 0x100, 0x0600},
729 {OV0_GAMMA_380_3BF, 0x100, 0x0700},
730 {OV0_GAMMA_3C0_3FF, 0x100, 0x0700}
731 };
732
733 GAMMA_SETTINGS r100_def_gamma[6] =
734 {
735 {OV0_GAMMA_0_F, 0x100, 0x0000},
736 {OV0_GAMMA_10_1F, 0x100, 0x0020},
737 {OV0_GAMMA_20_3F, 0x100, 0x0040},
738 {OV0_GAMMA_40_7F, 0x100, 0x0080},
739 {OV0_GAMMA_380_3BF, 0x100, 0x0100},
740 {OV0_GAMMA_3C0_3FF, 0x100, 0x0100}
741 };
742
743 static void make_default_gamma_correction( void )
744 {
745 size_t i;
746 if(RadeonFamily == 100) {
747 OUTREG(OV0_LIN_TRANS_A, 0x12A00000);
748 OUTREG(OV0_LIN_TRANS_B, 0x199018FE);
749 OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0);
750 OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B);
751 OUTREG(OV0_LIN_TRANS_E, 0x12A02050);
752 OUTREG(OV0_LIN_TRANS_F, 0x0000174E);
753 for(i=0; i<6; i++){
754 OUTREG(r100_def_gamma[i].gammaReg,
755 (r100_def_gamma[i].gammaSlope<<16) |
756 r100_def_gamma[i].gammaOffset);
757 }
758 }
759 else{
760 OUTREG(OV0_LIN_TRANS_A, 0x12a00000);
761 OUTREG(OV0_LIN_TRANS_B, 0x1990190e);
762 OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0);
763 OUTREG(OV0_LIN_TRANS_D, 0xf3000442);
764 OUTREG(OV0_LIN_TRANS_E, 0x12a02040);
765 OUTREG(OV0_LIN_TRANS_F, 0x175f);
766
767 /* Default Gamma,
768 Of 18 segments for gamma cure, all segments in R200 are programmable,
769 while only lower 4 and upper 2 segments are programmable in Radeon*/
770 for(i=0; i<18; i++){
771 OUTREG(r200_def_gamma[i].gammaReg,
772 (r200_def_gamma[i].gammaSlope<<16) |
773 r200_def_gamma[i].gammaOffset);
774 }
775 }
776 }
777 #endif
778
779 static void radeon_vid_make_default(void)
780 {
781 #ifdef RAGE128
782 OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brightness and saturation for Rage128 */
783 #else
784 make_default_gamma_correction();
785 #endif
786 besr.deinterlace_pattern = 0x900AAAAA;
787 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern);
788 besr.deinterlace_on=1;
789 besr.double_buff=1;
790 besr.ckey_on=0;
791 besr.graphics_key_msk=0;
792 besr.graphics_key_clr=0;
793 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND;
794 }
795
796
797 unsigned vixGetVersion( void ) { return VIDIX_VERSION; }
798
799 static unsigned short ati_card_ids[] =
800 {
801 #ifdef RAGE128
802 /*
803 This driver should be compatible with Rage128 (pro) chips.
804 (include adaptive deinterlacing!!!).
805 Moreover: the same logic can be used with Mach64 chips.
806 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility).
807 but they are incompatible by i/o ports. So if enthusiasts will want
808 then they can redefine OUTREG and INREG macros and redefine OV0_*
809 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY
810 fourccs (422 and 420 formats only).
811 */
812 /* Rage128 Pro GL */
813 DEVICE_ATI_RAGE_128_PA_PRO,
814 DEVICE_ATI_RAGE_128_PB_PRO,
815 DEVICE_ATI_RAGE_128_PC_PRO,
816 DEVICE_ATI_RAGE_128_PD_PRO,
817 DEVICE_ATI_RAGE_128_PE_PRO,
818 DEVICE_ATI_RAGE_128_PF_PRO,
819 /* Rage128 Pro VR */
820 DEVICE_ATI_RAGE_128_PG_PRO,
821 DEVICE_ATI_RAGE_128_PH_PRO,
822 DEVICE_ATI_RAGE_128_PI_PRO,
823 DEVICE_ATI_RAGE_128_PJ_PRO,
824 DEVICE_ATI_RAGE_128_PK_PRO,
825 DEVICE_ATI_RAGE_128_PL_PRO,
826 DEVICE_ATI_RAGE_128_PM_PRO,
827 DEVICE_ATI_RAGE_128_PN_PRO,
828 DEVICE_ATI_RAGE_128_PO_PRO,
829 DEVICE_ATI_RAGE_128_PP_PRO,
830 DEVICE_ATI_RAGE_128_PQ_PRO,
831 DEVICE_ATI_RAGE_128_PR_PRO,
832 DEVICE_ATI_RAGE_128_PS_PRO,
833 DEVICE_ATI_RAGE_128_PT_PRO,
834 DEVICE_ATI_RAGE_128_PU_PRO,
835 DEVICE_ATI_RAGE_128_PV_PRO,
836 DEVICE_ATI_RAGE_128_PW_PRO,
837 DEVICE_ATI_RAGE_128_PX_PRO,
838 /* Rage128 GL */
839 DEVICE_ATI_RAGE_128_RE_SG,
840 DEVICE_ATI_RAGE_128_RF_SG,
841 DEVICE_ATI_RAGE_128_RG,
842 DEVICE_ATI_RAGE_128_RK_VR,
843 DEVICE_ATI_RAGE_128_RL_VR,
844 DEVICE_ATI_RAGE_128_SE_4X,
845 DEVICE_ATI_RAGE_128_SF_4X,
846 DEVICE_ATI_RAGE_128_SG_4X,
847 DEVICE_ATI_RAGE_128_SH,
848 DEVICE_ATI_RAGE_128_SK_4X,
849 DEVICE_ATI_RAGE_128_SL_4X,
850 DEVICE_ATI_RAGE_128_SM_4X,
851 DEVICE_ATI_RAGE_128_4X,
852 DEVICE_ATI_RAGE_128_PRO,
853 DEVICE_ATI_RAGE_128_PRO2,
854 DEVICE_ATI_RAGE_128_PRO3,
855 /* these seem to be based on rage 128 instead of mach64 */
856 DEVICE_ATI_RAGE_MOBILITY_M3,
857 DEVICE_ATI_RAGE_MOBILITY_M32
858 #else
859 /* Radeons (indeed: Rage 256 Pro ;) */
860 DEVICE_ATI_RADEON_R100_QD,
861 DEVICE_ATI_RADEON_R100_QE,
862 DEVICE_ATI_RADEON_R100_QF,
863 DEVICE_ATI_RADEON_R100_QG,
864 DEVICE_ATI_RADEON_VE_QY,
865 DEVICE_ATI_RADEON_VE_QZ,
866 DEVICE_ATI_RADEON_MOBILITY_M7,
867 DEVICE_ATI_RADEON_MOBILITY_M72,
868 DEVICE_ATI_RADEON_MOBILITY_M6,
869 DEVICE_ATI_RADEON_MOBILITY_M62,
870 DEVICE_ATI_RADEON_MOBILITY_U1,
871 DEVICE_ATI_RADEON_R200_BB,
872 DEVICE_ATI_RADEON_R200_QH,
873 DEVICE_ATI_RADEON_R200_QI,
874 DEVICE_ATI_RADEON_R200_QJ,
875 DEVICE_ATI_RADEON_R200_QK,
876 DEVICE_ATI_RADEON_R200_QL,
877 DEVICE_ATI_RADEON_R200_QM,
878 DEVICE_ATI_RADEON_R200_QH2,
879 DEVICE_ATI_RADEON_R200_QI2,
880 DEVICE_ATI_RADEON_R200_QJ2,
881 DEVICE_ATI_RADEON_R200_QK2,
882 DEVICE_ATI_RADEON_RV200_QW,
883 DEVICE_ATI_RADEON_RV200_QX,
884 DEVICE_ATI_RADEON_R250_ID,
885 DEVICE_ATI_RADEON_R250_IE,
886 DEVICE_ATI_RADEON_R250_IF,
887 DEVICE_ATI_RADEON_R250_IG,
888 DEVICE_ATI_RADEON_R250_LD,
889 DEVICE_ATI_RADEON_R250_LE,
890 DEVICE_ATI_RADEON_R250_LF,
891 DEVICE_ATI_RADEON_R250_LG,
892 DEVICE_ATI_RV370_5B60_RADEON,
893 DEVICE_ATI_RV250_5C61_RADEON,
894 DEVICE_ATI_RV250_5C63_RADEON,
895 DEVICE_ATI_RV280_RADEON_9200,
896 DEVICE_ATI_RV280_RADEON_92002,
897 DEVICE_ATI_RV280_RADEON_92003,
898 DEVICE_ATI_RV280_RADEON_92004,
899 DEVICE_ATI_RV280_RADEON_92005,
900 DEVICE_ATI_RV280_RADEON_92006,
901 DEVICE_ATI_RADEON_R300_ND,
902 DEVICE_ATI_RADEON_R300_NE,
903 DEVICE_ATI_RADEON_R300_NF,
904 DEVICE_ATI_RADEON_R300_NG,
905 DEVICE_ATI_RADEON_R300_AE,
906 DEVICE_ATI_RADEON_R300_AF,
907 DEVICE_ATI_RADEON_RV350_AP,
908 DEVICE_ATI_RADEON_RV350_AQ,
909 DEVICE_ATI_RADEON_RV350_AR,
910 DEVICE_ATI_RADEON_RV350_BK,
911 DEVICE_ATI_RADEON_R350_AH,
912 DEVICE_ATI_RADEON_R350_AI,
913 DEVICE_ATI_RADEON_R350_NH,
914 DEVICE_ATI_RADEON_R360_NJ,
915 DEVICE_ATI_RV350_MOBILITY_RADEON,
916 DEVICE_ATI_RV350_MOBILITY_RADEON2
917 #endif
918 };
919
920 static int find_chip(unsigned chip_id)
921 {
922 unsigned i;
923 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++)
924 {
925 if(chip_id == ati_card_ids[i]) return i;
926 }
927 return -1;
928 }
929
930 static pciinfo_t pci_info;
931 static int probed=0;
932
933 vidix_capability_t def_cap =
934 {
935 #ifdef RAGE128
936 "BES driver for Rage128 cards",
937 #else
938 "BES driver for Radeon cards",
939 #endif
940 "Nick Kurshev",
941 TYPE_OUTPUT | TYPE_FX,
942 { 0, 0, 0, 0 },
943 2048,
944 2048,
945 4,
946 4,
947 -1,
948 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER,
949 VENDOR_ATI,
950 0,
951 { 0, 0, 0, 0}
952 };
953
954 #ifdef HAVE_X11
955 static void probe_fireGL_driver(void) {
956 Display *dp = XOpenDisplay ((void*)0);
957 int n = 0;
958 char **extlist;
959 if (dp==NULL) {
960 return;
961 }
962 extlist = XListExtensions (dp, &n);
963 XCloseDisplay (dp);
964 if (extlist) {
965 int i;
966 int ext_fgl = 0, ext_fglrx = 0;
967 for (i = 0; i < n; i++) {
968 if (!strcmp(extlist[i], "ATIFGLEXTENSION")) ext_fgl = 1;
969 if (!strcmp(extlist[i], "ATIFGLRXDRI")) ext_fglrx = 1;
970 }
971 if (ext_fgl) {
972 printf(RADEON_MSG" ATI FireGl driver detected");
973 firegl_shift = 0x500000;
974 if (!ext_fglrx) {
975 printf(", but DRI seems not to be activated\n");
976 printf(RADEON_MSG" Output may not work correctly, check your DRI configuration!");
977 }
978 printf("\n");
979 }
980 }
981 }
982 #endif
983
984 int vixProbe( int verbose,int force )
985 {
986 pciinfo_t lst[MAX_PCI_DEVICES];
987 unsigned i,num_pci;
988 int err;
989 __verbose = verbose;
990 err = pci_scan(lst,&num_pci);
991 if(err)
992 {
993 printf(RADEON_MSG" Error occurred during pci scan: %s\n",strerror(err));
994 return err;
995 }
996 else
997 {
998 err = ENXIO;
999 for(i=0;i<num_pci;i++)
1000 {
1001 if(lst[i].vendor == VENDOR_ATI)
1002 {
1003 int idx;
1004 const char *dname;
1005 idx = find_chip(lst[i].device);
1006 if(idx == -1 && force == PROBE_NORMAL) continue;
1007 dname = pci_device_name(VENDOR_ATI,lst[i].device);
1008 dname = dname ? dname : "Unknown chip";
1009 printf(RADEON_MSG" Found chip: %s\n",dname);
1010 #if 0
1011 if ((lst[i].command & PCI_COMMAND_IO) == 0)
1012 {
1013 printf("[radeon] Device is disabled, ignoring\n");
1014 continue;
1015 }
1016 #endif
1017 #ifndef RAGE128
1018 if(idx != -1)
1019 #ifdef HAVE_X11
1020 probe_fireGL_driver();
1021 #endif
1022 {
1023 switch(ati_card_ids[idx]) {
1024 /* Original radeon */
1025 case DEVICE_ATI_RADEON_R100_QD:
1026 case DEVICE_ATI_RADEON_R100_QE:
1027 case DEVICE_ATI_RADEON_R100_QF:
1028 case DEVICE_ATI_RADEON_R100_QG:
1029 RadeonFamily = 100;
1030 break;
1031
1032 /* Radeon VE / Radeon Mobility */
1033 case DEVICE_ATI_RADEON_VE_QY:
1034 case DEVICE_ATI_RADEON_VE_QZ:
1035 case DEVICE_ATI_RADEON_MOBILITY_M6:
1036 case DEVICE_ATI_RADEON_MOBILITY_M62:
1037 case DEVICE_ATI_RADEON_MOBILITY_U1:
1038 RadeonFamily = 120;
1039 break;
1040
1041 /* Radeon 7500 / Radeon Mobility 7500 */
1042 case DEVICE_ATI_RADEON_RV200_QW:
1043 case DEVICE_ATI_RADEON_RV200_QX:
1044 case DEVICE_ATI_RADEON_MOBILITY_M7:
1045 case DEVICE_ATI_RADEON_MOBILITY_M72:
1046 RadeonFamily = 150;
1047 break;
1048
1049 /* Radeon 8500 */
1050 case DEVICE_ATI_RADEON_R200_BB:
1051 case DEVICE_ATI_RADEON_R200_QH:
1052 case DEVICE_ATI_RADEON_R200_QI:
1053 case DEVICE_ATI_RADEON_R200_QJ:
1054 case DEVICE_ATI_RADEON_R200_QK:
1055 case DEVICE_ATI_RADEON_R200_QL:
1056 case DEVICE_ATI_RADEON_R200_QM:
1057 case DEVICE_ATI_RADEON_R200_QH2:
1058 case DEVICE_ATI_RADEON_R200_QI2:
1059 case DEVICE_ATI_RADEON_R200_QJ2:
1060 case DEVICE_ATI_RADEON_R200_QK2:
1061 RadeonFamily = 200;
1062 break;
1063
1064 /* Radeon 9000 */
1065 case DEVICE_ATI_RADEON_R250_ID:
1066 case DEVICE_ATI_RADEON_R250_IE:
1067 case DEVICE_ATI_RADEON_R250_IF:
1068 case DEVICE_ATI_RADEON_R250_IG:
1069 case DEVICE_ATI_RADEON_R250_LD:
1070 case DEVICE_ATI_RADEON_R250_LE:
1071 case DEVICE_ATI_RADEON_R250_LF:
1072 case DEVICE_ATI_RADEON_R250_LG:
1073 case DEVICE_ATI_RV250_5C61_RADEON:
1074 case DEVICE_ATI_RV250_5C63_RADEON:
1075 RadeonFamily = 250;
1076 break;
1077
1078 /* Radeon 9200 */
1079 case DEVICE_ATI_RV280_RADEON_9200:
1080 case DEVICE_ATI_RV280_RADEON_92002:
1081 case DEVICE_ATI_RV280_RADEON_92003:
1082 case DEVICE_ATI_RV280_RADEON_92004:
1083 case DEVICE_ATI_RV280_RADEON_92005:
1084 case DEVICE_ATI_RV280_RADEON_92006:
1085 RadeonFamily = 280;
1086 break;
1087
1088 /* Radeon 9700 */
1089 case DEVICE_ATI_RADEON_R300_ND:
1090 case DEVICE_ATI_RADEON_R300_NE:
1091 case DEVICE_ATI_RADEON_R300_NF:
1092 case DEVICE_ATI_RADEON_R300_NG:
1093 case DEVICE_ATI_RADEON_R300_AE:
1094 case DEVICE_ATI_RADEON_R300_AF:
1095 RadeonFamily = 300;
1096 break;
1097
1098 /* Radeon 9600/9800 */
1099 case DEVICE_ATI_RV370_5B60_RADEON:
1100 case DEVICE_ATI_RADEON_RV350_AP:
1101 case DEVICE_ATI_RADEON_RV350_AQ:
1102 case DEVICE_ATI_RADEON_RV350_AR:
1103 case DEVICE_ATI_RADEON_RV350_BK:
1104 case DEVICE_ATI_RADEON_R350_NH:
1105 case DEVICE_ATI_RADEON_R350_AH:
1106 case DEVICE_ATI_RADEON_R350_AI:
1107 case DEVICE_ATI_RADEON_R360_NJ:
1108 case DEVICE_ATI_RV350_MOBILITY_RADEON:
1109 case DEVICE_ATI_RV350_MOBILITY_RADEON2:
1110 RadeonFamily = 350;
1111 break;
1112
1113 default:
1114 break;
1115 }
1116 }
1117 #endif
1118 if(force > PROBE_NORMAL)
1119 {
1120 printf(RADEON_MSG" Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : "");
1121 if(idx == -1)
1122 #ifdef RAGE128
1123 printf(RADEON_MSG" Assuming it as Rage128\n");
1124 #else
1125 printf(RADEON_MSG" Assuming it as Radeon1\n");
1126 #endif
1127 }
1128 def_cap.device_id = lst[i].device;
1129 err = 0;
1130 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t));
1131 probed=1;
1132 break;
1133 }
1134 }
1135 }
1136 if(err && verbose) printf(RADEON_MSG" Can't find chip\n");
1137 return err;
1138 }
1139
1140 static void radeon_vid_dump_regs( void ); /* forward declaration */
1141
1142 int vixInit( void )
1143 {
1144 int err;
1145 if(!probed)
1146 {
1147 printf(RADEON_MSG" Driver was not probed but is being initializing\n");
1148 return EINTR;
1149 }
1150 if((radeon_mmio_base = map_phys_mem(pci_info.base2,0xFFFF))==(void *)-1) return ENOMEM;
1151 radeon_ram_size = INREG(CONFIG_MEMSIZE);
1152 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */
1153 radeon_ram_size &= CONFIG_MEMSIZE_MASK;
1154 #ifdef RADEON
1155 /* according to XFree86 4.2.0, some production M6's return 0 for 8MB */
1156 if (radeon_ram_size == 0 &&
1157 (def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M6 ||
1158 def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M62))
1159 {
1160 printf(RADEON_MSG" Workarounding buggy Radeon Mobility M6 (0 vs. 8MB ram)\n");
1161 radeon_ram_size = 8192*1024;
1162 }
1163 #else
1164 /* Rage Mobility (rage128) also has memsize bug */
1165 if (radeon_ram_size == 0 &&
1166 (def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M3 ||
1167 def_cap.device_id == DEVICE_ATI_RAGE_128_RL_VR ||
1168 def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M32))
1169 {
1170 printf(RADEON_MSG" Workarounding buggy Rage Mobility M3 (0 vs. 8MB ram)\n");
1171 radeon_ram_size = 8192*1024;
1172 }
1173 #endif
1174 printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000);
1175 #ifdef WIN32
1176 //mapping large areas of video ram will fail on windows
1177 if(radeon_ram_size > 16*1024*1024)radeon_ram_size=16*1024*1024;
1178 #endif
1179 if((radeon_mem_base = map_phys_mem(pci_info.base0,radeon_ram_size))==(void *)-1) return ENOMEM;
1180 memset(&besr,0,sizeof(bes_registers_t));
1181 radeon_vid_make_default();
1182 err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB);
1183 if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n");
1184
1185 radeon_fifo_wait(3);
1186 SAVED_OV0_GRAPHICS_KEY_CLR = INREG(OV0_GRAPHICS_KEY_CLR);
1187 SAVED_OV0_GRAPHICS_KEY_MSK = INREG(OV0_GRAPHICS_KEY_MSK);
1188 SAVED_OV0_VID_KEY_CLR = INREG(OV0_VID_KEY_CLR);
1189 SAVED_OV0_VID_KEY_MSK = INREG(OV0_VID_KEY_MSK);
1190 SAVED_OV0_KEY_CNTL = INREG(OV0_KEY_CNTL);
1191 printf(RADEON_MSG" Saved overlay colorkey settings\n");
1192
1193 #ifdef RADEON
1194 switch(RadeonFamily)
1195 {
1196 case 100:
1197 case 120:
1198 case 150:
1199 case 250:
1200 case 280:
1201 is_shift_required=1;
1202 break;
1203 default:
1204 break;
1205 }
1206 #endif
1207
1208 /* XXX: hack, but it works for me (tm) */
1209 #ifdef WORDS_BIGENDIAN
1210 #if defined(RAGE128)
1211 /* code from gatos */
1212 {
1213 SAVED_CONFIG_CNTL = INREG(CONFIG_CNTL);
1214 OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL &
1215 ~(APER_0_BIG_ENDIAN_16BPP_SWAP|APER_0_BIG_ENDIAN_32BPP_SWAP));
1216
1217 // printf("saved: %x, current: %x\n", SAVED_CONFIG_CNTL,
1218 // INREG(CONFIG_CNTL));
1219 }
1220 #else
1221 /*code from radeon_video.c*/
1222 {
1223 SAVED_CONFIG_CNTL = INREG(RADEON_SURFACE_CNTL);
1224 /* OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL |
1225 RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP);
1226 */
1227 OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL & ~(RADEON_NONSURF_AP0_SWP_32BPP
1228 | RADEON_NONSURF_AP0_SWP_16BPP));
1229
1230 /*
1231 OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | RADEON_NONSURF_AP0_SWP_32BPP)
1232 & ~RADEON_NONSURF_AP0_SWP_16BPP);
1233 */
1234 }
1235 #endif
1236 #endif
1237
1238 if(__verbose > 1) radeon_vid_dump_regs();
1239 return 0;
1240 }
1241
1242 void vixDestroy( void )
1243 {
1244 /* remove colorkeying */
1245 radeon_fifo_wait(3);
1246 OUTREG(OV0_GRAPHICS_KEY_CLR, SAVED_OV0_GRAPHICS_KEY_CLR);
1247 OUTREG(OV0_GRAPHICS_KEY_MSK, SAVED_OV0_GRAPHICS_KEY_MSK);
1248 OUTREG(OV0_VID_KEY_CLR, SAVED_OV0_VID_KEY_CLR);
1249 OUTREG(OV0_VID_KEY_MSK, SAVED_OV0_VID_KEY_MSK);
1250 OUTREG(OV0_KEY_CNTL, SAVED_OV0_KEY_CNTL);
1251 printf(RADEON_MSG" Restored overlay colorkey settings\n");
1252
1253 #ifdef WORDS_BIGENDIAN
1254 #if defined(RAGE128)
1255 OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL);
1256 // printf("saved: %x, restored: %x\n", SAVED_CONFIG_CNTL,
1257 // INREG(CONFIG_CNTL));
1258 #else
1259 OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL);
1260 #endif
1261 #endif
1262
1263 unmap_phys_mem(radeon_mem_base,radeon_ram_size);
1264 unmap_phys_mem(radeon_mmio_base,0xFFFF);
1265 }
1266
1267 int vixGetCapability(vidix_capability_t *to)
1268 {
1269 memcpy(to,&def_cap,sizeof(vidix_capability_t));
1270 return 0;
1271 }
1272
1273 /*
1274 Full list of fourcc which are supported by Win2K redeon driver:
1275 YUY2, UYVY, DDES, OGLT, OGL2, OGLS, OGLB, OGNT, OGNZ, OGNS,
1276 IF09, YVU9, IMC4, M2IA, IYUV, VBID, DXT1, DXT2, DXT3, DXT4, DXT5
1277 */
1278 uint32_t supported_fourcc[] =
1279 {
1280 IMGFMT_Y800, IMGFMT_Y8, IMGFMT_YVU9, IMGFMT_IF09,
1281 IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV,
1282 IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU,
1283 IMGFMT_RGB15, IMGFMT_BGR15,
1284 IMGFMT_RGB16, IMGFMT_BGR16,
1285 IMGFMT_RGB32, IMGFMT_BGR32
1286 };
1287
1288 inline static int is_supported_fourcc(uint32_t fourcc)
1289 {
1290 unsigned int i;
1291 for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++)
1292 {
1293 if(fourcc==supported_fourcc[i]) return 1;
1294 }
1295 return 0;
1296 }
1297
1298 int vixQueryFourcc(vidix_fourcc_t *to)
1299 {
1300 if(is_supported_fourcc(to->fourcc))
1301 {
1302 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP |
1303 VID_DEPTH_4BPP | VID_DEPTH_8BPP |
1304 VID_DEPTH_12BPP| VID_DEPTH_15BPP|
1305 VID_DEPTH_16BPP| VID_DEPTH_24BPP|
1306 VID_DEPTH_32BPP;
1307 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
1308 return 0;
1309 }
1310 else to->depth = to->flags = 0;
1311 return ENOSYS;
1312 }
1313
1314 static void radeon_vid_dump_regs( void )
1315 {
1316 size_t i;
1317 printf(RADEON_MSG"*** Begin of DRIVER variables dump ***\n");
1318 printf(RADEON_MSG"radeon_mmio_base=%p\n",radeon_mmio_base);
1319 printf(RADEON_MSG"radeon_mem_base=%p\n",radeon_mem_base);
1320 printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off);
1321 printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size);
1322 printf(RADEON_MSG"video mode: %ux%u@%u\n",radeon_get_xres(),radeon_get_yres(),radeon_vid_get_dbpp());
1323 printf(RADEON_MSG"flatpanel size: %ux%u\n",radeon_get_fp_xres(),radeon_get_fp_yres());
1324 printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n");
1325 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++)
1326 printf(RADEON_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name));
1327 printf(RADEON_MSG"*** End of OV0 registers dump ***\n");
1328 }
1329
1330 static void radeon_vid_stop_video( void )
1331 {
1332 radeon_engine_idle();
1333 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET);
1334 OUTREG(OV0_EXCLUSIVE_HORZ, 0);
1335 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */
1336 OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF);
1337 #ifdef RADEON
1338 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_EQ);
1339 #else
1340 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE);
1341 #endif
1342 OUTREG(OV0_TEST, 0);
1343 }
1344
1345 static void radeon_vid_display_video( void )
1346 {
1347 int bes_flags;
1348 /** workaround for Xorg-6.8 not saving the surface registers on bigendian architectures */
1349 #ifdef WORDS_BIGENDIAN
1350 #if defined(RAGE128)
1351 /* code from gatos */
1352 {
1353 SAVED_CONFIG_CNTL = INREG(CONFIG_CNTL);
1354 OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL &
1355 ~(APER_0_BIG_ENDIAN_16BPP_SWAP|APER_0_BIG_ENDIAN_32BPP_SWAP));
1356
1357 // printf("saved: %x, current: %x\n", SAVED_CONFIG_CNTL,
1358 // INREG(CONFIG_CNTL));
1359 }
1360 #else
1361 /*code from radeon_video.c*/
1362 {
1363 SAVED_CONFIG_CNTL = INREG(RADEON_SURFACE_CNTL);
1364 /* OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL |
1365 RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP);
1366 */
1367 OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL & ~(RADEON_NONSURF_AP0_SWP_32BPP
1368 | RADEON_NONSURF_AP0_SWP_16BPP));
1369
1370 /*
1371 OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | RADEON_NONSURF_AP0_SWP_32BPP)
1372 & ~RADEON_NONSURF_AP0_SWP_16BPP);
1373 */
1374 }
1375 #endif
1376 #endif
1377
1378
1379
1380 radeon_fifo_wait(2);
1381 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
1382 radeon_engine_idle();
1383 while(!(INREG(OV0_REG_LOAD_CNTL)&REG_LD_CTL_LOCK_READBACK));
1384 radeon_fifo_wait(15);
1385
1386 /* Shutdown capturing */
1387 OUTREG(FCP_CNTL, FCP_CNTL__GND);
1388 OUTREG(CAP0_TRIG_CNTL, 0);
1389
1390 OUTREG(VID_BUFFER_CONTROL, (1<<16) | 0x01);
1391 OUTREG(DISP_TEST_DEBUG_CNTL, 0);
1392
1393 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD);
1394
1395 if(besr.deinterlace_on) OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern);
1396 #ifdef RAGE128
1397 OUTREG(OV0_COLOUR_CNTL, (((besr.brightness*64)/1000) & 0x7f) |
1398 (((besr.saturation*31+31000)/2000) << 8) |
1399 (((besr.saturation*31+31000)/2000) << 16));
1400 #endif
1401 radeon_fifo_wait(2);
1402 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk);
1403 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr);
1404 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl);
1405
1406 OUTREG(OV0_H_INC, besr.h_inc);
1407 OUTREG(OV0_STEP_BY, besr.step_by);
1408 OUTREG(OV0_Y_X_START, besr.y_x_start);
1409 OUTREG(OV0_Y_X_END, besr.y_x_end);
1410 OUTREG(OV0_V_INC, besr.v_inc);
1411 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top);
1412 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top);
1413 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value);
1414 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value);
1415 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end);
1416 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end);
1417 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end);
1418 #ifdef RADEON
1419 OUTREG(OV0_BASE_ADDR, besr.base_addr);
1420 #endif
1421 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf_base_adrs_y[0]);
1422 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf_base_adrs_v[0]);
1423 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf_base_adrs_u[0]);
1424 radeon_fifo_wait(9);
1425 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf_base_adrs_y[0]);
1426 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf_base_adrs_v[0]);
1427 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf_base_adrs_u[0]);
1428 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init);
1429 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init);
1430 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init);
1431 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init);
1432
1433 #ifdef RADEON
1434 bes_flags = SCALER_ENABLE |
1435 SCALER_SMART_SWITCH;
1436 // SCALER_HORZ_PICK_NEAREST |
1437 // SCALER_VERT_PICK_NEAREST |
1438 #endif
1439 bes_flags = SCALER_ENABLE |
1440 SCALER_SMART_SWITCH |
1441 SCALER_Y2R_TEMP |
1442 SCALER_PIX_EXPAND;
1443 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER;
1444 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT;
1445 #ifdef RAGE128
1446 bes_flags |= SCALER_BURST_PER_PLANE;
1447 #endif
1448 switch(besr.fourcc)
1449 {
1450 case IMGFMT_RGB15:
1451 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break;
1452 case IMGFMT_RGB16:
1453 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break;
1454 /*
1455 case IMGFMT_RGB24:
1456 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break;
1457 */
1458 case IMGFMT_RGB32:
1459 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break;
1460 /* 4:1:0 */
1461 case IMGFMT_IF09:
1462 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break;
1463 /* 4:0:0 */
1464 case IMGFMT_Y800:
1465 case IMGFMT_Y8:
1466 /* 4:2:0 */
1467 case IMGFMT_IYUV:
1468 case IMGFMT_I420:
1469 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break;
1470 /* 4:2:2 */
1471 case IMGFMT_YVYU:
1472 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break;
1473 case IMGFMT_YUY2:
1474 default: bes_flags |= SCALER_SOURCE_VYUY422; break;
1475 }
1476 OUTREG(OV0_SCALE_CNTL, bes_flags);
1477 OUTREG(OV0_REG_LOAD_CNTL, 0);
1478 if(__verbose > 1) printf(RADEON_MSG"we wanted: scaler=%08X\n",bes_flags);
1479 if(__verbose > 1) radeon_vid_dump_regs();
1480 }
1481
1482 static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch)
1483 {
1484 unsigned pitch,spy,spv,spu;
1485 spy = spv = spu = 0;
1486 switch(spitch->y)
1487 {
1488 case 16:
1489 case 32:
1490 case 64:
1491 case 128:
1492 case 256: spy = spitch->y; break;
1493 default: break;
1494 }
1495 switch(spitch->u)
1496 {
1497 case 16:
1498 case 32:
1499 case 64:
1500 case 128:
1501 case 256: spu = spitch->u; break;
1502 default: break;
1503 }
1504 switch(spitch->v)
1505 {
1506 case 16:
1507 case 32:
1508 case 64:
1509 case 128:
1510 case 256: spv = spitch->v; break;
1511 default: break;
1512 }
1513 switch(fourcc)
1514 {
1515 /* 4:2:0 */
1516 case IMGFMT_IYUV:
1517 case IMGFMT_YV12:
1518 case IMGFMT_I420:
1519 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy;
1520 else pitch = 32;
1521 break;
1522 /* 4:1:0 */
1523 case IMGFMT_IF09:
1524 case IMGFMT_YVU9:
1525 if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy;
1526 else pitch = 64;
1527 break;
1528 default:
1529 if(spy >= 16) pitch = spy;
1530 else pitch = 16;
1531 break;
1532 }
1533 return pitch;
1534 }
1535
1536 static int radeon_vid_init_video( vidix_playback_t *config )
1537 {
1538 uint32_t i,tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top;
1539 int is_400,is_410,is_420,is_rgb32,is_rgb,best_pitch,mpitch;
1540 radeon_vid_stop_video();
1541 left = config->src.x << 16;
1542 top = config->src.y << 16;
1543 src_h = config->src.h;
1544 src_w = config->src.w;
1545 is_400 = is_410 = is_420 = is_rgb32 = is_rgb = 0;
1546 if(config->fourcc == IMGFMT_YV12 ||
1547 config->fourcc == IMGFMT_I420 ||
1548 config->fourcc == IMGFMT_IYUV) is_420 = 1;
1549 if(config->fourcc == IMGFMT_YVU9 ||
1550 config->fourcc == IMGFMT_IF09) is_410 = 1;
1551 if(config->fourcc == IMGFMT_Y800 ||
1552 config->fourcc == IMGFMT_Y8) is_400 = 1;
1553 if(config->fourcc == IMGFMT_RGB32 ||
1554 config->fourcc == IMGFMT_BGR32) is_rgb32 = 1;
1555 if(config->fourcc == IMGFMT_RGB32 ||
1556 config->fourcc == IMGFMT_BGR32 ||
1557 config->fourcc == IMGFMT_RGB24 ||
1558 config->fourcc == IMGFMT_BGR24 ||
1559 config->fourcc == IMGFMT_RGB16 ||
1560 config->fourcc == IMGFMT_BGR16 ||
1561 config->fourcc == IMGFMT_RGB15 ||
1562 config->fourcc == IMGFMT_BGR15) is_rgb = 1;
1563 best_pitch = radeon_query_pitch(config->fourcc,&config->src.pitch);
1564 mpitch = best_pitch-1;
1565 switch(config->fourcc)
1566 {
1567 /* 4:0:0 */
1568 case IMGFMT_Y800:
1569 case IMGFMT_Y8:
1570 /* 4:1:0 */
1571 case IMGFMT_YVU9:
1572 case IMGFMT_IF09:
1573 /* 4:2:0 */
1574 case IMGFMT_IYUV:
1575 case IMGFMT_YV12:
1576 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch;
1577 config->dest.pitch.y =
1578 config->dest.pitch.u =
1579 config->dest.pitch.v = best_pitch;
1580 break;
1581 /* RGB 4:4:4:4 */
1582 case IMGFMT_RGB32:
1583 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch;
1584 config->dest.pitch.y =
1585 config->dest.pitch.u =
1586 config->dest.pitch.v = best_pitch;
1587 break;
1588 /* 4:2:2 */
1589 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */
1590 pitch = ((src_w*2) + mpitch) & ~mpitch;
1591 config->dest.pitch.y =
1592 config->dest.pitch.u =
1593 config->dest.pitch.v = best_pitch;
1594 break;
1595 }
1596 dest_w = config->dest.w;
1597 dest_h = config->dest.h;
1598 if(radeon_is_dbl_scan()) dest_h *= 2;
1599 besr.dest_bpp = radeon_vid_get_dbpp();
1600 besr.fourcc = config->fourcc;
1601
1602 /* flat panel */
1603 if(INREG(FP_VERT_STRETCH)&VERT_STRETCH_ENABLE){
1604 besr.v_inc = (src_h * radeon_get_yres() / radeon_get_fp_yres() << 20) / dest_h;
1605 }
1606 else besr.v_inc = (src_h << 20) / dest_h;
1607 if(radeon_is_interlace()) besr.v_inc *= 2;
1608 h_inc = (src_w << 12) / dest_w;
1609
1610 {
1611 unsigned int ecp_div;
1612 ecp_div = (INPLL(VCLK_ECP_CNTL) >> 8) & 3;
1613 h_inc <<= ecp_div;
1614 }
1615
1616
1617 step_by = 1;
1618 while(h_inc >= (2 << 12)) {
1619 step_by++;
1620 h_inc >>= 1;
1621 }
1622
1623 /* keep everything in 16.16 */
1624 besr.base_addr = INREG(DISPLAY_BASE_ADDR);
1625 config->offsets[0] = 0;
1626 for(i=1;i<besr.vid_nbufs;i++)
1627 config->offsets[i] = config->offsets[i-1]+config->frame_size;
1628 if(is_420 || is_410 || is_400)
1629 {
1630 uint32_t d1line,d2line,d3line;
1631 d1line = top*pitch;
1632 if(is_420)
1633 {
1634 d2line = src_h*pitch+(d1line>>2);
1635 d3line = d2line+((src_h*pitch)>>2);
1636 }
1637 else
1638 if(is_410)
1639 {
1640 d2line = src_h*pitch+(d1line>>4);
1641 d3line = d2line+((src_h*pitch)>>4);
1642 }
1643 else
1644 {
1645 d2line = 0;
1646 d3line = 0;
1647 }
1648 d1line += (left >> 16) & ~15;
1649 if(is_420)
1650 {
1651 d2line += (left >> 17) & ~15;
1652 d3line += (left >> 17) & ~15;
1653 }
1654 else
1655 if(is_410)
1656 {
1657 d2line += (left >> 18) & ~15;
1658 d3line += (left >> 18) & ~15;
1659 }
1660 config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK;
1661 if(is_400)
1662 {
1663 config->offset.v = 0;
1664 config->offset.u = 0;
1665 }
1666 else
1667 {
1668 config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK;
1669 config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK;
1670 }
1671 for(i=0;i<besr.vid_nbufs;i++)
1672 {
1673 besr.vid_buf_base_adrs_y[i]=((radeon_overlay_off+config->offsets[i]+config->offset.y)&VIF_BUF0_BASE_ADRS_MASK);
1674 if(is_400)
1675 {
1676 besr.vid_buf_base_adrs_v[i]=0;
1677 besr.vid_buf_base_adrs_u[i]=0;
1678 }
1679 else
1680 {
1681 if (besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV)
1682 {
1683 besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL;
1684 besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL;
1685 }
1686 else
1687 {
1688 besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL;
1689 besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL;
1690 }
1691 }
1692 }
1693 config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off;
1694 if(is_400)
1695 {
1696 config->offset.v = 0;
1697 config->offset.u = 0;
1698 }
1699 else
1700 {
1701 config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off;
1702 config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off;
1703 }
1704 }
1705 else
1706 {
1707 config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK;
1708 for(i=0;i<besr.vid_nbufs;i++)
1709 {
1710 besr.vid_buf_base_adrs_y[i] =
1711 besr.vid_buf_base_adrs_u[i] =
1712 besr.vid_buf_base_adrs_v[i] = radeon_overlay_off + config->offsets[i] + config->offset.y;
1713 }
1714 }
1715
1716 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3);
1717 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) |
1718 ((tmp << 12) & 0xf0000000);
1719
1720 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2);
1721 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) |
1722 ((tmp << 12) & 0x70000000);
1723 tmp = (top & 0x0000ffff) + 0x00018000;
1724 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK)
1725 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1);
1726
1727 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000;
1728 besr.p23_v_accum_init = (is_420||is_410) ?
1729 ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK)
1730 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0;
1731
1732 leftUV = (left >> (is_410?18:17)) & 15;
1733 left = (left >> 16) & 15;
1734 if(is_rgb && !is_rgb32) h_inc<<=1;
1735 if(is_rgb32)
1736 besr.h_inc = (h_inc >> 1) | ((h_inc >> 1) << 16);
1737 else
1738 if(is_410)
1739 besr.h_inc = h_inc | ((h_inc >> 2) << 16);
1740 else
1741 besr.h_inc = h_inc | ((h_inc >> 1) << 16);
1742 besr.step_by = step_by | (step_by << 8);
1743 besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16);
1744 besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16);
1745 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16);
1746 if(is_420 || is_410)
1747 {
1748 src_h = (src_h + 1) >> (is_410?2:1);
1749 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16);
1750 }
1751 else besr.p23_blank_lines_at_top = 0;
1752 besr.vid_buf_pitch0_value = pitch;
1753 besr.vid_buf_pitch1_value = is_410 ? pitch>>2 : is_420 ? pitch>>1 : pitch;
1754 besr.p1_x_start_end = (src_w+left-1)|(left<<16);
1755 if (is_410||is_420) src_w>>=is_410?2:1;
1756 if(is_400)
1757 {
1758 besr.p2_x_start_end = 0;
1759 besr.p3_x_start_end = 0;
1760 }
1761 else
1762 {
1763 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16);
1764 besr.p3_x_start_end = besr.p2_x_start_end;
1765 }
1766
1767 return 0;
1768 }
1769
1770 static void radeon_compute_framesize(vidix_playback_t *info)
1771 {
1772 unsigned pitch,awidth,dbpp;
1773 pitch = radeon_query_pitch(info->fourcc,&info->src.pitch);
1774 dbpp = radeon_vid_get_dbpp();
1775 switch(info->fourcc)
1776 {
1777 case IMGFMT_I420:
1778 case IMGFMT_YV12:
1779 case IMGFMT_IYUV:
1780 awidth = (info->src.w + (pitch-1)) & ~(pitch-1);
1781 info->frame_size = awidth*(info->src.h+info->src.h/2);
1782 break;
1783 case IMGFMT_Y800:
1784 case IMGFMT_Y8:
1785 awidth = (info->src.w + (pitch-1)) & ~(pitch-1);
1786 info->frame_size = awidth*info->src.h;
1787 break;
1788 case IMGFMT_IF09:
1789 case IMGFMT_YVU9:
1790 awidth = (info->src.w + (pitch-1)) & ~(pitch-1);
1791 info->frame_size = awidth*(info->src.h+info->src.h/8);
1792 break;
1793 case IMGFMT_RGB32:
1794 case IMGFMT_BGR32:
1795 awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1);
1796 info->frame_size = awidth*info->src.h;
1797 break;
1798 /* YUY2 YVYU, RGB15, RGB16 */
1799 default:
1800 awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1);
1801 info->frame_size = awidth*info->src.h;
1802 break;
1803 }
1804 }
1805
1806 int vixConfigPlayback(vidix_playback_t *info)
1807 {
1808 unsigned rgb_size,nfr;
1809 if(!is_supported_fourcc(info->fourcc)) return ENOSYS;
1810 if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES;
1811 if(info->num_frames==1) besr.double_buff=0;
1812 else besr.double_buff=1;
1813 radeon_compute_framesize(info);
1814
1815 rgb_size = radeon_get_xres()*radeon_get_yres()*((radeon_vid_get_dbpp()+7)/8);
1816 nfr = info->num_frames;
1817 for(;nfr>0; nfr--)
1818 {
1819 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr;
1820 #ifdef HAVE_X11
1821 radeon_overlay_off -= firegl_shift;
1822 #endif
1823 radeon_overlay_off &= 0xffff0000;
1824 if(radeon_overlay_off >= (int)rgb_size ) break;
1825 }
1826 if(nfr <= 3)
1827 {
1828 nfr = info->num_frames;
1829 for(;nfr>0; nfr--)
1830 {
1831 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr;
1832 #ifdef HAVE_X11
1833 radeon_overlay_off -= firegl_shift;
1834 #endif
1835 radeon_overlay_off &= 0xffff0000;
1836 if(radeon_overlay_off > 0) break;
1837 }
1838 }
1839 if(nfr <= 0) return EINVAL;
1840 info->num_frames = nfr;
1841 besr.vid_nbufs = info->num_frames;
1842 info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off;
1843 radeon_vid_init_video(info);
1844 return 0;
1845 }
1846
1847 int vixPlaybackOn( void )
1848 {
1849 radeon_vid_display_video();
1850 return 0;
1851 }
1852
1853 int vixPlaybackOff( void )
1854 {
1855 radeon_vid_stop_video();
1856 return 0;
1857 }
1858
1859 int vixPlaybackFrameSelect(unsigned frame)
1860 {
1861 uint32_t off[6];
1862 int prev_frame= (frame-1+besr.vid_nbufs) % besr.vid_nbufs;
1863 /*
1864 buf3-5 always should point onto second buffer for better
1865 deinterlacing and TV-in
1866 */
1867 if(!besr.double_buff) return 0;
1868 if(frame > besr.vid_nbufs) frame = besr.vid_nbufs-1;
1869 if(prev_frame > (int)besr.vid_nbufs) prev_frame = besr.vid_nbufs-1;
1870 off[0] = besr.vid_buf_base_adrs_y[frame];
1871 off[1] = besr.vid_buf_base_adrs_v[frame];
1872 off[2] = besr.vid_buf_base_adrs_u[frame];
1873 off[3] = besr.vid_buf_base_adrs_y[prev_frame];
1874 off[4] = besr.vid_buf_base_adrs_v[prev_frame];
1875 off[5] = besr.vid_buf_base_adrs_u[prev_frame];
1876 radeon_fifo_wait(8);
1877 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
1878 radeon_engine_idle();
1879 while(!(INREG(OV0_REG_LOAD_CNTL)&REG_LD_CTL_LOCK_READBACK));
1880 OUTREG(OV0_VID_BUF0_BASE_ADRS, off[0]);
1881 OUTREG(OV0_VID_BUF1_BASE_ADRS, off[1]);
1882 OUTREG(OV0_VID_BUF2_BASE_ADRS, off[2]);
1883 OUTREG(OV0_VID_BUF3_BASE_ADRS, off[3]);
1884 OUTREG(OV0_VID_BUF4_BASE_ADRS, off[4]);
1885 OUTREG(OV0_VID_BUF5_BASE_ADRS, off[5]);
1886 OUTREG(OV0_REG_LOAD_CNTL, 0);
1887 if(besr.vid_nbufs == 2) radeon_wait_vsync();
1888 if(__verbose > 1) radeon_vid_dump_regs();
1889 return 0;
1890 }
1891
1892 vidix_video_eq_t equal =
1893 {
1894 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION
1895 #ifndef RAGE128
1896 | VEQ_CAP_CONTRAST | VEQ_CAP_HUE | VEQ_CAP_RGB_INTENSITY
1897 #endif
1898 ,
1899 0, 0, 0, 0, 0, 0, 0, 0 };
1900
1901 int vixPlaybackGetEq( vidix_video_eq_t * eq)
1902 {
1903 memcpy(eq,&equal,sizeof(vidix_video_eq_t));
1904 return 0;
1905 }
1906
1907 #ifndef RAGE128
1908 #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0)
1909 #define RTFBrightness(a) (((a)*1.0)/2000.0)
1910 #define RTFIntensity(a) (((a)*1.0)/2000.0)
1911 #define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0)
1912 #define RTFHue(a) (((a)*3.1416)/1000.0)
1913 #define RTFCheckParam(a) {if((a)<-1000) (a)=-1000; if((a)>1000) (a)=1000;}
1914 #endif
1915
1916 int vixPlaybackSetEq( const vidix_video_eq_t * eq)
1917 {
1918 #ifdef RAGE128
1919 int br,sat;
1920 #else
1921 int itu_space;
1922 #endif
1923 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness;
1924 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast;
1925 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation;
1926 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue;
1927 if(eq->cap & VEQ_CAP_RGB_INTENSITY)
1928 {
1929 equal.red_intensity = eq->red_intensity;
1930 equal.green_intensity = eq->green_intensity;
1931 equal.blue_intensity = eq->blue_intensity;
1932 }
1933 equal.flags = eq->flags;
1934 #ifdef RAGE128
1935 br = equal.brightness * 64 / 1000;
1936 if(br < -64) br = -64; if(br > 63) br = 63;
1937 sat = (equal.saturation + 1000) * 16 / 1000;
1938 if(sat < 0) sat = 0; if(sat > 31) sat = 31;
1939 OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16));
1940 #else
1941 itu_space = equal.flags == VEQ_FLG_ITU_R_BT_709 ? 1 : 0;
1942 RTFCheckParam(equal.brightness);
1943 RTFCheckParam(equal.saturation);
1944 RTFCheckParam(equal.contrast);
1945 RTFCheckParam(equal.hue);
1946 RTFCheckParam(equal.red_intensity);
1947 RTFCheckParam(equal.green_intensity);
1948 RTFCheckParam(equal.blue_intensity);
1949 radeon_set_transform(RTFBrightness(equal.brightness),
1950 RTFContrast(equal.contrast),
1951 RTFSaturation(equal.saturation),
1952 RTFHue(equal.hue),
1953 RTFIntensity(equal.red_intensity),
1954 RTFIntensity(equal.green_intensity),
1955 RTFIntensity(equal.blue_intensity),
1956 itu_space);
1957 #endif
1958 return 0;
1959 }
1960
1961 int vixPlaybackSetDeint( const vidix_deinterlace_t * info)
1962 {
1963 unsigned sflg;
1964 switch(info->flags)
1965 {
1966 default:
1967 case CFG_NON_INTERLACED:
1968 besr.deinterlace_on = 0;
1969 break;
1970 case CFG_EVEN_ODD_INTERLACING:
1971 case CFG_INTERLACED:
1972 besr.deinterlace_on = 1;
1973 besr.deinterlace_pattern = 0x900AAAAA;
1974 break;
1975 case CFG_ODD_EVEN_INTERLACING:
1976 besr.deinterlace_on = 1;
1977 besr.deinterlace_pattern = 0x00055555;
1978 break;
1979 case CFG_UNIQUE_INTERLACING:
1980 besr.deinterlace_on = 1;
1981 besr.deinterlace_pattern = info->deinterlace_pattern;
1982 break;
1983 }
1984 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
1985 radeon_engine_idle();
1986 while(!(INREG(OV0_REG_LOAD_CNTL)&REG_LD_CTL_LOCK_READBACK));
1987 radeon_fifo_wait(15);
1988 sflg = INREG(OV0_SCALE_CNTL);
1989 if(besr.deinterlace_on)
1990 {
1991 OUTREG(OV0_SCALE_CNTL,sflg | SCALER_ADAPTIVE_DEINT);
1992 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern);
1993 }
1994 else OUTREG(OV0_SCALE_CNTL,sflg & (~SCALER_ADAPTIVE_DEINT));
1995 OUTREG(OV0_REG_LOAD_CNTL, 0);
1996 return 0;
1997 }
1998
1999 int vixPlaybackGetDeint( vidix_deinterlace_t * info)
2000 {
2001 if(!besr.deinterlace_on) info->flags = CFG_NON_INTERLACED;
2002 else
2003 {
2004 info->flags = CFG_UNIQUE_INTERLACING;
2005 info->deinterlace_pattern = besr.deinterlace_pattern;
2006 }
2007 return 0;
2008 }
2009
2010
2011 /* Graphic keys */
2012 static vidix_grkey_t radeon_grkey;
2013
2014 static void set_gr_key( void )
2015 {
2016 if(radeon_grkey.ckey.op == CKEY_TRUE)
2017 {
2018 int dbpp=radeon_vid_get_dbpp();
2019 besr.ckey_on=1;
2020
2021 switch(dbpp)
2022 {
2023 case 15:
2024 #ifdef RADEON
2025 if(RadeonFamily > 100)
2026 besr.graphics_key_clr=
2027 ((radeon_grkey.ckey.blue &0xF8))
2028 | ((radeon_grkey.ckey.green&0xF8)<<8)
2029 | ((radeon_grkey.ckey.red &0xF8)<<16);
2030 else
2031 #endif
2032 besr.graphics_key_clr=
2033 ((radeon_grkey.ckey.blue &0xF8)>>3)
2034 | ((radeon_grkey.ckey.green&0xF8)<<2)
2035 | ((radeon_grkey.ckey.red &0xF8)<<7);
2036 break;
2037 case 16:
2038 #ifdef RADEON
2039 /* This test may be too general/specific */
2040 if(RadeonFamily > 100)
2041 besr.graphics_key_clr=
2042 ((radeon_grkey.ckey.blue &0xF8))
2043 | ((radeon_grkey.ckey.green&0xFC)<<8)
2044 | ((radeon_grkey.ckey.red &0xF8)<<16);
2045 else
2046 #endif
2047 besr.graphics_key_clr=
2048 ((radeon_grkey.ckey.blue &0xF8)>>3)
2049 | ((radeon_grkey.ckey.green&0xFC)<<3)
2050 | ((radeon_grkey.ckey.red &0xF8)<<8);
2051 break;
2052 case 24:
2053 besr.graphics_key_clr=
2054 ((radeon_grkey.ckey.blue &0xFF))
2055 | ((radeon_grkey.ckey.green&0xFF)<<8)
2056 | ((radeon_grkey.ckey.red &0xFF)<<16);
2057 break;
2058 case 32:
2059 besr.graphics_key_clr=
2060 ((radeon_grkey.ckey.blue &0xFF))
2061 | ((radeon_grkey.ckey.green&0xFF)<<8)
2062 | ((radeon_grkey.ckey.red &0xFF)<<16);
2063 break;
2064 default:
2065 besr.ckey_on=0;
2066 besr.graphics_key_msk=0;
2067 besr.graphics_key_clr=0;
2068 }
2069 #ifdef RAGE128
2070 besr.graphics_key_msk=(1<<dbpp)-1;
2071 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_NE|CMP_MIX_AND;
2072 #else
2073 besr.graphics_key_msk=besr.graphics_key_clr;
2074 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|CMP_MIX_AND|GRAPHIC_KEY_FN_EQ;
2075 #endif
2076 }
2077 else
2078 {
2079 besr.ckey_on=0;
2080 besr.graphics_key_msk=0;
2081 besr.graphics_key_clr=0;
2082 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND;
2083 }
2084 radeon_fifo_wait(3);
2085 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk);
2086 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr);
2087 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl);
2088 }
2089
2090 int vixGetGrKeys(vidix_grkey_t *grkey)
2091 {
2092 memcpy(grkey, &radeon_grkey, sizeof(vidix_grkey_t));
2093 return(0);
2094 }
2095
2096 int vixSetGrKeys(const vidix_grkey_t *grkey)
2097 {
2098 memcpy(&radeon_grkey, grkey, sizeof(vidix_grkey_t));
2099 set_gr_key();
2100 return(0);
2101 }