Mercurial > mplayer.hg
comparison vidix/sis_regs.h @ 22850:9a1e26fef45b
Move driver files directly into the vidix directory.
author | diego |
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date | Sun, 01 Apr 2007 00:02:43 +0000 |
parents | |
children | 109c80c869ac |
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1 /** | |
2 SiS register definitions and access macros. | |
3 From SiS X11 driver. | |
4 | |
5 Copyright 2001-2003 by Thomas Winischhofer, Vienna, Austria. | |
6 | |
7 This program is free software; you can redistribute it and/or modify | |
8 it under the terms of the GNU General Public License as published by | |
9 the Free Software Foundation; either version 2 of the License, or | |
10 (at your option) any later version. | |
11 | |
12 This program is distributed in the hope that it will be useful, | |
13 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 GNU General Public License for more details. | |
16 | |
17 You should have received a copy of the GNU General Public License | |
18 along with this program; if not, write to the Free Software | |
19 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | |
21 **/ | |
22 | |
23 #ifndef VIDIX_SIS_REGS_H | |
24 #define VIDIX_SIS_REGS_H | |
25 | |
26 #define inSISREG(base) INPORT8(base) | |
27 #define outSISREG(base,val) OUTPORT8(base, val) | |
28 #define orSISREG(base,val) do { \ | |
29 unsigned char __Temp = INPORT8(base); \ | |
30 outSISREG(base, __Temp | (val)); \ | |
31 } while (0) | |
32 #define andSISREG(base,val) do { \ | |
33 unsigned char __Temp = INPORT8(base); \ | |
34 outSISREG(base, __Temp & (val)); \ | |
35 } while (0) | |
36 | |
37 #define inSISIDXREG(base,idx,var) do { \ | |
38 OUTPORT8(base, idx); var=INPORT8((base)+1); \ | |
39 } while (0) | |
40 #define outSISIDXREG(base,idx,val) do { \ | |
41 OUTPORT8(base, idx); OUTPORT8((base)+1, val); \ | |
42 } while (0) | |
43 #define orSISIDXREG(base,idx,val) do { \ | |
44 unsigned char __Temp; \ | |
45 OUTPORT8(base, idx); \ | |
46 __Temp = INPORT8((base)+1)|(val); \ | |
47 outSISIDXREG(base,idx,__Temp); \ | |
48 } while (0) | |
49 #define andSISIDXREG(base,idx,and) do { \ | |
50 unsigned char __Temp; \ | |
51 OUTPORT8(base, idx); \ | |
52 __Temp = INPORT8((base)+1)&(and); \ | |
53 outSISIDXREG(base,idx,__Temp); \ | |
54 } while (0) | |
55 #define setSISIDXREG(base,idx,and,or) do { \ | |
56 unsigned char __Temp; \ | |
57 OUTPORT8(base, idx); \ | |
58 __Temp = (INPORT8((base)+1)&(and))|(or); \ | |
59 outSISIDXREG(base,idx,__Temp); \ | |
60 } while (0) | |
61 | |
62 #define BITMASK(h,l) (((unsigned)(1U << ((h)-(l)+1))-1)<<(l)) | |
63 #define GENMASK(mask) BITMASK(1?mask,0?mask) | |
64 | |
65 #define GETBITS(var,mask) (((var) & GENMASK(mask)) >> (0?mask)) | |
66 #define SETBITS(val,mask) ((val) << (0?mask)) | |
67 #define SETBIT(n) (1<<(n)) | |
68 | |
69 #define GETBITSTR(val,from,to) ((GETBITS(val,from)) << (0?to)) | |
70 #define SETVARBITS(var,val,from,to) (((var)&(~(GENMASK(to)))) | \ | |
71 GETBITSTR(val,from,to)) | |
72 #define GETVAR8(var) ((var)&0xFF) | |
73 #define SETVAR8(var,val) (var) = GETVAR8(val) | |
74 | |
75 /* #define VGA_RELIO_BASE 0x380 */ | |
76 | |
77 #define AROFFSET 0x40 /* VGA_ATTR_INDEX - VGA_RELIO_BASE */ | |
78 #define ARROFFSET 0x41 /* VGA_ATTR_DATA_R - VGA_RELIO_BASE */ | |
79 #define GROFFSET 0x4e /* VGA_GRAPH_INDEX - VGA_RELIO_BASE */ | |
80 #define SROFFSET 0x44 /* VGA_SEQ_INDEX - VGA_RELIO_BASE */ | |
81 #define CROFFSET 0x54 /* VGA_CRTC_INDEX_OFFSET + VGA_IOBASE_COLOR - VGA_RELIO_BASE */ | |
82 #define MISCROFFSET 0x4c /* VGA_MISC_OUT_R - VGA_RELIO_BASE */ | |
83 #define MISCWOFFSET 0x42 /* VGA_MISC_OUT_W - VGA_RELIO_BASE */ | |
84 #define INPUTSTATOFFSET 0x5A | |
85 #define PART1OFFSET 0x04 | |
86 #define PART2OFFSET 0x10 | |
87 #define PART3OFFSET 0x12 | |
88 #define PART4OFFSET 0x14 | |
89 #define PART5OFFSET 0x16 | |
90 #define VIDEOOFFSET 0x02 | |
91 #define COLREGOFFSET 0x48 | |
92 | |
93 #define SIS_IOBASE sis_iobase /* var defined in sis_vid.c */ | |
94 #define SISAR SIS_IOBASE + AROFFSET | |
95 #define SISARR SIS_IOBASE + ARROFFSET | |
96 #define SISGR SIS_IOBASE + GROFFSET | |
97 #define SISSR SIS_IOBASE + SROFFSET | |
98 #define SISCR SIS_IOBASE + CROFFSET | |
99 #define SISMISCR SIS_IOBASE + MISCROFFSET | |
100 #define SISMISCW SIS_IOBASE + MISCWOFFSET | |
101 #define SISINPSTAT SIS_IOBASE + INPUTSTATOFFSET | |
102 #define SISPART1 SIS_IOBASE + PART1OFFSET | |
103 #define SISPART2 SIS_IOBASE + PART2OFFSET | |
104 #define SISPART3 SIS_IOBASE + PART3OFFSET | |
105 #define SISPART4 SIS_IOBASE + PART4OFFSET | |
106 #define SISPART5 SIS_IOBASE + PART5OFFSET | |
107 #define SISVID SIS_IOBASE + VIDEOOFFSET | |
108 #define SISCOLIDX SIS_IOBASE + COLREGOFFSET | |
109 #define SISCOLDATA SIS_IOBASE + COLREGOFFSET + 1 | |
110 #define SISCOL2IDX SISPART5 | |
111 #define SISCOL2DATA SISPART5 + 1 | |
112 | |
113 | |
114 #define vc_index_offset 0x00 /* Video capture - unused */ | |
115 #define vc_data_offset 0x01 | |
116 #define vi_index_offset VIDEOOFFSET | |
117 #define vi_data_offset (VIDEOOFFSET + 1) | |
118 #define crt2_index_offset PART1OFFSET | |
119 #define crt2_port_offset (PART1OFFSET + 1) | |
120 #define sr_index_offset SROFFSET | |
121 #define sr_data_offset (SROFFSET + 1) | |
122 #define cr_index_offset CROFFSET | |
123 #define cr_data_offset (CROFFSET + 1) | |
124 #define input_stat INPUTSTATOFFSET | |
125 | |
126 /* For old chipsets (5597/5598, 6326, 530/620) ------------ */ | |
127 /* SR (3C4) */ | |
128 #define BankReg 0x06 | |
129 #define ClockReg 0x07 | |
130 #define CPUThreshold 0x08 | |
131 #define CRTThreshold 0x09 | |
132 #define CRTCOff 0x0A | |
133 #define DualBanks 0x0B | |
134 #define MMIOEnable 0x0B | |
135 #define RAMSize 0x0C | |
136 #define Mode64 0x0C | |
137 #define ExtConfStatus1 0x0E | |
138 #define ClockBase 0x13 | |
139 #define LinearAdd0 0x20 | |
140 #define LinearAdd1 0x21 | |
141 #define GraphEng 0x27 | |
142 #define MemClock0 0x28 | |
143 #define MemClock1 0x29 | |
144 #define XR2A 0x2A | |
145 #define XR2B 0x2B | |
146 #define TurboQueueBase 0x2C | |
147 #define FBSize 0x2F | |
148 #define ExtMiscCont5 0x34 | |
149 #define ExtMiscCont9 0x3C | |
150 | |
151 /* 3x4 */ | |
152 #define Offset 0x13 | |
153 | |
154 /* SiS Registers for 300, 540, 630, 730, 315, 550, 650, 740 */ | |
155 | |
156 /* VGA standard register */ | |
157 #define Index_SR_Graphic_Mode 0x06 | |
158 #define Index_SR_RAMDAC_Ctrl 0x07 | |
159 #define Index_SR_Threshold_Ctrl1 0x08 | |
160 #define Index_SR_Threshold_Ctrl2 0x09 | |
161 #define Index_SR_Misc_Ctrl 0x0F | |
162 #define Index_SR_DDC 0x11 | |
163 #define Index_SR_Feature_Connector_Ctrl 0x12 | |
164 #define Index_SR_DRAM_Sizing 0x14 | |
165 #define Index_SR_DRAM_State_Machine_Ctrl 0x15 | |
166 #define Index_SR_AGP_PCI_State_Machine 0x21 | |
167 #define Index_SR_Internal_MCLK0 0x28 | |
168 #define Index_SR_Internal_MCLK1 0x29 | |
169 #define Index_SR_Internal_DCLK1 0x2B | |
170 #define Index_SR_Internal_DCLK2 0x2C | |
171 #define Index_SR_Internal_DCLK3 0x2D | |
172 #define Index_SR_Ext_Clock_Sel 0x32 | |
173 #define Index_SR_Int_Status 0x34 | |
174 #define Index_SR_Int_Enable 0x35 | |
175 #define Index_SR_Int_Reset 0x36 | |
176 #define Index_SR_Power_On_Trap 0x38 | |
177 #define Index_SR_Power_On_Trap2 0x39 | |
178 #define Index_SR_Power_On_Trap3 0x3A | |
179 | |
180 /* video registers (300/630/730/315/550/650/740 only) */ | |
181 #define Index_VI_Passwd 0x00 | |
182 | |
183 /* Video overlay horizontal start/end, unit=screen pixels */ | |
184 #define Index_VI_Win_Hor_Disp_Start_Low 0x01 | |
185 #define Index_VI_Win_Hor_Disp_End_Low 0x02 | |
186 #define Index_VI_Win_Hor_Over 0x03 /* Overflow */ | |
187 | |
188 /* Video overlay vertical start/end, unit=screen pixels */ | |
189 #define Index_VI_Win_Ver_Disp_Start_Low 0x04 | |
190 #define Index_VI_Win_Ver_Disp_End_Low 0x05 | |
191 #define Index_VI_Win_Ver_Over 0x06 /* Overflow */ | |
192 | |
193 /* Y Plane (4:2:0) or YUV (4:2:2) buffer start address, unit=word */ | |
194 #define Index_VI_Disp_Y_Buf_Start_Low 0x07 | |
195 #define Index_VI_Disp_Y_Buf_Start_Middle 0x08 | |
196 #define Index_VI_Disp_Y_Buf_Start_High 0x09 | |
197 | |
198 /* U Plane (4:2:0) buffer start address, unit=word */ | |
199 #define Index_VI_U_Buf_Start_Low 0x0A | |
200 #define Index_VI_U_Buf_Start_Middle 0x0B | |
201 #define Index_VI_U_Buf_Start_High 0x0C | |
202 | |
203 /* V Plane (4:2:0) buffer start address, unit=word */ | |
204 #define Index_VI_V_Buf_Start_Low 0x0D | |
205 #define Index_VI_V_Buf_Start_Middle 0x0E | |
206 #define Index_VI_V_Buf_Start_High 0x0F | |
207 | |
208 /* Pitch for Y, UV Planes, unit=word */ | |
209 #define Index_VI_Disp_Y_Buf_Pitch_Low 0x10 | |
210 #define Index_VI_Disp_UV_Buf_Pitch_Low 0x11 | |
211 #define Index_VI_Disp_Y_UV_Buf_Pitch_Middle 0x12 | |
212 | |
213 /* What is this ? */ | |
214 #define Index_VI_Disp_Y_Buf_Preset_Low 0x13 | |
215 #define Index_VI_Disp_Y_Buf_Preset_Middle 0x14 | |
216 | |
217 #define Index_VI_UV_Buf_Preset_Low 0x15 | |
218 #define Index_VI_UV_Buf_Preset_Middle 0x16 | |
219 #define Index_VI_Disp_Y_UV_Buf_Preset_High 0x17 | |
220 | |
221 /* Scaling control registers */ | |
222 #define Index_VI_Hor_Post_Up_Scale_Low 0x18 | |
223 #define Index_VI_Hor_Post_Up_Scale_High 0x19 | |
224 #define Index_VI_Ver_Up_Scale_Low 0x1A | |
225 #define Index_VI_Ver_Up_Scale_High 0x1B | |
226 #define Index_VI_Scale_Control 0x1C | |
227 | |
228 /* Playback line buffer control */ | |
229 #define Index_VI_Play_Threshold_Low 0x1D | |
230 #define Index_VI_Play_Threshold_High 0x1E | |
231 #define Index_VI_Line_Buffer_Size 0x1F | |
232 | |
233 /* Destination color key */ | |
234 #define Index_VI_Overlay_ColorKey_Red_Min 0x20 | |
235 #define Index_VI_Overlay_ColorKey_Green_Min 0x21 | |
236 #define Index_VI_Overlay_ColorKey_Blue_Min 0x22 | |
237 #define Index_VI_Overlay_ColorKey_Red_Max 0x23 | |
238 #define Index_VI_Overlay_ColorKey_Green_Max 0x24 | |
239 #define Index_VI_Overlay_ColorKey_Blue_Max 0x25 | |
240 | |
241 /* Source color key, YUV color space */ | |
242 #define Index_VI_Overlay_ChromaKey_Red_Y_Min 0x26 | |
243 #define Index_VI_Overlay_ChromaKey_Green_U_Min 0x27 | |
244 #define Index_VI_Overlay_ChromaKey_Blue_V_Min 0x28 | |
245 #define Index_VI_Overlay_ChromaKey_Red_Y_Max 0x29 | |
246 #define Index_VI_Overlay_ChromaKey_Green_U_Max 0x2A | |
247 #define Index_VI_Overlay_ChromaKey_Blue_V_Max 0x2B | |
248 | |
249 /* Contrast enhancement and brightness control */ | |
250 #define Index_VI_Contrast_Factor 0x2C /* obviously unused/undefined */ | |
251 #define Index_VI_Brightness 0x2D | |
252 #define Index_VI_Contrast_Enh_Ctrl 0x2E | |
253 | |
254 #define Index_VI_Key_Overlay_OP 0x2F | |
255 | |
256 #define Index_VI_Control_Misc0 0x30 | |
257 #define Index_VI_Control_Misc1 0x31 | |
258 #define Index_VI_Control_Misc2 0x32 | |
259 | |
260 /* TW: Subpicture registers */ | |
261 #define Index_VI_SubPict_Buf_Start_Low 0x33 | |
262 #define Index_VI_SubPict_Buf_Start_Middle 0x34 | |
263 #define Index_VI_SubPict_Buf_Start_High 0x35 | |
264 | |
265 /* TW: What is this ? */ | |
266 #define Index_VI_SubPict_Buf_Preset_Low 0x36 | |
267 #define Index_VI_SubPict_Buf_Preset_Middle 0x37 | |
268 | |
269 /* TW: Subpicture pitch, unit=16 bytes */ | |
270 #define Index_VI_SubPict_Buf_Pitch 0x38 | |
271 | |
272 /* TW: Subpicture scaling control */ | |
273 #define Index_VI_SubPict_Hor_Scale_Low 0x39 | |
274 #define Index_VI_SubPict_Hor_Scale_High 0x3A | |
275 #define Index_VI_SubPict_Vert_Scale_Low 0x3B | |
276 #define Index_VI_SubPict_Vert_Scale_High 0x3C | |
277 | |
278 #define Index_VI_SubPict_Scale_Control 0x3D | |
279 /* (0x40 = enable/disable subpicture) */ | |
280 | |
281 /* TW: Subpicture line buffer control */ | |
282 #define Index_VI_SubPict_Threshold 0x3E | |
283 | |
284 /* TW: What is this? */ | |
285 #define Index_VI_FIFO_Max 0x3F | |
286 | |
287 /* TW: Subpicture palette; 16 colors, total 32 bytes address space */ | |
288 #define Index_VI_SubPict_Pal_Base_Low 0x40 | |
289 #define Index_VI_SubPict_Pal_Base_High 0x41 | |
290 | |
291 /* I wish I knew how to use these ... */ | |
292 #define Index_MPEG_Read_Ctrl0 0x60 /* MPEG auto flip */ | |
293 #define Index_MPEG_Read_Ctrl1 0x61 /* MPEG auto flip */ | |
294 #define Index_MPEG_Read_Ctrl2 0x62 /* MPEG auto flip */ | |
295 #define Index_MPEG_Read_Ctrl3 0x63 /* MPEG auto flip */ | |
296 | |
297 /* TW: MPEG AutoFlip scale */ | |
298 #define Index_MPEG_Ver_Up_Scale_Low 0x64 | |
299 #define Index_MPEG_Ver_Up_Scale_High 0x65 | |
300 | |
301 #define Index_MPEG_Y_Buf_Preset_Low 0x66 | |
302 #define Index_MPEG_Y_Buf_Preset_Middle 0x67 | |
303 #define Index_MPEG_UV_Buf_Preset_Low 0x68 | |
304 #define Index_MPEG_UV_Buf_Preset_Middle 0x69 | |
305 #define Index_MPEG_Y_UV_Buf_Preset_High 0x6A | |
306 | |
307 /* TW: The following registers only exist on the 310/325 series */ | |
308 | |
309 /* TW: Bit 16:24 of Y_U_V buf start address (?) */ | |
310 #define Index_VI_Y_Buf_Start_Over 0x6B | |
311 #define Index_VI_U_Buf_Start_Over 0x6C | |
312 #define Index_VI_V_Buf_Start_Over 0x6D | |
313 | |
314 #define Index_VI_Disp_Y_Buf_Pitch_High 0x6E | |
315 #define Index_VI_Disp_UV_Buf_Pitch_High 0x6F | |
316 | |
317 /* Hue and saturation */ | |
318 #define Index_VI_Hue 0x70 | |
319 #define Index_VI_Saturation 0x71 | |
320 | |
321 #define Index_VI_SubPict_Start_Over 0x72 | |
322 #define Index_VI_SubPict_Buf_Pitch_High 0x73 | |
323 | |
324 #define Index_VI_Control_Misc3 0x74 | |
325 | |
326 | |
327 /* TW: Bits (and helpers) for Index_VI_Control_Misc0 */ | |
328 #define VI_Misc0_Enable_Overlay 0x02 | |
329 #define VI_Misc0_420_Plane_Enable 0x04 /* Select Plane or Packed mode */ | |
330 #define VI_Misc0_422_Enable 0x20 /* Select 422 or 411 mode */ | |
331 #define VI_Misc0_Fmt_YVU420P 0x0C /* YUV420 Planar (I420, YV12) */ | |
332 #define VI_Misc0_Fmt_YUYV 0x28 /* YUYV Packed (YUY2) */ | |
333 #define VI_Misc0_Fmt_UYVY 0x08 /* (UYVY) */ | |
334 | |
335 /* TW: Bits for Index_VI_Control_Misc1 */ | |
336 /* #define VI_Misc1_? 0x01 */ | |
337 #define VI_Misc1_BOB_Enable 0x02 | |
338 #define VI_Misc1_Line_Merge 0x04 | |
339 #define VI_Misc1_Field_Mode 0x08 | |
340 /* #define VI_Misc1_? 0x10 */ | |
341 #define VI_Misc1_Non_Interleave 0x20 /* 300 series only? */ | |
342 #define VI_Misc1_Buf_Addr_Lock 0x20 /* 310 series only? */ | |
343 /* #define VI_Misc1_? 0x40 */ | |
344 /* #define VI_Misc1_? 0x80 */ | |
345 | |
346 /* TW: Bits for Index_VI_Control_Misc2 */ | |
347 #define VI_Misc2_Select_Video2 0x01 | |
348 #define VI_Misc2_Video2_On_Top 0x02 | |
349 /* #define VI_Misc2_? 0x04 */ | |
350 #define VI_Misc2_Vertical_Interpol 0x08 | |
351 #define VI_Misc2_Dual_Line_Merge 0x10 | |
352 #define VI_Misc2_All_Line_Merge 0x20 /* 310 series only? */ | |
353 #define VI_Misc2_Auto_Flip_Enable 0x40 /* 300 series only? */ | |
354 #define VI_Misc2_Video_Reg_Write_Enable 0x80 /* 310 series only? */ | |
355 | |
356 /* TW: Bits for Index_VI_Control_Misc3 */ | |
357 #define VI_Misc3_Submit_Video_1 0x01 /* AKA "address ready" */ | |
358 #define VI_Misc3_Submit_Video_2 0x02 /* AKA "address ready" */ | |
359 #define VI_Misc3_Submit_SubPict 0x04 /* AKA "address ready" */ | |
360 | |
361 /* TW: Values for Index_VI_Key_Overlay_OP (0x2F) */ | |
362 #define VI_ROP_Never 0x00 | |
363 #define VI_ROP_DestKey 0x03 | |
364 #define VI_ROP_Always 0x0F | |
365 | |
366 /* | |
367 * CRT_2 function control register --------------------------------- | |
368 */ | |
369 #define Index_CRT2_FC_CONTROL 0x00 | |
370 #define Index_CRT2_FC_SCREEN_HIGH 0x04 | |
371 #define Index_CRT2_FC_SCREEN_MID 0x05 | |
372 #define Index_CRT2_FC_SCREEN_LOW 0x06 | |
373 #define Index_CRT2_FC_ENABLE_WRITE 0x24 | |
374 #define Index_CRT2_FC_VR 0x25 | |
375 #define Index_CRT2_FC_VCount 0x27 | |
376 #define Index_CRT2_FC_VCount1 0x28 | |
377 | |
378 #define Index_310_CRT2_FC_VR 0x30 /* d[1] = vertical retrace */ | |
379 #define Index_310_CRT2_FC_RT 0x33 /* d[7] = retrace in progress */ | |
380 | |
381 /* video attributes - these should probably be configurable on the fly | |
382 * so users with different desktop sizes can keep | |
383 * captured data off the desktop | |
384 */ | |
385 #define _VINWID 704 | |
386 #define _VINHGT _VINHGT_NTSC | |
387 #define _VINHGT_NTSC 240 | |
388 #define _VINHGT_PAL 290 | |
389 #define _VIN_WINDOW (704 * 291 * 2) | |
390 #define _VBI_WINDOW (704 * 64 * 2) | |
391 | |
392 #define _VIN_FIELD_EVEN 1 | |
393 #define _VIN_FIELD_ODD 2 | |
394 #define _VIN_FIELD_BOTH 4 | |
395 | |
396 | |
397 /* i2c registers (TW; not on 300/310/325 series) */ | |
398 #define X_INDEXREG 0x14 | |
399 #define X_PORTREG 0x15 | |
400 #define X_DATA 0x0f | |
401 #define I2C_SCL 0x00 | |
402 #define I2C_SDA 0x01 | |
403 #define I2C_DELAY 10 | |
404 | |
405 /* mmio registers for video */ | |
406 #define REG_PRIM_CRT_COUNTER 0x8514 | |
407 | |
408 /* TW: MPEG MMIO registers (630 and later) ----------------------------*/ | |
409 | |
410 /* Not public (yet?) */ | |
411 | |
412 #endif /* VIDIX_SIS_REGS_H */ |