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comparison vidix/sis_vid.c @ 22850:9a1e26fef45b

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Move driver files directly into the vidix directory.
author diego
date Sun, 01 Apr 2007 00:02:43 +0000
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children 77def5093daf
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22849:bddb09395c3e 22850:9a1e26fef45b
1 /**
2 VIDIX driver for SiS 300 and 310/325 series chips.
3
4 Copyright 2003 Jake Page, Sugar Media.
5
6 Based on SiS Xv driver:
7 Copyright 2002-2003 by Thomas Winischhofer, Vienna, Austria.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22
23 2003/10/08 integrated into mplayer/vidix architecture -- Alex Beregszaszi
24 **/
25
26 #include <errno.h>
27 #include <stdio.h>
28 #include <stdlib.h>
29 #include <string.h>
30 #include <inttypes.h>
31 #include <unistd.h>
32
33 #include "vidix.h"
34 #include "fourcc.h"
35 #include "../libdha/libdha.h"
36 #include "../libdha/pci_ids.h"
37 #include "../libdha/pci_names.h"
38 #include "../config.h"
39
40 #include "sis_regs.h"
41 #include "sis_defs.h"
42
43
44 /** Random defines **/
45
46 #define WATCHDOG_DELAY 500000 /* Watchdog counter for retrace waiting */
47 #define IMAGE_MIN_WIDTH 32 /* Min and max source image sizes */
48 #define IMAGE_MIN_HEIGHT 24
49 #define IMAGE_MAX_WIDTH 720
50 #define IMAGE_MAX_HEIGHT 576
51 #define IMAGE_MAX_WIDTH_M650 1920
52 #define IMAGE_MAX_HEIGHT_M650 1080
53
54 #define OVERLAY_MIN_WIDTH 32 /* Minimum overlay sizes */
55 #define OVERLAY_MIN_HEIGHT 24
56
57 #define DISPMODE_SINGLE1 0x1 /* TW: CRT1 only */
58 #define DISPMODE_SINGLE2 0x2 /* TW: CRT2 only */
59 #define DISPMODE_MIRROR 0x4 /* TW: CRT1 + CRT2 MIRROR */
60
61 #define VMODE_INTERLACED 0x1
62 #define VMODE_DOUBLESCAN 0x2
63
64 typedef struct {
65 short x1, y1, x2, y2;
66 } BoxRec;
67
68 typedef struct {
69 int pixelFormat;
70
71 uint16_t pitch;
72 uint16_t origPitch;
73
74 uint8_t keyOP;
75 uint16_t HUSF;
76 uint16_t VUSF;
77 uint8_t IntBit;
78 uint8_t wHPre;
79
80 uint16_t srcW;
81 uint16_t srcH;
82
83 BoxRec dstBox;
84
85 uint32_t PSY;
86 uint32_t PSV;
87 uint32_t PSU;
88 uint8_t bobEnable;
89
90 uint8_t contrastCtrl;
91 uint8_t contrastFactor;
92
93 uint8_t lineBufSize;
94
95 uint8_t(*VBlankActiveFunc) ();
96
97 uint16_t SCREENheight;
98
99 } SISOverlayRec, *SISOverlayPtr;
100
101
102 /** static variable definitions **/
103 static int sis_probed = 0;
104 static pciinfo_t pci_info;
105 unsigned int sis_verbose = 0;
106
107 static void *sis_mem_base;
108 /* static void *sis_reg_base; */
109 unsigned short sis_iobase;
110
111 unsigned int sis_vga_engine = UNKNOWN_VGA;
112 static unsigned int sis_displaymode = DISPMODE_SINGLE1;
113 static unsigned int sis_has_two_overlays = 0;
114 static unsigned int sis_bridge_is_slave = 0;
115 static unsigned int sis_shift_value = 1;
116 static unsigned int sis_vmode = 0;
117 unsigned int sis_vbflags = DISPTYPE_DISP1;
118 unsigned int sis_overlay_on_crt1 = 1;
119 unsigned int sis_crt1_off = -1;
120 unsigned int sis_detected_crt2_devices;
121 unsigned int sis_force_crt2_type = CRT2_DEFAULT;
122 unsigned int sis_device_id = -1;
123
124 static int sis_format;
125 static int sis_Yoff = 0;
126 static int sis_Voff = 0;
127 static int sis_Uoff = 0;
128 static int sis_screen_width = 640;
129 static int sis_screen_height = 480;
130
131 static int sis_frames[VID_PLAY_MAXFRAMES];
132
133 static vidix_grkey_t sis_grkey;
134
135 static vidix_capability_t sis_cap = {
136 "SiS 300/310/325 Video Driver",
137 "Jake Page",
138 TYPE_OUTPUT,
139 {0, 0, 0, 0},
140 2048,
141 2048,
142 4,
143 4,
144 -1,
145 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER,
146 VENDOR_SIS,
147 -1,
148 {0, 0, 0, 0}
149 };
150
151 vidix_video_eq_t sis_equal = {
152 VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST,
153 200, 0, 0, 0, 0, 0, 0, 0
154 };
155
156 static unsigned short sis_card_ids[] = {
157 DEVICE_SIS_300,
158 DEVICE_SIS_315H,
159 DEVICE_SIS_315,
160 DEVICE_SIS_315PRO,
161 DEVICE_SIS_330,
162 DEVICE_SIS_540_VGA,
163 DEVICE_SIS_550_VGA,
164 DEVICE_SIS_630_VGA,
165 DEVICE_SIS_650_VGA
166 };
167
168 /** function declarations **/
169
170 extern void sis_init_video_bridge(void);
171
172
173 static void set_overlay(SISOverlayPtr pOverlay, int index);
174 static void close_overlay(void);
175 static void calc_scale_factor(SISOverlayPtr pOverlay,
176 int index, int iscrt2);
177 static void set_line_buf_size(SISOverlayPtr pOverlay);
178 static void merge_line_buf(int enable);
179 static void set_format(SISOverlayPtr pOverlay);
180 static void set_colorkey(void);
181
182 static void set_brightness(uint8_t brightness);
183 static void set_contrast(uint8_t contrast);
184 static void set_saturation(char saturation);
185 static void set_hue(uint8_t hue);
186 #if 0
187 static void set_alpha(uint8_t alpha);
188 #endif
189
190 /* IO Port access functions */
191 static uint8_t getvideoreg(uint8_t reg)
192 {
193 uint8_t ret;
194 inSISIDXREG(SISVID, reg, ret);
195 return (ret);
196 }
197
198 static void setvideoreg(uint8_t reg, uint8_t data)
199 {
200 outSISIDXREG(SISVID, reg, data);
201 }
202
203 static void setvideoregmask(uint8_t reg, uint8_t data, uint8_t mask)
204 {
205 uint8_t old;
206
207 inSISIDXREG(SISVID, reg, old);
208 data = (data & mask) | (old & (~mask));
209 outSISIDXREG(SISVID, reg, data);
210 }
211
212 static void setsrregmask(uint8_t reg, uint8_t data, uint8_t mask)
213 {
214 uint8_t old;
215
216 inSISIDXREG(SISSR, reg, old);
217 data = (data & mask) | (old & (~mask));
218 outSISIDXREG(SISSR, reg, data);
219 }
220
221 /* vblank checking*/
222 static uint8_t vblank_active_CRT1(void)
223 {
224 /* this may be too simplistic? */
225 return (inSISREG(SISINPSTAT) & 0x08);
226 }
227
228 static uint8_t vblank_active_CRT2(void)
229 {
230 uint8_t ret;
231 if (sis_vga_engine == SIS_315_VGA) {
232 inSISIDXREG(SISPART1, Index_310_CRT2_FC_VR, ret);
233 } else {
234 inSISIDXREG(SISPART1, Index_CRT2_FC_VR, ret);
235 }
236 return ((ret & 0x02) ^ 0x02);
237 }
238
239
240 unsigned int vixGetVersion(void)
241 {
242 return (VIDIX_VERSION);
243 }
244
245 static int find_chip(unsigned chip_id)
246 {
247 unsigned i;
248 for (i = 0; i < sizeof(sis_card_ids) / sizeof(unsigned short); i++) {
249 if (chip_id == sis_card_ids[i])
250 return i;
251 }
252 return -1;
253 }
254
255 int vixProbe(int verbose, int force)
256 {
257 pciinfo_t lst[MAX_PCI_DEVICES];
258 unsigned i, num_pci;
259 int err;
260
261 sis_verbose = verbose;
262 force = force;
263 err = pci_scan(lst, &num_pci);
264 if (err) {
265 printf("[SiS] Error occurred during pci scan: %s\n", strerror(err));
266 return err;
267 } else {
268 err = ENXIO;
269 for (i = 0; i < num_pci; i++) {
270 if (lst[i].vendor == VENDOR_SIS) {
271 int idx;
272 const char *dname;
273 idx = find_chip(lst[i].device);
274 if (idx == -1)
275 continue;
276 dname = pci_device_name(VENDOR_SIS, lst[i].device);
277 dname = dname ? dname : "Unknown chip";
278 if (sis_verbose > 0)
279 printf("[SiS] Found chip: %s (0x%X)\n",
280 dname, lst[i].device);
281 sis_device_id = sis_cap.device_id = lst[i].device;
282 err = 0;
283 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));
284
285 sis_has_two_overlays = 0;
286 switch (sis_cap.device_id) {
287 case DEVICE_SIS_300:
288 case DEVICE_SIS_630_VGA:
289 sis_has_two_overlays = 1;
290 case DEVICE_SIS_540_VGA:
291 sis_vga_engine = SIS_300_VGA;
292 break;
293 case DEVICE_SIS_330:
294 case DEVICE_SIS_550_VGA:
295 sis_has_two_overlays = 1;
296 case DEVICE_SIS_315H:
297 case DEVICE_SIS_315:
298 case DEVICE_SIS_315PRO:
299 case DEVICE_SIS_650_VGA:
300 /* M650 & 651 have 2 overlays */
301 /* JCP: I think this works, but not really tested yet */
302 {
303 unsigned char CR5F;
304 unsigned char tempreg1, tempreg2;
305
306 inSISIDXREG(SISCR, 0x5F, CR5F);
307 CR5F &= 0xf0;
308 andSISIDXREG(SISCR, 0x5c, 0x07);
309 inSISIDXREG(SISCR, 0x5c, tempreg1);
310 tempreg1 &= 0xf8;
311 setSISIDXREG(SISCR, 0x5c, 0x07, 0xf8);
312 inSISIDXREG(SISCR, 0x5c, tempreg2);
313 tempreg2 &= 0xf8;
314 if ((!tempreg1) || (tempreg2)) {
315 if (CR5F & 0x80) {
316 sis_has_two_overlays = 1;
317 }
318 } else {
319 sis_has_two_overlays = 1; /* ? */
320 }
321 if (sis_has_two_overlays) {
322 if (sis_verbose > 0)
323 printf
324 ("[SiS] detected M650/651 with 2 overlays\n");
325 }
326 }
327 sis_vga_engine = SIS_315_VGA;
328 break;
329 default:
330 /* should never get here */
331 sis_vga_engine = UNKNOWN_VGA;
332 break;
333 }
334 }
335 }
336 }
337 if (err && sis_verbose) {
338 printf("[SiS] Can't find chip\n");
339 } else {
340 sis_probed = 1;
341 }
342
343 return err;
344 }
345
346 int vixInit(void)
347 {
348 uint8_t sr_data, cr_data, cr_data2;
349 char *env_overlay_crt;
350
351 if (!sis_probed) {
352 printf("[SiS] driver was not probed but is being initialized\n");
353 return (EINTR);
354 }
355
356 /* JCP: this is WRONG. Need to coordinate w/ sisfb to use correct mem */
357 /* map 16MB scary hack for now. */
358 sis_mem_base = map_phys_mem(pci_info.base0, 0x1000000);
359 /* sis_reg_base = map_phys_mem(pci_info.base1, 0x20000); */
360 sis_iobase = pci_info.base2 & 0xFFFC;
361
362 /* would like to use fb ioctl - or some other method - here to get
363 current resolution. */
364 inSISIDXREG(SISCR, 0x12, cr_data);
365 inSISIDXREG(SISCR, 0x07, cr_data2);
366 sis_screen_height =
367 ((cr_data & 0xff) | ((uint16_t) (cr_data2 & 0x02) << 7) |
368 ((uint16_t) (cr_data2 & 0x40) << 3) | ((uint16_t) (cr_data & 0x02)
369 << 9)) + 1;
370
371 inSISIDXREG(SISSR, 0x0b, sr_data);
372 inSISIDXREG(SISCR, 0x01, cr_data);
373 sis_screen_width = (((cr_data & 0xff) |
374 ((uint16_t) (sr_data & 0x0C) << 6)) + 1) * 8;
375
376 inSISIDXREG(SISSR, Index_SR_Graphic_Mode, sr_data);
377 if (sr_data & 0x20) /* interlaced mode */
378 sis_vmode |= VMODE_INTERLACED;
379
380 #if 0 /* getting back false data here... */
381 /* CR9 bit 7 set = double scan active */
382 inSISIDXREG(SISCR, 0x09, cr_data);
383 if (cr_data & 0x40) {
384 sis_vmode |= VMODE_DOUBLESCAN;
385 }
386 #endif
387
388 /* JCP: eventually I'd like to replace this with a call to sisfb
389 SISFB_GET_INFO ioctl to get video bridge info. Not for now,
390 since it requires a very new and not widely distributed version. */
391 sis_init_video_bridge();
392
393 env_overlay_crt = getenv("VIDIX_CRT");
394 if (env_overlay_crt) {
395 int crt = atoi(env_overlay_crt);
396 if (crt == 1 || crt == 2) {
397 sis_overlay_on_crt1 = (crt == 1);
398 if (sis_verbose > 0) {
399 printf
400 ("[SiS] override: using overlay on CRT%d from VIDIX_CRT\n",
401 crt);
402 }
403 }
404 }
405
406 return 0;
407 }
408
409 void vixDestroy(void)
410 {
411 /* unmap_phys_mem(sis_reg_base, 0x20000); */
412 /* JCP: see above, hence also a hack. */
413 unmap_phys_mem(sis_mem_base, 0x1000000);
414 }
415
416 int vixGetCapability(vidix_capability_t * to)
417 {
418 memcpy(to, &sis_cap, sizeof(vidix_capability_t));
419 return 0;
420 }
421
422 static int is_supported_fourcc(uint32_t fourcc)
423 {
424 switch (fourcc) {
425 case IMGFMT_YV12:
426 case IMGFMT_I420:
427 case IMGFMT_UYVY:
428 case IMGFMT_YUY2:
429 case IMGFMT_RGB15:
430 case IMGFMT_RGB16:
431 return 1;
432 default:
433 return 0;
434 }
435 }
436
437 int vixQueryFourcc(vidix_fourcc_t * to)
438 {
439 if (is_supported_fourcc(to->fourcc)) {
440 to->depth = VID_DEPTH_8BPP | VID_DEPTH_16BPP | VID_DEPTH_32BPP;
441 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
442 return 0;
443 } else
444 to->depth = to->flags = 0;
445 return ENOSYS;
446 }
447
448 static int bridge_in_slave_mode(void)
449 {
450 unsigned char usScratchP1_00;
451
452 if (!(sis_vbflags & VB_VIDEOBRIDGE))
453 return 0;
454
455 inSISIDXREG(SISPART1, 0x00, usScratchP1_00);
456 if (((sis_vga_engine == SIS_300_VGA)
457 && (usScratchP1_00 & 0xa0) == 0x20)
458 || ((sis_vga_engine == SIS_315_VGA)
459 && (usScratchP1_00 & 0x50) == 0x10)) {
460 return 1;
461 } else {
462 return 0;
463 }
464 }
465
466 /* This does not handle X dual head mode, since 1) vidix doesn't support it
467 and 2) it doesn't make sense for other gfx drivers */
468 static void set_dispmode(void)
469 {
470 sis_bridge_is_slave = 0;
471
472 if (bridge_in_slave_mode())
473 sis_bridge_is_slave = 1;
474
475 if ((sis_vbflags & VB_DISPMODE_MIRROR) ||
476 (sis_bridge_is_slave && (sis_vbflags & DISPTYPE_DISP2))) {
477 if (sis_has_two_overlays)
478 sis_displaymode = DISPMODE_MIRROR; /* TW: CRT1+CRT2 (2 overlays) */
479 else if (!sis_overlay_on_crt1)
480 sis_displaymode = DISPMODE_SINGLE2;
481 else
482 sis_displaymode = DISPMODE_SINGLE1;
483 } else {
484 if (sis_vbflags & DISPTYPE_DISP1) {
485 sis_displaymode = DISPMODE_SINGLE1; /* TW: CRT1 only */
486 } else {
487 sis_displaymode = DISPMODE_SINGLE2; /* TW: CRT2 only */
488 }
489 }
490 }
491
492 static void set_disptype_regs(void)
493 {
494 switch (sis_displaymode) {
495 case DISPMODE_SINGLE1: /* TW: CRT1 only */
496 if (sis_verbose > 2) {
497 printf("[SiS] Setting up overlay on CRT1\n");
498 }
499 if (sis_has_two_overlays) {
500 setsrregmask(0x06, 0x00, 0xc0);
501 setsrregmask(0x32, 0x00, 0xc0);
502 } else {
503 setsrregmask(0x06, 0x00, 0xc0);
504 setsrregmask(0x32, 0x00, 0xc0);
505 }
506 break;
507 case DISPMODE_SINGLE2: /* TW: CRT2 only */
508 if (sis_verbose > 2) {
509 printf("[SiS] Setting up overlay on CRT2\n");
510 }
511 if (sis_has_two_overlays) {
512 setsrregmask(0x06, 0x80, 0xc0);
513 setsrregmask(0x32, 0x80, 0xc0);
514 } else {
515 setsrregmask(0x06, 0x40, 0xc0);
516 setsrregmask(0x32, 0x40, 0xc0);
517 }
518 break;
519 case DISPMODE_MIRROR: /* TW: CRT1 + CRT2 */
520 default:
521 if (sis_verbose > 2) {
522 printf("[SiS] Setting up overlay on CRT1 AND CRT2!\n");
523 }
524 setsrregmask(0x06, 0x80, 0xc0);
525 setsrregmask(0x32, 0x80, 0xc0);
526 break;
527 }
528 }
529
530 static void init_overlay(void)
531 {
532 /* Initialize first overlay (CRT1) */
533
534 /* Write-enable video registers */
535 setvideoregmask(Index_VI_Control_Misc2, 0x80, 0x81);
536
537 /* Disable overlay */
538 setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
539
540 /* Disable bobEnable */
541 setvideoregmask(Index_VI_Control_Misc1, 0x02, 0x02);
542
543 /* Reset scale control and contrast */
544 setvideoregmask(Index_VI_Scale_Control, 0x60, 0x60);
545 setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x1F);
546
547 setvideoreg(Index_VI_Disp_Y_Buf_Preset_Low, 0x00);
548 setvideoreg(Index_VI_Disp_Y_Buf_Preset_Middle, 0x00);
549 setvideoreg(Index_VI_UV_Buf_Preset_Low, 0x00);
550 setvideoreg(Index_VI_UV_Buf_Preset_Middle, 0x00);
551 setvideoreg(Index_VI_Disp_Y_UV_Buf_Preset_High, 0x00);
552 setvideoreg(Index_VI_Play_Threshold_Low, 0x00);
553 setvideoreg(Index_VI_Play_Threshold_High, 0x00);
554
555 /* may not want to init these here, could already be set to other
556 values by app? */
557 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01);
558 setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x07);
559 setvideoreg(Index_VI_Brightness, 0x20);
560 if (sis_vga_engine == SIS_315_VGA) {
561 setvideoreg(Index_VI_Hue, 0x00);
562 setvideoreg(Index_VI_Saturation, 0x00);
563 }
564
565 /* Initialize second overlay (CRT2) */
566 if (sis_has_two_overlays) {
567 /* Write-enable video registers */
568 setvideoregmask(Index_VI_Control_Misc2, 0x81, 0x81);
569
570 /* Disable overlay */
571 setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
572
573 /* Disable bobEnable */
574 setvideoregmask(Index_VI_Control_Misc1, 0x02, 0x02);
575
576 /* Reset scale control and contrast */
577 setvideoregmask(Index_VI_Scale_Control, 0x60, 0x60);
578 setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x1F);
579
580 setvideoreg(Index_VI_Disp_Y_Buf_Preset_Low, 0x00);
581 setvideoreg(Index_VI_Disp_Y_Buf_Preset_Middle, 0x00);
582 setvideoreg(Index_VI_UV_Buf_Preset_Low, 0x00);
583 setvideoreg(Index_VI_UV_Buf_Preset_Middle, 0x00);
584 setvideoreg(Index_VI_Disp_Y_UV_Buf_Preset_High, 0x00);
585 setvideoreg(Index_VI_Play_Threshold_Low, 0x00);
586 setvideoreg(Index_VI_Play_Threshold_High, 0x00);
587
588 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x01);
589 setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x07);
590 setvideoreg(Index_VI_Brightness, 0x20);
591 if (sis_vga_engine == SIS_315_VGA) {
592 setvideoreg(Index_VI_Hue, 0x00);
593 setvideoreg(Index_VI_Saturation, 0x00);
594 }
595 }
596 }
597
598 int vixConfigPlayback(vidix_playback_t * info)
599 {
600 SISOverlayRec overlay;
601 int srcOffsetX = 0, srcOffsetY = 0;
602 int sx, sy;
603 int index = 0, iscrt2 = 0;
604 int total_size;
605
606 short src_w, drw_w;
607 short src_h, drw_h;
608 short src_x, drw_x;
609 short src_y, drw_y;
610 long dga_offset;
611 int pitch;
612 unsigned int i;
613
614 if (!is_supported_fourcc(info->fourcc))
615 return -1;
616
617 /* set chipset/engine.dependent config info */
618 /* which CRT to use, etc.? */
619 switch (sis_vga_engine) {
620 case SIS_315_VGA:
621 sis_shift_value = 1;
622 sis_equal.cap |= VEQ_CAP_SATURATION | VEQ_CAP_HUE;
623 break;
624 case SIS_300_VGA:
625 default:
626 sis_shift_value = 2;
627 break;
628 }
629
630 sis_displaymode = DISPMODE_SINGLE1; /* xV driver code in set_dispmode() */
631 set_dispmode();
632
633 set_disptype_regs();
634
635 init_overlay();
636
637 /* get basic dimension info */
638 src_x = info->src.x;
639 src_y = info->src.y;
640 src_w = info->src.w;
641 src_h = info->src.h;
642
643 drw_x = info->dest.x;
644 drw_y = info->dest.y;
645 drw_w = info->dest.w;
646 drw_h = info->dest.h;
647
648 switch (info->fourcc) {
649 case IMGFMT_YV12:
650 case IMGFMT_I420:
651 pitch = (src_w + 7) & ~7;
652 total_size = (pitch * src_h * 3) >> 1;
653 break;
654 case IMGFMT_YUY2:
655 case IMGFMT_UYVY:
656 case IMGFMT_RGB15:
657 case IMGFMT_RGB16:
658 pitch = ((src_w << 1) + 3) & ~3;
659 total_size = pitch * src_h;
660 break;
661 default:
662 return -1;
663 }
664
665 /* "allocate" memory for overlay! */
666 /* start at 8MB = sisfb's "dri reserved space" -
667 really shouldn't hardcode though */
668 /* XXX: JCP - this can use the sisfb FBIO_ALLOC ioctl to safely
669 allocate "video heap" memory... */
670 dga_offset = 0x800000;
671
672 /* use 7MB for now. need to calc/get real info from sisfb? */
673 /* this can result in a LOT of frames - probably not necessary */
674 info->num_frames = 0x700000 / (total_size * 2);
675 if (info->num_frames > VID_PLAY_MAXFRAMES)
676 info->num_frames = VID_PLAY_MAXFRAMES;
677
678 info->dga_addr = sis_mem_base + dga_offset;
679 info->dest.pitch.y = 16;
680 info->dest.pitch.u = 16;
681 info->dest.pitch.v = 16;
682 info->offset.y = 0;
683 info->offset.u = 0;
684 info->offset.v = 0;
685 info->frame_size = (total_size * 2); /* why times 2 ? */
686 for (i = 0; i < info->num_frames; i++) {
687 info->offsets[i] = info->frame_size * i;
688 /* save ptrs to mem buffers */
689 sis_frames[i] = (dga_offset + info->offsets[i]);
690 }
691
692 memset(&overlay, 0, sizeof(overlay));
693 overlay.pixelFormat = sis_format = info->fourcc;
694 overlay.pitch = overlay.origPitch = pitch;
695
696
697 overlay.keyOP = (sis_grkey.ckey.op == CKEY_TRUE ?
698 VI_ROP_DestKey : VI_ROP_Always);
699
700 overlay.bobEnable = 0x00;
701
702 overlay.SCREENheight = sis_screen_height;
703
704 /* probably will not support X virtual screen > phys very well? */
705 overlay.dstBox.x1 = drw_x; /* - pScrn->frameX0; */
706 overlay.dstBox.x2 = drw_x + drw_w; /* - pScrn->frameX0; ??? */
707 overlay.dstBox.y1 = drw_y; /* - pScrn->frameY0; */
708 overlay.dstBox.y2 = drw_y + drw_h; /* - pScrn->frameY0; ??? */
709
710 if ((overlay.dstBox.x1 > overlay.dstBox.x2) ||
711 (overlay.dstBox.y1 > overlay.dstBox.y2))
712 return -1;
713
714 if ((overlay.dstBox.x2 < 0) || (overlay.dstBox.y2 < 0))
715 return -1;
716
717 if (overlay.dstBox.x1 < 0) {
718 srcOffsetX = src_w * (-overlay.dstBox.x1) / drw_w;
719 overlay.dstBox.x1 = 0;
720 }
721 if (overlay.dstBox.y1 < 0) {
722 srcOffsetY = src_h * (-overlay.dstBox.y1) / drw_h;
723 overlay.dstBox.y1 = 0;
724 }
725
726 switch (info->fourcc) {
727 case IMGFMT_YV12:
728 info->dest.pitch.y = 16;
729 sx = (src_x + srcOffsetX) & ~7;
730 sy = (src_y + srcOffsetY) & ~1;
731 info->offset.y = sis_Yoff = sx + sy * pitch;
732 /* JCP: NOTE reversed u & v here! Not sure why this is needed.
733 maybe mplayer & sis define U & V differently?? */
734 info->offset.u = sis_Voff =
735 src_h * pitch + ((sx + sy * pitch / 2) >> 1);
736 info->offset.v = sis_Uoff =
737 src_h * pitch * 5 / 4 + ((sx + sy * pitch / 2) >> 1);
738
739 overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value;
740 overlay.PSV = (sis_frames[0] + sis_Voff) >> sis_shift_value;
741 overlay.PSU = (sis_frames[0] + sis_Uoff) >> sis_shift_value;
742 break;
743 case IMGFMT_I420:
744 sx = (src_x + srcOffsetX) & ~7;
745 sy = (src_y + srcOffsetY) & ~1;
746 info->offset.y = sis_Yoff = sx + sy * pitch;
747 /* JCP: see above... */
748 info->offset.u = sis_Voff =
749 src_h * pitch * 5 / 4 + ((sx + sy * pitch / 2) >> 1);
750 info->offset.v = sis_Uoff =
751 src_h * pitch + ((sx + sy * pitch / 2) >> 1);
752
753 overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value;
754 overlay.PSV = (sis_frames[0] + sis_Voff) >> sis_shift_value;
755 overlay.PSU = (sis_frames[0] + sis_Uoff) >> sis_shift_value;
756 break;
757 case IMGFMT_YUY2:
758 case IMGFMT_UYVY:
759 case IMGFMT_RGB16:
760 case IMGFMT_RGB15:
761 default:
762 sx = (src_x + srcOffsetX) & ~1;
763 sy = (src_y + srcOffsetY);
764 info->offset.y = sis_Yoff = sx * 2 + sy * pitch;
765
766 overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value;
767 break;
768 }
769
770 /* FIXME: is it possible that srcW < 0? */
771 overlay.srcW = src_w - (sx - src_x);
772 overlay.srcH = src_h - (sy - src_y);
773
774 /* JCP: what to do about this? */
775 #if 0
776 if ((pPriv->oldx1 != overlay.dstBox.x1) ||
777 (pPriv->oldx2 != overlay.dstBox.x2) ||
778 (pPriv->oldy1 != overlay.dstBox.y1) ||
779 (pPriv->oldy2 != overlay.dstBox.y2)) {
780 pPriv->mustwait = 1;
781 pPriv->oldx1 = overlay.dstBox.x1;
782 pPriv->oldx2 = overlay.dstBox.x2;
783 pPriv->oldy1 = overlay.dstBox.y1;
784 pPriv->oldy2 = overlay.dstBox.y2;
785 }
786 #endif
787
788 /* set merge line buffer */
789 merge_line_buf(overlay.srcW > 384);
790
791 /* calculate line buffer length */
792 set_line_buf_size(&overlay);
793
794 if (sis_displaymode == DISPMODE_SINGLE2) {
795 if (sis_has_two_overlays) {
796 /* TW: On chips with two overlays we use
797 * overlay 2 for CRT2 */
798 index = 1;
799 iscrt2 = 1;
800 } else {
801 /* TW: On chips with only one overlay we
802 * use that only overlay for CRT2 */
803 index = 0;
804 iscrt2 = 1;
805 }
806 overlay.VBlankActiveFunc = vblank_active_CRT2;
807 /* overlay.GetScanLineFunc = get_scanline_CRT2; */
808 } else {
809 index = 0;
810 iscrt2 = 0;
811 overlay.VBlankActiveFunc = vblank_active_CRT1;
812 /* overlay.GetScanLineFunc = get_scanline_CRT1; */
813 }
814
815 /* calc scale factor (to use below) */
816 calc_scale_factor(&overlay, index, iscrt2);
817
818 /* Select video1 (used for CRT1) or video2 (used for CRT2) */
819 setvideoregmask(Index_VI_Control_Misc2, index, 0x01);
820
821 set_format(&overlay);
822
823 set_colorkey();
824
825 vixPlaybackSetEq(&sis_equal);
826
827 /* set up video overlay registers */
828 set_overlay(&overlay, index);
829
830 /* prevent badness if bits are not at default setting */
831 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x01);
832 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x04);
833
834 /* JCP: Xv driver implementation loops back over above code to
835 setup mirror CRT2 */
836
837 return 0;
838 }
839
840 int vixPlaybackOn(void)
841 {
842 setvideoregmask(Index_VI_Control_Misc0, 0x02, 0x02);
843 return 0;
844 }
845
846 int vixPlaybackOff(void)
847 {
848 unsigned char sridx, cridx;
849 sridx = inSISREG(SISSR);
850 cridx = inSISREG(SISCR);
851 close_overlay();
852 outSISREG(SISSR, sridx);
853 outSISREG(SISCR, cridx);
854
855 return 0;
856 }
857
858 int vixPlaybackFrameSelect(unsigned int frame)
859 {
860 uint8_t data;
861 int index = 0;
862 uint32_t PSY;
863
864 if (sis_displaymode == DISPMODE_SINGLE2 && sis_has_two_overlays) {
865 index = 1;
866 }
867
868 PSY = (sis_frames[frame] + sis_Yoff) >> sis_shift_value;
869
870 /* Unlock address registers */
871 data = getvideoreg(Index_VI_Control_Misc1);
872 setvideoreg(Index_VI_Control_Misc1, data | 0x20);
873 /* TEST: Is this required? */
874 setvideoreg(Index_VI_Control_Misc1, data | 0x20);
875 /* TEST end */
876 /* TEST: Is this required? */
877 if (sis_vga_engine == SIS_315_VGA)
878 setvideoreg(Index_VI_Control_Misc3, 0x00);
879 /* TEST end */
880
881 /* set Y start address */
882 setvideoreg(Index_VI_Disp_Y_Buf_Start_Low, (uint8_t) (PSY));
883 setvideoreg(Index_VI_Disp_Y_Buf_Start_Middle, (uint8_t) ((PSY) >> 8));
884 setvideoreg(Index_VI_Disp_Y_Buf_Start_High, (uint8_t) ((PSY) >> 16));
885 /* set 310/325 series overflow bits for Y plane */
886 if (sis_vga_engine == SIS_315_VGA) {
887 setvideoreg(Index_VI_Y_Buf_Start_Over,
888 ((uint8_t) ((PSY) >> 24) & 0x01));
889 }
890
891 /* Set U/V data if using plane formats */
892 if ((sis_format == IMGFMT_YV12) || (sis_format == IMGFMT_I420)) {
893
894 uint32_t PSU, PSV;
895
896 PSU = (sis_frames[frame] + sis_Uoff) >> sis_shift_value;
897 PSV = (sis_frames[frame] + sis_Voff) >> sis_shift_value;
898
899 /* set U/V start address */
900 setvideoreg(Index_VI_U_Buf_Start_Low, (uint8_t) PSU);
901 setvideoreg(Index_VI_U_Buf_Start_Middle, (uint8_t) (PSU >> 8));
902 setvideoreg(Index_VI_U_Buf_Start_High, (uint8_t) (PSU >> 16));
903
904 setvideoreg(Index_VI_V_Buf_Start_Low, (uint8_t) PSV);
905 setvideoreg(Index_VI_V_Buf_Start_Middle, (uint8_t) (PSV >> 8));
906 setvideoreg(Index_VI_V_Buf_Start_High, (uint8_t) (PSV >> 16));
907
908 /* 310/325 series overflow bits */
909 if (sis_vga_engine == SIS_315_VGA) {
910 setvideoreg(Index_VI_U_Buf_Start_Over,
911 ((uint8_t) (PSU >> 24) & 0x01));
912 setvideoreg(Index_VI_V_Buf_Start_Over,
913 ((uint8_t) (PSV >> 24) & 0x01));
914 }
915 }
916
917 if (sis_vga_engine == SIS_315_VGA) {
918 /* Trigger register copy for 310 series */
919 setvideoreg(Index_VI_Control_Misc3, 1 << index);
920 }
921
922 /* Lock the address registers */
923 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x20);
924
925 return 0;
926 }
927
928 int vixGetGrKeys(vidix_grkey_t * grkey)
929 {
930 memcpy(grkey, &sis_grkey, sizeof(vidix_grkey_t));
931 return 0;
932 }
933
934 int vixSetGrKeys(const vidix_grkey_t * grkey)
935 {
936 memcpy(&sis_grkey, grkey, sizeof(vidix_grkey_t));
937 set_colorkey();
938 return 0;
939 }
940
941 int vixPlaybackGetEq(vidix_video_eq_t * eq)
942 {
943 memcpy(eq, &sis_equal, sizeof(vidix_video_eq_t));
944 return 0;
945 }
946
947 int vixPlaybackSetEq(const vidix_video_eq_t * eq)
948 {
949 int br, sat, cr, hue;
950 if (eq->cap & VEQ_CAP_BRIGHTNESS)
951 sis_equal.brightness = eq->brightness;
952 if (eq->cap & VEQ_CAP_CONTRAST)
953 sis_equal.contrast = eq->contrast;
954 if (eq->cap & VEQ_CAP_SATURATION)
955 sis_equal.saturation = eq->saturation;
956 if (eq->cap & VEQ_CAP_HUE)
957 sis_equal.hue = eq->hue;
958 if (eq->cap & VEQ_CAP_RGB_INTENSITY) {
959 sis_equal.red_intensity = eq->red_intensity;
960 sis_equal.green_intensity = eq->green_intensity;
961 sis_equal.blue_intensity = eq->blue_intensity;
962 }
963 sis_equal.flags = eq->flags;
964
965 cr = (sis_equal.contrast + 1000) * 7 / 2000;
966 if (cr < 0)
967 cr = 0;
968 if (cr > 7)
969 cr = 7;
970
971 br = sis_equal.brightness * 127 / 1000;
972 if (br < -128)
973 br = -128;
974 if (br > 127)
975 br = 127;
976
977 sat = (sis_equal.saturation * 7) / 1000;
978 if (sat < -7)
979 sat = -7;
980 if (sat > 7)
981 sat = 7;
982
983 hue = sis_equal.hue * 7 / 1000;
984 if (hue < -8)
985 hue = -8;
986 if (hue > 7)
987 hue = 7;
988
989 set_brightness(br);
990 set_contrast(cr);
991 if (sis_vga_engine == SIS_315_VGA) {
992 set_saturation(sat);
993 set_hue(hue);
994 }
995
996 return 0;
997 }
998
999 static void set_overlay(SISOverlayPtr pOverlay, int index)
1000 {
1001 uint16_t pitch = 0;
1002 uint8_t h_over = 0, v_over = 0;
1003 uint16_t top, bottom, left, right;
1004 uint16_t screenX = sis_screen_width;
1005 uint16_t screenY = sis_screen_height;
1006 uint8_t data;
1007 uint32_t watchdog;
1008
1009 top = pOverlay->dstBox.y1;
1010 bottom = pOverlay->dstBox.y2;
1011 if (bottom > screenY) {
1012 bottom = screenY;
1013 }
1014
1015 left = pOverlay->dstBox.x1;
1016 right = pOverlay->dstBox.x2;
1017 if (right > screenX) {
1018 right = screenX;
1019 }
1020
1021 /* JCP: these aren't really tested... */
1022 /* TW: DoubleScan modes require Y coordinates * 2 */
1023 if (sis_vmode & VMODE_DOUBLESCAN) {
1024 top <<= 1;
1025 bottom <<= 1;
1026 }
1027 /* TW: Interlace modes require Y coordinates / 2 */
1028 if (sis_vmode & VMODE_INTERLACED) {
1029 top >>= 1;
1030 bottom >>= 1;
1031 }
1032
1033 h_over = (((left >> 8) & 0x0f) | ((right >> 4) & 0xf0));
1034 v_over = (((top >> 8) & 0x0f) | ((bottom >> 4) & 0xf0));
1035
1036 pitch = pOverlay->pitch >> sis_shift_value;
1037
1038 /* set line buffer size */
1039 setvideoreg(Index_VI_Line_Buffer_Size, pOverlay->lineBufSize);
1040
1041 /* set color key mode */
1042 setvideoregmask(Index_VI_Key_Overlay_OP, pOverlay->keyOP, 0x0F);
1043
1044 /* TW: We don't have to wait for vertical retrace in all cases */
1045 /* JCP: be safe for now. */
1046 if (1 /*pPriv->mustwait */ ) {
1047 watchdog = WATCHDOG_DELAY;
1048 while (pOverlay->VBlankActiveFunc() && --watchdog);
1049 watchdog = WATCHDOG_DELAY;
1050 while ((!pOverlay->VBlankActiveFunc()) && --watchdog);
1051 if (!watchdog && sis_verbose > 0) {
1052 printf("[SiS]: timed out waiting for vertical retrace\n");
1053 }
1054 }
1055
1056 /* Unlock address registers */
1057 data = getvideoreg(Index_VI_Control_Misc1);
1058 setvideoreg(Index_VI_Control_Misc1, data | 0x20);
1059 /* TEST: Is this required? */
1060 setvideoreg(Index_VI_Control_Misc1, data | 0x20);
1061 /* TEST end */
1062
1063 /* TEST: Is this required? */
1064 if (sis_vga_engine == SIS_315_VGA)
1065 setvideoreg(Index_VI_Control_Misc3, 0x00);
1066 /* TEST end */
1067
1068 /* Set Y buf pitch */
1069 setvideoreg(Index_VI_Disp_Y_Buf_Pitch_Low, (uint8_t) (pitch));
1070 setvideoregmask(Index_VI_Disp_Y_UV_Buf_Pitch_Middle,
1071 (uint8_t) (pitch >> 8), 0x0f);
1072
1073 /* Set Y start address */
1074 setvideoreg(Index_VI_Disp_Y_Buf_Start_Low, (uint8_t) (pOverlay->PSY));
1075 setvideoreg(Index_VI_Disp_Y_Buf_Start_Middle,
1076 (uint8_t) ((pOverlay->PSY) >> 8));
1077 setvideoreg(Index_VI_Disp_Y_Buf_Start_High,
1078 (uint8_t) ((pOverlay->PSY) >> 16));
1079
1080 /* set 310/325 series overflow bits for Y plane */
1081 if (sis_vga_engine == SIS_315_VGA) {
1082 setvideoreg(Index_VI_Disp_Y_Buf_Pitch_High,
1083 (uint8_t) (pitch >> 12));
1084 setvideoreg(Index_VI_Y_Buf_Start_Over,
1085 ((uint8_t) ((pOverlay->PSY) >> 24) & 0x01));
1086 }
1087
1088 /* Set U/V data if using plane formats */
1089 if ((pOverlay->pixelFormat == IMGFMT_YV12) ||
1090 (pOverlay->pixelFormat == IMGFMT_I420)) {
1091
1092 uint32_t PSU, PSV;
1093
1094 PSU = pOverlay->PSU;
1095 PSV = pOverlay->PSV;
1096
1097 /* Set U/V pitch */
1098 setvideoreg(Index_VI_Disp_UV_Buf_Pitch_Low,
1099 (uint8_t) (pitch >> 1));
1100 setvideoregmask(Index_VI_Disp_Y_UV_Buf_Pitch_Middle,
1101 (uint8_t) (pitch >> 5), 0xf0);
1102
1103 /* set U/V start address */
1104 setvideoreg(Index_VI_U_Buf_Start_Low, (uint8_t) PSU);
1105 setvideoreg(Index_VI_U_Buf_Start_Middle, (uint8_t) (PSU >> 8));
1106 setvideoreg(Index_VI_U_Buf_Start_High, (uint8_t) (PSU >> 16));
1107
1108 setvideoreg(Index_VI_V_Buf_Start_Low, (uint8_t) PSV);
1109 setvideoreg(Index_VI_V_Buf_Start_Middle, (uint8_t) (PSV >> 8));
1110 setvideoreg(Index_VI_V_Buf_Start_High, (uint8_t) (PSV >> 16));
1111
1112 /* 310/325 series overflow bits */
1113 if (sis_vga_engine == SIS_315_VGA) {
1114 setvideoreg(Index_VI_Disp_UV_Buf_Pitch_High,
1115 (uint8_t) (pitch >> 13));
1116 setvideoreg(Index_VI_U_Buf_Start_Over,
1117 ((uint8_t) (PSU >> 24) & 0x01));
1118 setvideoreg(Index_VI_V_Buf_Start_Over,
1119 ((uint8_t) (PSV >> 24) & 0x01));
1120 }
1121 }
1122
1123 if (sis_vga_engine == SIS_315_VGA) {
1124 /* Trigger register copy for 310 series */
1125 setvideoreg(Index_VI_Control_Misc3, 1 << index);
1126 }
1127
1128 /* set scale factor */
1129 setvideoreg(Index_VI_Hor_Post_Up_Scale_Low,
1130 (uint8_t) (pOverlay->HUSF));
1131 setvideoreg(Index_VI_Hor_Post_Up_Scale_High,
1132 (uint8_t) ((pOverlay->HUSF) >> 8));
1133 setvideoreg(Index_VI_Ver_Up_Scale_Low, (uint8_t) (pOverlay->VUSF));
1134 setvideoreg(Index_VI_Ver_Up_Scale_High,
1135 (uint8_t) ((pOverlay->VUSF) >> 8));
1136
1137 setvideoregmask(Index_VI_Scale_Control, (pOverlay->IntBit << 3)
1138 | (pOverlay->wHPre), 0x7f);
1139
1140 /* set destination window position */
1141 setvideoreg(Index_VI_Win_Hor_Disp_Start_Low, (uint8_t) left);
1142 setvideoreg(Index_VI_Win_Hor_Disp_End_Low, (uint8_t) right);
1143 setvideoreg(Index_VI_Win_Hor_Over, (uint8_t) h_over);
1144
1145 setvideoreg(Index_VI_Win_Ver_Disp_Start_Low, (uint8_t) top);
1146 setvideoreg(Index_VI_Win_Ver_Disp_End_Low, (uint8_t) bottom);
1147 setvideoreg(Index_VI_Win_Ver_Over, (uint8_t) v_over);
1148
1149 setvideoregmask(Index_VI_Control_Misc1, pOverlay->bobEnable, 0x1a);
1150
1151 /* Lock the address registers */
1152 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x20);
1153 }
1154
1155
1156 /* TW: Overlay MUST NOT be switched off while beam is over it */
1157 static void close_overlay(void)
1158 {
1159 uint32_t watchdog;
1160
1161 if ((sis_displaymode == DISPMODE_SINGLE2) ||
1162 (sis_displaymode == DISPMODE_MIRROR)) {
1163 if (sis_has_two_overlays) {
1164 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x01);
1165 watchdog = WATCHDOG_DELAY;
1166 while (vblank_active_CRT2() && --watchdog);
1167 watchdog = WATCHDOG_DELAY;
1168 while ((!vblank_active_CRT2()) && --watchdog);
1169 setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
1170 watchdog = WATCHDOG_DELAY;
1171 while (vblank_active_CRT2() && --watchdog);
1172 watchdog = WATCHDOG_DELAY;
1173 while ((!vblank_active_CRT2()) && --watchdog);
1174 } else if (sis_displaymode == DISPMODE_SINGLE2) {
1175 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01);
1176 watchdog = WATCHDOG_DELAY;
1177 while (vblank_active_CRT1() && --watchdog);
1178 watchdog = WATCHDOG_DELAY;
1179 while ((!vblank_active_CRT1()) && --watchdog);
1180 setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
1181 watchdog = WATCHDOG_DELAY;
1182 while (vblank_active_CRT1() && --watchdog);
1183 watchdog = WATCHDOG_DELAY;
1184 while ((!vblank_active_CRT1()) && --watchdog);
1185 }
1186 }
1187 if ((sis_displaymode == DISPMODE_SINGLE1) ||
1188 (sis_displaymode == DISPMODE_MIRROR)) {
1189 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01);
1190 watchdog = WATCHDOG_DELAY;
1191 while (vblank_active_CRT1() && --watchdog);
1192 watchdog = WATCHDOG_DELAY;
1193 while ((!vblank_active_CRT1()) && --watchdog);
1194 setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
1195 watchdog = WATCHDOG_DELAY;
1196 while (vblank_active_CRT1() && --watchdog);
1197 watchdog = WATCHDOG_DELAY;
1198 while ((!vblank_active_CRT1()) && --watchdog);
1199 }
1200 }
1201
1202
1203 static void
1204 calc_scale_factor(SISOverlayPtr pOverlay, int index, int iscrt2)
1205 {
1206 uint32_t i = 0, mult = 0;
1207 int flag = 0;
1208
1209 int dstW = pOverlay->dstBox.x2 - pOverlay->dstBox.x1;
1210 int dstH = pOverlay->dstBox.y2 - pOverlay->dstBox.y1;
1211 int srcW = pOverlay->srcW;
1212 int srcH = pOverlay->srcH;
1213 /* uint16_t LCDheight = pSiS->LCDheight; */
1214 int srcPitch = pOverlay->origPitch;
1215 int origdstH = dstH;
1216
1217 /* get rid of warnings for now */
1218 index = index;
1219 iscrt2 = iscrt2;
1220
1221 #if 0 /* JCP: don't bother with this for now. */
1222 /* TW: Stretch image due to idiotic LCD "auto"-scaling on LVDS (and 630+301B) */
1223 if (pSiS->VBFlags & CRT2_LCD) {
1224 if (sis_bridge_is_slave) {
1225 if (pSiS->VBFlags & VB_LVDS) {
1226 dstH = (dstH * LCDheight) / pOverlay->SCREENheight;
1227 } else if ((sis_vga_engine == SIS_300_VGA) &&
1228 (pSiS->
1229 VBFlags & (VB_301B | VB_302B | VB_301LV |
1230 VB_302LV))) {
1231 dstH = (dstH * LCDheight) / pOverlay->SCREENheight;
1232 }
1233 } else if (iscrt2) {
1234 if (pSiS->VBFlags & VB_LVDS) {
1235 dstH = (dstH * LCDheight) / pOverlay->SCREENheight;
1236 if (sis_displaymode == DISPMODE_MIRROR)
1237 flag = 1;
1238 } else if ((sis_vga_engine == SIS_300_VGA) &&
1239 (pSiS->
1240 VBFlags & (VB_301B | VB_302B | VB_301LV |
1241 VB_302LV))) {
1242 dstH = (dstH * LCDheight) / pOverlay->SCREENheight;
1243 if (sis_displaymode == DISPMODE_MIRROR)
1244 flag = 1;
1245 }
1246 }
1247 }
1248 #endif
1249
1250 /* TW: For double scan modes, we need to double the height
1251 * (Perhaps we also need to scale LVDS, but I'm not sure.)
1252 * On 310/325 series, we need to double the width as well.
1253 * Interlace mode vice versa.
1254 */
1255 if (sis_vmode & VMODE_DOUBLESCAN) {
1256 dstH = origdstH << 1;
1257 flag = 0;
1258 if (sis_vga_engine == SIS_315_VGA) {
1259 dstW <<= 1;
1260 }
1261 }
1262 if (sis_vmode & VMODE_INTERLACED) {
1263 dstH = origdstH >> 1;
1264 flag = 0;
1265 }
1266
1267 if (dstW < OVERLAY_MIN_WIDTH)
1268 dstW = OVERLAY_MIN_WIDTH;
1269 if (dstW == srcW) {
1270 pOverlay->HUSF = 0x00;
1271 pOverlay->IntBit = 0x05;
1272 pOverlay->wHPre = 0;
1273 } else if (dstW > srcW) {
1274 dstW += 2;
1275 pOverlay->HUSF = (srcW << 16) / dstW;
1276 pOverlay->IntBit = 0x04;
1277 pOverlay->wHPre = 0;
1278 } else {
1279 int tmpW = dstW;
1280
1281 /* TW: It seems, the hardware can't scale below factor .125 (=1/8) if the
1282 pitch isn't a multiple of 256.
1283 TODO: Test this on the 310/325 series!
1284 */
1285 if ((srcPitch % 256) || (srcPitch < 256)) {
1286 if (((dstW * 1000) / srcW) < 125)
1287 dstW = tmpW = ((srcW * 125) / 1000) + 1;
1288 }
1289
1290 i = 0;
1291 pOverlay->IntBit = 0x01;
1292 while (srcW >= tmpW) {
1293 tmpW <<= 1;
1294 i++;
1295 }
1296 pOverlay->wHPre = (uint8_t) (i - 1);
1297 dstW <<= (i - 1);
1298 if ((srcW % dstW))
1299 pOverlay->HUSF = ((srcW - dstW) << 16) / dstW;
1300 else
1301 pOverlay->HUSF = 0x00;
1302 }
1303
1304 if (dstH < OVERLAY_MIN_HEIGHT)
1305 dstH = OVERLAY_MIN_HEIGHT;
1306 if (dstH == srcH) {
1307 pOverlay->VUSF = 0x00;
1308 pOverlay->IntBit |= 0x0A;
1309 } else if (dstH > srcH) {
1310 dstH += 0x02;
1311 pOverlay->VUSF = (srcH << 16) / dstH;
1312 pOverlay->IntBit |= 0x08;
1313 } else {
1314 uint32_t realI;
1315
1316 i = realI = srcH / dstH;
1317 pOverlay->IntBit |= 0x02;
1318
1319 if (i < 2) {
1320 pOverlay->VUSF = ((srcH - dstH) << 16) / dstH;
1321 /* TW: Needed for LCD-scaling modes */
1322 if ((flag) && (mult = (srcH / origdstH)) >= 2)
1323 pOverlay->pitch /= mult;
1324 } else {
1325 #if 0
1326 if (((pOverlay->bobEnable & 0x08) == 0x00) &&
1327 (((srcPitch * i) >> 2) > 0xFFF)) {
1328 pOverlay->bobEnable |= 0x08;
1329 srcPitch >>= 1;
1330 }
1331 #endif
1332 if (((srcPitch * i) >> 2) > 0xFFF) {
1333 i = (0xFFF * 2 / srcPitch);
1334 pOverlay->VUSF = 0xFFFF;
1335 } else {
1336 dstH = i * dstH;
1337 if (srcH % dstH)
1338 pOverlay->VUSF = ((srcH - dstH) << 16) / dstH;
1339 else
1340 pOverlay->VUSF = 0x00;
1341 }
1342 /* set video frame buffer offset */
1343 pOverlay->pitch = (uint16_t) (srcPitch * i);
1344 }
1345 }
1346 }
1347
1348 static void set_line_buf_size(SISOverlayPtr pOverlay)
1349 {
1350 uint8_t preHIDF;
1351 uint32_t i;
1352 uint32_t line = pOverlay->srcW;
1353
1354 if ((pOverlay->pixelFormat == IMGFMT_YV12) ||
1355 (pOverlay->pixelFormat == IMGFMT_I420)) {
1356 preHIDF = pOverlay->wHPre & 0x07;
1357 switch (preHIDF) {
1358 case 3:
1359 if ((line & 0xffffff00) == line)
1360 i = (line >> 8);
1361 else
1362 i = (line >> 8) + 1;
1363 pOverlay->lineBufSize = (uint8_t) (i * 32 - 1);
1364 break;
1365 case 4:
1366 if ((line & 0xfffffe00) == line)
1367 i = (line >> 9);
1368 else
1369 i = (line >> 9) + 1;
1370 pOverlay->lineBufSize = (uint8_t) (i * 64 - 1);
1371 break;
1372 case 5:
1373 if ((line & 0xfffffc00) == line)
1374 i = (line >> 10);
1375 else
1376 i = (line >> 10) + 1;
1377 pOverlay->lineBufSize = (uint8_t) (i * 128 - 1);
1378 break;
1379 case 6:
1380 if ((line & 0xfffff800) == line)
1381 i = (line >> 11);
1382 else
1383 i = (line >> 11) + 1;
1384 pOverlay->lineBufSize = (uint8_t) (i * 256 - 1);
1385 break;
1386 default:
1387 if ((line & 0xffffff80) == line)
1388 i = (line >> 7);
1389 else
1390 i = (line >> 7) + 1;
1391 pOverlay->lineBufSize = (uint8_t) (i * 16 - 1);
1392 break;
1393 }
1394 } else { /* YUV2, UYVY */
1395 if ((line & 0xffffff8) == line)
1396 i = (line >> 3);
1397 else
1398 i = (line >> 3) + 1;
1399 pOverlay->lineBufSize = (uint8_t) (i - 1);
1400 }
1401 }
1402
1403 static void merge_line_buf(int enable)
1404 {
1405 if (enable) {
1406 switch (sis_displaymode) {
1407 case DISPMODE_SINGLE1:
1408 if (sis_has_two_overlays) {
1409 /* dual line merge */
1410 setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11);
1411 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1412 } else {
1413 setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11);
1414 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1415 }
1416 break;
1417 case DISPMODE_SINGLE2:
1418 if (sis_has_two_overlays) {
1419 /* line merge */
1420 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11);
1421 setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04);
1422 } else {
1423 setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11);
1424 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1425 }
1426 break;
1427 case DISPMODE_MIRROR:
1428 default:
1429 /* line merge */
1430 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11);
1431 setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04);
1432 if (sis_has_two_overlays) {
1433 /* line merge */
1434 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11);
1435 setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04);
1436 }
1437 break;
1438 }
1439 } else {
1440 switch (sis_displaymode) {
1441 case DISPMODE_SINGLE1:
1442 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11);
1443 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1444 break;
1445 case DISPMODE_SINGLE2:
1446 if (sis_has_two_overlays) {
1447 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11);
1448 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1449 } else {
1450 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11);
1451 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1452 }
1453 break;
1454 case DISPMODE_MIRROR:
1455 default:
1456 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11);
1457 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1458 if (sis_has_two_overlays) {
1459 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11);
1460 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1461 }
1462 break;
1463 }
1464 }
1465 }
1466
1467
1468 static void set_format(SISOverlayPtr pOverlay)
1469 {
1470 uint8_t fmt;
1471
1472 switch (pOverlay->pixelFormat) {
1473 case IMGFMT_YV12:
1474 case IMGFMT_I420:
1475 fmt = 0x0c;
1476 break;
1477 case IMGFMT_YUY2:
1478 fmt = 0x28;
1479 break;
1480 case IMGFMT_UYVY:
1481 fmt = 0x08;
1482 break;
1483 case IMGFMT_RGB15: /* D[5:4] : 00 RGB555, 01 RGB 565 */
1484 fmt = 0x00;
1485 break;
1486 case IMGFMT_RGB16:
1487 fmt = 0x10;
1488 break;
1489 default:
1490 fmt = 0x00;
1491 break;
1492 }
1493 setvideoregmask(Index_VI_Control_Misc0, fmt, 0x7c);
1494 }
1495
1496 static void set_colorkey(void)
1497 {
1498 uint8_t r, g, b;
1499
1500 b = (uint8_t) sis_grkey.ckey.blue;
1501 g = (uint8_t) sis_grkey.ckey.green;
1502 r = (uint8_t) sis_grkey.ckey.red;
1503
1504 /* set color key mode */
1505 setvideoregmask(Index_VI_Key_Overlay_OP,
1506 sis_grkey.ckey.op == CKEY_TRUE ?
1507 VI_ROP_DestKey : VI_ROP_Always, 0x0F);
1508
1509 /* set colorkey values */
1510 setvideoreg(Index_VI_Overlay_ColorKey_Blue_Min, (uint8_t) b);
1511 setvideoreg(Index_VI_Overlay_ColorKey_Green_Min, (uint8_t) g);
1512 setvideoreg(Index_VI_Overlay_ColorKey_Red_Min, (uint8_t) r);
1513
1514 setvideoreg(Index_VI_Overlay_ColorKey_Blue_Max, (uint8_t) b);
1515 setvideoreg(Index_VI_Overlay_ColorKey_Green_Max, (uint8_t) g);
1516 setvideoreg(Index_VI_Overlay_ColorKey_Red_Max, (uint8_t) r);
1517 }
1518
1519 static void set_brightness(uint8_t brightness)
1520 {
1521 setvideoreg(Index_VI_Brightness, brightness);
1522 }
1523
1524 static void set_contrast(uint8_t contrast)
1525 {
1526 setvideoregmask(Index_VI_Contrast_Enh_Ctrl, contrast, 0x07);
1527 }
1528
1529 /* Next 3 functions are 310/325 series only */
1530
1531 static void set_saturation(char saturation)
1532 {
1533 uint8_t temp = 0;
1534
1535 if (saturation < 0) {
1536 temp |= 0x88;
1537 saturation = -saturation;
1538 }
1539 temp |= (saturation & 0x07);
1540 temp |= ((saturation & 0x07) << 4);
1541
1542 setvideoreg(Index_VI_Saturation, temp);
1543 }
1544
1545 static void set_hue(uint8_t hue)
1546 {
1547 setvideoreg(Index_VI_Hue, (hue & 0x08) ? (hue ^ 0x07) : hue);
1548 }
1549
1550 #if 0
1551 /* JCP: not used (I don't think it's correct anyway) */
1552 static void set_alpha(uint8_t alpha)
1553 {
1554 uint8_t data;
1555
1556 data = getvideoreg(Index_VI_Key_Overlay_OP);
1557 data &= 0x0F;
1558 setvideoreg(Index_VI_Key_Overlay_OP, data | (alpha << 4));
1559 }
1560 #endif