comparison vidix/unichrome_vid.c @ 22850:9a1e26fef45b

Move driver files directly into the vidix directory.
author diego
date Sun, 01 Apr 2007 00:02:43 +0000
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children 77def5093daf
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22849:bddb09395c3e 22850:9a1e26fef45b
1 /*
2 Driver for VIA CLE266 Unichrome - Version 0.1.0
3
4 Copyright (C) 2004 by Timothy Lee
5
6 Based on Cyberblade/i driver by Alastair M. Robison.
7
8 Thanks to Gilles Frattini for bugfixes
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23
24 Changes:
25 2004-03-10
26 Initial version
27 2004-10-09
28 Added Doxygen documentation (Benjamin Zores <ben@geexbox.org>)
29 2004-11-08
30 Added h/w revision detection (Timothy Lee <timothy.lee@siriushk.com>)
31
32 To Do:
33 */
34
35 #include <errno.h>
36 #include <stdio.h>
37 #include <stdlib.h>
38 #include <string.h>
39 #include <inttypes.h>
40 #include <unistd.h>
41
42 #include "vidix.h"
43 #include "fourcc.h"
44 #include "../libdha/libdha.h"
45 #include "../libdha/pci_ids.h"
46 #include "../libdha/pci_names.h"
47 #include "../config.h"
48
49 #include "unichrome_regs.h"
50
51 /**
52 * @brief Information on PCI device.
53 */
54 pciinfo_t pci_info;
55
56 /**
57 * @brief Unichrome driver colorkey settings.
58 */
59 static vidix_grkey_t uc_grkey;
60
61 static int frames[VID_PLAY_MAXFRAMES];
62 uint8_t *vio;
63 uint8_t *uc_mem;
64 uint8_t mclk_save[3];
65 uint8_t hwrev;
66
67 #define VIA_OUT(hwregs, reg, val) *(volatile uint32_t *)((hwregs) + (reg)) = (val)
68 #define VIA_IN(hwregs, reg) *(volatile uint32_t *)((hwregs) + (reg))
69 #define VGA_OUT8(hwregs, reg, val) *(volatile uint8_t *)((hwregs) + (reg) + 0x8000) = (val)
70 #define VGA_IN8(hwregs, reg) *(volatile uint8_t *)((hwregs) + (reg) + 0x8000)
71 #define VIDEO_OUT(hwregs, reg, val) VIA_OUT((hwregs)+0x200, reg, val)
72 #define VIDEO_IN(hwregs, reg) VIA_IN((hwregs)+0x200, reg)
73
74 #define outb(val,reg) OUTPORT8(reg,val)
75 #define inb(reg) INPORT8(reg)
76
77 #define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1))
78 #define UC_MAP_V1_FIFO_CONTROL(depth, pre_thr, thr) \
79 (((depth)-1) | ((thr) << 8) | ((pre_thr) << 24))
80
81 #define VIDEOMEMORY_SIZE (8 * 1024 * 1024)
82 #define FRAMEBUFFER_SIZE 0x200000
83 #define FRAMEBUFFER_START (VIDEOMEMORY_SIZE - FRAMEBUFFER_SIZE)
84
85 #ifdef DEBUG_LOGFILE
86 FILE *logfile = 0;
87 #define LOGWRITE(x) {if(logfile) fprintf(logfile,x);}
88 #else
89 #define LOGWRITE(x)
90 #endif
91
92 /**
93 * @brief Unichrome driver vidix capabilities.
94 */
95 static vidix_capability_t uc_cap = {
96 "VIA CLE266 Unichrome driver",
97 "Timothy Lee <timothy@siriushk.com>",
98 TYPE_OUTPUT,
99 {0, 0, 0, 0},
100 4096,
101 4096,
102 4,
103 4,
104 -1,
105 FLAG_UPSCALER | FLAG_DOWNSCALER,
106 VENDOR_VIA2,
107 -1,
108 {0, 0, 0, 0}
109 };
110
111 /**
112 * @brief list of card IDs compliant with the Unichrome driver .
113 */
114 static unsigned short uc_card_ids[] = {
115 DEVICE_VIA2_VT8623_CLE266_AGP
116 };
117
118 /**
119 * @brief Check age of driver.
120 *
121 * @return vidix version number.
122 */
123 unsigned int
124 vixGetVersion (void)
125 {
126 return (VIDIX_VERSION);
127 }
128
129 /**
130 * @brief Find chip index in Unichrome compliant devices list.
131 *
132 * @param chip_id PCI device ID.
133 *
134 * @returns index position in uc_card_ids if successful.
135 * -1 if chip_id is not a compliant chipset ID.
136 */
137 static int
138 find_chip (unsigned chip_id)
139 {
140 unsigned i;
141 for (i = 0; i < sizeof (uc_card_ids) / sizeof (unsigned short); i++)
142 {
143 if (chip_id == uc_card_ids[i])
144 return i;
145 }
146 return -1;
147 }
148
149 /**
150 * @brief Map hardware settings for vertical scaling.
151 *
152 * @param sh source height.
153 * @param dh destination height.
154 * @param zoom will hold vertical setting of zoom register.
155 * @param mini will hold vertical setting of mini register.
156 *
157 * @returns 1 if successful.
158 * 0 if the zooming factor is too large or small.
159 *
160 * @note Derived from VIA's V4L driver.
161 * See ddover.c, DDOVER_HQVCalcZoomHeight()
162 */
163 static int
164 uc_ovl_map_vzoom (int sh, int dh, uint32_t * zoom, uint32_t * mini)
165 {
166 uint32_t sh1, tmp, d;
167 int zoom_ok = 1;
168
169 if (sh == dh) /* No zoom */
170 {
171 /* Do nothing */
172 }
173 else if (sh < dh) /* Zoom in */
174 {
175 tmp = (sh * 0x0400) / dh;
176 zoom_ok = !(tmp > 0x3ff);
177
178 *zoom |= (tmp & 0x3ff) | V1_Y_ZOOM_ENABLE;
179 *mini |= V1_Y_INTERPOLY | V1_YCBCR_INTERPOLY;
180 }
181 else /* sw > dh - Zoom out */
182 {
183 /* Find a suitable divider (1 << d) = {2, 4, 8 or 16} */
184 sh1 = sh;
185 for (d = 1; d < 5; d++)
186 {
187 sh1 >>= 1;
188 if (sh1 <= dh)
189 break;
190 }
191 if (d == 5) /* too small */
192 {
193 d = 4;
194 zoom_ok = 0;
195 }
196
197 *mini |= ((d << 1) - 1) << 16; /* <= {1,3,5,7} << 16 */
198
199 /* Add scaling */
200 if (sh1 < dh)
201 {
202 tmp = (sh1 * 0x400) / dh;
203 *zoom |= ((tmp & 0x3ff) | V1_Y_ZOOM_ENABLE);
204 *mini |= V1_Y_INTERPOLY | V1_YCBCR_INTERPOLY;
205 }
206 }
207
208 return zoom_ok;
209 }
210
211 /**
212 * @brief Map hardware settings for horizontal scaling.
213 *
214 * @param sw source width.
215 * @param dw destination width.
216 * @param zoom will hold horizontal setting of zoom register.
217 * @param mini will hold horizontal setting of mini register.
218 * @param falign will hold fetch aligment.
219 * @param dcount will hold display count.
220 *
221 * @returns 1 if successful.
222 * 0 if the zooming factor is too large or small.
223 *
224 * @note Derived from VIA's V4L driver.
225 * See ddover.c, DDOVER_HQVCalcZoomWidth() and DDOver_GetDisplayCount()
226 */
227 static int
228 uc_ovl_map_hzoom (int sw, int dw, uint32_t * zoom, uint32_t * mini,
229 int *falign, int *dcount)
230 {
231 uint32_t tmp, sw1, d;
232 int md; /* Minify-divider */
233 int zoom_ok = 1;
234
235 md = 1;
236 *falign = 0;
237
238 if (sw == dw) /* no zoom */
239 {
240 /* Do nothing */
241 }
242 else if (sw < dw) /* zoom in */
243 {
244 tmp = (sw * 0x0800) / dw;
245 zoom_ok = !(tmp > 0x7ff);
246
247 *zoom |= ((tmp & 0x7ff) << 16) | V1_X_ZOOM_ENABLE;
248 *mini |= V1_X_INTERPOLY;
249 }
250 else /* sw > dw - Zoom out */
251 {
252 /* Find a suitable divider (1 << d) = {2, 4, 8 or 16} */
253 sw1 = sw;
254 for (d = 1; d < 5; d++)
255 {
256 sw1 >>= 1;
257 if (sw1 <= dw)
258 break;
259 }
260 if (d == 5) /* too small */
261 {
262 d = 4;
263 zoom_ok = 0;
264 }
265
266 md = 1 << d; /* <= {2,4,8,16} */
267 *falign = ((md << 1) - 1) & 0xf; /* <= {3,7,15,15} */
268 *mini |= V1_X_INTERPOLY;
269 *mini |= ((d << 1) - 1) << 24; /* <= {1,3,5,7} << 24 */
270
271 /* Add scaling */
272 if (sw1 < dw)
273 {
274 /* CLE bug */
275 /* tmp = sw1*0x0800 / dw; */
276 tmp = (sw1 - 2) * 0x0800 / dw;
277 *zoom |= ((tmp & 0x7ff) << 16) | V1_X_ZOOM_ENABLE;
278 }
279 }
280
281 *dcount = sw - md;
282 return zoom_ok;
283 }
284
285 /**
286 * @brief qword fetch register setting.
287 *
288 * @param format overlay pixel format.
289 * @param sw source width.
290 *
291 * @return qword fetch register setting
292 *
293 * @note Derived from VIA's V4L driver. See ddover.c, DDOver_GetFetch()
294 * @note Only call after uc_ovl_map_hzoom()
295 */
296 static uint32_t
297 uc_ovl_map_qwfetch (uint32_t format, int sw)
298 {
299 uint32_t fetch = 0;
300
301 switch (format)
302 {
303 case IMGFMT_YV12:
304 case IMGFMT_I420:
305 fetch = ALIGN_TO (sw, 32) >> 4;
306 break;
307 case IMGFMT_UYVY:
308 case IMGFMT_YVYU:
309 case IMGFMT_YUY2:
310 fetch = (ALIGN_TO (sw << 1, 16) >> 4) + 1;
311 break;
312 case IMGFMT_BGR15:
313 case IMGFMT_BGR16:
314 fetch = (ALIGN_TO (sw << 1, 16) >> 4) + 1;
315 break;
316 case IMGFMT_BGR32:
317 fetch = (ALIGN_TO (sw << 2, 16) >> 4) + 1;
318 break;
319 default:
320 printf ("[unichrome] Unexpected pixelformat!");
321 break;
322 }
323
324 if (fetch < 4)
325 fetch = 4;
326
327 return fetch;
328 }
329
330 /**
331 * @brief Map pixel format.
332 *
333 * @param format pixel format.
334 *
335 * @return the mapped pixel format.
336 *
337 * @note Derived from VIA's V4L driver. See ddover.c, DDOver_GetV1Format()
338 */
339 static uint32_t
340 uc_ovl_map_format (uint32_t format)
341 {
342 switch (format)
343 {
344 case IMGFMT_UYVY:
345 case IMGFMT_YVYU:
346 case IMGFMT_YUY2:
347 return V1_COLORSPACE_SIGN | V1_YUV422;
348 case IMGFMT_IYUV:
349 return V1_COLORSPACE_SIGN | V1_YCbCr420 | V1_SWAP_SW;
350 case IMGFMT_YV12:
351 case IMGFMT_I420:
352 return V1_COLORSPACE_SIGN | V1_YCbCr420;
353 case IMGFMT_BGR15:
354 return V1_RGB15;
355 case IMGFMT_BGR16:
356 return V1_RGB16;
357 case IMGFMT_BGR32:
358 return V1_RGB32;
359 default:
360 printf ("[unichrome] Unexpected pixelformat!");
361 return V1_YUV422;
362 }
363 }
364
365 /**
366 * @brief Calculate V1 control and fifo-control register values.
367 *
368 * @param format pixel format.
369 * @param sw source width.
370 * @param hwrev CLE266 hardware revision.
371 * @param extfifo_on set this 1 if the extended FIFO is enabled.
372 * @param control will hold value for V1_CONTROL.
373 * @param fifo will hold value for V1_FIFO_CONTROL.
374 */
375 static void
376 uc_ovl_map_v1_control (uint32_t format, int sw,
377 int hwrev, int extfifo_on,
378 uint32_t * control, uint32_t * fifo)
379 {
380 *control = V1_BOB_ENABLE | uc_ovl_map_format (format);
381
382 if (hwrev == 0x10)
383 {
384 *control |= V1_EXPIRE_NUM_F;
385 }
386 else
387 {
388 if (extfifo_on)
389 {
390 *control |= V1_EXPIRE_NUM_A | V1_FIFO_EXTENDED;
391 }
392 else
393 {
394 *control |= V1_EXPIRE_NUM;
395 }
396 }
397
398 if ((format == IMGFMT_YV12) || (format == IMGFMT_I420))
399 {
400 /* Minified video will be skewed without this workaround. */
401 if (sw <= 80) /* Fetch count <= 5 */
402 {
403 *fifo = UC_MAP_V1_FIFO_CONTROL (16, 0, 0);
404 }
405 else
406 {
407 if (hwrev == 0x10)
408 *fifo = UC_MAP_V1_FIFO_CONTROL (64, 56, 56);
409 else
410 *fifo = UC_MAP_V1_FIFO_CONTROL (16, 12, 8);
411 }
412 }
413 else
414 {
415 if (hwrev == 0x10)
416 {
417 *fifo = UC_MAP_V1_FIFO_CONTROL (64, 56, 56); /* Default rev 0x10 */
418 }
419 else
420 {
421 if (extfifo_on)
422 *fifo = UC_MAP_V1_FIFO_CONTROL (48, 40, 40);
423 else
424 *fifo = UC_MAP_V1_FIFO_CONTROL (32, 29, 16); /* Default */
425 }
426 }
427 }
428
429 /**
430 * @brief Setup extended FIFO.
431 *
432 * @param extfifo_on pointer determining if extended fifo is enable or not.
433 * @param dst_w destination width.
434 */
435 static void
436 uc_ovl_setup_fifo (int *extfifo_on, int dst_w)
437 {
438 if (dst_w <= 1024) /* Disable extended FIFO */
439 {
440 outb (0x16, 0x3c4);
441 outb (mclk_save[0], 0x3c5);
442 outb (0x17, 0x3c4);
443 outb (mclk_save[1], 0x3c5);
444 outb (0x18, 0x3c4);
445 outb (mclk_save[2], 0x3c5);
446 *extfifo_on = 0;
447 }
448 else /* Enable extended FIFO */
449 {
450 outb (0x17, 0x3c4);
451 outb (0x2f, 0x3c5);
452 outb (0x16, 0x3c4);
453 outb ((mclk_save[0] & 0xf0) | 0x14, 0x3c5);
454 outb (0x18, 0x3c4);
455 outb (0x56, 0x3c5);
456 *extfifo_on = 1;
457 }
458 }
459
460 static void
461 uc_ovl_vcmd_wait (volatile uint8_t * vio)
462 {
463 while ((VIDEO_IN (vio, V_COMPOSE_MODE)
464 & (V1_COMMAND_FIRE | V3_COMMAND_FIRE)));
465 }
466
467 /**
468 * @brief Probe hardware to find some useable chipset.
469 *
470 * @param verbose specifies verbose level.
471 * @param force specifies force mode : driver should ignore
472 * device_id (danger but useful for new devices)
473 *
474 * @returns 0 if it can handle something in PC.
475 * a negative error code otherwise.
476 */
477 int
478 vixProbe (int verbose, int force)
479 {
480 pciinfo_t lst[MAX_PCI_DEVICES];
481 unsigned i, num_pci;
482 int err;
483 err = pci_scan (lst, &num_pci);
484 if (err)
485 {
486 printf ("[unichrome] Error occurred during pci scan: %s\n",
487 strerror (err));
488 return err;
489 }
490 else
491 {
492 err = ENXIO;
493 for (i = 0; i < num_pci; i++)
494 {
495 if (lst[i].vendor == VENDOR_VIA2)
496 {
497 int idx;
498 const char *dname;
499 idx = find_chip (lst[i].device);
500 if (idx == -1)
501 continue;
502 dname = pci_device_name (VENDOR_VIA2, lst[i].device);
503 dname = dname ? dname : "Unknown chip";
504 printf ("[unichrome] Found chip: %s\n", dname);
505 if ((lst[i].command & PCI_COMMAND_IO) == 0)
506 {
507 printf ("[unichrome] Device is disabled, ignoring\n");
508 continue;
509 }
510 uc_cap.device_id = lst[i].device;
511 err = 0;
512 memcpy (&pci_info, &lst[i], sizeof (pciinfo_t));
513 break;
514 }
515 }
516 }
517
518 if (err && verbose)
519 printf ("[unichrome] Can't find chip\n");
520 return err;
521 }
522
523 /**
524 * @brief Initializes driver.
525 *
526 * @returns 0 if ok.
527 * a negative error code otherwise.
528 */
529 int
530 vixInit (void)
531 {
532 long tmp;
533 uc_mem = map_phys_mem (pci_info.base0, VIDEOMEMORY_SIZE);
534 enable_app_io ();
535
536 outb (0x2f, 0x3c4);
537 tmp = inb (0x3c5) << 0x18;
538 vio = map_phys_mem (tmp, 0x1000);
539
540 outb (0x16, 0x3c4);
541 mclk_save[0] = inb (0x3c5);
542 outb (0x17, 0x3c4);
543 mclk_save[1] = inb (0x3c5);
544 outb (0x18, 0x3c4);
545 mclk_save[2] = inb (0x3c5);
546
547 uc_grkey.ckey.blue = 0x00;
548 uc_grkey.ckey.green = 0x00;
549 uc_grkey.ckey.red = 0x00;
550
551 /* Detect whether we have a CLE266Ax or CLE266Cx */
552 outb (0x4f, 0x3d4);
553 tmp = inb (0x3d5);
554 outb (0x4f, 0x3d4);
555 outb (0x55, 0x3d5);
556 outb (0x4f, 0x3d4);
557 if (0x55 == inb (0x3d5))
558 {
559 /* Only CLE266Cx supports CR4F */
560 hwrev = 0x11;
561 }
562 else
563 {
564 /* Otherwise assume to be a CLE266Ax */
565 hwrev = 0x00;
566 }
567 outb (0x4f, 0x3d4);
568 outb (tmp, 0x3d5);
569
570 #ifdef DEBUG_LOGFILE
571 logfile = fopen ("/tmp/uc_vidix.log", "w");
572 #endif
573 return 0;
574 }
575
576 /**
577 * @brief Destroys driver.
578 */
579 void
580 vixDestroy (void)
581 {
582 #ifdef DEBUG_LOGFILE
583 if (logfile)
584 fclose (logfile);
585 #endif
586 outb (0x16, 0x3c4);
587 outb (mclk_save[0], 0x3c5);
588 outb (0x17, 0x3c4);
589 outb (mclk_save[1], 0x3c5);
590 outb (0x18, 0x3c4);
591 outb (mclk_save[2], 0x3c5);
592
593 disable_app_io ();
594 unmap_phys_mem (uc_mem, VIDEOMEMORY_SIZE);
595 unmap_phys_mem (vio, 0x1000);
596 }
597
598 /**
599 * @brief Get chipset's hardware capabilities.
600 *
601 * @param to Pointer to the vidix_capability_t structure to be filled.
602 *
603 * @returns 0.
604 */
605 int
606 vixGetCapability (vidix_capability_t * to)
607 {
608 memcpy (to, &uc_cap, sizeof (vidix_capability_t));
609 return 0;
610 }
611
612 /**
613 * @brief Report if the video FourCC is supported by hardware.
614 *
615 * @param fourcc input image format.
616 *
617 * @returns 1 if the fourcc is supported.
618 * 0 otherwise.
619 */
620 static int
621 is_supported_fourcc (uint32_t fourcc)
622 {
623 switch (fourcc)
624 {
625 case IMGFMT_YV12:
626 case IMGFMT_I420:
627 case IMGFMT_UYVY:
628 case IMGFMT_YVYU:
629 case IMGFMT_YUY2:
630 case IMGFMT_BGR15:
631 case IMGFMT_BGR16:
632 case IMGFMT_BGR32:
633 return 1;
634 default:
635 return 0;
636 }
637 }
638
639 /**
640 * @brief Try to configure video memory for given fourcc.
641 *
642 * @param to Pointer to the vidix_fourcc_t structure to be filled.
643 *
644 * @returns 0 if ok.
645 * errno otherwise.
646 */
647 int
648 vixQueryFourcc (vidix_fourcc_t * to)
649 {
650 if (is_supported_fourcc (to->fourcc))
651 {
652 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP |
653 VID_DEPTH_4BPP | VID_DEPTH_8BPP |
654 VID_DEPTH_12BPP | VID_DEPTH_15BPP |
655 VID_DEPTH_16BPP | VID_DEPTH_24BPP | VID_DEPTH_32BPP;
656 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
657 return 0;
658 }
659 else
660 to->depth = to->flags = 0;
661 return ENOSYS;
662 }
663
664 /**
665 * @brief Get the GrKeys
666 *
667 * @param grkey Pointer to the vidix_grkey_t structure to be filled by driver.
668 *
669 * @return 0.
670 */
671 int
672 vixGetGrKeys (vidix_grkey_t * grkey)
673 {
674 memcpy (grkey, &uc_grkey, sizeof (vidix_grkey_t));
675 return (0);
676 }
677
678 /**
679 * @brief Set the GrKeys
680 *
681 * @param grkey Colorkey to be set.
682 *
683 * @return 0.
684 */
685 int
686 vixSetGrKeys (const vidix_grkey_t * grkey)
687 {
688 unsigned long dwCompose = VIDEO_IN (vio, V_COMPOSE_MODE) & ~0x0f;
689 memcpy (&uc_grkey, grkey, sizeof (vidix_grkey_t));
690 if (uc_grkey.ckey.op != CKEY_FALSE)
691 {
692 /* Set colorkey (how do I detect BPP in hardware ??) */
693 unsigned long ckey;
694 if (1) /* Assume 16-bit graphics */
695 {
696 ckey = (grkey->ckey.blue & 0x1f)
697 | ((grkey->ckey.green & 0x3f) << 5)
698 | ((grkey->ckey.red & 0x1f) << 11);
699 }
700 else
701 {
702 ckey = (grkey->ckey.blue)
703 | (grkey->ckey.green << 8) | (grkey->ckey.red << 16);
704 }
705 VIDEO_OUT (vio, V_COLOR_KEY, ckey);
706 dwCompose |= SELECT_VIDEO_IF_COLOR_KEY;
707 }
708
709 /* Execute the changes */
710 VIDEO_OUT (vio, V_COMPOSE_MODE, dwCompose | V1_COMMAND_FIRE);
711 return (0);
712 }
713
714 /**
715 * @brief Unichrome driver equalizer capabilities.
716 */
717 vidix_video_eq_t equal = {
718 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | VEQ_CAP_HUE,
719 300, 100, 0, 0, 0, 0, 0, 0
720 };
721
722
723 /**
724 * @brief Get the equalizer capabilities.
725 *
726 * @param eq Pointer to the vidix_video_eq_t structure to be filled by driver.
727 *
728 * @return 0.
729 */
730 int
731 vixPlaybackGetEq (vidix_video_eq_t * eq)
732 {
733 memcpy (eq, &equal, sizeof (vidix_video_eq_t));
734 return 0;
735 }
736
737 /**
738 * @brief Set the equalizer capabilities for color correction
739 *
740 * @param eq equalizer capabilities to be set.
741 *
742 * @return 0.
743 */
744 int
745 vixPlaybackSetEq (const vidix_video_eq_t * eq)
746 {
747 return 0;
748 }
749
750 /**
751 * @brief Y, U, V offsets.
752 */
753 static int YOffs, UOffs, VOffs;
754
755 /**
756 * @brief Configure driver for playback. Driver should prepare BES.
757 *
758 * @param info configuration description for playback.
759 *
760 * @returns 0 in case of success.
761 * -1 otherwise.
762 */
763 int
764 vixConfigPlayback (vidix_playback_t * info)
765 {
766 int src_w, drw_w;
767 int src_h, drw_h;
768 long base0, pitch;
769 int uv_size, swap_uv;
770 unsigned int i;
771 int extfifo_on;
772
773 /* Overlay register settings */
774 uint32_t win_start, win_end;
775 uint32_t zoom, mini;
776 uint32_t dcount, falign, qwfetch;
777 uint32_t y_start, u_start, v_start;
778 uint32_t v_ctrl, fifo_ctrl;
779
780 if (!is_supported_fourcc (info->fourcc))
781 return -1;
782
783 src_w = info->src.w;
784 src_h = info->src.h;
785
786 drw_w = info->dest.w;
787 drw_h = info->dest.h;
788
789 /* Setup FIFO */
790 uc_ovl_setup_fifo (&extfifo_on, src_w);
791
792 /* Get image format, FIFO size, etc. */
793 uc_ovl_map_v1_control (info->fourcc, src_w, hwrev, extfifo_on,
794 &v_ctrl, &fifo_ctrl);
795
796 /* Setup layer window */
797 win_start = (info->dest.x << 16) | info->dest.y;
798 win_end = ((info->dest.x + drw_w - 1) << 16) | (info->dest.y + drw_h - 1);
799
800 /* Get scaling and data-fetch parameters */
801 zoom = 0;
802 mini = 0;
803 uc_ovl_map_vzoom (src_h, drw_h, &zoom, &mini);
804 uc_ovl_map_hzoom (src_w, drw_w, &zoom, &mini, &falign, &dcount);
805 qwfetch = uc_ovl_map_qwfetch (info->fourcc, src_w);
806
807 /* Calculate buffer sizes */
808 swap_uv = 0;
809 switch (info->fourcc)
810 {
811 case IMGFMT_YV12:
812 swap_uv = 1;
813 case IMGFMT_I420:
814 case IMGFMT_UYVY:
815 case IMGFMT_YVYU:
816 pitch = ALIGN_TO (src_w, 32);
817 uv_size = (pitch >> 1) * (src_h >> 1);
818 break;
819
820 case IMGFMT_YUY2:
821 case IMGFMT_BGR15:
822 case IMGFMT_BGR16:
823 pitch = ALIGN_TO (src_w << 1, 32);
824 uv_size = 0;
825 break;
826
827 case IMGFMT_BGR32:
828 pitch = ALIGN_TO (src_w << 2, 32);
829 uv_size = 0;
830 break;
831 }
832 if ((src_w > 4096) || (src_h > 4096) ||
833 (src_w < 32) || (src_h < 1) || (pitch > 0x1fff))
834 {
835 printf ("[unichrome] Layer size out of bounds\n");
836 }
837
838 /* Calculate offsets */
839 info->offset.y = 0;
840 info->offset.v = info->offset.y + pitch * src_h;
841 info->offset.u = info->offset.v + uv_size;
842 info->frame_size = info->offset.u + uv_size;
843 YOffs = info->offset.y;
844 UOffs = (swap_uv ? info->offset.v : info->offset.u);
845 VOffs = (swap_uv ? info->offset.u : info->offset.v);
846
847 /* Assume we have 2 MB to play with */
848 info->num_frames = FRAMEBUFFER_SIZE / info->frame_size;
849 if (info->num_frames > VID_PLAY_MAXFRAMES)
850 info->num_frames = VID_PLAY_MAXFRAMES;
851
852 /* Start at 6 MB. Let's hope it's not in use. */
853 base0 = FRAMEBUFFER_START;
854 info->dga_addr = uc_mem + base0;
855
856 info->dest.pitch.y = 32;
857 info->dest.pitch.u = 32;
858 info->dest.pitch.v = 32;
859
860 for (i = 0; i < info->num_frames; i++)
861 {
862 info->offsets[i] = info->frame_size * i;
863 frames[i] = base0 + info->offsets[i];
864 }
865
866 /* Write to the hardware */
867 uc_ovl_vcmd_wait (vio);
868
869 /* Configure diy_pitchlay parameters now */
870 if (v_ctrl & V1_COLORSPACE_SIGN)
871 {
872 if (hwrev >= 0x10)
873 {
874 VIDEO_OUT (vio, V1_ColorSpaceReg_2, ColorSpaceValue_2_3123C0);
875 VIDEO_OUT (vio, V1_ColorSpaceReg_1, ColorSpaceValue_1_3123C0);
876 }
877 else
878 {
879 VIDEO_OUT (vio, V1_ColorSpaceReg_2, ColorSpaceValue_2);
880 VIDEO_OUT (vio, V1_ColorSpaceReg_1, ColorSpaceValue_1);
881 }
882 }
883
884 VIDEO_OUT (vio, V1_CONTROL, v_ctrl);
885 VIDEO_OUT (vio, V_FIFO_CONTROL, fifo_ctrl);
886
887 VIDEO_OUT (vio, V1_WIN_START_Y, win_start);
888 VIDEO_OUT (vio, V1_WIN_END_Y, win_end);
889
890 VIDEO_OUT (vio, V1_SOURCE_HEIGHT, (src_h << 16) | dcount);
891
892 VIDEO_OUT (vio, V12_QWORD_PER_LINE, qwfetch << 20);
893 VIDEO_OUT (vio, V1_STRIDE, pitch | ((pitch >> 1) << 16));
894
895 VIDEO_OUT (vio, V1_MINI_CONTROL, mini);
896 VIDEO_OUT (vio, V1_ZOOM_CONTROL, zoom);
897
898 /* Configure buffer address and execute the changes now! */
899 vixPlaybackFrameSelect (0);
900
901 return 0;
902 }
903
904 /**
905 * @brief Set playback on : driver should activate BES on this call.
906 *
907 * @return 0.
908 */
909 int
910 vixPlaybackOn (void)
911 {
912 LOGWRITE ("Enable overlay\n");
913
914 /* Turn on overlay */
915 VIDEO_OUT (vio, V1_CONTROL, VIDEO_IN (vio, V1_CONTROL) | V1_ENABLE);
916
917 /* Execute the changes */
918 VIDEO_OUT (vio, V_COMPOSE_MODE,
919 VIDEO_IN (vio, V_COMPOSE_MODE) | V1_COMMAND_FIRE);
920
921 return 0;
922 }
923
924 /**
925 * @brief Set playback off : driver should deactivate BES on this call.
926 *
927 * @return 0.
928 */
929 int
930 vixPlaybackOff (void)
931 {
932 LOGWRITE ("Disable overlay\n");
933
934 uc_ovl_vcmd_wait (vio);
935
936 /* Restore FIFO */
937 VIDEO_OUT (vio, V_FIFO_CONTROL, UC_MAP_V1_FIFO_CONTROL (16, 12, 8));
938
939 /* Turn off overlay */
940 VIDEO_OUT (vio, V1_CONTROL, VIDEO_IN (vio, V1_CONTROL) & ~V1_ENABLE);
941
942 /* Execute the changes */
943 VIDEO_OUT (vio, V_COMPOSE_MODE,
944 VIDEO_IN (vio, V_COMPOSE_MODE) | V1_COMMAND_FIRE);
945
946 return 0;
947 }
948
949 /**
950 * @brief Driver should prepare and activate corresponded frame.
951 *
952 * @param frame the frame index.
953 *
954 * @return 0.
955 *
956 * @note This function is used only for double and triple buffering
957 * and never used for single buffering playback.
958 */
959 int
960 vixPlaybackFrameSelect (unsigned int frame)
961 {
962 LOGWRITE ("Frame select\n");
963
964 uc_ovl_vcmd_wait (vio);
965
966 /* Configure buffer address */
967 VIDEO_OUT (vio, V1_STARTADDR_Y0, frames[frame] + YOffs);
968 VIDEO_OUT (vio, V1_STARTADDR_CB0, frames[frame] + UOffs);
969 VIDEO_OUT (vio, V1_STARTADDR_CR0, frames[frame] + VOffs);
970
971 /* Execute the changes */
972 VIDEO_OUT (vio, V_COMPOSE_MODE,
973 VIDEO_IN (vio, V_COMPOSE_MODE) | V1_COMMAND_FIRE);
974
975 return 0;
976 }