Mercurial > mplayer.hg

comparison vidix/drivers/radeon_vid.c @ 8553:d952b097c720

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
author alex
date Tue, 24 Dec 2002 17:40:57 +0000
parents 8996a4599a41
children 82ecba0b039b
comparison
equal deleted inserted replaced
8552:37dd9f68ab71 8553:d952b097c720
196 196
197 static void * radeon_mmio_base = 0; 197 static void * radeon_mmio_base = 0;
198 static void * radeon_mem_base = 0; 198 static void * radeon_mem_base = 0;
199 static int32_t radeon_overlay_off = 0; 199 static int32_t radeon_overlay_off = 0;
200 static uint32_t radeon_ram_size = 0; 200 static uint32_t radeon_ram_size = 0;
201 /* Restore on exit */
202 static uint32_t SAVED_OV0_GRAPHICS_KEY_CLR = 0;
203 static uint32_t SAVED_OV0_GRAPHICS_KEY_MSK = 0;
204 static uint32_t SAVED_OV0_VID_KEY_CLR = 0;
205 static uint32_t SAVED_OV0_VID_KEY_MSK = 0;
206 static uint32_t SAVED_OV0_KEY_CNTL = 0;
201 207
202 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) 208 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ))))
203 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL 209 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL
204 210
205 #define INREG8(addr) GETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr) 211 #define INREG8(addr) GETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr)
930 radeon_vid_make_default(); 936 radeon_vid_make_default();
931 printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); 937 printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000);
932 err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB); 938 err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB);
933 if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n"); 939 if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n");
934 940
941 radeon_fifo_wait(3);
942 SAVED_OV0_GRAPHICS_KEY_CLR = INREG(OV0_GRAPHICS_KEY_CLR);
943 SAVED_OV0_GRAPHICS_KEY_MSK = INREG(OV0_GRAPHICS_KEY_MSK);
944 SAVED_OV0_VID_KEY_CLR = INREG(OV0_VID_KEY_CLR);
945 SAVED_OV0_VID_KEY_MSK = INREG(OV0_VID_KEY_MSK);
946 SAVED_OV0_KEY_CNTL = INREG(OV0_KEY_CNTL);
947 printf(RADEON_MSG" Saved overlay colorkey settings\n");
948
935 #ifdef RADEON 949 #ifdef RADEON
936 switch(def_cap.device_id) 950 switch(def_cap.device_id)
937 { 951 {
938 case DEVICE_ATI_RADEON_QW: 952 case DEVICE_ATI_RADEON_QW:
939 case DEVICE_ATI_RADEON_MOBILITY_M6: 953 case DEVICE_ATI_RADEON_MOBILITY_M6:
961 975
962 void vixDestroy( void ) 976 void vixDestroy( void )
963 { 977 {
964 /* remove colorkeying */ 978 /* remove colorkeying */
965 radeon_fifo_wait(3); 979 radeon_fifo_wait(3);
966 OUTREG(OV0_GRAPHICS_KEY_CLR, 0); 980 OUTREG(OV0_GRAPHICS_KEY_CLR, SAVED_OV0_GRAPHICS_KEY_CLR);
967 OUTREG(OV0_GRAPHICS_KEY_MSK, 0); 981 OUTREG(OV0_GRAPHICS_KEY_MSK, SAVED_OV0_GRAPHICS_KEY_MSK);
968 OUTREG(OV0_VID_KEY_CLR, 0); 982 OUTREG(OV0_VID_KEY_CLR, SAVED_OV0_VID_KEY_CLR);
969 OUTREG(OV0_VID_KEY_MSK, 0); 983 OUTREG(OV0_VID_KEY_MSK, SAVED_OV0_VID_KEY_MSK);
970 OUTREG(OV0_KEY_CNTL, 0); 984 OUTREG(OV0_KEY_CNTL, SAVED_OV0_KEY_CNTL);
985 printf(RADEON_MSG" Restored overlay colorkey settings\n");
971 986
972 unmap_phys_mem(radeon_mem_base,radeon_ram_size); 987 unmap_phys_mem(radeon_mem_base,radeon_ram_size);
973 unmap_phys_mem(radeon_mmio_base,0xFFFF); 988 unmap_phys_mem(radeon_mmio_base,0xFFFF);
974 } 989 }
975 990