Mercurial > mplayer.hg
annotate vidix/drivers/radeon_vid.c @ 8553:d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
author | alex |
---|---|
date | Tue, 24 Dec 2002 17:40:57 +0000 |
parents | 8996a4599a41 |
children | 82ecba0b039b |
rev | line source |
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3996 | 1 /* |
2 radeon_vid - VIDIX based video driver for Radeon and Rage128 chips | |
4030 | 3 Copyrights 2002 Nick Kurshev. This file is based on sources from |
4 GATOS (gatos.sf.net) and X11 (www.xfree86.org) | |
5 Licence: GPL | |
3996 | 6 */ |
7 | |
8 #include <errno.h> | |
9 #include <stdio.h> | |
10 #include <stdlib.h> | |
11 #include <string.h> | |
12 #include <math.h> | |
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13 #include <inttypes.h> |
4201 | 14 #include "../../libdha/pci_ids.h" |
15 #include "../../libdha/pci_names.h" | |
3996 | 16 #include "../vidix.h" |
17 #include "../fourcc.h" | |
18 #include "../../libdha/libdha.h" | |
19 #include "radeon.h" | |
20 | |
21 #ifdef RAGE128 | |
22 #define RADEON_MSG "Rage128_vid:" | |
23 #define X_ADJUST 0 | |
24 #else | |
25 #define RADEON_MSG "Radeon_vid:" | |
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26 #define X_ADJUST (is_shift_required ? 8 : 0) |
3996 | 27 #ifndef RADEON |
28 #define RADEON | |
29 #endif | |
30 #endif | |
31 | |
4030 | 32 static int __verbose = 0; |
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33 #ifdef RADEON |
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34 static int rage_ckey_model=0; |
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35 static int is_shift_required; |
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36 #endif |
4015 | 37 |
3996 | 38 typedef struct bes_registers_s |
39 { | |
40 /* base address of yuv framebuffer */ | |
41 uint32_t yuv_base; | |
42 uint32_t fourcc; | |
43 uint32_t dest_bpp; | |
44 /* YUV BES registers */ | |
45 uint32_t reg_load_cntl; | |
46 uint32_t h_inc; | |
47 uint32_t step_by; | |
48 uint32_t y_x_start; | |
49 uint32_t y_x_end; | |
50 uint32_t v_inc; | |
51 uint32_t p1_blank_lines_at_top; | |
52 uint32_t p23_blank_lines_at_top; | |
53 uint32_t vid_buf_pitch0_value; | |
54 uint32_t vid_buf_pitch1_value; | |
55 uint32_t p1_x_start_end; | |
56 uint32_t p2_x_start_end; | |
57 uint32_t p3_x_start_end; | |
58 uint32_t base_addr; | |
4930 | 59 uint32_t vid_buf_base_adrs_y[VID_PLAY_MAXFRAMES]; |
60 uint32_t vid_buf_base_adrs_u[VID_PLAY_MAXFRAMES]; | |
61 uint32_t vid_buf_base_adrs_v[VID_PLAY_MAXFRAMES]; | |
62 uint32_t vid_nbufs; | |
3996 | 63 |
64 uint32_t p1_v_accum_init; | |
65 uint32_t p1_h_accum_init; | |
66 uint32_t p23_v_accum_init; | |
67 uint32_t p23_h_accum_init; | |
68 uint32_t scale_cntl; | |
69 uint32_t exclusive_horz; | |
70 uint32_t auto_flip_cntl; | |
71 uint32_t filter_cntl; | |
72 uint32_t key_cntl; | |
73 uint32_t test; | |
74 /* Configurable stuff */ | |
75 int double_buff; | |
76 | |
77 int brightness; | |
78 int saturation; | |
79 | |
80 int ckey_on; | |
81 uint32_t graphics_key_clr; | |
82 uint32_t graphics_key_msk; | |
4869 | 83 uint32_t ckey_cntl; |
3996 | 84 |
85 int deinterlace_on; | |
86 uint32_t deinterlace_pattern; | |
87 | |
88 } bes_registers_t; | |
89 | |
90 typedef struct video_registers_s | |
91 { | |
92 const char * sname; | |
93 uint32_t name; | |
94 uint32_t value; | |
95 }video_registers_t; | |
96 | |
97 static bes_registers_t besr; | |
98 #ifndef RAGE128 | |
99 static int IsR200=0; | |
100 #endif | |
101 #define DECLARE_VREG(name) { #name, name, 0 } | |
102 static video_registers_t vregs[] = | |
103 { | |
104 DECLARE_VREG(VIDEOMUX_CNTL), | |
105 DECLARE_VREG(VIPPAD_MASK), | |
106 DECLARE_VREG(VIPPAD1_A), | |
107 DECLARE_VREG(VIPPAD1_EN), | |
108 DECLARE_VREG(VIPPAD1_Y), | |
109 DECLARE_VREG(OV0_Y_X_START), | |
110 DECLARE_VREG(OV0_Y_X_END), | |
111 DECLARE_VREG(OV0_PIPELINE_CNTL), | |
112 DECLARE_VREG(OV0_EXCLUSIVE_HORZ), | |
113 DECLARE_VREG(OV0_EXCLUSIVE_VERT), | |
114 DECLARE_VREG(OV0_REG_LOAD_CNTL), | |
115 DECLARE_VREG(OV0_SCALE_CNTL), | |
116 DECLARE_VREG(OV0_V_INC), | |
117 DECLARE_VREG(OV0_P1_V_ACCUM_INIT), | |
118 DECLARE_VREG(OV0_P23_V_ACCUM_INIT), | |
119 DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), | |
120 DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), | |
121 #ifdef RADEON | |
122 DECLARE_VREG(OV0_BASE_ADDR), | |
123 #endif | |
124 DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), | |
125 DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), | |
126 DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), | |
127 DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), | |
128 DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), | |
129 DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), | |
130 DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), | |
131 DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), | |
132 DECLARE_VREG(OV0_AUTO_FLIP_CNTL), | |
133 DECLARE_VREG(OV0_DEINTERLACE_PATTERN), | |
134 DECLARE_VREG(OV0_SUBMIT_HISTORY), | |
135 DECLARE_VREG(OV0_H_INC), | |
136 DECLARE_VREG(OV0_STEP_BY), | |
137 DECLARE_VREG(OV0_P1_H_ACCUM_INIT), | |
138 DECLARE_VREG(OV0_P23_H_ACCUM_INIT), | |
139 DECLARE_VREG(OV0_P1_X_START_END), | |
140 DECLARE_VREG(OV0_P2_X_START_END), | |
141 DECLARE_VREG(OV0_P3_X_START_END), | |
142 DECLARE_VREG(OV0_FILTER_CNTL), | |
143 DECLARE_VREG(OV0_FOUR_TAP_COEF_0), | |
144 DECLARE_VREG(OV0_FOUR_TAP_COEF_1), | |
145 DECLARE_VREG(OV0_FOUR_TAP_COEF_2), | |
146 DECLARE_VREG(OV0_FOUR_TAP_COEF_3), | |
147 DECLARE_VREG(OV0_FOUR_TAP_COEF_4), | |
148 DECLARE_VREG(OV0_FLAG_CNTL), | |
149 #ifdef RAGE128 | |
150 DECLARE_VREG(OV0_COLOUR_CNTL), | |
151 #else | |
152 DECLARE_VREG(OV0_SLICE_CNTL), | |
153 #endif | |
154 DECLARE_VREG(OV0_VID_KEY_CLR), | |
155 DECLARE_VREG(OV0_VID_KEY_MSK), | |
156 DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), | |
157 DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), | |
158 DECLARE_VREG(OV0_KEY_CNTL), | |
159 DECLARE_VREG(OV0_TEST), | |
160 DECLARE_VREG(OV0_LIN_TRANS_A), | |
161 DECLARE_VREG(OV0_LIN_TRANS_B), | |
162 DECLARE_VREG(OV0_LIN_TRANS_C), | |
163 DECLARE_VREG(OV0_LIN_TRANS_D), | |
164 DECLARE_VREG(OV0_LIN_TRANS_E), | |
165 DECLARE_VREG(OV0_LIN_TRANS_F), | |
166 DECLARE_VREG(OV0_GAMMA_0_F), | |
167 DECLARE_VREG(OV0_GAMMA_10_1F), | |
168 DECLARE_VREG(OV0_GAMMA_20_3F), | |
169 DECLARE_VREG(OV0_GAMMA_40_7F), | |
170 DECLARE_VREG(OV0_GAMMA_380_3BF), | |
171 DECLARE_VREG(OV0_GAMMA_3C0_3FF), | |
172 DECLARE_VREG(SUBPIC_CNTL), | |
173 DECLARE_VREG(SUBPIC_DEFCOLCON), | |
174 DECLARE_VREG(SUBPIC_Y_X_START), | |
175 DECLARE_VREG(SUBPIC_Y_X_END), | |
176 DECLARE_VREG(SUBPIC_V_INC), | |
177 DECLARE_VREG(SUBPIC_H_INC), | |
178 DECLARE_VREG(SUBPIC_BUF0_OFFSET), | |
179 DECLARE_VREG(SUBPIC_BUF1_OFFSET), | |
180 DECLARE_VREG(SUBPIC_LC0_OFFSET), | |
181 DECLARE_VREG(SUBPIC_LC1_OFFSET), | |
182 DECLARE_VREG(SUBPIC_PITCH), | |
183 DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), | |
184 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), | |
185 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), | |
186 DECLARE_VREG(SUBPIC_PALETTE_INDEX), | |
187 DECLARE_VREG(SUBPIC_PALETTE_DATA), | |
188 DECLARE_VREG(SUBPIC_H_ACCUM_INIT), | |
189 DECLARE_VREG(SUBPIC_V_ACCUM_INIT), | |
190 DECLARE_VREG(IDCT_RUNS), | |
191 DECLARE_VREG(IDCT_LEVELS), | |
192 DECLARE_VREG(IDCT_AUTH_CONTROL), | |
193 DECLARE_VREG(IDCT_AUTH), | |
194 DECLARE_VREG(IDCT_CONTROL) | |
195 }; | |
4030 | 196 |
3996 | 197 static void * radeon_mmio_base = 0; |
198 static void * radeon_mem_base = 0; | |
199 static int32_t radeon_overlay_off = 0; | |
200 static uint32_t radeon_ram_size = 0; | |
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201 /* Restore on exit */ |
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202 static uint32_t SAVED_OV0_GRAPHICS_KEY_CLR = 0; |
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203 static uint32_t SAVED_OV0_GRAPHICS_KEY_MSK = 0; |
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204 static uint32_t SAVED_OV0_VID_KEY_CLR = 0; |
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205 static uint32_t SAVED_OV0_VID_KEY_MSK = 0; |
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206 static uint32_t SAVED_OV0_KEY_CNTL = 0; |
3996 | 207 |
4012 | 208 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) |
209 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
210 | |
211 #define INREG8(addr) GETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr) | |
212 #define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr,val) | |
213 #define INREG(addr) GETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr) | |
214 #define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,val) | |
3996 | 215 #define OUTREGP(addr,val,mask) \ |
216 do { \ | |
217 unsigned int _tmp = INREG(addr); \ | |
218 _tmp &= (mask); \ | |
219 _tmp |= (val); \ | |
220 OUTREG(addr, _tmp); \ | |
221 } while (0) | |
222 | |
4666 | 223 static __inline__ uint32_t INPLL(uint32_t addr) |
224 { | |
225 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f); | |
226 return (INREG(CLOCK_CNTL_DATA)); | |
227 } | |
228 | |
229 #define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \ | |
230 OUTREG(CLOCK_CNTL_DATA, val) | |
231 #define OUTPLLP(addr,val,mask) \ | |
232 do { \ | |
233 unsigned int _tmp = INPLL(addr); \ | |
234 _tmp &= (mask); \ | |
235 _tmp |= (val); \ | |
236 OUTPLL(addr, _tmp); \ | |
237 } while (0) | |
238 | |
3996 | 239 static uint32_t radeon_vid_get_dbpp( void ) |
240 { | |
241 uint32_t dbpp,retval; | |
242 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; | |
243 switch(dbpp) | |
244 { | |
245 case DST_8BPP: retval = 8; break; | |
246 case DST_15BPP: retval = 15; break; | |
247 case DST_16BPP: retval = 16; break; | |
248 case DST_24BPP: retval = 24; break; | |
249 default: retval=32; break; | |
250 } | |
251 return retval; | |
252 } | |
253 | |
254 static int radeon_is_dbl_scan( void ) | |
255 { | |
256 return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; | |
257 } | |
258 | |
259 static int radeon_is_interlace( void ) | |
260 { | |
261 return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; | |
262 } | |
263 | |
4666 | 264 static uint32_t radeon_get_xres( void ) |
265 { | |
266 /* FIXME: currently we extract that from CRTC!!!*/ | |
267 uint32_t xres,h_total; | |
268 h_total = INREG(CRTC_H_TOTAL_DISP); | |
269 xres = (h_total >> 16) & 0xffff; | |
270 return (xres + 1)*8; | |
271 } | |
272 | |
273 static uint32_t radeon_get_yres( void ) | |
274 { | |
275 /* FIXME: currently we extract that from CRTC!!!*/ | |
276 uint32_t yres,v_total; | |
277 v_total = INREG(CRTC_V_TOTAL_DISP); | |
278 yres = (v_total >> 16) & 0xffff; | |
279 return yres + 1; | |
280 } | |
281 | |
4689 | 282 static void radeon_wait_vsync(void) |
283 { | |
284 int i; | |
285 | |
286 OUTREG(GEN_INT_STATUS, VSYNC_INT_AK); | |
287 for (i = 0; i < 2000000; i++) | |
288 { | |
289 if (INREG(GEN_INT_STATUS) & VSYNC_INT) break; | |
290 } | |
291 } | |
292 | |
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293 #ifdef RAGE128 |
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294 static void _radeon_engine_idle(void); |
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295 static void _radeon_fifo_wait(unsigned); |
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296 #define radeon_engine_idle() _radeon_engine_idle() |
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297 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) |
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298 /* Flush all dirty data in the Pixel Cache to memory. */ |
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299 static __inline__ void radeon_engine_flush ( void ) |
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300 { |
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301 unsigned i; |
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302 |
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303 OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL); |
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304 for (i = 0; i < 2000000; i++) { |
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305 if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break; |
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306 } |
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307 } |
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308 |
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309 /* Reset graphics card to known state. */ |
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310 static void radeon_engine_reset( void ) |
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311 { |
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312 uint32_t clock_cntl_index; |
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313 uint32_t mclk_cntl; |
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314 uint32_t gen_reset_cntl; |
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315 |
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316 radeon_engine_flush(); |
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317 |
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318 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); |
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319 mclk_cntl = INPLL(MCLK_CNTL); |
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320 |
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321 OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP); |
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322 |
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323 gen_reset_cntl = INREG(GEN_RESET_CNTL); |
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324 |
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325 OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); |
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326 INREG(GEN_RESET_CNTL); |
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327 OUTREG(GEN_RESET_CNTL, |
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328 gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI)); |
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329 INREG(GEN_RESET_CNTL); |
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330 |
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331 OUTPLL(MCLK_CNTL, mclk_cntl); |
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332 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); |
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333 OUTREG(GEN_RESET_CNTL, gen_reset_cntl); |
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334 } |
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335 #else |
4689 | 336 |
3996 | 337 static __inline__ void radeon_engine_flush ( void ) |
338 { | |
339 int i; | |
340 | |
341 /* initiate flush */ | |
342 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, | |
343 ~RB2D_DC_FLUSH_ALL); | |
344 | |
345 for (i=0; i < 2000000; i++) { | |
346 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) | |
347 break; | |
348 } | |
349 } | |
350 | |
4666 | 351 static void _radeon_engine_idle(void); |
352 static void _radeon_fifo_wait(unsigned); | |
353 #define radeon_engine_idle() _radeon_engine_idle() | |
354 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) | |
3996 | 355 |
4666 | 356 static void radeon_engine_reset( void ) |
3996 | 357 { |
4666 | 358 uint32_t clock_cntl_index, mclk_cntl, rbbm_soft_reset; |
359 | |
360 radeon_engine_flush (); | |
361 | |
362 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); | |
363 mclk_cntl = INPLL(MCLK_CNTL); | |
364 | |
365 OUTPLL(MCLK_CNTL, (mclk_cntl | | |
366 FORCEON_MCLKA | | |
367 FORCEON_MCLKB | | |
368 FORCEON_YCLKA | | |
369 FORCEON_YCLKB | | |
370 FORCEON_MC | | |
371 FORCEON_AIC)); | |
372 rbbm_soft_reset = INREG(RBBM_SOFT_RESET); | |
3996 | 373 |
4666 | 374 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | |
375 SOFT_RESET_CP | | |
376 SOFT_RESET_HI | | |
377 SOFT_RESET_SE | | |
378 SOFT_RESET_RE | | |
379 SOFT_RESET_PP | | |
380 SOFT_RESET_E2 | | |
381 SOFT_RESET_RB | | |
382 SOFT_RESET_HDP); | |
383 INREG(RBBM_SOFT_RESET); | |
384 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (uint32_t) | |
385 ~(SOFT_RESET_CP | | |
386 SOFT_RESET_HI | | |
387 SOFT_RESET_SE | | |
388 SOFT_RESET_RE | | |
389 SOFT_RESET_PP | | |
390 SOFT_RESET_E2 | | |
391 SOFT_RESET_RB | | |
392 SOFT_RESET_HDP)); | |
393 INREG(RBBM_SOFT_RESET); | |
394 | |
395 OUTPLL(MCLK_CNTL, mclk_cntl); | |
396 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); | |
397 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); | |
398 | |
399 return; | |
3996 | 400 } |
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401 #endif |
4666 | 402 static void radeon_engine_restore( void ) |
3996 | 403 { |
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404 #ifndef RAGE128 |
4666 | 405 int pitch64; |
406 uint32_t xres,yres,bpp; | |
407 radeon_fifo_wait(1); | |
408 xres = radeon_get_xres(); | |
409 yres = radeon_get_yres(); | |
410 bpp = radeon_vid_get_dbpp(); | |
411 /* turn of all automatic flushing - we'll do it all */ | |
412 OUTREG(RB2D_DSTCACHE_MODE, 0); | |
413 | |
414 pitch64 = ((xres * (bpp / 8) + 0x3f)) >> 6; | |
415 | |
416 radeon_fifo_wait(1); | |
417 OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) | | |
418 (pitch64 << 22)); | |
419 | |
420 radeon_fifo_wait(1); | |
421 #if defined(__BIG_ENDIAN) | |
422 OUTREGP(DP_DATATYPE, | |
423 HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); | |
424 #else | |
425 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); | |
426 #endif | |
427 | |
428 radeon_fifo_wait(1); | |
429 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | |
430 | DEFAULT_SC_BOTTOM_MAX)); | |
431 radeon_fifo_wait(1); | |
432 OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL) | |
433 | GMC_BRUSH_SOLID_COLOR | |
434 | GMC_SRC_DATATYPE_COLOR)); | |
3996 | 435 |
4666 | 436 radeon_fifo_wait(7); |
437 OUTREG(DST_LINE_START, 0); | |
438 OUTREG(DST_LINE_END, 0); | |
439 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); | |
440 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); | |
441 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); | |
442 OUTREG(DP_SRC_BKGD_CLR, 0x00000000); | |
443 OUTREG(DP_WRITE_MASK, 0xffffffff); | |
444 | |
445 radeon_engine_idle(); | |
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446 #endif |
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447 } |
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448 #ifdef RAGE128 |
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449 static void _radeon_fifo_wait (unsigned entries) |
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450 { |
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451 unsigned i; |
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452 |
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453 for(;;) |
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454 { |
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455 for (i=0; i<2000000; i++) |
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456 if ((INREG(GUI_STAT) & GUI_FIFOCNT_MASK) >= entries) |
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457 return; |
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458 radeon_engine_reset(); |
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459 radeon_engine_restore(); |
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460 } |
4666 | 461 } |
462 | |
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463 static void _radeon_engine_idle ( void ) |
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464 { |
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465 unsigned i; |
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466 |
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467 /* ensure FIFO is empty before waiting for idle */ |
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468 radeon_fifo_wait (64); |
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469 for(;;) |
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470 { |
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471 for (i=0; i<2000000; i++) { |
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472 if ((INREG(GUI_STAT) & GUI_ACTIVE) == 0) { |
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473 radeon_engine_flush (); |
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474 return; |
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475 } |
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476 } |
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477 radeon_engine_reset(); |
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478 radeon_engine_restore(); |
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479 } |
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480 } |
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481 #else |
4666 | 482 static void _radeon_fifo_wait (unsigned entries) |
483 { | |
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484 unsigned i; |
3996 | 485 |
4666 | 486 for(;;) |
487 { | |
488 for (i=0; i<2000000; i++) | |
489 if ((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries) | |
490 return; | |
491 radeon_engine_reset(); | |
492 radeon_engine_restore(); | |
493 } | |
494 } | |
495 static void _radeon_engine_idle ( void ) | |
496 { | |
497 int i; | |
498 | |
499 /* ensure FIFO is empty before waiting for idle */ | |
500 radeon_fifo_wait (64); | |
501 for(;;) | |
502 { | |
3996 | 503 for (i=0; i<2000000; i++) { |
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504 if (((INREG(RBBM_STATUS) & RBBM_ACTIVE)) == 0) { |
3996 | 505 radeon_engine_flush (); |
506 return; | |
507 } | |
508 } | |
4666 | 509 radeon_engine_reset(); |
510 radeon_engine_restore(); | |
511 } | |
3996 | 512 } |
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513 #endif |
3996 | 514 |
515 #ifndef RAGE128 | |
516 /* Reference color space transform data */ | |
517 typedef struct tagREF_TRANSFORM | |
518 { | |
519 float RefLuma; | |
520 float RefRCb; | |
521 float RefRCr; | |
522 float RefGCb; | |
523 float RefGCr; | |
524 float RefBCb; | |
525 float RefBCr; | |
526 } REF_TRANSFORM; | |
527 | |
528 /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ | |
529 REF_TRANSFORM trans[2] = | |
530 { | |
531 {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ | |
532 {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ | |
533 }; | |
534 /**************************************************************************** | |
535 * SetTransform * | |
536 * Function: Calculates and sets color space transform from supplied * | |
537 * reference transform, gamma, brightness, contrast, hue and * | |
538 * saturation. * | |
539 * Inputs: bright - brightness * | |
540 * cont - contrast * | |
541 * sat - saturation * | |
542 * hue - hue * | |
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543 * red_intensity - intense of red component * |
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544 * green_intensity - intense of green component * |
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545 * blue_intensity - intense of blue component * |
3996 | 546 * ref - index to the table of refernce transforms * |
547 * Outputs: NONE * | |
548 ****************************************************************************/ | |
549 | |
550 static void radeon_set_transform(float bright, float cont, float sat, | |
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551 float hue, float red_intensity, |
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552 float green_intensity,float blue_intensity, |
4284 | 553 unsigned ref) |
3996 | 554 { |
555 float OvHueSin, OvHueCos; | |
556 float CAdjLuma, CAdjOff; | |
4284 | 557 float RedAdj,GreenAdj,BlueAdj; |
3996 | 558 float CAdjRCb, CAdjRCr; |
559 float CAdjGCb, CAdjGCr; | |
560 float CAdjBCb, CAdjBCr; | |
561 float OvLuma, OvROff, OvGOff, OvBOff; | |
562 float OvRCb, OvRCr; | |
563 float OvGCb, OvGCr; | |
564 float OvBCb, OvBCr; | |
565 float Loff = 64.0; | |
566 float Coff = 512.0f; | |
567 | |
568 uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; | |
569 uint32_t dwOvRCb, dwOvRCr; | |
570 uint32_t dwOvGCb, dwOvGCr; | |
571 uint32_t dwOvBCb, dwOvBCr; | |
572 | |
573 if (ref >= 2) return; | |
574 | |
575 OvHueSin = sin((double)hue); | |
576 OvHueCos = cos((double)hue); | |
577 | |
578 CAdjLuma = cont * trans[ref].RefLuma; | |
579 CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; | |
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580 RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0; |
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581 GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0; |
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582 BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0; |
3996 | 583 |
584 CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; | |
585 CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; | |
586 CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); | |
587 CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); | |
588 CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; | |
589 CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; | |
590 | |
591 #if 0 /* default constants */ | |
592 CAdjLuma = 1.16455078125; | |
593 | |
594 CAdjRCb = 0.0; | |
595 CAdjRCr = 1.59619140625; | |
596 CAdjGCb = -0.39111328125; | |
597 CAdjGCr = -0.8125; | |
598 CAdjBCb = 2.01708984375; | |
599 CAdjBCr = 0; | |
600 #endif | |
601 OvLuma = CAdjLuma; | |
602 OvRCb = CAdjRCb; | |
603 OvRCr = CAdjRCr; | |
604 OvGCb = CAdjGCb; | |
605 OvGCr = CAdjGCr; | |
606 OvBCb = CAdjBCb; | |
607 OvBCr = CAdjBCr; | |
4284 | 608 OvROff = RedAdj + CAdjOff - |
3996 | 609 OvLuma * Loff - (OvRCb + OvRCr) * Coff; |
4284 | 610 OvGOff = GreenAdj + CAdjOff - |
3996 | 611 OvLuma * Loff - (OvGCb + OvGCr) * Coff; |
4284 | 612 OvBOff = BlueAdj + CAdjOff - |
3996 | 613 OvLuma * Loff - (OvBCb + OvBCr) * Coff; |
614 #if 0 /* default constants */ | |
615 OvROff = -888.5; | |
616 OvGOff = 545; | |
617 OvBOff = -1104; | |
618 #endif | |
619 | |
620 dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; | |
621 dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; | |
622 dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; | |
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623 /* Whatever docs say about R200 having 3.8 format instead of 3.11 |
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624 as in Radeon is a lie */ |
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625 #if 0 |
3996 | 626 if(!IsR200) |
627 { | |
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628 #endif |
3996 | 629 dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; |
630 dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; | |
631 dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; | |
632 dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; | |
633 dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; | |
634 dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; | |
635 dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; | |
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636 #if 0 |
3996 | 637 } |
638 else | |
639 { | |
640 dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; | |
641 dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; | |
642 dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; | |
643 dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; | |
644 dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; | |
645 dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; | |
646 dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; | |
647 } | |
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intense->intensity + capability extension + fixing R200 color correction bug
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changeset
|
648 #endif |
3996 | 649 OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); |
650 OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); | |
651 OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); | |
652 OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); | |
653 OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); | |
654 OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); | |
655 } | |
656 | |
657 /* Gamma curve definition */ | |
658 typedef struct | |
659 { | |
660 unsigned int gammaReg; | |
661 unsigned int gammaSlope; | |
662 unsigned int gammaOffset; | |
663 }GAMMA_SETTINGS; | |
664 | |
665 /* Recommended gamma curve parameters */ | |
666 GAMMA_SETTINGS r200_def_gamma[18] = | |
667 { | |
668 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
669 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
670 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
671 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
672 {OV0_GAMMA_80_BF, 0x100, 0x0100}, | |
673 {OV0_GAMMA_C0_FF, 0x100, 0x0100}, | |
674 {OV0_GAMMA_100_13F, 0x100, 0x0200}, | |
675 {OV0_GAMMA_140_17F, 0x100, 0x0200}, | |
676 {OV0_GAMMA_180_1BF, 0x100, 0x0300}, | |
677 {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, | |
678 {OV0_GAMMA_200_23F, 0x100, 0x0400}, | |
679 {OV0_GAMMA_240_27F, 0x100, 0x0400}, | |
680 {OV0_GAMMA_280_2BF, 0x100, 0x0500}, | |
681 {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, | |
682 {OV0_GAMMA_300_33F, 0x100, 0x0600}, | |
683 {OV0_GAMMA_340_37F, 0x100, 0x0600}, | |
684 {OV0_GAMMA_380_3BF, 0x100, 0x0700}, | |
685 {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} | |
686 }; | |
687 | |
688 GAMMA_SETTINGS r100_def_gamma[6] = | |
689 { | |
690 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
691 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
692 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
693 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
694 {OV0_GAMMA_380_3BF, 0x100, 0x0100}, | |
695 {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} | |
696 }; | |
697 | |
698 static void make_default_gamma_correction( void ) | |
699 { | |
700 size_t i; | |
701 if(!IsR200){ | |
702 OUTREG(OV0_LIN_TRANS_A, 0x12A00000); | |
703 OUTREG(OV0_LIN_TRANS_B, 0x199018FE); | |
704 OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); | |
705 OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); | |
706 OUTREG(OV0_LIN_TRANS_E, 0x12A02050); | |
707 OUTREG(OV0_LIN_TRANS_F, 0x0000174E); | |
708 for(i=0; i<6; i++){ | |
709 OUTREG(r100_def_gamma[i].gammaReg, | |
710 (r100_def_gamma[i].gammaSlope<<16) | | |
711 r100_def_gamma[i].gammaOffset); | |
712 } | |
713 } | |
714 else{ | |
715 OUTREG(OV0_LIN_TRANS_A, 0x12a00000); | |
716 OUTREG(OV0_LIN_TRANS_B, 0x1990190e); | |
717 OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); | |
718 OUTREG(OV0_LIN_TRANS_D, 0xf3000442); | |
719 OUTREG(OV0_LIN_TRANS_E, 0x12a02040); | |
720 OUTREG(OV0_LIN_TRANS_F, 0x175f); | |
721 | |
722 /* Default Gamma, | |
723 Of 18 segments for gamma cure, all segments in R200 are programmable, | |
724 while only lower 4 and upper 2 segments are programmable in Radeon*/ | |
725 for(i=0; i<18; i++){ | |
726 OUTREG(r200_def_gamma[i].gammaReg, | |
727 (r200_def_gamma[i].gammaSlope<<16) | | |
728 r200_def_gamma[i].gammaOffset); | |
729 } | |
730 } | |
731 } | |
732 #endif | |
733 | |
734 static void radeon_vid_make_default(void) | |
735 { | |
736 #ifdef RAGE128 | |
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changeset
|
737 OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brightness and saturation for Rage128 */ |
3996 | 738 #else |
739 make_default_gamma_correction(); | |
740 #endif | |
741 besr.deinterlace_pattern = 0x900AAAAA; | |
742 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
743 besr.deinterlace_on=1; | |
744 besr.double_buff=1; | |
4869 | 745 besr.ckey_on=0; |
746 besr.graphics_key_msk=0; | |
747 besr.graphics_key_clr=0; | |
5044
43dc579db3d1
Fixed color key definitions. Waiting for new bugreports ;)
nick
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diff
changeset
|
748 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; |
3996 | 749 } |
750 | |
751 | |
752 unsigned vixGetVersion( void ) { return VIDIX_VERSION; } | |
753 | |
4107 | 754 static unsigned short ati_card_ids[] = |
3996 | 755 { |
756 #ifdef RAGE128 | |
757 /* | |
758 This driver should be compatible with Rage128 (pro) chips. | |
759 (include adaptive deinterlacing!!!). | |
760 Moreover: the same logic can be used with Mach64 chips. | |
761 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
762 but they are incompatible by i/o ports. So if enthusiasts will want | |
763 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
764 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
765 fourccs (422 and 420 formats only). | |
766 */ | |
767 /* Rage128 Pro GL */ | |
4107 | 768 DEVICE_ATI_RAGE_128_PA_PRO, |
769 DEVICE_ATI_RAGE_128_PB_PRO, | |
770 DEVICE_ATI_RAGE_128_PC_PRO, | |
771 DEVICE_ATI_RAGE_128_PD_PRO, | |
772 DEVICE_ATI_RAGE_128_PE_PRO, | |
773 DEVICE_ATI_RAGE_128_PF_PRO, | |
3996 | 774 /* Rage128 Pro VR */ |
4107 | 775 DEVICE_ATI_RAGE_128_PG_PRO, |
776 DEVICE_ATI_RAGE_128_PH_PRO, | |
777 DEVICE_ATI_RAGE_128_PI_PRO, | |
778 DEVICE_ATI_RAGE_128_PJ_PRO, | |
779 DEVICE_ATI_RAGE_128_PK_PRO, | |
780 DEVICE_ATI_RAGE_128_PL_PRO, | |
781 DEVICE_ATI_RAGE_128_PM_PRO, | |
782 DEVICE_ATI_RAGE_128_PN_PRO, | |
783 DEVICE_ATI_RAGE_128_PO_PRO, | |
784 DEVICE_ATI_RAGE_128_PP_PRO, | |
785 DEVICE_ATI_RAGE_128_PQ_PRO, | |
786 DEVICE_ATI_RAGE_128_PR_PRO, | |
787 DEVICE_ATI_RAGE_128_PS_PRO, | |
788 DEVICE_ATI_RAGE_128_PT_PRO, | |
789 DEVICE_ATI_RAGE_128_PU_PRO, | |
790 DEVICE_ATI_RAGE_128_PV_PRO, | |
791 DEVICE_ATI_RAGE_128_PW_PRO, | |
792 DEVICE_ATI_RAGE_128_PX_PRO, | |
3996 | 793 /* Rage128 GL */ |
4107 | 794 DEVICE_ATI_RAGE_128_RE_SG, |
795 DEVICE_ATI_RAGE_128_RF_SG, | |
796 DEVICE_ATI_RAGE_128_RG, | |
797 DEVICE_ATI_RAGE_128_RK_VR, | |
798 DEVICE_ATI_RAGE_128_RL_VR, | |
799 DEVICE_ATI_RAGE_128_SE_4X, | |
800 DEVICE_ATI_RAGE_128_SF_4X, | |
801 DEVICE_ATI_RAGE_128_SG_4X, | |
802 DEVICE_ATI_RAGE_128_4X, | |
803 DEVICE_ATI_RAGE_128_SK_4X, | |
804 DEVICE_ATI_RAGE_128_SL_4X, | |
805 DEVICE_ATI_RAGE_128_SM_4X, | |
806 DEVICE_ATI_RAGE_128_4X2, | |
807 DEVICE_ATI_RAGE_128_PRO, | |
808 DEVICE_ATI_RAGE_128_PRO2, | |
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rage mobility m3 is rage128 based and not mach64 ...
michael
parents:
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diff
changeset
|
809 DEVICE_ATI_RAGE_128_PRO3, |
51fcb1e5c96e
rage mobility m3 is rage128 based and not mach64 ...
michael
parents:
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diff
changeset
|
810 /* these seem to be based on rage 128 instead of mach64 */ |
51fcb1e5c96e
rage mobility m3 is rage128 based and not mach64 ...
michael
parents:
5044
diff
changeset
|
811 DEVICE_ATI_RAGE_MOBILITY_M3, |
51fcb1e5c96e
rage mobility m3 is rage128 based and not mach64 ...
michael
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|
812 DEVICE_ATI_RAGE_MOBILITY_M32 |
3996 | 813 #else |
814 /* Radeons (indeed: Rage 256 Pro ;) */ | |
4107 | 815 DEVICE_ATI_RADEON_8500_DV, |
816 DEVICE_ATI_RADEON_MOBILITY_M6, | |
817 DEVICE_ATI_RADEON_MOBILITY_M62, | |
818 DEVICE_ATI_RADEON_MOBILITY_M63, | |
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Radeon Mobility M6 LX support by Daniel Pittman <daniel@rimspace.net>
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changeset
|
819 DEVICE_ATI_RADEON_MOBILITY_M64, |
4107 | 820 DEVICE_ATI_RADEON_QD, |
821 DEVICE_ATI_RADEON_QE, | |
822 DEVICE_ATI_RADEON_QF, | |
823 DEVICE_ATI_RADEON_QG, | |
824 DEVICE_ATI_RADEON_QL, | |
825 DEVICE_ATI_RADEON_QW, | |
826 DEVICE_ATI_RADEON_VE_QY, | |
827 DEVICE_ATI_RADEON_VE_QZ | |
3996 | 828 #endif |
829 }; | |
830 | |
831 static int find_chip(unsigned chip_id) | |
832 { | |
833 unsigned i; | |
4107 | 834 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) |
3996 | 835 { |
4107 | 836 if(chip_id == ati_card_ids[i]) return i; |
3996 | 837 } |
838 return -1; | |
839 } | |
840 | |
841 pciinfo_t pci_info; | |
842 static int probed=0; | |
843 | |
844 vidix_capability_t def_cap = | |
845 { | |
846 #ifdef RAGE128 | |
847 "BES driver for rage128 cards", | |
848 #else | |
849 "BES driver for radeon cards", | |
850 #endif | |
4327 | 851 "Nick Kurshev", |
3996 | 852 TYPE_OUTPUT | TYPE_FX, |
4191 | 853 { 0, 0, 0, 0 }, |
4282 | 854 2048, |
855 2048, | |
3996 | 856 4, |
857 4, | |
858 -1, | |
4264 | 859 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, |
4134 | 860 VENDOR_ATI, |
3996 | 861 0, |
862 { 0, 0, 0, 0} | |
863 }; | |
864 | |
865 | |
4191 | 866 int vixProbe( int verbose,int force ) |
3996 | 867 { |
868 pciinfo_t lst[MAX_PCI_DEVICES]; | |
869 unsigned i,num_pci; | |
870 int err; | |
4030 | 871 __verbose = verbose; |
3996 | 872 err = pci_scan(lst,&num_pci); |
873 if(err) | |
874 { | |
875 printf(RADEON_MSG" Error occured during pci scan: %s\n",strerror(err)); | |
876 return err; | |
877 } | |
878 else | |
879 { | |
880 err = ENXIO; | |
881 for(i=0;i<num_pci;i++) | |
882 { | |
4107 | 883 if(lst[i].vendor == VENDOR_ATI) |
3996 | 884 { |
885 int idx; | |
4191 | 886 const char *dname; |
3996 | 887 idx = find_chip(lst[i].device); |
4191 | 888 if(idx == -1 && force == PROBE_NORMAL) continue; |
889 dname = pci_device_name(VENDOR_ATI,lst[i].device); | |
890 dname = dname ? dname : "Unknown chip"; | |
891 printf(RADEON_MSG" Found chip: %s\n",dname); | |
3996 | 892 #ifndef RAGE128 |
4191 | 893 if(idx != -1) |
894 if(ati_card_ids[idx] == DEVICE_ATI_RADEON_QL || | |
895 ati_card_ids[idx] == DEVICE_ATI_RADEON_8500_DV || | |
896 ati_card_ids[idx] == DEVICE_ATI_RADEON_QW) IsR200 = 1; | |
3996 | 897 #endif |
4193 | 898 if(force > PROBE_NORMAL) |
899 { | |
900 printf(RADEON_MSG" Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); | |
901 if(idx == -1) | |
902 #ifdef RAGE128 | |
4373 | 903 printf(RADEON_MSG" Assuming it as Rage128\n"); |
4193 | 904 #else |
4373 | 905 printf(RADEON_MSG" Assuming it as Radeon1\n"); |
4193 | 906 #endif |
907 } | |
4191 | 908 def_cap.device_id = lst[i].device; |
3996 | 909 err = 0; |
910 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); | |
911 probed=1; | |
912 break; | |
913 } | |
914 } | |
915 } | |
916 if(err && verbose) printf(RADEON_MSG" Can't find chip\n"); | |
917 return err; | |
918 } | |
919 | |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
920 static void radeon_vid_dump_regs( void ); /* forward declaration */ |
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
921 |
3996 | 922 int vixInit( void ) |
923 { | |
4477 | 924 int err; |
4012 | 925 if(!probed) |
926 { | |
927 printf(RADEON_MSG" Driver was not probed but is being initializing\n"); | |
928 return EINTR; | |
929 } | |
930 if((radeon_mmio_base = map_phys_mem(pci_info.base2,0xFFFF))==(void *)-1) return ENOMEM; | |
3996 | 931 radeon_ram_size = INREG(CONFIG_MEMSIZE); |
932 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ | |
933 radeon_ram_size &= CONFIG_MEMSIZE_MASK; | |
934 if((radeon_mem_base = map_phys_mem(pci_info.base0,radeon_ram_size))==(void *)-1) return ENOMEM; | |
4070
b61ba6c256dd
Minor interface changes: color and video keys are moved out from playback configuring
nick
parents:
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diff
changeset
|
935 memset(&besr,0,sizeof(bes_registers_t)); |
3996 | 936 radeon_vid_make_default(); |
937 printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); | |
4477 | 938 err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB); |
939 if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n"); | |
8521
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
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changeset
|
940 |
8553
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
941 radeon_fifo_wait(3); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
942 SAVED_OV0_GRAPHICS_KEY_CLR = INREG(OV0_GRAPHICS_KEY_CLR); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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changeset
|
943 SAVED_OV0_GRAPHICS_KEY_MSK = INREG(OV0_GRAPHICS_KEY_MSK); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
944 SAVED_OV0_VID_KEY_CLR = INREG(OV0_VID_KEY_CLR); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
945 SAVED_OV0_VID_KEY_MSK = INREG(OV0_VID_KEY_MSK); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
946 SAVED_OV0_KEY_CNTL = INREG(OV0_KEY_CNTL); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
947 printf(RADEON_MSG" Saved overlay colorkey settings\n"); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
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diff
changeset
|
948 |
8521
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
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changeset
|
949 #ifdef RADEON |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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950 switch(def_cap.device_id) |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
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|
951 { |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
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changeset
|
952 case DEVICE_ATI_RADEON_QW: |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
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changeset
|
953 case DEVICE_ATI_RADEON_MOBILITY_M6: |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
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changeset
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954 case DEVICE_ATI_RADEON_MOBILITY_M62: |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
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changeset
|
955 case DEVICE_ATI_RADEON_MOBILITY_M63: |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
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diff
changeset
|
956 case DEVICE_ATI_RADEON_MOBILITY_M64: |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
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changeset
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957 rage_ckey_model=1; |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
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958 is_shift_required=1; |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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parents:
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changeset
|
959 break; |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
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changeset
|
960 case DEVICE_ATI_RADEON_QD: |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
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changeset
|
961 case DEVICE_ATI_RADEON_QE: |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
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changeset
|
962 case DEVICE_ATI_RADEON_QF: |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
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changeset
|
963 case DEVICE_ATI_RADEON_QG: |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
8238
diff
changeset
|
964 case DEVICE_ATI_RADEON_VE_QY: |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
8238
diff
changeset
|
965 case DEVICE_ATI_RADEON_VE_QZ: |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
8238
diff
changeset
|
966 is_shift_required=1; |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
8238
diff
changeset
|
967 break; |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
8238
diff
changeset
|
968 default: break; |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
8238
diff
changeset
|
969 } |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
8238
diff
changeset
|
970 #endif |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
8238
diff
changeset
|
971 |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
972 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 973 return 0; |
974 } | |
975 | |
976 void vixDestroy( void ) | |
977 { | |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
978 /* remove colorkeying */ |
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
979 radeon_fifo_wait(3); |
8553
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
980 OUTREG(OV0_GRAPHICS_KEY_CLR, SAVED_OV0_GRAPHICS_KEY_CLR); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
981 OUTREG(OV0_GRAPHICS_KEY_MSK, SAVED_OV0_GRAPHICS_KEY_MSK); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
982 OUTREG(OV0_VID_KEY_CLR, SAVED_OV0_VID_KEY_CLR); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
983 OUTREG(OV0_VID_KEY_MSK, SAVED_OV0_VID_KEY_MSK); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
984 OUTREG(OV0_KEY_CNTL, SAVED_OV0_KEY_CNTL); |
d952b097c720
correctly save and restore colorkey settings (based on patch by Svante Signell <svante.signell@telia.com>)
alex
parents:
8521
diff
changeset
|
985 printf(RADEON_MSG" Restored overlay colorkey settings\n"); |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
986 |
3996 | 987 unmap_phys_mem(radeon_mem_base,radeon_ram_size); |
4855 | 988 unmap_phys_mem(radeon_mmio_base,0xFFFF); |
3996 | 989 } |
990 | |
991 int vixGetCapability(vidix_capability_t *to) | |
992 { | |
993 memcpy(to,&def_cap,sizeof(vidix_capability_t)); | |
994 return 0; | |
995 } | |
996 | |
6483 | 997 /* |
998 Full list of fourcc which are supported by Win2K redeon driver: | |
6564
652ada9f9b66
remove colorkeying if destroying the driver - fixes some bugs
alex
parents:
6483
diff
changeset
|
999 YUY2, UYVY, DDES, OGLT, OGL2, OGLS, OGLB, OGNT, OGNZ, OGNS, |
6483 | 1000 IF09, YVU9, IMC4, M2IA, IYUV, VBID, DXT1, DXT2, DXT3, DXT4, DXT5 |
1001 */ | |
3996 | 1002 uint32_t supported_fourcc[] = |
1003 { | |
6483 | 1004 IMGFMT_Y800, IMGFMT_Y8, IMGFMT_YVU9, IMGFMT_IF09, |
3996 | 1005 IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV, |
4455 | 1006 IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU, |
4429 | 1007 IMGFMT_RGB15, IMGFMT_BGR15, |
4416 | 1008 IMGFMT_RGB16, IMGFMT_BGR16, |
1009 IMGFMT_RGB32, IMGFMT_BGR32 | |
3996 | 1010 }; |
1011 | |
6483 | 1012 inline static int is_supported_fourcc(uint32_t fourcc) |
3996 | 1013 { |
6483 | 1014 unsigned int i; |
3996 | 1015 for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++) |
1016 { | |
1017 if(fourcc==supported_fourcc[i]) return 1; | |
1018 } | |
1019 return 0; | |
1020 } | |
1021 | |
1022 int vixQueryFourcc(vidix_fourcc_t *to) | |
1023 { | |
1024 if(is_supported_fourcc(to->fourcc)) | |
1025 { | |
1026 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
1027 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
1028 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
1029 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
1030 VID_DEPTH_32BPP; | |
5044
43dc579db3d1
Fixed color key definitions. Waiting for new bugreports ;)
nick
parents:
5041
diff
changeset
|
1031 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; |
3996 | 1032 return 0; |
1033 } | |
4015 | 1034 else to->depth = to->flags = 0; |
3996 | 1035 return ENOSYS; |
1036 } | |
1037 | |
1038 static void radeon_vid_dump_regs( void ) | |
1039 { | |
1040 size_t i; | |
4015 | 1041 printf(RADEON_MSG"*** Begin of DRIVER variables dump ***\n"); |
1042 printf(RADEON_MSG"radeon_mmio_base=%p\n",radeon_mmio_base); | |
1043 printf(RADEON_MSG"radeon_mem_base=%p\n",radeon_mem_base); | |
1044 printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off); | |
1045 printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size); | |
4666 | 1046 printf(RADEON_MSG"video mode: %ux%u@%u\n",radeon_get_xres(),radeon_get_yres(),radeon_vid_get_dbpp()); |
4015 | 1047 printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n"); |
3996 | 1048 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) |
4015 | 1049 printf(RADEON_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); |
1050 printf(RADEON_MSG"*** End of OV0 registers dump ***\n"); | |
3996 | 1051 } |
1052 | |
1053 static void radeon_vid_stop_video( void ) | |
1054 { | |
1055 radeon_engine_idle(); | |
1056 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
1057 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
1058 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
1059 OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); | |
1060 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); | |
1061 OUTREG(OV0_TEST, 0); | |
1062 } | |
1063 | |
1064 static void radeon_vid_display_video( void ) | |
1065 { | |
1066 int bes_flags; | |
1067 radeon_fifo_wait(2); | |
1068 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1069 radeon_engine_idle(); | |
1070 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1071 radeon_fifo_wait(15); | |
4666 | 1072 |
1073 /* Shutdown capturing */ | |
1074 OUTREG(FCP_CNTL, FCP_CNTL__GND); | |
1075 OUTREG(CAP0_TRIG_CNTL, 0); | |
1076 | |
4689 | 1077 OUTREG(VID_BUFFER_CONTROL, (1<<16) | 0x01); |
1078 OUTREG(DISP_TEST_DEBUG_CNTL, 0); | |
4666 | 1079 |
3996 | 1080 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); |
1081 | |
4611 | 1082 if(besr.deinterlace_on) OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); |
3996 | 1083 #ifdef RAGE128 |
7493 | 1084 OUTREG(OV0_COLOUR_CNTL, (((besr.brightness*64)/1000) & 0x7f) | |
1085 (((besr.saturation*31+31000)/2000) << 8) | | |
1086 (((besr.saturation*31+31000)/2000) << 16)); | |
3996 | 1087 #endif |
1088 radeon_fifo_wait(2); | |
4869 | 1089 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); |
1090 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1091 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
3996 | 1092 |
1093 OUTREG(OV0_H_INC, besr.h_inc); | |
1094 OUTREG(OV0_STEP_BY, besr.step_by); | |
1095 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
1096 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
1097 OUTREG(OV0_V_INC, besr.v_inc); | |
1098 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
1099 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); | |
1100 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); | |
1101 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); | |
1102 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); | |
1103 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
1104 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
1105 #ifdef RADEON | |
1106 OUTREG(OV0_BASE_ADDR, besr.base_addr); | |
1107 #endif | |
4930 | 1108 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); |
5041 | 1109 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); |
1110 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
3996 | 1111 radeon_fifo_wait(9); |
4930 | 1112 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); |
5041 | 1113 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); |
1114 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
3996 | 1115 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); |
1116 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
1117 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
1118 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); | |
1119 | |
6678 | 1120 #ifdef RADEON |
1121 bes_flags = SCALER_ENABLE | | |
1122 SCALER_SMART_SWITCH; | |
1123 // SCALER_HORZ_PICK_NEAREST | | |
1124 // SCALER_VERT_PICK_NEAREST | | |
1125 #endif | |
3996 | 1126 bes_flags = SCALER_ENABLE | |
1127 SCALER_SMART_SWITCH | | |
1128 SCALER_Y2R_TEMP | | |
1129 SCALER_PIX_EXPAND; | |
1130 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; | |
1131 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
1132 #ifdef RAGE128 | |
1133 bes_flags |= SCALER_BURST_PER_PLANE; | |
1134 #endif | |
1135 switch(besr.fourcc) | |
1136 { | |
1137 case IMGFMT_RGB15: | |
1138 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
4429 | 1139 case IMGFMT_RGB16: |
3996 | 1140 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; |
4416 | 1141 /* |
3996 | 1142 case IMGFMT_RGB24: |
1143 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
4416 | 1144 */ |
3996 | 1145 case IMGFMT_RGB32: |
1146 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
6483 | 1147 /* 4:1:0 */ |
3996 | 1148 case IMGFMT_IF09: |
1149 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; | |
6483 | 1150 /* 4:0:0 */ |
1151 case IMGFMT_Y800: | |
1152 case IMGFMT_Y8: | |
3996 | 1153 /* 4:2:0 */ |
1154 case IMGFMT_IYUV: | |
1155 case IMGFMT_I420: | |
6483 | 1156 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break; |
3996 | 1157 /* 4:2:2 */ |
4455 | 1158 case IMGFMT_YVYU: |
3996 | 1159 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; |
1160 case IMGFMT_YUY2: | |
1161 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
1162 } | |
1163 OUTREG(OV0_SCALE_CNTL, bes_flags); | |
1164 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
4666 | 1165 if(__verbose > 1) printf(RADEON_MSG"we wanted: scaler=%08X\n",bes_flags); |
4030 | 1166 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1167 } |
1168 | |
4456 | 1169 static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) |
4009 | 1170 { |
4456 | 1171 unsigned pitch,spy,spv,spu; |
1172 spy = spv = spu = 0; | |
1173 switch(spitch->y) | |
1174 { | |
1175 case 16: | |
1176 case 32: | |
1177 case 64: | |
1178 case 128: | |
1179 case 256: spy = spitch->y; break; | |
1180 default: break; | |
1181 } | |
1182 switch(spitch->u) | |
1183 { | |
1184 case 16: | |
1185 case 32: | |
1186 case 64: | |
1187 case 128: | |
1188 case 256: spu = spitch->u; break; | |
1189 default: break; | |
1190 } | |
1191 switch(spitch->v) | |
1192 { | |
1193 case 16: | |
1194 case 32: | |
1195 case 64: | |
1196 case 128: | |
1197 case 256: spv = spitch->v; break; | |
1198 default: break; | |
1199 } | |
4009 | 1200 switch(fourcc) |
1201 { | |
1202 /* 4:2:0 */ | |
1203 case IMGFMT_IYUV: | |
1204 case IMGFMT_YV12: | |
4456 | 1205 case IMGFMT_I420: |
1206 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; | |
1207 else pitch = 32; | |
1208 break; | |
6483 | 1209 /* 4:1:0 */ |
1210 case IMGFMT_IF09: | |
6254
034b12194350
rage128/radeon fixes, mach64 mess^H^H^H^Hcleanup, pm3 driver.
arpi
parents:
5165
diff
changeset
|
1211 case IMGFMT_YVU9: |
034b12194350
rage128/radeon fixes, mach64 mess^H^H^H^Hcleanup, pm3 driver.
arpi
parents:
5165
diff
changeset
|
1212 if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; |
034b12194350
rage128/radeon fixes, mach64 mess^H^H^H^Hcleanup, pm3 driver.
arpi
parents:
5165
diff
changeset
|
1213 else pitch = 64; |
034b12194350
rage128/radeon fixes, mach64 mess^H^H^H^Hcleanup, pm3 driver.
arpi
parents:
5165
diff
changeset
|
1214 break; |
4456 | 1215 default: |
1216 if(spy >= 16) pitch = spy; | |
1217 else pitch = 16; | |
1218 break; | |
4009 | 1219 } |
1220 return pitch; | |
1221 } | |
1222 | |
3996 | 1223 static int radeon_vid_init_video( vidix_playback_t *config ) |
1224 { | |
4930 | 1225 uint32_t i,tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top; |
6483 | 1226 int is_400,is_410,is_420,is_rgb32,is_rgb,best_pitch,mpitch; |
3996 | 1227 radeon_vid_stop_video(); |
1228 left = config->src.x << 16; | |
1229 top = config->src.y << 16; | |
1230 src_h = config->src.h; | |
1231 src_w = config->src.w; | |
6483 | 1232 is_400 = is_410 = is_420 = is_rgb32 = is_rgb = 0; |
3996 | 1233 if(config->fourcc == IMGFMT_YV12 || |
1234 config->fourcc == IMGFMT_I420 || | |
1235 config->fourcc == IMGFMT_IYUV) is_420 = 1; | |
6483 | 1236 if(config->fourcc == IMGFMT_YVU9 || |
1237 config->fourcc == IMGFMT_IF09) is_410 = 1; | |
1238 if(config->fourcc == IMGFMT_Y800 || | |
1239 config->fourcc == IMGFMT_Y8) is_400 = 1; | |
4416 | 1240 if(config->fourcc == IMGFMT_RGB32 || |
1241 config->fourcc == IMGFMT_BGR32) is_rgb32 = 1; | |
4571 | 1242 if(config->fourcc == IMGFMT_RGB32 || |
1243 config->fourcc == IMGFMT_BGR32 || | |
1244 config->fourcc == IMGFMT_RGB24 || | |
1245 config->fourcc == IMGFMT_BGR24 || | |
1246 config->fourcc == IMGFMT_RGB16 || | |
1247 config->fourcc == IMGFMT_BGR16 || | |
1248 config->fourcc == IMGFMT_RGB15 || | |
1249 config->fourcc == IMGFMT_BGR15) is_rgb = 1; | |
4456 | 1250 best_pitch = radeon_query_pitch(config->fourcc,&config->src.pitch); |
4415 | 1251 mpitch = best_pitch-1; |
3996 | 1252 switch(config->fourcc) |
1253 { | |
6483 | 1254 /* 4:0:0 */ |
1255 case IMGFMT_Y800: | |
1256 case IMGFMT_Y8: | |
1257 /* 4:1:0 */ | |
6254
034b12194350
rage128/radeon fixes, mach64 mess^H^H^H^Hcleanup, pm3 driver.
arpi
parents:
5165
diff
changeset
|
1258 case IMGFMT_YVU9: |
6483 | 1259 case IMGFMT_IF09: |
3996 | 1260 /* 4:2:0 */ |
1261 case IMGFMT_IYUV: | |
1262 case IMGFMT_YV12: | |
4415 | 1263 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; |
4015 | 1264 config->dest.pitch.y = |
1265 config->dest.pitch.u = | |
4415 | 1266 config->dest.pitch.v = best_pitch; |
3996 | 1267 break; |
4416 | 1268 /* RGB 4:4:4:4 */ |
1269 case IMGFMT_RGB32: | |
1270 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; | |
1271 config->dest.pitch.y = | |
1272 config->dest.pitch.u = | |
1273 config->dest.pitch.v = best_pitch; | |
1274 break; | |
3996 | 1275 /* 4:2:2 */ |
4455 | 1276 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ |
4415 | 1277 pitch = ((src_w*2) + mpitch) & ~mpitch; |
3996 | 1278 config->dest.pitch.y = |
1279 config->dest.pitch.u = | |
4415 | 1280 config->dest.pitch.v = best_pitch; |
3996 | 1281 break; |
1282 } | |
1283 dest_w = config->dest.w; | |
1284 dest_h = config->dest.h; | |
1285 if(radeon_is_dbl_scan()) dest_h *= 2; | |
1286 besr.dest_bpp = radeon_vid_get_dbpp(); | |
1287 besr.fourcc = config->fourcc; | |
1288 besr.v_inc = (src_h << 20) / dest_h; | |
6254
034b12194350
rage128/radeon fixes, mach64 mess^H^H^H^Hcleanup, pm3 driver.
arpi
parents:
5165
diff
changeset
|
1289 if(radeon_is_interlace()) besr.v_inc *= 2; |
3996 | 1290 h_inc = (src_w << 12) / dest_w; |
1291 step_by = 1; | |
1292 while(h_inc >= (2 << 12)) { | |
1293 step_by++; | |
1294 h_inc >>= 1; | |
1295 } | |
1296 | |
1297 /* keep everything in 16.16 */ | |
4015 | 1298 besr.base_addr = INREG(DISPLAY_BASE_ADDR); |
4666 | 1299 config->offsets[0] = 0; |
4930 | 1300 for(i=1;i<besr.vid_nbufs;i++) |
1301 config->offsets[i] = config->offsets[i-1]+config->frame_size; | |
6483 | 1302 if(is_420 || is_410 || is_400) |
3996 | 1303 { |
1304 uint32_t d1line,d2line,d3line; | |
1305 d1line = top*pitch; | |
6483 | 1306 if(is_420) |
1307 { | |
1308 d2line = src_h*pitch+(d1line>>2); | |
1309 d3line = d2line+((src_h*pitch)>>2); | |
1310 } | |
1311 else | |
1312 if(is_410) | |
1313 { | |
1314 d2line = src_h*pitch+(d1line>>4); | |
1315 d3line = d2line+((src_h*pitch)>>4); | |
1316 } | |
1317 else | |
1318 { | |
1319 d2line = 0; | |
1320 d3line = 0; | |
1321 } | |
3996 | 1322 d1line += (left >> 16) & ~15; |
6483 | 1323 if(is_420) |
1324 { | |
1325 d2line += (left >> 17) & ~15; | |
1326 d3line += (left >> 17) & ~15; | |
1327 } | |
1328 else | |
1329 if(is_410) | |
1330 { | |
1331 d2line += (left >> 18) & ~15; | |
1332 d3line += (left >> 18) & ~15; | |
1333 } | |
3996 | 1334 config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK; |
6483 | 1335 if(is_400) |
1336 { | |
1337 config->offset.v = 0; | |
1338 config->offset.u = 0; | |
1339 } | |
1340 else | |
1341 { | |
1342 config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; | |
1343 config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; | |
1344 } | |
4930 | 1345 for(i=0;i<besr.vid_nbufs;i++) |
1346 { | |
1347 besr.vid_buf_base_adrs_y[i]=((radeon_overlay_off+config->offsets[i]+config->offset.y)&VIF_BUF0_BASE_ADRS_MASK); | |
6483 | 1348 if(is_400) |
1349 { | |
1350 besr.vid_buf_base_adrs_v[i]=0; | |
1351 besr.vid_buf_base_adrs_u[i]=0; | |
1352 } | |
1353 else | |
1354 { | |
1355 besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
1356 besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
1357 } | |
4930 | 1358 } |
1359 config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off; | |
6483 | 1360 if(is_400) |
1361 { | |
1362 config->offset.v = 0; | |
1363 config->offset.u = 0; | |
1364 } | |
1365 else | |
1366 { | |
1367 config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off; | |
1368 config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off; | |
1369 } | |
3996 | 1370 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) |
1371 { | |
1372 uint32_t tmp; | |
1373 tmp = config->offset.u; | |
1374 config->offset.u = config->offset.v; | |
1375 config->offset.v = tmp; | |
1376 } | |
1377 } | |
1378 else | |
1379 { | |
1380 config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; | |
4930 | 1381 for(i=0;i<besr.vid_nbufs;i++) |
1382 { | |
1383 besr.vid_buf_base_adrs_y[i] = | |
1384 besr.vid_buf_base_adrs_u[i] = | |
4932 | 1385 besr.vid_buf_base_adrs_v[i] = radeon_overlay_off + config->offsets[i] + config->offset.y; |
4930 | 1386 } |
3996 | 1387 } |
1388 | |
1389 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); | |
1390 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1391 ((tmp << 12) & 0xf0000000); | |
1392 | |
1393 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); | |
1394 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1395 ((tmp << 12) & 0x70000000); | |
1396 tmp = (top & 0x0000ffff) + 0x00018000; | |
1397 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) | |
1398 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
1399 | |
1400 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
6483 | 1401 besr.p23_v_accum_init = (is_420||is_410) ? |
1402 ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) | |
3996 | 1403 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; |
1404 | |
6483 | 1405 leftUV = (left >> (is_410?18:17)) & 15; |
3996 | 1406 left = (left >> 16) & 15; |
4571 | 1407 if(is_rgb && !is_rgb32) h_inc<<=1; |
4416 | 1408 if(is_rgb32) |
4571 | 1409 besr.h_inc = (h_inc >> 1) | ((h_inc >> 1) << 16); |
4416 | 1410 else |
6483 | 1411 if(is_410) |
1412 besr.h_inc = h_inc | ((h_inc >> 2) << 16); | |
1413 else | |
4416 | 1414 besr.h_inc = h_inc | ((h_inc >> 1) << 16); |
3996 | 1415 besr.step_by = step_by | (step_by << 8); |
1416 besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16); | |
1417 besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16); | |
1418 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
6483 | 1419 if(is_420 || is_410) |
3996 | 1420 { |
6483 | 1421 src_h = (src_h + 1) >> (is_410?2:1); |
3996 | 1422 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); |
1423 } | |
1424 else besr.p23_blank_lines_at_top = 0; | |
1425 besr.vid_buf_pitch0_value = pitch; | |
6483 | 1426 besr.vid_buf_pitch1_value = is_410 ? pitch>>2 : is_420 ? pitch>>1 : pitch; |
3996 | 1427 besr.p1_x_start_end = (src_w+left-1)|(left<<16); |
6483 | 1428 if (is_410||is_420) src_w>>=is_410?2:1; |
1429 if(is_400) | |
1430 { | |
1431 besr.p2_x_start_end = 0; | |
1432 besr.p3_x_start_end = 0; | |
1433 } | |
1434 else | |
1435 { | |
1436 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
1437 besr.p3_x_start_end = besr.p2_x_start_end; | |
1438 } | |
4869 | 1439 |
3996 | 1440 return 0; |
1441 } | |
1442 | |
4009 | 1443 static void radeon_compute_framesize(vidix_playback_t *info) |
1444 { | |
4666 | 1445 unsigned pitch,awidth,dbpp; |
4456 | 1446 pitch = radeon_query_pitch(info->fourcc,&info->src.pitch); |
4666 | 1447 dbpp = radeon_vid_get_dbpp(); |
4033 | 1448 switch(info->fourcc) |
1449 { | |
1450 case IMGFMT_I420: | |
1451 case IMGFMT_YV12: | |
1452 case IMGFMT_IYUV: | |
4666 | 1453 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); |
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1454 info->frame_size = awidth*(info->src.h+info->src.h/2); |
4033 | 1455 break; |
6483 | 1456 case IMGFMT_Y800: |
1457 case IMGFMT_Y8: | |
1458 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1459 info->frame_size = awidth*info->src.h; | |
1460 break; | |
1461 case IMGFMT_IF09: | |
1462 case IMGFMT_YVU9: | |
1463 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1464 info->frame_size = awidth*(info->src.h+info->src.h/8); | |
1465 break; | |
4429 | 1466 case IMGFMT_RGB32: |
1467 case IMGFMT_BGR32: | |
4666 | 1468 awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); |
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1469 info->frame_size = awidth*info->src.h; |
4429 | 1470 break; |
1471 /* YUY2 YVYU, RGB15, RGB16 */ | |
4666 | 1472 default: |
1473 awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); | |
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1474 info->frame_size = awidth*info->src.h; |
4033 | 1475 break; |
1476 } | |
4009 | 1477 } |
1478 | |
3996 | 1479 int vixConfigPlayback(vidix_playback_t *info) |
1480 { | |
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1481 unsigned rgb_size,nfr; |
3996 | 1482 if(!is_supported_fourcc(info->fourcc)) return ENOSYS; |
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1483 if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; |
4666 | 1484 if(info->num_frames==1) besr.double_buff=0; |
1485 else besr.double_buff=1; | |
4009 | 1486 radeon_compute_framesize(info); |
4930 | 1487 |
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1488 rgb_size = radeon_get_xres()*radeon_get_yres()*((radeon_vid_get_dbpp()+7)/8); |
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1489 nfr = info->num_frames; |
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1490 for(;nfr>0; nfr--) |
4930 | 1491 { |
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1492 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; |
4930 | 1493 radeon_overlay_off &= 0xffff0000; |
1494 if(radeon_overlay_off >= (int)rgb_size ) break; | |
1495 } | |
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1496 if(nfr <= 3) |
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1497 { |
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1498 nfr = info->num_frames; |
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1499 for(;nfr>0; nfr--) |
4930 | 1500 { |
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1501 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; |
4930 | 1502 radeon_overlay_off &= 0xffff0000; |
1503 if(radeon_overlay_off > 0) break; | |
1504 } | |
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1505 } |
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1506 if(nfr <= 0) return EINVAL; |
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1507 info->num_frames = nfr; |
4930 | 1508 besr.vid_nbufs = info->num_frames; |
1509 info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off; | |
3996 | 1510 radeon_vid_init_video(info); |
1511 return 0; | |
1512 } | |
1513 | |
1514 int vixPlaybackOn( void ) | |
1515 { | |
1516 radeon_vid_display_video(); | |
1517 return 0; | |
1518 } | |
1519 | |
1520 int vixPlaybackOff( void ) | |
1521 { | |
1522 radeon_vid_stop_video(); | |
1523 return 0; | |
1524 } | |
1525 | |
4033 | 1526 int vixPlaybackFrameSelect(unsigned frame) |
3996 | 1527 { |
4412 | 1528 uint32_t off[6]; |
4930 | 1529 int prev_frame= (frame-1+besr.vid_nbufs) % besr.vid_nbufs; |
4412 | 1530 /* |
1531 buf3-5 always should point onto second buffer for better | |
1532 deinterlacing and TV-in | |
1533 */ | |
4666 | 1534 if(!besr.double_buff) return 0; |
4930 | 1535 if(frame > besr.vid_nbufs) frame = besr.vid_nbufs-1; |
1536 if(prev_frame > (int)besr.vid_nbufs) prev_frame = besr.vid_nbufs-1; | |
1537 off[0] = besr.vid_buf_base_adrs_y[frame]; | |
1538 off[1] = besr.vid_buf_base_adrs_v[frame]; | |
1539 off[2] = besr.vid_buf_base_adrs_u[frame]; | |
1540 off[3] = besr.vid_buf_base_adrs_y[prev_frame]; | |
1541 off[4] = besr.vid_buf_base_adrs_v[prev_frame]; | |
1542 off[5] = besr.vid_buf_base_adrs_u[prev_frame]; | |
4855 | 1543 radeon_fifo_wait(8); |
3996 | 1544 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
4666 | 1545 radeon_engine_idle(); |
3996 | 1546 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); |
4412 | 1547 OUTREG(OV0_VID_BUF0_BASE_ADRS, off[0]); |
1548 OUTREG(OV0_VID_BUF1_BASE_ADRS, off[1]); | |
1549 OUTREG(OV0_VID_BUF2_BASE_ADRS, off[2]); | |
4413 | 1550 OUTREG(OV0_VID_BUF3_BASE_ADRS, off[3]); |
1551 OUTREG(OV0_VID_BUF4_BASE_ADRS, off[4]); | |
1552 OUTREG(OV0_VID_BUF5_BASE_ADRS, off[5]); | |
3996 | 1553 OUTREG(OV0_REG_LOAD_CNTL, 0); |
4930 | 1554 if(besr.vid_nbufs == 2) radeon_wait_vsync(); |
4030 | 1555 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1556 return 0; |
1557 } | |
1558 | |
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1559 vidix_video_eq_t equal = |
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1560 { |
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1561 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION |
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1562 #ifndef RAGE128 |
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1563 | VEQ_CAP_CONTRAST | VEQ_CAP_HUE | VEQ_CAP_RGB_INTENSITY |
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1564 #endif |
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1565 , |
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1566 0, 0, 0, 0, 0, 0, 0, 0 }; |
3996 | 1567 |
1568 int vixPlaybackGetEq( vidix_video_eq_t * eq) | |
1569 { | |
1570 memcpy(eq,&equal,sizeof(vidix_video_eq_t)); | |
1571 return 0; | |
1572 } | |
1573 | |
4229 | 1574 #ifndef RAGE128 |
1575 #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) | |
1576 #define RTFBrightness(a) (((a)*1.0)/2000.0) | |
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1577 #define RTFIntensity(a) (((a)*1.0)/2000.0) |
4229 | 1578 #define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) |
1579 #define RTFHue(a) (((a)*3.1416)/1000.0) | |
1580 #define RTFCheckParam(a) {if((a)<-1000) (a)=-1000; if((a)>1000) (a)=1000;} | |
1581 #endif | |
1582 | |
3996 | 1583 int vixPlaybackSetEq( const vidix_video_eq_t * eq) |
1584 { | |
1585 #ifdef RAGE128 | |
1586 int br,sat; | |
4229 | 1587 #else |
1588 int itu_space; | |
3996 | 1589 #endif |
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1590 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; |
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1591 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; |
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1592 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; |
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1593 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; |
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1594 if(eq->cap & VEQ_CAP_RGB_INTENSITY) |
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1595 { |
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1596 equal.red_intensity = eq->red_intensity; |
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1597 equal.green_intensity = eq->green_intensity; |
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1598 equal.blue_intensity = eq->blue_intensity; |
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1599 } |
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1600 equal.flags = eq->flags; |
3996 | 1601 #ifdef RAGE128 |
1602 br = equal.brightness * 64 / 1000; | |
4229 | 1603 if(br < -64) br = -64; if(br > 63) br = 63; |
4230 | 1604 sat = (equal.saturation + 1000) * 16 / 1000; |
4229 | 1605 if(sat < 0) sat = 0; if(sat > 31) sat = 31; |
3996 | 1606 OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); |
1607 #else | |
4229 | 1608 itu_space = equal.flags == VEQ_FLG_ITU_R_BT_709 ? 1 : 0; |
1609 RTFCheckParam(equal.brightness); | |
1610 RTFCheckParam(equal.saturation); | |
1611 RTFCheckParam(equal.contrast); | |
1612 RTFCheckParam(equal.hue); | |
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1613 RTFCheckParam(equal.red_intensity); |
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1614 RTFCheckParam(equal.green_intensity); |
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1615 RTFCheckParam(equal.blue_intensity); |
4229 | 1616 radeon_set_transform(RTFBrightness(equal.brightness), |
1617 RTFContrast(equal.contrast), | |
1618 RTFSaturation(equal.saturation), | |
1619 RTFHue(equal.hue), | |
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1620 RTFIntensity(equal.red_intensity), |
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1621 RTFIntensity(equal.green_intensity), |
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1622 RTFIntensity(equal.blue_intensity), |
4229 | 1623 itu_space); |
3996 | 1624 #endif |
1625 return 0; | |
1626 } | |
1627 | |
4611 | 1628 int vixPlaybackSetDeint( const vidix_deinterlace_t * info) |
1629 { | |
1630 unsigned sflg; | |
1631 switch(info->flags) | |
1632 { | |
1633 default: | |
1634 case CFG_NON_INTERLACED: | |
1635 besr.deinterlace_on = 0; | |
1636 break; | |
1637 case CFG_EVEN_ODD_INTERLACING: | |
1638 case CFG_INTERLACED: | |
1639 besr.deinterlace_on = 1; | |
1640 besr.deinterlace_pattern = 0x900AAAAA; | |
1641 break; | |
1642 case CFG_ODD_EVEN_INTERLACING: | |
1643 besr.deinterlace_on = 1; | |
1644 besr.deinterlace_pattern = 0x00055555; | |
1645 break; | |
1646 case CFG_UNIQUE_INTERLACING: | |
1647 besr.deinterlace_on = 1; | |
1648 besr.deinterlace_pattern = info->deinterlace_pattern; | |
1649 break; | |
1650 } | |
1651 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1652 radeon_engine_idle(); | |
1653 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1654 radeon_fifo_wait(15); | |
1655 sflg = INREG(OV0_SCALE_CNTL); | |
1656 if(besr.deinterlace_on) | |
1657 { | |
1658 OUTREG(OV0_SCALE_CNTL,sflg | SCALER_ADAPTIVE_DEINT); | |
1659 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
1660 } | |
1661 else OUTREG(OV0_SCALE_CNTL,sflg & (~SCALER_ADAPTIVE_DEINT)); | |
1662 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
1663 return 0; | |
1664 } | |
1665 | |
1666 int vixPlaybackGetDeint( vidix_deinterlace_t * info) | |
1667 { | |
1668 if(!besr.deinterlace_on) info->flags = CFG_NON_INTERLACED; | |
1669 else | |
1670 { | |
1671 info->flags = CFG_UNIQUE_INTERLACING; | |
1672 info->deinterlace_pattern = besr.deinterlace_pattern; | |
1673 } | |
1674 return 0; | |
1675 } | |
4869 | 1676 |
1677 | |
1678 /* Graphic keys */ | |
1679 static vidix_grkey_t radeon_grkey; | |
1680 | |
1681 static void set_gr_key( void ) | |
1682 { | |
1683 if(radeon_grkey.ckey.op == CKEY_TRUE) | |
1684 { | |
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rage128/radeon fixes, mach64 mess^H^H^H^Hcleanup, pm3 driver.
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diff
changeset
|
1685 int dbpp=radeon_vid_get_dbpp(); |
4869 | 1686 besr.ckey_on=1; |
1687 | |
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arpi
parents:
5165
diff
changeset
|
1688 switch(dbpp) |
4869 | 1689 { |
1690 case 15: | |
1691 besr.graphics_key_clr= | |
1692 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
1693 | ((radeon_grkey.ckey.green&0xF8)<<2) | |
1694 | ((radeon_grkey.ckey.red &0xF8)<<7); | |
1695 break; | |
1696 case 16: | |
1697 besr.graphics_key_clr= | |
1698 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
1699 | ((radeon_grkey.ckey.green&0xFC)<<3) | |
1700 | ((radeon_grkey.ckey.red &0xF8)<<8); | |
1701 break; | |
1702 case 24: | |
1703 besr.graphics_key_clr= | |
1704 ((radeon_grkey.ckey.blue &0xFF)) | |
1705 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
1706 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
1707 break; | |
1708 case 32: | |
1709 besr.graphics_key_clr= | |
1710 ((radeon_grkey.ckey.blue &0xFF)) | |
1711 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
1712 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
1713 break; | |
1714 default: | |
1715 besr.ckey_on=0; | |
1716 besr.graphics_key_msk=0; | |
1717 besr.graphics_key_clr=0; | |
1718 } | |
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diff
changeset
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1719 #ifdef RAGE128 |
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changeset
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1720 besr.graphics_key_msk=(1<<dbpp)-1; |
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arpi
parents:
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diff
changeset
|
1721 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_NE|CMP_MIX_AND; |
034b12194350
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parents:
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changeset
|
1722 #else |
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parents:
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changeset
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1723 besr.graphics_key_msk=besr.graphics_key_clr; |
8521
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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diff
changeset
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1724 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|CMP_MIX_AND; |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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parents:
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diff
changeset
|
1725 if(rage_ckey_model) |
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the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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parents:
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changeset
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1726 besr.ckey_cntl |= GRAPHIC_KEY_FN_NE; |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
alex
parents:
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diff
changeset
|
1727 else |
8996a4599a41
the long awaited pink screen + shift fix for radeon, based on patch by Svante Signell <svante.signell@telia.com>, Carl (mlist.mplayer.users@urs.us) and Nick Kurshve <nickolsk@yandex.ru>
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parents:
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diff
changeset
|
1728 besr.ckey_cntl |= GRAPHIC_KEY_FN_EQ; |
6254
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arpi
parents:
5165
diff
changeset
|
1729 #endif |
4869 | 1730 } |
1731 else | |
1732 { | |
1733 besr.ckey_on=0; | |
1734 besr.graphics_key_msk=0; | |
1735 besr.graphics_key_clr=0; | |
5044
43dc579db3d1
Fixed color key definitions. Waiting for new bugreports ;)
nick
parents:
5041
diff
changeset
|
1736 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; |
4869 | 1737 } |
5044
43dc579db3d1
Fixed color key definitions. Waiting for new bugreports ;)
nick
parents:
5041
diff
changeset
|
1738 radeon_fifo_wait(3); |
4869 | 1739 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); |
1740 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1741 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
1742 } | |
1743 | |
1744 int vixGetGrKeys(vidix_grkey_t *grkey) | |
1745 { | |
1746 memcpy(grkey, &radeon_grkey, sizeof(vidix_grkey_t)); | |
1747 return(0); | |
1748 } | |
1749 | |
1750 int vixSetGrKeys(const vidix_grkey_t *grkey) | |
1751 { | |
1752 memcpy(&radeon_grkey, grkey, sizeof(vidix_grkey_t)); | |
1753 set_gr_key(); | |
1754 return(0); | |
1755 } |