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changeset 4855:f7f847e2d7c2

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Minor fixes and probably final fix of vsync
author nick
date Mon, 25 Feb 2002 08:12:58 +0000
parents 4a6dde59834c
children 7dfcfd1b9bf7
files vidix/drivers/radeon_vid.c
diffstat 1 files changed, 3 insertions(+), 4 deletions(-) [+]
line wrap: on
line diff
--- a/vidix/drivers/radeon_vid.c	Mon Feb 25 02:48:37 2002 +0000
+++ b/vidix/drivers/radeon_vid.c	Mon Feb 25 08:12:58 2002 +0000
@@ -848,7 +848,7 @@
 void vixDestroy( void )
 {
   unmap_phys_mem(radeon_mem_base,radeon_ram_size);
-  unmap_phys_mem(radeon_mmio_base,0x7FFF);
+  unmap_phys_mem(radeon_mmio_base,0xFFFF);
 }
 
 int vixGetCapability(vidix_capability_t *to)
@@ -1306,19 +1306,18 @@
       off[4] = besr.vid_buf4_base_adrs;
       off[5] = besr.vid_buf5_base_adrs;
     }
-    radeon_wait_vsync();
-    radeon_fifo_wait(2);
+    radeon_fifo_wait(8);
     OUTREG(OV0_REG_LOAD_CNTL,		REG_LD_CTL_LOCK);
     radeon_engine_idle();
     while(!(INREG(OV0_REG_LOAD_CNTL)&REG_LD_CTL_LOCK_READBACK));
     OUTREG(OV0_VID_BUF0_BASE_ADRS,	off[0]);
     OUTREG(OV0_VID_BUF1_BASE_ADRS,	off[1]);
     OUTREG(OV0_VID_BUF2_BASE_ADRS,	off[2]);
-    radeon_fifo_wait(9);
     OUTREG(OV0_VID_BUF3_BASE_ADRS,	off[3]);
     OUTREG(OV0_VID_BUF4_BASE_ADRS,	off[4]);
     OUTREG(OV0_VID_BUF5_BASE_ADRS,	off[5]);
     OUTREG(OV0_REG_LOAD_CNTL,		0);
+    radeon_wait_vsync();
     if(__verbose > 1) radeon_vid_dump_regs();
     return 0;
 }