changeset 1123:5b69dabe5823

Issues about P3 performance and SSE2 support.
author nickols_k
date Wed, 13 Jun 2001 16:12:14 +0000
parents fe9ef743be91
children 0e95f30ffd4c
files libvo/aclib.c libvo/aclib_template.c
diffstat 2 files changed, 18 insertions(+), 4 deletions(-) [+]
line wrap: on
line diff
--- a/libvo/aclib.c	Wed Jun 13 15:03:27 2001 +0000
+++ b/libvo/aclib.c	Wed Jun 13 16:12:14 2001 +0000
@@ -8,8 +8,15 @@
 
 #include <stddef.h>
 
-/* Enable this code, if SSE version works (faster) for you! */
-#if 1
+#ifndef HAVE_SSE2
+/*
+   P3 processor has only one SSE decoder so can execute only 1 sse insn per
+   cpu clock, but it has 3 mmx decoders (include load/store unit)
+   and executes 3 mmx insns per cpu clock.
+   P4 processor has some chances, but after reading:
+   http://www.emulators.com/pentium4.htm
+   I have doubts. Anyway SSE2 version of this code can be written better.
+*/
 #undef HAVE_SSE
 #endif
 
--- a/libvo/aclib_template.c	Wed Jun 13 15:03:27 2001 +0000
+++ b/libvo/aclib_template.c	Wed Jun 13 16:12:14 2001 +0000
@@ -8,8 +8,15 @@
 
 #include <stddef.h>
 
-/* Enable this code, if SSE version works (faster) for you! */
-#if 1
+#ifndef HAVE_SSE2
+/*
+   P3 processor has only one SSE decoder so can execute only 1 sse insn per
+   cpu clock, but it has 3 mmx decoders (include load/store unit)
+   and executes 3 mmx insns per cpu clock.
+   P4 processor has some chances, but after reading:
+   http://www.emulators.com/pentium4.htm
+   I have doubts. Anyway SSE2 version of this code can be written better.
+*/
 #undef HAVE_SSE
 #endif