annotate driver/pt1_tuner.c @ 71:28f25ec7f962

correct number of initialization data.
author Yoshiki Yazawa <yaz@honeyplanet.jp>
date Sat, 31 Oct 2009 04:15:22 +0900
parents 272a8fba970b
children 517e61637f7b
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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0
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1 /* pt1-tuner.c: A PT1 on Tuner driver for Linux. */
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2
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3 #include <linux/module.h>
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4 #include <linux/kernel.h>
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5 #include <linux/errno.h>
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6 #include <linux/pci.h>
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7 #include <linux/init.h>
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8 #include <linux/interrupt.h>
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9 #include <linux/mutex.h>
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10
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11 #include <asm/system.h>
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12 #include <asm/io.h>
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13 #include <asm/irq.h>
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14 #include <asm/uaccess.h>
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15
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16 #include "pt1_com.h"
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17 #include "pt1_pci.h"
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18 #include "pt1_i2c.h"
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19 #include "pt1_tuner.h"
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20 #include "pt1_tuner_data.h"
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21
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22 typedef struct _TUNER_INFO{
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23 int isdb_s ;
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24 int isdb_t ;
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25 }TUNER_INFO;
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26
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27 TUNER_INFO tuner_info[2] = {
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28 {T0_ISDB_S, T0_ISDB_T},
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29 {T1_ISDB_S, T1_ISDB_T}
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30 };
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31
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32 typedef struct _isdb_t_freq_add_table{
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33 __u16 pos ; // Äɲ乤ë¥Á¥ã¥ó¥Í¥ë¥Ý¥¸¥·¥ç¥ó
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34 __u16 add_freq ; // Äɲ乤ëÃÍ
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35 }isdb_t_freq_add_table;
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36
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37 isdb_t_freq_add_table isdb_t_freq_add[10] = {
64
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38 { 7, 0x8081}, // 0¡Á7Ëø
0
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39 { 12, 0x80A1}, // 8¡Á12Ëø
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40 { 21, 0x8062}, // 13¡Á21Ëø
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41 { 39, 0x80A2}, // 22¡Á39Ëø
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42 { 51, 0x80E2}, // 40¡Á51Ëø
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43 { 59, 0x8064}, // 52¡Á59Ëø
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44 { 75, 0x8084}, // 60¡Á75Ëø
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45 { 84, 0x80a4}, // 76¡Á84Ëø
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46 {100, 0x80C4}, // 85¡Á100Ëø
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47 {112, 0x80E4} // 101¡Á112Ëø
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48 };
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49
64
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50 void settuner_reset(void __iomem *regs, int cardtype, __u32 lnb, __u32 tuner)
0
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51 {
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52 __u32 val = 0;
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53 switch(lnb){
64
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54 case LNB_11V:
65
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55 val = (1 << BIT_LNB_DOWN);
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56 break ;
64
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57 case LNB_15V:
65
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58 val = (1 << BIT_LNB_UP) | (1 << BIT_LNB_DOWN);
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59 break ;
0
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60 }
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61
64
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62 if(cardtype == PT1) {
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63 switch(tuner){
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64 case TUNER_POWER_ON_RESET_ENABLE:
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65 val |= (1 << BIT_TUNER);
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66 break;
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67 case TUNER_POWER_ON_RESET_DISABLE:
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68 val |= (1 << BIT_TUNER) | (1 << BIT_RESET);
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69 break ;
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70 }
0
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71 }
64
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72 else if(cardtype == PT2) {
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73 switch(tuner){
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74 case TUNER_POWER_ON_RESET_ENABLE:
69
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75 val |= (1 << BIT_TUNER)
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76 | (1 << BIT_33A1)
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77 | (1 << BIT_33A2)
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78 | (1 << BIT_5A_)
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79 | (1 << BIT_5A1)
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80 | (1 << BIT_5A2);
64
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81 break;
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82 case TUNER_POWER_ON_RESET_DISABLE:
69
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83 val |= (1 << BIT_TUNER)
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84 | (1 << BIT_RESET)
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85 | (1 << BIT_33A1)
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86 | (1 << BIT_33A2)
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87 | (1 << BIT_5A_)
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88 | (1 << BIT_5A1)
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89 | (1 << BIT_5A2);
64
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90 break ;
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91 }
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92 }
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93 writel(val, (regs + CFG_REGS_ADDR));
0
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94 }
69
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95 static int init_isdb_s(void __iomem *regs, int cardtype, struct mutex *lock, __u32 addr)
0
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96 {
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97
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98 WBLOCK wk;
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99 int lp ;
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100 __u32 val ;
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101
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102 // ISDB-S/T½é´ü²½
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103 memcpy(&wk, &com_initdata, sizeof(WBLOCK));
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104
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105 // ½é´ü²½£±(¤Ê¤¼¤«READ¤Ê¤Î¤Ç)
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106 memcpy(&wk, &isdb_s_init1, sizeof(WBLOCK));
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107 wk.addr = addr;
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108 val = i2c_read(regs, lock, &wk, 1);
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109 if((val & 0xff) != 0x41){
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110 printk(KERN_INFO "PT1:ISDB-S Read(%x)\n", val);
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111 return -EIO ;
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112 }
71
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113
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114 if(cardtype == PT1) {
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115 for(lp = 0 ; lp < MAX_ISDB_S_INIT ; lp++){
69
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116 memcpy(&wk, isdb_s_initial_pt1[lp], sizeof(WBLOCK));
71
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117 wk.addr = addr;
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118 i2c_write(regs, lock, &wk);
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119 }
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120 }
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121 else if(cardtype == PT2) {
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122 for(lp = 0 ; lp < MAX_ISDB_S_INIT2 ; lp++){
69
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123 memcpy(&wk, isdb_s_initial_pt2[lp], sizeof(WBLOCK));
71
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124 wk.addr = addr;
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125 i2c_write(regs, lock, &wk);
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126 }
0
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127 }
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128
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129 return 0 ;
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130 }
69
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131 static void init_isdb_t(void __iomem *regs, int cardtype, struct mutex *lock, __u32 addr)
0
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132 {
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133 int lp ;
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134 WBLOCK wk;
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135
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136 // ISDB-S/T½é´ü²½
71
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137 if(cardtype == PT1) {
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138 for(lp = 0 ; lp < MAX_ISDB_T_INIT ; lp++){
69
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139 memcpy(&wk, isdb_t_initial_pt1[lp], sizeof(WBLOCK));
71
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140 wk.addr = addr;
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141 i2c_write(regs, lock, &wk);
28f25ec7f962 correct number of initialization data.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 69
diff changeset
142 }
28f25ec7f962 correct number of initialization data.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 69
diff changeset
143 }
28f25ec7f962 correct number of initialization data.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 69
diff changeset
144 else if(cardtype == PT2) {
28f25ec7f962 correct number of initialization data.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 69
diff changeset
145 for(lp = 0 ; lp < MAX_ISDB_T_INIT2 ; lp++){
69
272a8fba970b added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 65
diff changeset
146 memcpy(&wk, isdb_t_initial_pt2[lp], sizeof(WBLOCK));
71
28f25ec7f962 correct number of initialization data.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 69
diff changeset
147 wk.addr = addr;
28f25ec7f962 correct number of initialization data.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 69
diff changeset
148 i2c_write(regs, lock, &wk);
28f25ec7f962 correct number of initialization data.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 69
diff changeset
149 }
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
150 }
71
28f25ec7f962 correct number of initialization data.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 69
diff changeset
151 }
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
152
69
272a8fba970b added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 65
diff changeset
153 int tuner_init(void __iomem *regs, int cardtype, struct mutex *lock, int tuner_no)
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
154 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
155
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
156 int rc ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
157 WBLOCK wk;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
158
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
159 // ISDB-S/T½é´ü²½
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
160 memcpy(&wk, &com_initdata, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
161
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
162 // ½é´ü²½(¶¦ÄÌ)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
163 wk.addr = tuner_info[tuner_no].isdb_t ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
164 i2c_write(regs, lock, &wk);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
165 wk.addr = tuner_info[tuner_no].isdb_s ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
166 i2c_write(regs, lock, &wk);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
167
69
272a8fba970b added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 65
diff changeset
168 rc = init_isdb_s(regs, cardtype, lock, tuner_info[tuner_no].isdb_s);
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
169 if(rc < 0){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
170 return rc ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
171 }
69
272a8fba970b added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 65
diff changeset
172 init_isdb_t(regs, cardtype, lock, tuner_info[tuner_no].isdb_t);
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
173
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
174 memcpy(&wk, &isdb_s_init21, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
175 wk.addr = tuner_info[tuner_no].isdb_s ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
176 i2c_write(regs, lock, &wk);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
177
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
178 memcpy(&wk, &isdb_t_init17, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
179 wk.addr = tuner_info[tuner_no].isdb_t ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
180 i2c_write(regs, lock, &wk);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
181
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
182 return 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
183 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
184 void set_sleepmode(void __iomem *regs, struct mutex *lock, int address, int tuner_type, int type)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
185 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
186 WBLOCK wk;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
187
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
188 if(type == TYPE_WAKEUP){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
189 switch(tuner_type){
64
98a92ce5382e added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 9
diff changeset
190 case CHANNEL_TYPE_ISDB_S:
98a92ce5382e added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 9
diff changeset
191 memcpy(&wk, &isdb_s_wake, sizeof(WBLOCK));
98a92ce5382e added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 9
diff changeset
192 break ;
98a92ce5382e added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 9
diff changeset
193 case CHANNEL_TYPE_ISDB_T:
98a92ce5382e added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 9
diff changeset
194 memcpy(&wk, &isdb_t_wake, sizeof(WBLOCK));
98a92ce5382e added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 9
diff changeset
195 break ;
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
196 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
197 wk.addr = address ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
198 i2c_write(regs, lock, &wk);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
199 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
200 switch(tuner_type){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
201 case CHANNEL_TYPE_ISDB_S:
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
202 printk(KERN_INFO "PT1:ISDB-S Sleep\n");
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
203 memcpy(&wk, &isdb_s_sleep, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
204 if(type == TYPE_WAKEUP){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
205 wk.value[1] = 0x01 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
206 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
207 break ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
208 case CHANNEL_TYPE_ISDB_T:
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
209 printk(KERN_INFO "PT1:ISDB-T Sleep\n");
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
210 memcpy(&wk, &isdb_t_sleep, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
211 if(type == TYPE_WAKEUP){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
212 wk.value[1] = 0x90 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
213 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
214 break ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
215 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
216 wk.addr = address;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
217 i2c_write(regs, lock, &wk);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
218 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
219
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
220 int bs_frequency(void __iomem *regs, struct mutex *lock, int addr, int channel)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
221 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
222 int lp ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
223 int tmcclock = FALSE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
224 WBLOCK wk;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
225 __u32 val ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
226
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
227 if(channel >= MAX_BS_CHANNEL){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
228 return -EIO ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
229 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
230 // ISDB-S PLL¥í¥Ã¥¯
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
231 for(lp = 0 ; lp < MAX_BS_CHANNEL_PLL_COMMAND ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
232 memcpy(&wk, bs_pll[channel].wblock[lp], sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
233 wk.addr = addr ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
234 i2c_write(regs, lock, &wk);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
235 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
236
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
237 // PLL¥í¥Ã¥¯³Îǧ
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
238 // ¥Á¥§¥Ã¥¯ÍÑ
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
239 for(lp = 0 ; lp < 200 ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
240 memcpy(&wk, &bs_pll_lock, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
241 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
242 val = i2c_read(regs, lock, &wk, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
243 if(((val & 0xFF) != 0) && ((val & 0XFF) != 0XFF)){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
244 tmcclock = TRUE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
245 break ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
246 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
247 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
248
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
249 if(tmcclock == FALSE){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
250 printk(KERN_INFO "PLL LOCK ERROR\n");
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
251 return -EIO;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
252 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
253
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
254 memcpy(&wk, &bs_tmcc_get_1, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
255 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
256 i2c_write(regs, lock, &wk);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
257
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
258 tmcclock = FALSE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
259
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
260 for(lp = 0 ; lp < 200 ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
261 memcpy(&wk, &bs_tmcc_get_2, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
262 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
263
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
264 val = i2c_read(regs, lock, &wk, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
265 if(((val & 0XFF) != 0XFF) && (!(val & 0x10))){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
266 tmcclock = TRUE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
267 break ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
268 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
269 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
270
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
271 if(tmcclock == FALSE){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
272 printk(KERN_INFO "TMCC LOCK ERROR\n");
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
273 return -EIO;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
274 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
275
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
276 return 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
277 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
278 int ts_lock(void __iomem *regs, struct mutex *lock, int addr, __u16 ts_id)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
279 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
280
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
281 int lp ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
282 WBLOCK wk;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
283 __u32 val ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
284 union{
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
285 __u8 ts[2];
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
286 __u16 tsid;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
287 }uts_id ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
288
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
289 uts_id.tsid = ts_id ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
290 memcpy(&wk, &bs_set_ts_lock, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
291 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
292 // TS-IDÀßÄê
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
293 wk.value[1] = uts_id.ts[1];
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
294 wk.value[2] = uts_id.ts[0];
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
295 i2c_write(regs, lock, &wk);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
296
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
297 for(lp = 0 ; lp < 100 ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
298 memcpy(&wk, &bs_get_ts_lock, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
299 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
300 val = i2c_read(regs, lock, &wk, 2);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
301 if((val & 0xFFFF) == ts_id){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
302 return 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
303 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
304 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
305 printk(KERN_INFO "PT1:ERROR TS-LOCK(%x)\n", ts_id);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
306 return -EIO ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
307 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
308 int bs_tune(void __iomem *regs, struct mutex *lock, int addr, int channel, ISDB_S_TMCC *tmcc)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
309 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
310
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
311 int lp ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
312 int lp2;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
313 WBLOCK wk;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
314 __u32 val ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
315 ISDB_S_TS_ID *tsid ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
316 union{
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
317 __u8 slot[4];
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
318 __u32 u32slot;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
319 }ts_slot ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
320 union{
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
321 __u16 ts[2];
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
322 __u32 tsid;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
323 }ts_id ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
324
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
325 if(channel >= MAX_BS_CHANNEL){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
326 printk(KERN_INFO "Invalid Channel(%d)\n", channel);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
327 return -EIO ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
328 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
329 val = bs_frequency(regs, lock, addr, channel);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
330 if(val == -EIO){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
331 return val ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
332 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
333
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
334 tsid = &tmcc->ts_id[0] ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
335 // ³ºÅö¼þÇÈ¿ô¤ÎTS-ID¤ò¼èÆÀ
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
336 for(lp = 0 ; lp < (MAX_BS_TS_ID / 2) ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
337 for(lp2 = 0 ; lp2 < 100 ; lp2++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
338 memcpy(&wk, bs_get_ts_id[lp], sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
339 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
340 ts_id.tsid = i2c_read(regs, lock, &wk, 4);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
341 // TS-ID¤¬0¤Î¾ì¹ç¤ÏºÆ¼èÆÀ¤¹¤ë
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
342 if((ts_id.ts[0] != 0) && (ts_id.ts[1] != 0)){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
343 break ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
344 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
345 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
346 tsid->ts_id = ts_id.ts[1] ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
347 tsid += 1;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
348 tsid->ts_id = ts_id.ts[0] ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
349 tsid += 1;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
350 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
351
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
352 memcpy(&wk, &bs_get_agc, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
353 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
354 tmcc->agc = i2c_read(regs, lock, &wk, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
355
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
356 // TS-IDÊ̤ξðÊó¤ò¼èÆÀ
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
357 tsid = &tmcc->ts_id[0] ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
358 for(lp = 0 ; lp < MAX_BS_TS_ID ; lp++, tsid += 1){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
359 // TS-ID¤Ê¤·=0XFFFF
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
360 if(tsid->ts_id == 0xFFFF){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
361 continue ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
362 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
363 ts_lock(regs, lock, addr, tsid->ts_id);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
364
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
365 //¥¹¥í¥Ã¥È¼èÆÀ
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
366 memcpy(&wk, &bs_get_slot, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
367 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
368 ts_slot.u32slot = i2c_read(regs, lock, &wk, 3);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
369 tsid->high_mode = 0;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
370 tsid->low_slot = ts_slot.slot[0] ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
371 tsid->high_slot = ts_slot.slot[1] ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
372 tsid->low_mode = ts_slot.slot[2] ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
373 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
374
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
375 memcpy(&wk, &bs_get_clock, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
376 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
377 tmcc->clockmargin = i2c_read(regs, lock, &wk, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
378
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
379 memcpy(&wk, &bs_get_carrir, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
380 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
381 tmcc->carriermargin = i2c_read(regs, lock, &wk, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
382 return 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
383 }
9
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
384 int isdb_s_read_signal_strength(void __iomem *regs, struct mutex *lock, int addr)
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
385 {
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
386 WBLOCK wk;
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
387 __u32 val ;
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
388 __u32 val2;
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
389 int val3 ;
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
390
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
391 memcpy(&wk, &bs_get_signal1, sizeof(WBLOCK));
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
392 wk.addr = addr;
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
393 val = i2c_read(regs, lock, &wk, 1);
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
394
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
395 memcpy(&wk, &bs_get_signal2, sizeof(WBLOCK));
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
396 wk.addr = addr;
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
397 val2 = i2c_read(regs, lock, &wk, 1);
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
398 val3 = (((val << 8) & 0XFF00) | (val2 & 0XFF));
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
399
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
400 return val3 ;
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
401 }
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
402
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
403 __u32 getfrequency_add(__u32 channel)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
404 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
405 int lp ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
406
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
407 for(lp = 0 ; lp < 10 ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
408 if(channel <= isdb_t_freq_add[lp].pos){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
409 return isdb_t_freq_add[lp].add_freq ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
410 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
411 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
412 return 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
413 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
414 __u32 getfrequency(__u32 channel, int addfreq)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
415 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
416 __u32 frequencyoffset = 0;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
417 __u32 frequencyOffset = 0;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
418
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
419 if (12 <= channel){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
420 frequencyoffset += 2;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
421 }else if (17 <= channel){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
422 frequencyoffset = 0;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
423 }else if (63 <= channel){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
424 frequencyoffset += 2;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
425 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
426 #if 0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
427 return (((93 + channel * 6 + frequencyOffset) + addfreq) * 7) + 400;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
428 #endif
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
429 frequencyOffset = 93 + channel * 6 + frequencyoffset;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
430 frequencyOffset = 7 * (frequencyOffset + addfreq);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
431 return frequencyOffset + 400;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
432
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
433 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
434 int isdb_t_frequency(void __iomem *regs, struct mutex *lock, int addr, int channel, int addfreq)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
435 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
436
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
437 int lp ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
438 WBLOCK wk;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
439 __u32 val ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
440 int tmcclock = FALSE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
441 union{
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
442 __u8 charfreq[2];
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
443 __u16 freq;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
444 }freq[2] ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
445
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
446 if(channel >= MAX_ISDB_T_CHANNEL){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
447 return -EIO ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
448 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
449
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
450 freq[0].freq = getfrequency(channel, addfreq);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
451 freq[1].freq = getfrequency_add(channel);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
452 //»ØÄê¼þÇÈ¿ô
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
453 memcpy(&wk, &isdb_t_pll_base, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
454 wk.addr = addr ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
455 // ·×»»¤·¤¿¼þÇÈ¿ô¤òÀßÄê
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
456 wk.value[wk.count] = freq[0].charfreq[1];
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
457 wk.count += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
458 wk.value[wk.count] = freq[0].charfreq[0];
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
459 wk.count += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
460
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
461 // ·×»»¤·¤¿¼þÇÈ¿ôÉղþðÊó¤òÀßÄê
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
462 wk.value[wk.count] = freq[1].charfreq[1];
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
463 wk.count += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
464 wk.value[wk.count] = freq[1].charfreq[0];
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
465 wk.count += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
466
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
467 i2c_write(regs, lock, &wk);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
468
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
469 for(lp = 0 ; lp < 100 ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
470 memcpy(&wk, &isdb_t_pll_lock, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
471 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
472 val = i2c_read(regs, lock, &wk, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
473 if(((val & 0xFF) != 0XFF) && ((val & 0X50) == 0x50)){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
474 tmcclock = TRUE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
475 break ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
476 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
477 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
478 if(tmcclock != TRUE){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
479 printk(KERN_INFO "PT1:ISDB-T LOCK NG(%08x)\n", val);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
480 return -EIO ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
481 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
482
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
483 memcpy(&wk, &isdb_t_check_tune, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
484 wk.addr = addr ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
485 i2c_write(regs, lock, &wk);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
486
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
487 tmcclock = FALSE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
488 for(lp = 0 ; lp < 1000 ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
489 memcpy(&wk, &isdb_t_tune_read, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
490 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
491 val = i2c_read(regs, lock, &wk, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
492 if(((val & 0xFF) != 0XFF) && ((val & 0X8) != 8)){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
493 tmcclock = TRUE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
494 break ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
495 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
496 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
497 if(tmcclock != TRUE){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
498 return -EIO ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
499 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
500 return 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
501 }
9
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
502 int isdb_t_read_signal_strength(void __iomem *regs, struct mutex *lock, int addr)
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
503 {
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
504 __u32 val ;
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
505 __u32 val2;
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
506 __u32 val3;
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
507 WBLOCK wk;
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
508
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
509 memcpy(&wk, &isdb_t_signal1, sizeof(WBLOCK));
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
510 wk.addr = addr;
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
511 val = i2c_read(regs, lock, &wk, 1);
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
512 printk(KERN_INFO "CN(1)Val(%x)\n", val);
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
513
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
514 memcpy(&wk, &isdb_t_signal2, sizeof(WBLOCK));
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
515 wk.addr = addr;
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
516 val2 = i2c_read(regs, lock, &wk, 1);
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
517 val3 = (((val << 8) & 0XFF00) | (val2 & 0XFF));
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
518 return val3 ;
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
519 }
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
520 #if 0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
521 int isdb_t_tune(void __iomem *regs, struct mutex *lock, int addr, int channel, ISDB_T_TMCC *tmcc)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
522 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
523
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
524 int lp ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
525 int rc ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
526 int lp2 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
527 WBLOCK wk;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
528 __u32 val ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
529
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
530 printk(KERN_INFO "Channel(%d) Start\n", channel);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
531 if(channel >= MAX_ISDB_T_CHANNEL){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
532 return -EIO ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
533 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
534 rc = isdb_t_frequency(regs, lock, addr, channel);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
535 if(rc < 0){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
536 return -EIO ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
537 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
538 for(lp = 0 ; lp < 100 ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
539 memcpy(&wk, &isdb_t_tmcc_read_1, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
540 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
541 val = i2c_read(regs, lock, &wk, 4);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
542 if((val & 0xFF) != 0){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
543 break ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
544 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
545 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
546 printk(KERN_INFO "TMCC(1)Val(%x)\n", val);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
547
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
548 for(lp = 0 ; lp < 100 ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
549 memcpy(&wk, &isdb_t_tmcc_read_2, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
550 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
551 val = i2c_read(regs, lock, &wk, 4);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
552 if((val & 0xFF) != 0){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
553 break ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
554 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
555 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
556 printk(KERN_INFO "TMCC(2)Val(%x)\n", val);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
557
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
558 memcpy(&wk, &isdb_t_cn_1, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
559 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
560 val = i2c_read(regs, lock, &wk, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
561 printk(KERN_INFO "CN(1)Val(%x)\n", val);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
562
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
563 memcpy(&wk, &isdb_t_cn_2, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
564 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
565 val = i2c_read(regs, lock, &wk, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
566 printk(KERN_INFO "CN(2)Val(%x)\n", val);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
567
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
568 memcpy(&wk, &isdb_t_agc_1, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
569 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
570 val = i2c_read(regs, lock, &wk, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
571 printk(KERN_INFO "AGC(1)Val(%x)\n", val);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
572
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
573 memcpy(&wk, &isdb_t_agc_2, sizeof(WBLOCK));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
574 wk.addr = addr;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
575 val = i2c_read(regs, lock, &wk, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
576 printk(KERN_INFO "AGC(2)Val(%x)\n", val);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
577 return 0;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
578 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
579 #endif