Mercurial > emacs
annotate lisp/progmodes/verilog-mode.el @ 80355:35dfb85c0e6b
(verilog-easy-menu-filter): New function.
(verilog-stmt-menu, verilog-menu): Add :help.
(verilog-customize, verilog-font-customize)
(electric-verilog-backward-sexp, electric-verilog-forward-sexp)
(verilog-mode): Update documentation strings to match tool tips.
(verilog-auto-search-do, verilog-auto-re-search-do)
(verilog-skip-forward-comment-or-string): Fix verilog-auto
expansion when a .* appears inside a string.
(verilog-re-search-forward, verilog-re-search-backward): Add
comment to recall how this works.
author | Dan Nicolaescu <dann@ics.uci.edu> |
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date | Thu, 20 Mar 2008 06:15:05 +0000 |
parents | b7bed0a77336 |
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rev | line source |
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79545 | 1 ;; verilog-mode.el --- major mode for editing verilog source in Emacs |
79551 | 2 |
3 ;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, | |
79717 | 4 ;; 2005, 2006, 2007, 2008 Free Software Foundation, Inc. |
79545 | 5 |
6 ;; Author: Michael McNamara (mac@verilog.com) | |
7 ;; http://www.verilog.com | |
8 ;; | |
9 ;; AUTO features, signal, modsig; by: Wilson Snyder | |
10 ;; (wsnyder@wsnyder.org) | |
11 ;; http://www.veripool.com | |
12 ;; Keywords: languages | |
13 | |
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14 ;; This code supports Emacs 21.1 and later |
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15 ;; And XEmacs 21.1 and later |
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16 ;; Please do not make changes that break Emacs 21. Thanks! |
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17 ;; |
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18 ;; |
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19 |
79551 | 20 ;; This file is part of GNU Emacs. |
21 | |
22 ;; GNU Emacs is free software; you can redistribute it and/or modify | |
79545 | 23 ;; it under the terms of the GNU General Public License as published by |
79551 | 24 ;; the Free Software Foundation; either version 3, or (at your option) |
25 ;; any later version. | |
26 | |
27 ;; GNU Emacs is distributed in the hope that it will be useful, | |
79545 | 28 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
29 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
30 ;; GNU General Public License for more details. | |
31 | |
32 ;; You should have received a copy of the GNU General Public License | |
79551 | 33 ;; along with GNU Emacs; see the file COPYING. If not, write to the |
34 ;; Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, | |
35 ;; Boston, MA 02110-1301, USA. | |
79545 | 36 |
37 ;;; Commentary: | |
38 | |
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39 ;; This mode borrows heavily from the Pascal-mode and the cc-mode of Emacs |
79545 | 40 |
41 ;; USAGE | |
42 ;; ===== | |
43 | |
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44 ;; A major mode for editing Verilog HDL source code. When you have |
79545 | 45 ;; entered Verilog mode, you may get more info by pressing C-h m. You |
46 ;; may also get online help describing various functions by: C-h f | |
47 ;; <Name of function you want described> | |
48 | |
49 ;; KNOWN BUGS / BUG REPORTS | |
50 ;; ======================= | |
51 | |
52 ;; Verilog is a rapidly evolving language, and hence this mode is | |
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53 ;; under continuous development. Hence this is beta code, and likely |
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54 ;; has bugs. Please report any and all bugs to me at mac@verilog.com. |
79545 | 55 ;; Please use verilog-submit-bug-report to submit a report; type C-c |
56 ;; C-b to invoke this and as a result I will have a much easier time | |
57 ;; of reproducing the bug you find, and hence fixing it. | |
58 | |
59 ;; INSTALLING THE MODE | |
60 ;; =================== | |
61 | |
62 ;; An older version of this mode may be already installed as a part of | |
63 ;; your environment, and one method of updating would be to update | |
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64 ;; your Emacs environment. Sometimes this is difficult for local |
79545 | 65 ;; political/control reasons, and hence you can always install a |
66 ;; private copy (or even a shared copy) which overrides the system | |
67 ;; default. | |
68 | |
69 ;; You can get step by step help in installing this file by going to | |
70 ;; <http://www.verilog.com/emacs_install.html> | |
71 | |
72 ;; The short list of installation instructions are: To set up | |
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73 ;; automatic Verilog mode, put this file in your load path, and put |
79545 | 74 ;; the following in code (please un comment it first!) in your |
75 ;; .emacs, or in your site's site-load.el | |
76 | |
77 ; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t ) | |
78 ; (setq auto-mode-alist (cons '("\\.v\\'" . verilog-mode) auto-mode-alist)) | |
79 ; (setq auto-mode-alist (cons '("\\.dv\\'" . verilog-mode) auto-mode-alist)) | |
80 | |
81 ;; If you want to customize Verilog mode to fit your needs better, | |
82 ;; you may add these lines (the values of the variables presented | |
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83 ;; here are the defaults). Note also that if you use an Emacs that |
79545 | 84 ;; supports custom, it's probably better to use the custom menu to |
85 ;; edit these. | |
86 ;; | |
87 ;; Be sure to examine at the help for verilog-auto, and the other | |
88 ;; verilog-auto-* functions for some major coding time savers. | |
89 ;; | |
90 ; ;; User customization for Verilog mode | |
91 ; (setq verilog-indent-level 3 | |
92 ; verilog-indent-level-module 3 | |
93 ; verilog-indent-level-declaration 3 | |
94 ; verilog-indent-level-behavioral 3 | |
95 ; verilog-indent-level-directive 1 | |
96 ; verilog-case-indent 2 | |
97 ; verilog-auto-newline t | |
98 ; verilog-auto-indent-on-newline t | |
99 ; verilog-tab-always-indent t | |
100 ; verilog-auto-endcomments t | |
101 ; verilog-minimum-comment-distance 40 | |
102 ; verilog-indent-begin-after-if t | |
103 ; verilog-auto-lineup '(all) | |
104 ; verilog-highlight-p1800-keywords nil | |
105 ; verilog-linter "my_lint_shell_command" | |
106 ; ) | |
107 | |
108 ;; | |
109 | |
110 ;;; History: | |
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111 ;; |
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112 ;; See commit history at http://www.veripool.com/verilog-mode.html |
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113 ;; (This section is required to appease checkdoc.) |
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114 |
79545 | 115 ;;; Code: |
116 | |
117 ;; This variable will always hold the version number of the mode | |
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118 (defconst verilog-mode-version "404" |
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119 "Version of this Verilog mode.") |
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120 (defconst verilog-mode-release-date "2008-03-02-GNU" |
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121 "Release date of this Verilog mode.") |
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122 (defconst verilog-mode-release-emacs t |
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123 "If non-nil, this version of Verilog mode was released with Emacs itself.") |
79545 | 124 |
125 (defun verilog-version () | |
126 "Inform caller of the version of this file." | |
127 (interactive) | |
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128 (message "Using verilog-mode version %s" verilog-mode-version)) |
79545 | 129 |
130 ;; Insure we have certain packages, and deal with it if we don't | |
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131 ;; Be sure to note which Emacs flavor and version added each feature. |
79546 | 132 (eval-when-compile |
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133 ;; The below were disabled when GNU Emacs 22 was released; |
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134 ;; perhaps some still need to be there to support Emacs 21. |
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135 (when (featurep 'xemacs) |
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136 (condition-case nil |
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137 (require 'easymenu) |
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138 (error nil)) |
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139 (condition-case nil |
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140 (require 'regexp-opt) |
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141 (error nil)) |
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142 ;; Bug in 19.28 through 19.30 skeleton.el, not provided. |
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143 (condition-case nil |
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144 (load "skeleton") |
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145 (error nil)) |
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146 (condition-case nil |
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147 (if (fboundp 'when) |
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148 nil ;; fab |
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149 (defmacro when (cond &rest body) |
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150 (list 'if cond (cons 'progn body)))) |
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151 (error nil)) |
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152 (condition-case nil |
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153 (if (fboundp 'unless) |
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154 nil ;; fab |
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155 (defmacro unless (cond &rest body) |
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156 (cons 'if (cons cond (cons nil body))))) |
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157 (error nil)) |
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158 (condition-case nil |
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159 (if (fboundp 'store-match-data) |
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160 nil ;; fab |
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161 (defmacro store-match-data (&rest args) nil)) |
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162 (error nil)) |
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163 (condition-case nil |
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164 (if (fboundp 'char-before) |
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165 nil ;; great |
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166 (defmacro char-before (&rest body) |
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167 (char-after (1- (point))))) |
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168 (error nil)) |
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169 (condition-case nil |
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170 (require 'custom) |
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171 (error nil)) |
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172 (condition-case nil |
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173 (if (fboundp 'match-string-no-properties) |
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174 nil ;; great |
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175 (defsubst match-string-no-properties (num &optional string) |
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176 "Return string of text matched by last search, without text properties. |
79545 | 177 NUM specifies which parenthesized expression in the last regexp. |
178 Value is nil if NUMth pair didn't match, or there were less than NUM pairs. | |
179 Zero means the entire text matched by the whole regexp or whole string. | |
180 STRING should be given if the last search was by `string-match' on STRING." | |
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181 (if (match-beginning num) |
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182 (if string |
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183 (let ((result |
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184 (substring string |
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185 (match-beginning num) (match-end num)))) |
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186 (set-text-properties 0 (length result) nil result) |
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187 result) |
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188 (buffer-substring-no-properties (match-beginning num) |
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189 (match-end num) |
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190 (current-buffer))))) |
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191 ) |
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192 (error nil)) |
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193 (if (and (featurep 'custom) (fboundp 'custom-declare-variable)) |
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194 nil ;; We've got what we needed |
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195 ;; We have the old custom-library, hack around it! |
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196 (defmacro defgroup (&rest args) nil) |
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197 (defmacro customize (&rest args) |
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198 (message |
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199 "Sorry, Customize is not available with this version of Emacs")) |
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200 (defmacro defcustom (var value doc &rest args) |
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201 `(defvar ,var ,value ,doc)) |
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202 ) |
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203 (if (fboundp 'defface) |
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204 nil ; great! |
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205 (defmacro defface (var values doc &rest args) |
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206 `(make-face ,var)) |
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207 ) |
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208 |
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209 (if (and (featurep 'custom) (fboundp 'customize-group)) |
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210 nil ;; We've got what we needed |
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211 ;; We have an intermediate custom-library, hack around it! |
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212 (defmacro customize-group (var &rest args) |
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213 `(customize ,var)) |
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214 ))) |
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215 |
79545 | 216 ;; Provide a regular expression optimization routine, using regexp-opt |
217 ;; if provided by the user's elisp libraries | |
218 (eval-and-compile | |
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219 ;; The below were disabled when GNU Emacs 22 was released; |
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220 ;; perhaps some still need to be there to support Emacs 21. |
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221 (if (featurep 'xemacs) |
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222 (if (fboundp 'regexp-opt) |
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223 ;; regexp-opt is defined, does it take 3 or 2 arguments? |
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224 (if (fboundp 'function-max-args) |
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225 (let ((args (function-max-args `regexp-opt))) |
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226 (cond |
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227 ((eq args 3) ;; It takes 3 |
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228 (condition-case nil ; Hide this defun from emacses |
79545 | 229 ;with just a two input regexp |
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230 (defun verilog-regexp-opt (a b) |
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231 "Deal with differing number of required arguments for `regexp-opt'. |
79545 | 232 Call 'regexp-opt' on A and B." |
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233 (regexp-opt a b 't)) |
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234 (error nil)) |
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235 ) |
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236 ((eq args 2) ;; It takes 2 |
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237 (defun verilog-regexp-opt (a b) |
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238 "Call 'regexp-opt' on A and B." |
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239 (regexp-opt a b)) |
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240 ) |
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241 (t nil))) |
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242 ;; We can't tell; assume it takes 2 |
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243 (defun verilog-regexp-opt (a b) |
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244 "Call 'regexp-opt' on A and B." |
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245 (regexp-opt a b)) |
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246 ) |
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247 ;; There is no regexp-opt, provide our own |
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248 (defun verilog-regexp-opt (strings &optional paren shy) |
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249 (let ((open (if paren "\\(" "")) (close (if paren "\\)" ""))) |
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250 (concat open (mapconcat 'regexp-quote strings "\\|") close))) |
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251 ) |
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252 ;; Emacs. |
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253 (defalias 'verilog-regexp-opt 'regexp-opt))) |
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255 (eval-when-compile |
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256 (defun verilog-regexp-words (a) |
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257 "Call 'regexp-opt' with word delimiters for the words A." |
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258 (concat "\\<" (verilog-regexp-opt a t) "\\>"))) |
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260 (defun verilog-easy-menu-filter (menu) |
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261 "Filter a easy-menu-define to support new features." |
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262 (cond ((not (featurep 'xemacs)) |
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263 menu) ;; GNU Emacs - passthru |
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264 ;; Xemacs doesn't support :help. Strip it. |
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265 ;; Recursively filter the a submenu |
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266 ((listp menu) |
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267 (mapcar 'verilog-easy-menu-filter menu)) |
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268 ;; Look for [:help "blah"] and remove |
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269 ((vectorp menu) |
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270 (let ((i 0) (out [])) |
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271 (while (< i (length menu)) |
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272 (if (equal `:help (aref menu i)) |
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273 (setq i (+ 2 i)) |
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274 (setq out (vconcat out (vector (aref menu i))) |
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275 i (1+ i)))) |
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276 out)) |
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277 (t menu))) ;; Default - ok |
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278 ;;(verilog-easy-menu-filter |
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279 ;; `("Verilog" ("MA" ["SAA" nil :help "Help SAA"] ["SAB" nil :help "Help SAA"]) |
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280 ;; "----" ["MB" nil :help "Help MB"])) |
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281 |
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283 "Customize variables and other settings used by Verilog-Mode." |
79545 | 284 (interactive) |
285 (customize-group 'verilog-mode)) | |
286 | |
287 (defun verilog-font-customize () | |
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288 "Customize fonts used by Verilog-Mode." |
79545 | 289 (interactive) |
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290 (if (fboundp 'customize-apropos) |
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291 (customize-apropos "font-lock-*" 'faces))) |
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293 (defun verilog-booleanp (value) |
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294 "Return t if VALUE is boolean. |
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295 This implements GNU Emacs 22.1's `booleanp' function in earlier Emacs. |
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296 This function may be removed when Emacs 21 is no longer supported." |
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297 (or (equal value t) (equal value nil))) |
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298 |
79545 | 299 (defgroup verilog-mode nil |
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300 "Facilitates easy editing of Verilog source text." |
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301 :version "22.2" |
79545 | 302 :group 'languages) |
303 | |
304 ; (defgroup verilog-mode-fonts nil | |
305 ; "Facilitates easy customization fonts used in Verilog source text" | |
306 ; :link '(customize-apropos "font-lock-*" 'faces) | |
307 ; :group 'verilog-mode) | |
308 | |
309 (defgroup verilog-mode-indent nil | |
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310 "Customize indentation and highlighting of Verilog source text." |
79545 | 311 :group 'verilog-mode) |
312 | |
313 (defgroup verilog-mode-actions nil | |
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314 "Customize actions on Verilog source text." |
79545 | 315 :group 'verilog-mode) |
316 | |
317 (defgroup verilog-mode-auto nil | |
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318 "Customize AUTO actions when expanding Verilog source text." |
79545 | 319 :group 'verilog-mode) |
320 | |
321 (defcustom verilog-linter | |
322 "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'" | |
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323 "*Unix program and arguments to call to run a lint checker on Verilog source. |
79545 | 324 Depending on the `verilog-set-compile-command', this may be invoked when |
325 you type \\[compile]. When the compile completes, \\[next-error] will take | |
326 you to the next lint error." | |
327 :type 'string | |
328 :group 'verilog-mode-actions) | |
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329 ;; We don't mark it safe, as it's used as a shell command |
79545 | 330 |
331 (defcustom verilog-coverage | |
332 "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'" | |
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333 "*Program and arguments to use to annotate for coverage Verilog source. |
79545 | 334 Depending on the `verilog-set-compile-command', this may be invoked when |
335 you type \\[compile]. When the compile completes, \\[next-error] will take | |
336 you to the next lint error." | |
337 :type 'string | |
338 :group 'verilog-mode-actions) | |
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339 ;; We don't mark it safe, as it's used as a shell command |
79545 | 340 |
341 (defcustom verilog-simulator | |
342 "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'" | |
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343 "*Program and arguments to use to interpret Verilog source. |
79545 | 344 Depending on the `verilog-set-compile-command', this may be invoked when |
345 you type \\[compile]. When the compile completes, \\[next-error] will take | |
346 you to the next lint error." | |
347 :type 'string | |
348 :group 'verilog-mode-actions) | |
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349 ;; We don't mark it safe, as it's used as a shell command |
79545 | 350 |
351 (defcustom verilog-compiler | |
352 "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'" | |
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353 "*Program and arguments to use to compile Verilog source. |
79545 | 354 Depending on the `verilog-set-compile-command', this may be invoked when |
355 you type \\[compile]. When the compile completes, \\[next-error] will take | |
356 you to the next lint error." | |
357 :type 'string | |
358 :group 'verilog-mode-actions) | |
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359 ;; We don't mark it safe, as it's used as a shell command |
79545 | 360 |
361 (defvar verilog-tool 'verilog-linter | |
362 "Which tool to use for building compiler-command. | |
363 Either nil, `verilog-linter, `verilog-coverage, `verilog-simulator, or | |
364 `verilog-compiler. Alternatively use the \"Choose Compilation Action\" | |
365 menu. See `verilog-set-compile-command' for more information.") | |
366 | |
367 (defcustom verilog-highlight-translate-off nil | |
368 "*Non-nil means background-highlight code excluded from translation. | |
369 That is, all code between \"// synopsys translate_off\" and | |
370 \"// synopsys translate_on\" is highlighted using a different background color | |
371 \(face `verilog-font-lock-translate-off-face'). | |
372 | |
373 Note: This will slow down on-the-fly fontification (and thus editing). | |
374 | |
375 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu | |
376 entry \"Fontify Buffer\"). XEmacs: turn off and on font locking." | |
377 :type 'boolean | |
378 :group 'verilog-mode-indent) | |
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379 ;; Note we don't use :safe, as that would break on Emacsen before 22.0. |
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380 (put 'verilog-highlight-translate-off 'safe-local-variable 'verilog-booleanp) |
79545 | 381 |
382 (defcustom verilog-indent-level 3 | |
383 "*Indentation of Verilog statements with respect to containing block." | |
384 :group 'verilog-mode-indent | |
385 :type 'integer) | |
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386 (put 'verilog-indent-level 'safe-local-variable 'integerp) |
79545 | 387 |
388 (defcustom verilog-indent-level-module 3 | |
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389 "*Indentation of Module level Verilog statements (eg always, initial). |
79545 | 390 Set to 0 to get initial and always statements lined up on the left side of |
391 your screen." | |
392 :group 'verilog-mode-indent | |
393 :type 'integer) | |
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394 (put 'verilog-indent-level-module 'safe-local-variable 'integerp) |
79545 | 395 |
396 (defcustom verilog-indent-level-declaration 3 | |
397 "*Indentation of declarations with respect to containing block. | |
398 Set to 0 to get them list right under containing block." | |
399 :group 'verilog-mode-indent | |
400 :type 'integer) | |
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401 (put 'verilog-indent-level-declaration 'safe-local-variable 'integerp) |
79545 | 402 |
403 (defcustom verilog-indent-declaration-macros nil | |
404 "*How to treat macro expansions in a declaration. | |
405 If nil, indent as: | |
406 input [31:0] a; | |
407 input `CP; | |
408 output c; | |
409 If non nil, treat as: | |
410 input [31:0] a; | |
411 input `CP ; | |
412 output c;" | |
413 :group 'verilog-mode-indent | |
414 :type 'boolean) | |
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415 (put 'verilog-indent-declaration-macros 'safe-local-variable 'verilog-booleanp) |
79545 | 416 |
417 (defcustom verilog-indent-lists t | |
418 "*How to treat indenting items in a list. | |
419 If t (the default), indent as: | |
420 always @( posedge a or | |
421 reset ) begin | |
422 | |
423 If nil, treat as: | |
424 always @( posedge a or | |
425 reset ) begin" | |
426 :group 'verilog-mode-indent | |
427 :type 'boolean) | |
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428 (put 'verilog-indent-lists 'safe-local-variable 'verilog-booleanp) |
79545 | 429 |
430 (defcustom verilog-indent-level-behavioral 3 | |
431 "*Absolute indentation of first begin in a task or function block. | |
432 Set to 0 to get such code to start at the left side of the screen." | |
433 :group 'verilog-mode-indent | |
434 :type 'integer) | |
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435 (put 'verilog-indent-level-behavioral 'safe-local-variable 'integerp) |
79545 | 436 |
437 (defcustom verilog-indent-level-directive 1 | |
438 "*Indentation to add to each level of `ifdef declarations. | |
439 Set to 0 to have all directives start at the left side of the screen." | |
440 :group 'verilog-mode-indent | |
441 :type 'integer) | |
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442 (put 'verilog-indent-level-directive 'safe-local-variable 'integerp) |
79545 | 443 |
444 (defcustom verilog-cexp-indent 2 | |
445 "*Indentation of Verilog statements split across lines." | |
446 :group 'verilog-mode-indent | |
447 :type 'integer) | |
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448 (put 'verilog-cexp-indent 'safe-local-variable 'integerp) |
79545 | 449 |
450 (defcustom verilog-case-indent 2 | |
451 "*Indentation for case statements." | |
452 :group 'verilog-mode-indent | |
453 :type 'integer) | |
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454 (put 'verilog-case-indent 'safe-local-variable 'integerp) |
79545 | 455 |
456 (defcustom verilog-auto-newline t | |
457 "*True means automatically newline after semicolons." | |
458 :group 'verilog-mode-indent | |
459 :type 'boolean) | |
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460 (put 'verilog-auto-newline 'safe-local-variable 'verilog-booleanp) |
79545 | 461 |
462 (defcustom verilog-auto-indent-on-newline t | |
463 "*True means automatically indent line after newline." | |
464 :group 'verilog-mode-indent | |
465 :type 'boolean) | |
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466 (put 'verilog-auto-indent-on-newline 'safe-local-variable 'verilog-booleanp) |
79545 | 467 |
468 (defcustom verilog-tab-always-indent t | |
469 "*True means TAB should always re-indent the current line. | |
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470 A nil value means TAB will only reindent when at the beginning of the line." |
79545 | 471 :group 'verilog-mode-indent |
472 :type 'boolean) | |
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473 (put 'verilog-tab-always-indent 'safe-local-variable 'verilog-booleanp) |
79545 | 474 |
475 (defcustom verilog-tab-to-comment nil | |
476 "*True means TAB moves to the right hand column in preparation for a comment." | |
477 :group 'verilog-mode-actions | |
478 :type 'boolean) | |
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479 (put 'verilog-tab-to-comment 'safe-local-variable 'verilog-booleanp) |
79545 | 480 |
481 (defcustom verilog-indent-begin-after-if t | |
482 "*If true, indent begin statements following if, else, while, for and repeat. | |
483 Otherwise, line them up." | |
484 :group 'verilog-mode-indent | |
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485 :type 'boolean) |
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486 (put 'verilog-indent-begin-after-if 'safe-local-variable 'verilog-booleanp) |
79545 | 487 |
488 | |
489 (defcustom verilog-align-ifelse nil | |
490 "*If true, align `else' under matching `if'. | |
491 Otherwise else is lined up with first character on line holding matching if." | |
492 :group 'verilog-mode-indent | |
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493 :type 'boolean) |
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494 (put 'verilog-align-ifelse 'safe-local-variable 'verilog-booleanp) |
79545 | 495 |
496 (defcustom verilog-minimum-comment-distance 10 | |
497 "*Minimum distance (in lines) between begin and end required before a comment. | |
498 Setting this variable to zero results in every end acquiring a comment; the | |
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499 default avoids too many redundant comments in tight quarters." |
79545 | 500 :group 'verilog-mode-indent |
501 :type 'integer) | |
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502 (put 'verilog-minimum-comment-distance 'safe-local-variable 'integerp) |
79545 | 503 |
504 (defcustom verilog-auto-lineup '(declaration) | |
505 "*Algorithm for lining up statements on multiple lines. | |
506 | |
507 If this list contains the symbol 'all', then all line ups described below | |
508 are done. | |
509 | |
510 If this list contains the symbol 'declaration', then declarations are lined up | |
511 with any preceding declarations, taking into account widths and the like, so | |
512 for example the code: | |
513 reg [31:0] a; | |
514 reg b; | |
515 would become | |
516 reg [31:0] a; | |
517 reg b; | |
518 | |
519 If this list contains the symbol 'assignment', then assignments are lined up | |
520 with any preceding assignments, so for example the code | |
521 a_long_variable = b + c; | |
522 d = e + f; | |
523 would become | |
524 a_long_variable = b + c; | |
525 d = e + f;" | |
526 | |
527 ;; The following is not implemented: | |
528 ;If this list contains the symbol 'case', then case items are lined up | |
529 ;with any preceding case items, so for example the code | |
530 ; case (a) begin | |
531 ; a_long_state : a = 3; | |
532 ; b: a = 4; | |
533 ; endcase | |
534 ;would become | |
535 ; case (a) begin | |
536 ; a_long_state : a = 3; | |
537 ; b : a = 4; | |
538 ; endcase | |
539 ; | |
540 | |
541 :group 'verilog-mode-indent | |
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542 :type 'list) |
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543 (put 'verilog-auto-lineup 'safe-local-variable 'listp) |
79545 | 544 |
545 (defcustom verilog-highlight-p1800-keywords nil | |
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546 "*True means highlight words newly reserved by IEEE-1800. |
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547 These will appear in `verilog-font-lock-p1800-face' in order to gently |
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548 suggest changing where these words are used as variables to something else. |
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549 A nil value means highlight these words as appropriate for the SystemVerilog |
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550 IEEE-1800 standard. Note that changing this will require restarting Emacs |
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551 to see the effect as font color choices are cached by Emacs." |
79545 | 552 :group 'verilog-mode-indent |
553 :type 'boolean) | |
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554 (put 'verilog-highlight-p1800-keywords 'safe-local-variable 'verilog-booleanp) |
79545 | 555 |
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556 (defcustom verilog-highlight-grouping-keywords nil |
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557 "*True means highlight grouping keywords 'begin' and 'end' more dramatically. |
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558 If false, these words are in the font-lock-type-face; if True then they are in |
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559 `verilog-font-lock-ams-face'. Some find that special highlighting on these |
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560 grouping constructs allow the structure of the code to be understood at a glance." |
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561 :group 'verilog-mode-indent |
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562 :type 'boolean) |
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563 (put 'verilog-highlight-grouping-keywords 'safe-local-variable 'verilog-booleanp) |
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564 |
79545 | 565 (defcustom verilog-auto-endcomments t |
566 "*True means insert a comment /* ... */ after 'end's. | |
567 The name of the function or case will be set between the braces." | |
568 :group 'verilog-mode-actions | |
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569 :type 'boolean) |
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570 (put 'verilog-auto-endcomments 'safe-local-variable 'verilog-booleanp) |
79545 | 571 |
572 (defcustom verilog-auto-read-includes nil | |
573 "*True means to automatically read includes before AUTOs. | |
574 This will do a `verilog-read-defines' and `verilog-read-includes' before | |
575 each AUTO expansion. This makes it easier to embed defines and includes, | |
576 but can result in very slow reading times if there are many or large | |
577 include files." | |
578 :group 'verilog-mode-actions | |
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579 :type 'boolean) |
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580 (put 'verilog-auto-read-includes 'safe-local-variable 'verilog-booleanp) |
79545 | 581 |
582 (defcustom verilog-auto-save-policy nil | |
583 "*Non-nil indicates action to take when saving a Verilog buffer with AUTOs. | |
584 A value of `force' will always do a \\[verilog-auto] automatically if | |
585 needed on every save. A value of `detect' will do \\[verilog-auto] | |
586 automatically when it thinks necessary. A value of `ask' will query the | |
587 user when it thinks updating is needed. | |
588 | |
589 You should not rely on the 'ask or 'detect policies, they are safeguards | |
590 only. They do not detect when AUTOINSTs need to be updated because a | |
591 sub-module's port list has changed." | |
592 :group 'verilog-mode-actions | |
593 :type '(choice (const nil) (const ask) (const detect) (const force))) | |
594 | |
595 (defcustom verilog-auto-star-expand t | |
596 "*Non-nil indicates to expand a SystemVerilog .* instance ports. | |
597 They will be expanded in the same way as if there was a AUTOINST in the | |
598 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'." | |
599 :group 'verilog-mode-actions | |
600 :type 'boolean) | |
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601 (put 'verilog-auto-star-expand 'safe-local-variable 'verilog-booleanp) |
79545 | 602 |
603 (defcustom verilog-auto-star-save nil | |
604 "*Non-nil indicates to save to disk SystemVerilog .* instance expansions. | |
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605 A nil value indicates direct connections will be removed before saving. |
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606 Only meaningful to those created due to `verilog-auto-star-expand' being set. |
79545 | 607 |
608 Instead of setting this, you may want to use /*AUTOINST*/, which will | |
609 always be saved." | |
610 :group 'verilog-mode-actions | |
611 :type 'boolean) | |
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612 (put 'verilog-auto-star-save 'safe-local-variable 'verilog-booleanp) |
79545 | 613 |
614 (defvar verilog-auto-update-tick nil | |
615 "Modification tick at which autos were last performed.") | |
616 | |
617 (defvar verilog-auto-last-file-locals nil | |
618 "Text from file-local-variables during last evaluation.") | |
619 | |
620 (defvar verilog-error-regexp-add-didit nil) | |
621 (defvar verilog-error-regexp nil) | |
622 (setq verilog-error-regexp-add-didit nil | |
623 verilog-error-regexp | |
624 '( | |
625 ; SureLint | |
626 ;; ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2) | |
627 ; Most SureFire tools | |
628 ("\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\), \\(line \\|\\)\\([0-9]+\\):" 2 4 ) | |
629 ("\ | |
630 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\ | |
631 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5) | |
632 ; xsim | |
633 ; Error! in file /homes/mac/Axis/Xsim/test.v at line 13 [OBJ_NOT_DECLARED] | |
634 ("\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3) | |
635 ; vcs | |
636 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3) | |
637 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2) | |
638 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3) | |
639 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2) | |
640 ; Verilator | |
641 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4) | |
642 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4) | |
643 ; vxl | |
644 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3) | |
645 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 2) ; vxl | |
646 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 2) | |
647 ; nc-verilog | |
648 (".*\\*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 2) | |
649 ; Leda | |
650 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 2) | |
651 ) | |
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652 ; "*List of regexps for Verilog compilers, like verilint. See compilation-error-regexp-alist for the formatting." |
79545 | 653 ) |
654 | |
655 (defvar verilog-error-font-lock-keywords | |
656 '( | |
657 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t) | |
658 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t) | |
659 | |
660 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t) | |
661 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t) | |
662 | |
663 ("\ | |
664 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\ | |
665 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t) | |
666 ("\ | |
667 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\ | |
668 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t) | |
669 | |
670 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t) | |
671 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t) | |
672 | |
673 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t) | |
674 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t) | |
675 | |
676 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t) | |
677 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t) | |
678 | |
679 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t) | |
680 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t) | |
681 | |
682 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t) | |
683 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t) | |
684 ; vxl | |
685 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t) | |
686 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t) | |
687 | |
688 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 bold t) | |
689 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 2 bold t) | |
690 | |
691 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 bold t) | |
692 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 2 bold t) | |
693 ; nc-verilog | |
694 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 bold t) | |
695 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t) | |
696 ; Leda | |
697 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 bold t) | |
698 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 2 bold t) | |
699 ) | |
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700 "*Keywords to also highlight in Verilog *compilation* buffers.") |
79545 | 701 |
702 (defcustom verilog-library-flags '("") | |
703 "*List of standard Verilog arguments to use for /*AUTOINST*/. | |
704 These arguments are used to find files for `verilog-auto', and match | |
705 the flags accepted by a standard Verilog-XL simulator. | |
706 | |
707 -f filename Reads more `verilog-library-flags' from the filename. | |
708 +incdir+dir Adds the directory to `verilog-library-directories'. | |
709 -Idir Adds the directory to `verilog-library-directories'. | |
710 -y dir Adds the directory to `verilog-library-directories'. | |
711 +libext+.v Adds the extensions to `verilog-library-extensions'. | |
712 -v filename Adds the filename to `verilog-library-files'. | |
713 | |
714 filename Adds the filename to `verilog-library-files'. | |
715 This is not recommended, -v is a better choice. | |
716 | |
717 You might want these defined in each file; put at the *END* of your file | |
718 something like: | |
719 | |
720 // Local Variables: | |
721 // verilog-library-flags:(\"-y dir -y otherdir\") | |
722 // End: | |
723 | |
724 Verilog-mode attempts to detect changes to this local variable, but they | |
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725 are only insured to be correct when the file is first visited. Thus if you |
79545 | 726 have problems, use \\[find-alternate-file] RET to have these take effect. |
727 | |
728 See also the variables mentioned above." | |
729 :group 'verilog-mode-auto | |
730 :type '(repeat string)) | |
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731 (put 'verilog-library-flags 'safe-local-variable 'listp) |
79545 | 732 |
733 (defcustom verilog-library-directories '(".") | |
734 "*List of directories when looking for files for /*AUTOINST*/. | |
735 The directory may be relative to the current file, or absolute. | |
736 Environment variables are also expanded in the directory names. | |
737 Having at least the current directory is a good idea. | |
738 | |
739 You might want these defined in each file; put at the *END* of your file | |
740 something like: | |
741 | |
742 // Local Variables: | |
743 // verilog-library-directories:(\".\" \"subdir\" \"subdir2\") | |
744 // End: | |
745 | |
746 Verilog-mode attempts to detect changes to this local variable, but they | |
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747 are only insured to be correct when the file is first visited. Thus if you |
79545 | 748 have problems, use \\[find-alternate-file] RET to have these take effect. |
749 | |
750 See also `verilog-library-flags', `verilog-library-files' | |
751 and `verilog-library-extensions'." | |
752 :group 'verilog-mode-auto | |
753 :type '(repeat file)) | |
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754 (put 'verilog-library-directories 'safe-local-variable 'listp) |
79545 | 755 |
756 (defcustom verilog-library-files '() | |
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757 "*List of files to search for modules. |
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758 AUTOINST will use this when it needs to resolve a module name. |
79545 | 759 This is a complete path, usually to a technology file with many standard |
760 cells defined in it. | |
761 | |
762 You might want these defined in each file; put at the *END* of your file | |
763 something like: | |
764 | |
765 // Local Variables: | |
766 // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\") | |
767 // End: | |
768 | |
769 Verilog-mode attempts to detect changes to this local variable, but they | |
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770 are only insured to be correct when the file is first visited. Thus if you |
79545 | 771 have problems, use \\[find-alternate-file] RET to have these take effect. |
772 | |
773 See also `verilog-library-flags', `verilog-library-directories'." | |
774 :group 'verilog-mode-auto | |
775 :type '(repeat directory)) | |
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776 (put 'verilog-library-files 'safe-local-variable 'listp) |
79545 | 777 |
778 (defcustom verilog-library-extensions '(".v") | |
779 "*List of extensions to use when looking for files for /*AUTOINST*/. | |
780 See also `verilog-library-flags', `verilog-library-directories'." | |
781 :type '(repeat string) | |
782 :group 'verilog-mode-auto) | |
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783 (put 'verilog-library-extensions 'safe-local-variable 'listp) |
79545 | 784 |
785 (defcustom verilog-active-low-regexp nil | |
786 "*If set, treat signals matching this regexp as active low. | |
787 This is used for AUTORESET and AUTOTIEOFF. For proper behavior, | |
788 you will probably also need `verilog-auto-reset-widths' set." | |
789 :group 'verilog-mode-auto | |
790 :type 'string) | |
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791 (put 'verilog-active-low-regexp 'safe-local-variable 'stringp) |
79545 | 792 |
793 (defcustom verilog-auto-sense-include-inputs nil | |
794 "*If true, AUTOSENSE should include all inputs. | |
795 If nil, only inputs that are NOT output signals in the same block are | |
796 included." | |
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797 :group 'verilog-mode-auto |
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798 :type 'boolean) |
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799 (put 'verilog-auto-sense-include-inputs 'safe-local-variable 'verilog-booleanp) |
79545 | 800 |
801 (defcustom verilog-auto-sense-defines-constant nil | |
802 "*If true, AUTOSENSE should assume all defines represent constants. | |
803 When true, the defines will not be included in sensitivity lists. To | |
804 maintain compatibility with other sites, this should be set at the bottom | |
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805 of each Verilog file that requires it, rather than being set globally." |
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806 :group 'verilog-mode-auto |
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807 :type 'boolean) |
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808 (put 'verilog-auto-sense-defines-constant 'safe-local-variable 'verilog-booleanp) |
79545 | 809 |
810 (defcustom verilog-auto-reset-widths t | |
811 "*If true, AUTORESET should determine the width of signals. | |
812 This is then used to set the width of the zero (32'h0 for example). This | |
813 is required by some lint tools that aren't smart enough to ignore widths of | |
814 the constant zero. This may result in ugly code when parameters determine | |
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815 the MSB or LSB of a signal inside an AUTORESET." |
79545 | 816 :type 'boolean |
817 :group 'verilog-mode-auto) | |
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818 (put 'verilog-auto-reset-widths 'safe-local-variable 'verilog-booleanp) |
79545 | 819 |
820 (defcustom verilog-assignment-delay "" | |
821 "*Text used for delays in delayed assignments. Add a trailing space if set." | |
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822 :group 'verilog-mode-auto |
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823 :type 'string) |
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824 (put 'verilog-assignment-delay 'safe-local-variable 'stringp) |
79545 | 825 |
826 (defcustom verilog-auto-inst-vector t | |
827 "*If true, when creating default ports with AUTOINST, use bus subscripts. | |
828 If nil, skip the subscript when it matches the entire bus as declared in | |
829 the module (AUTOWIRE signals always are subscripted, you must manually | |
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830 declare the wire to have the subscripts removed.) Setting this to nil may |
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831 speed up some simulators, but is less general and harder to read, so avoid." |
79545 | 832 :group 'verilog-mode-auto |
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833 :type 'boolean) |
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834 (put 'verilog-auto-inst-vector 'safe-local-variable 'verilog-booleanp) |
79545 | 835 |
836 (defcustom verilog-auto-inst-template-numbers nil | |
837 "*If true, when creating templated ports with AUTOINST, add a comment. | |
838 The comment will add the line number of the template that was used for that | |
839 port declaration. Setting this aids in debugging, but nil is suggested for | |
840 regular use to prevent large numbers of merge conflicts." | |
841 :group 'verilog-mode-auto | |
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842 :type 'boolean) |
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843 (put 'verilog-auto-inst-template-numbers 'safe-local-variable 'verilog-booleanp) |
79545 | 844 |
845 (defvar verilog-auto-inst-column 40 | |
846 "Column number for first part of auto-inst.") | |
847 | |
848 (defcustom verilog-auto-input-ignore-regexp nil | |
849 "*If set, when creating AUTOINPUT list, ignore signals matching this regexp. | |
850 See the \\[verilog-faq] for examples on using this." | |
851 :group 'verilog-mode-auto | |
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852 :type 'string) |
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853 (put 'verilog-auto-input-ignore-regexp 'safe-local-variable 'stringp) |
79545 | 854 |
855 (defcustom verilog-auto-inout-ignore-regexp nil | |
856 "*If set, when creating AUTOINOUT list, ignore signals matching this regexp. | |
857 See the \\[verilog-faq] for examples on using this." | |
858 :group 'verilog-mode-auto | |
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859 :type 'string) |
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860 (put 'verilog-auto-inout-ignore-regexp 'safe-local-variable 'stringp) |
79545 | 861 |
862 (defcustom verilog-auto-output-ignore-regexp nil | |
863 "*If set, when creating AUTOOUTPUT list, ignore signals matching this regexp. | |
864 See the \\[verilog-faq] for examples on using this." | |
865 :group 'verilog-mode-auto | |
79799
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(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
866 :type 'string) |
57956dd69d3f
(top-level): Fix spacing.
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diff
changeset
|
867 (put 'verilog-auto-output-ignore-regexp 'safe-local-variable 'stringp) |
79545 | 868 |
869 (defcustom verilog-auto-unused-ignore-regexp nil | |
870 "*If set, when creating AUTOUNUSED list, ignore signals matching this regexp. | |
871 See the \\[verilog-faq] for examples on using this." | |
872 :group 'verilog-mode-auto | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
873 :type 'string) |
57956dd69d3f
(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
874 (put 'verilog-auto-unused-ignore-regexp 'safe-local-variable 'stringp) |
79545 | 875 |
876 (defcustom verilog-typedef-regexp nil | |
877 "*If non-nil, regular expression that matches Verilog-2001 typedef names. | |
878 For example, \"_t$\" matches typedefs named with _t, as in the C language." | |
879 :group 'verilog-mode-auto | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
880 :type 'string) |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
881 (put 'verilog-typedef-regexp 'safe-local-variable 'stringp) |
79545 | 882 |
883 (defcustom verilog-mode-hook 'verilog-set-compile-command | |
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Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
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80163
diff
changeset
|
884 "*Hook run after Verilog mode is loaded." |
79545 | 885 :type 'hook |
886 :group 'verilog-mode) | |
887 | |
888 (defcustom verilog-auto-hook nil | |
889 "*Hook run after `verilog-mode' updates AUTOs." | |
79799
57956dd69d3f
(top-level): Fix spacing.
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parents:
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diff
changeset
|
890 :group 'verilog-mode-auto |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
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diff
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|
891 :type 'hook) |
79545 | 892 |
893 (defcustom verilog-before-auto-hook nil | |
894 "*Hook run before `verilog-mode' updates AUTOs." | |
79799
57956dd69d3f
(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
895 :group 'verilog-mode-auto |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
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|
896 :type 'hook) |
79545 | 897 |
898 (defcustom verilog-delete-auto-hook nil | |
899 "*Hook run after `verilog-mode' deletes AUTOs." | |
79799
57956dd69d3f
(top-level): Fix spacing.
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parents:
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diff
changeset
|
900 :group 'verilog-mode-auto |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
901 :type 'hook) |
79545 | 902 |
903 (defcustom verilog-before-delete-auto-hook nil | |
904 "*Hook run before `verilog-mode' deletes AUTOs." | |
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(top-level): Fix spacing.
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parents:
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diff
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|
905 :group 'verilog-mode-auto |
57956dd69d3f
(top-level): Fix spacing.
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79717
diff
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|
906 :type 'hook) |
79545 | 907 |
908 (defcustom verilog-getopt-flags-hook nil | |
909 "*Hook run after `verilog-getopt-flags' determines the Verilog option lists." | |
79799
57956dd69d3f
(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
910 :group 'verilog-mode-auto |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
911 :type 'hook) |
79545 | 912 |
913 (defcustom verilog-before-getopt-flags-hook nil | |
914 "*Hook run before `verilog-getopt-flags' determines the Verilog option lists." | |
79799
57956dd69d3f
(top-level): Fix spacing.
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parents:
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diff
changeset
|
915 :group 'verilog-mode-auto |
57956dd69d3f
(top-level): Fix spacing.
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parents:
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|
916 :type 'hook) |
79545 | 917 |
918 (defvar verilog-imenu-generic-expression | |
919 '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4) | |
920 ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3)) | |
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parents:
80163
diff
changeset
|
921 "Imenu expression for Verilog mode. See `imenu-generic-expression'.") |
79545 | 922 |
923 ;; | |
924 ;; provide a verilog-header function. | |
925 ;; Customization variables: | |
926 ;; | |
927 (defvar verilog-date-scientific-format nil | |
928 "*If non-nil, dates are written in scientific format (e.g. 1997/09/17). | |
929 If nil, in European format (e.g. 17.09.1997). The brain-dead American | |
930 format (e.g. 09/17/1997) is not supported.") | |
931 | |
932 (defvar verilog-company nil | |
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parents:
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diff
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|
933 "*Default name of Company for Verilog header. |
79545 | 934 If set will become buffer local.") |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
935 (make-variable-buffer-local 'verilog-company) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
936 |
79545 | 937 (defvar verilog-project nil |
80165
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Re-commit doc fixes accidentally reverted.
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parents:
80163
diff
changeset
|
938 "*Default name of Project for Verilog header. |
79545 | 939 If set will become buffer local.") |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
940 (make-variable-buffer-local 'verilog-project) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
941 |
79549
d9595ed9b084
* progmodes/verilog-mode.el (verilog-mode-map): Fix typo.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79547
diff
changeset
|
942 (defvar verilog-mode-map |
79546 | 943 (let ((map (make-sparse-keymap))) |
944 (define-key map ";" 'electric-verilog-semi) | |
945 (define-key map [(control 59)] 'electric-verilog-semi-with-comment) | |
946 (define-key map ":" 'electric-verilog-colon) | |
947 ;;(define-key map "=" 'electric-verilog-equal) | |
948 (define-key map "\`" 'electric-verilog-tick) | |
949 (define-key map "\t" 'electric-verilog-tab) | |
950 (define-key map "\r" 'electric-verilog-terminate-line) | |
951 ;; backspace/delete key bindings | |
952 (define-key map [backspace] 'backward-delete-char-untabify) | |
953 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable | |
954 (define-key map [delete] 'delete-char) | |
955 (define-key map [(meta delete)] 'kill-word)) | |
956 (define-key map "\M-\C-b" 'electric-verilog-backward-sexp) | |
957 (define-key map "\M-\C-f" 'electric-verilog-forward-sexp) | |
958 (define-key map "\M-\r" `electric-verilog-terminate-and-indent) | |
959 (define-key map "\M-\t" 'verilog-complete-word) | |
960 (define-key map "\M-?" 'verilog-show-completions) | |
961 (define-key map "\C-c\`" 'verilog-lint-off) | |
962 (define-key map "\C-c\*" 'verilog-delete-auto-star-implicit) | |
963 (define-key map "\C-c\C-r" 'verilog-label-be) | |
964 (define-key map "\C-c\C-i" 'verilog-pretty-declarations) | |
965 (define-key map "\C-c=" 'verilog-pretty-expr) | |
966 (define-key map "\C-c\C-b" 'verilog-submit-bug-report) | |
967 (define-key map "\M-*" 'verilog-star-comment) | |
968 (define-key map "\C-c\C-c" 'verilog-comment-region) | |
969 (define-key map "\C-c\C-u" 'verilog-uncomment-region) | |
79810
606faa750dd7
(verilog-mode-map): Don't bind C-M-a,
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79801
diff
changeset
|
970 (when (featurep 'xemacs) |
606faa750dd7
(verilog-mode-map): Don't bind C-M-a,
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parents:
79801
diff
changeset
|
971 (define-key map [(meta control h)] 'verilog-mark-defun) |
606faa750dd7
(verilog-mode-map): Don't bind C-M-a,
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79801
diff
changeset
|
972 (define-key map "\M-\C-a" 'verilog-beg-of-defun) |
606faa750dd7
(verilog-mode-map): Don't bind C-M-a,
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parents:
79801
diff
changeset
|
973 (define-key map "\M-\C-e" 'verilog-end-of-defun)) |
79546 | 974 (define-key map "\C-c\C-d" 'verilog-goto-defun) |
975 (define-key map "\C-c\C-k" 'verilog-delete-auto) | |
976 (define-key map "\C-c\C-a" 'verilog-auto) | |
977 (define-key map "\C-c\C-s" 'verilog-auto-save-compile) | |
978 (define-key map "\C-c\C-z" 'verilog-inject-auto) | |
979 (define-key map "\C-c\C-e" 'verilog-expand-vector) | |
79550
7f3b93a179a2
* progmodes/verilog-mode.el (verilog-mode-map)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79549
diff
changeset
|
980 (define-key map "\C-c\C-h" 'verilog-header) |
7f3b93a179a2
* progmodes/verilog-mode.el (verilog-mode-map)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79549
diff
changeset
|
981 map) |
79545 | 982 "Keymap used in Verilog mode.") |
983 | |
984 ;; menus | |
80172
7d8f87158250
(eval-when-compile): Don't define
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80171
diff
changeset
|
985 (easy-menu-define |
7d8f87158250
(eval-when-compile): Don't define
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80171
diff
changeset
|
986 verilog-menu verilog-mode-map "Menu for Verilog mode" |
80355
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
987 '("Verilog" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
988 ("Choose Compilation Action" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
989 ["None" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
990 (progn |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
991 (setq verilog-tool nil) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
992 (verilog-set-compile-command)) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
993 :style radio |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
994 :selected (equal verilog-tool nil) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
995 :help "When invoking compilation, use compile-command"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
996 ["Lint" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
997 (progn |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
998 (setq verilog-tool 'verilog-linter) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
999 (verilog-set-compile-command)) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1000 :style radio |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1001 :selected (equal verilog-tool `verilog-linter) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1002 :help "When invoking compilation, use lint checker"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1003 ["Coverage" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1004 (progn |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1005 (setq verilog-tool 'verilog-coverage) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1006 (verilog-set-compile-command)) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1007 :style radio |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1008 :selected (equal verilog-tool `verilog-coverage) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1009 :help "When invoking compilation, annotate for coverage"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1010 ["Simulator" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1011 (progn |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1012 (setq verilog-tool 'verilog-simulator) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1013 (verilog-set-compile-command)) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1014 :style radio |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1015 :selected (equal verilog-tool `verilog-simulator) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1016 :help "When invoking compilation, interpret Verilog source"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1017 ["Compiler" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1018 (progn |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1019 (setq verilog-tool 'verilog-compiler) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1020 (verilog-set-compile-command)) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1021 :style radio |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1022 :selected (equal verilog-tool `verilog-compiler) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1023 :help "When invoking compilation, compile Verilog source"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1024 ) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1025 ("Move" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1026 ["Beginning of function" verilog-beg-of-defun |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
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parents:
80342
diff
changeset
|
1027 :keys "C-M-a" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1028 :help "Move backward to the beginning of the current function or procedure"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1029 ["End of function" verilog-end-of-defun |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1030 :keys "C-M-e" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1031 :help "Move forward to the end of the current function or procedure"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1032 ["Mark function" verilog-mark-defun |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1033 :keys "C-M-h" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1034 :help "Mark the current Verilog function or procedure"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1035 ["Goto function/module" verilog-goto-defun |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1036 :help "Move to specified Verilog module/task/function"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1037 ["Move to beginning of block" electric-verilog-backward-sexp |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1038 :help "Move backward over one balanced expression"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1039 ["Move to end of block" electric-verilog-forward-sexp |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1040 :help "Move forward over one balanced expression"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1041 ) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1042 ("Comments" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1043 ["Comment Region" verilog-comment-region |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1044 :help "Put marked area into a comment"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1045 ["UnComment Region" verilog-uncomment-region |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1046 :help "Uncomment an area commented with Comment Region"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1047 ["Multi-line comment insert" verilog-star-comment |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1048 :help "Insert Verilog /* */ comment at point"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1049 ["Lint error to comment" verilog-lint-off |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1050 :help "Convert a Verilog linter warning line into a disable statement"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1051 ) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1052 "----" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1053 ["Compile" compile |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1054 :help "Perform compilation-action (above) on the current buffer"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1055 ["AUTO, Save, Compile" verilog-auto-save-compile |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1056 :help "Recompute AUTOs, save buffer, and compile"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1057 ["Next Compile Error" next-error |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1058 :help "Visit next compilation error message and corresponding source code"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1059 ["Ignore Lint Warning at point" verilog-lint-off |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1060 :help "Convert a Verilog linter warning line into a disable statement"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1061 "----" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1062 ["Line up declarations around point" verilog-pretty-declarations |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1063 :help "Line up declarations around point"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1064 ["Line up equations around point" verilog-pretty-expr |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1065 :help "Line up expressions around point"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1066 ["Redo/insert comments on every end" verilog-label-be |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1067 :help "Label matching begin ... end statements"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1068 ["Expand [x:y] vector line" verilog-expand-vector |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1069 :help "Take a signal vector on the current line and expand it to multiple lines"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1070 ["Insert begin-end block" verilog-insert-block |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1071 :help "Insert begin ... end"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1072 ["Complete word" verilog-complete-word |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1073 :help "Complete word at point"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1074 "----" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1075 ["Recompute AUTOs" verilog-auto |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1076 :help "Expand AUTO meta-comment statements"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1077 ["Kill AUTOs" verilog-delete-auto |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1078 :help "Remove AUTO expansions"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1079 ["Inject AUTOs" verilog-inject-auto |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1080 :help "Inject AUTOs into legacy non-AUTO buffer"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1081 ("AUTO Help..." |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1082 ["AUTO General" (describe-function 'verilog-auto) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1083 :help "Help introduction on AUTOs"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1084 ["AUTO Library Flags" (describe-variable 'verilog-library-flags) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1085 :help "Help on verilog-library-flags"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1086 ["AUTO Library Path" (describe-variable 'verilog-library-directories) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1087 :help "Help on verilog-library-directories"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1088 ["AUTO Library Files" (describe-variable 'verilog-library-files) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1089 :help "Help on verilog-library-files"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1090 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1091 :help "Help on verilog-library-extensions"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1092 ["AUTO `define Reading" (describe-function 'verilog-read-defines) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1093 :help "Help on reading `defines"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1094 ["AUTO `include Reading" (describe-function 'verilog-read-includes) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1095 :help "Help on parsing `includes"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1096 ["AUTOARG" (describe-function 'verilog-auto-arg) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1097 :help "Help on AUTOARG - declaring module port list"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1098 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1099 :help "Help on AUTOASCIIENUM - creating ASCII for enumerations"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1100 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1101 :help "Help on AUTOINOUTMODULE - copying i/o from another file"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1102 ["AUTOINOUT" (describe-function 'verilog-auto-inout) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1103 :help "Help on AUTOINOUT - adding inouts from cells"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1104 ["AUTOINPUT" (describe-function 'verilog-auto-input) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1105 :help "Help on AUTOINPUT - adding inputs from cells"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1106 ["AUTOINST" (describe-function 'verilog-auto-inst) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1107 :help "Help on AUTOINST - adding pins for cells"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1108 ["AUTOINST (.*)" (describe-function 'verilog-auto-star) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1109 :help "Help on expanding Verilog-2001 .* pins"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1110 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1111 :help "Help on AUTOINSTPARAM - adding parameter pins to cells"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1112 ["AUTOOUTPUT" (describe-function 'verilog-auto-output) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1113 :help "Help on AUTOOUTPUT - adding outputs from cells"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1114 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1115 :help "Help on AUTOOUTPUTEVERY - adding outputs of all signals"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1116 ["AUTOREG" (describe-function 'verilog-auto-reg) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1117 :help "Help on AUTOREG - declaring registers for non-wires"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1118 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1119 :help "Help on AUTOREGINPUT - declaring inputs for non-wires"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1120 ["AUTORESET" (describe-function 'verilog-auto-reset) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1121 :help "Help on AUTORESET - resetting always blocks"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1122 ["AUTOSENSE" (describe-function 'verilog-auto-sense) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1123 :help "Help on AUTOSENSE - sensitivity lists for always blocks"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1124 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1125 :help "Help on AUTOTIEOFF - tieing off unused outputs"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1126 ["AUTOUNUSED" (describe-function 'verilog-auto-unused) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1127 :help "Help on AUTOUNUSED - terminating unused inputs"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1128 ["AUTOWIRE" (describe-function 'verilog-auto-wire) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1129 :help "Help on AUTOWIRE - declaring wires for cells"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1130 ) |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1131 "----" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1132 ["Submit bug report" verilog-submit-bug-report |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1133 :help "Submit via mail a bug report on verilog-mode.el"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1134 ["Version and FAQ" verilog-faq |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1135 :help "Show the current version, and where to get the FAQ etc"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1136 ["Customize Verilog Mode..." verilog-customize |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1137 :help "Customize variables and other settings used by Verilog-Mode"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1138 ["Customize Verilog Fonts & Colors" verilog-font-customize |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1139 :help "Customize fonts used by Verilog-Mode."])) |
80172
7d8f87158250
(eval-when-compile): Don't define
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80171
diff
changeset
|
1140 |
7d8f87158250
(eval-when-compile): Don't define
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80171
diff
changeset
|
1141 (easy-menu-define |
7d8f87158250
(eval-when-compile): Don't define
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80171
diff
changeset
|
1142 verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog." |
80355
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1143 '("Statements" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1144 ["Header" verilog-sk-header |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1145 :help "Insert a header block at the top of file"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1146 ["Comment" verilog-sk-comment |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1147 :help "Insert a comment block"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1148 "----" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1149 ["Module" verilog-sk-module |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1150 :help "Insert a module .. (/*AUTOARG*/);.. endmodule block"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1151 ["Primitive" verilog-sk-primitive |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1152 :help "Insert a primitive .. (.. );.. endprimitive block"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1153 "----" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1154 ["Input" verilog-sk-input |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1155 :help "Insert an input declaration"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1156 ["Output" verilog-sk-output |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1157 :help "Insert an output declaration"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1158 ["Inout" verilog-sk-inout |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1159 :help "Insert an inout declaration"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1160 ["Wire" verilog-sk-wire |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1161 :help "Insert a wire declaration"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1162 ["Reg" verilog-sk-reg |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1163 :help "Insert a register declaration"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1164 ["Define thing under point as a register" verilog-sk-define-signal |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1165 :help "Define signal under point as a register at the top of the module"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1166 "----" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1167 ["Initial" verilog-sk-initial |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1168 :help "Insert an initial begin .. end block"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1169 ["Always" verilog-sk-always |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1170 :help "Insert an always @(AS) begin .. end block"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1171 ["Function" verilog-sk-function |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1172 :help "Insert a function .. begin .. end endfunction block"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1173 ["Task" verilog-sk-task |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1174 :help "Insert a task .. begin .. end endtask block"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1175 ["Specify" verilog-sk-specify |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1176 :help "Insert a specify .. endspecify block"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1177 ["Generate" verilog-sk-generate |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1178 :help "Insert a generate .. endgenerate block"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1179 "----" |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1180 ["Begin" verilog-sk-begin |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1181 :help "Insert a begin .. end block"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1182 ["If" verilog-sk-if |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1183 :help "Insert an if (..) begin .. end block"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1184 ["(if) else" verilog-sk-else-if |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1185 :help "Insert an else if (..) begin .. end block"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1186 ["For" verilog-sk-for |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1187 :help "Insert a for (...) begin .. end block"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1188 ["While" verilog-sk-while |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1189 :help "Insert a while (...) begin .. end block"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1190 ["Fork" verilog-sk-fork |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1191 :help "Insert a fork begin .. end .. join block"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1192 ["Repeat" verilog-sk-repeat |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1193 :help "Insert a repeat (..) begin .. end block"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1194 ["Case" verilog-sk-case |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1195 :help "Insert a case block, prompting for details"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1196 ["Casex" verilog-sk-casex |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1197 :help "Insert a casex (...) item: begin.. end endcase block"] |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1198 ["Casez" verilog-sk-casez |
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1199 :help "Insert a casez (...) item: begin.. end endcase block"])) |
79545 | 1200 |
1201 (defvar verilog-mode-abbrev-table nil | |
1202 "Abbrev table in use in Verilog-mode buffers.") | |
1203 | |
1204 (define-abbrev-table 'verilog-mode-abbrev-table ()) | |
1205 | |
79547
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1206 ;; |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1207 ;; Macros |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1208 ;; |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1209 |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1210 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string) |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1211 "Replace occurrences of FROM-STRING with TO-STRING. |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1212 FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace. |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1213 The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\") |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1214 will break, as the o's continuously replace. xa -> x works ok though." |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1215 ;; Hopefully soon to a emacs built-in |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1216 (let ((start 0)) |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1217 (while (string-match from-string string start) |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1218 (setq string (replace-match to-string fixedcase literal string) |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1219 start (min (length string) (match-end 0)))) |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1220 string)) |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1221 |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1222 (defsubst verilog-string-remove-spaces (string) |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1223 "Remove spaces surrounding STRING." |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1224 (save-match-data |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1225 (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string)) |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1226 (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string)) |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1227 string)) |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1228 |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1229 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR) |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1230 ; checkdoc-params: (REGEXP BOUND NOERROR) |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1231 "Like `re-search-forward', but skips over match in comments or strings." |
80355
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
1232 (store-match-data '(nil nil)) ;; So match-end will return nil if no matches found |
79547
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1233 (while (and |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1234 (re-search-forward REGEXP BOUND NOERROR) |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1235 (and (verilog-skip-forward-comment-or-string) |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1236 (progn |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1237 (store-match-data '(nil nil)) |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1238 (if BOUND |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1239 (< (point) BOUND) |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
1240 t))))) |
79547
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1241 (match-end 0)) |
46725aa288e8
(verilog-string-replace-matches)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79546
diff
changeset
|
1242 |
46725aa288e8
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1243 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR) |
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1244 ; checkdoc-params: (REGEXP BOUND NOERROR) |
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1245 "Like `re-search-backward', but skips over match in comments or strings." |
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1246 (store-match-data '(nil nil)) ;; So match-end will return nil if no matches found |
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1247 (while (and |
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1248 (re-search-backward REGEXP BOUND NOERROR) |
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1249 (and (verilog-skip-backward-comment-or-string) |
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1250 (progn |
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1251 (store-match-data '(nil nil)) |
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1252 (if BOUND |
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1253 (> (point) BOUND) |
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1254 t))))) |
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1255 (match-end 0)) |
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1256 |
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1257 (defsubst verilog-re-search-forward-quick (regexp bound noerror) |
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1258 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR, |
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1259 but trashes match data and is faster for REGEXP that doesn't match often. |
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1260 This may at some point use text properties to ignore comments, |
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1261 so there may be a large up front penalty for the first search." |
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1262 (let (pt) |
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1263 (while (and (not pt) |
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1264 (re-search-forward regexp bound noerror)) |
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1265 (if (not (verilog-inside-comment-p)) |
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1266 (setq pt (match-end 0)))) |
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1267 pt)) |
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1268 |
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1269 (defsubst verilog-re-search-backward-quick (regexp bound noerror) |
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1270 ; checkdoc-params: (REGEXP BOUND NOERROR) |
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1271 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR, |
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1272 but trashes match data and is faster for REGEXP that doesn't match often. |
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1273 This may at some point use text properties to ignore comments, |
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1274 so there may be a large up front penalty for the first search." |
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1275 (let (pt) |
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1276 (while (and (not pt) |
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1277 (re-search-backward regexp bound noerror)) |
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1278 (if (not (verilog-inside-comment-p)) |
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1279 (setq pt (match-end 0)))) |
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1280 pt)) |
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|
1281 |
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1282 (defsubst verilog-get-beg-of-line (&optional arg) |
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1283 (save-excursion |
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1284 (beginning-of-line arg) |
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1285 (point))) |
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|
1286 |
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1287 (defsubst verilog-get-end-of-line (&optional arg) |
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1288 (save-excursion |
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1289 (end-of-line arg) |
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1290 (point))) |
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|
1291 |
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1292 (defsubst verilog-within-string () |
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1293 (save-excursion |
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1294 (nth 3 (parse-partial-sexp (verilog-get-beg-of-line) (point))))) |
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1295 |
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1296 (defvar compile-command) |
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1297 |
79545 | 1298 ;; compilation program |
1299 (defun verilog-set-compile-command () | |
80165
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1300 "Function to compute shell command to compile Verilog. |
79545 | 1301 |
1302 This reads `verilog-tool' and sets `compile-command'. This specifies the | |
1303 program that executes when you type \\[compile] or | |
1304 \\[verilog-auto-save-compile]. | |
1305 | |
1306 By default `verilog-tool' uses a Makefile if one exists in the current | |
1307 directory. If not, it is set to the `verilog-linter', `verilog-coverage', | |
1308 `verilog-simulator', or `verilog-compiler' variables, as selected with the | |
1309 Verilog -> \"Choose Compilation Action\" menu. | |
1310 | |
1311 You should set `verilog-tool' or the other variables to the path and | |
1312 arguments for your Verilog simulator. For example: | |
1313 \"vcs -p123 -O\" | |
1314 or a string like: | |
1315 \"(cd /tmp; surecov %s)\". | |
1316 | |
1317 In the former case, the path to the current buffer is concat'ed to the | |
1318 value of `verilog-tool'; in the later, the path to the current buffer is | |
1319 substituted for the %s. | |
1320 | |
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1321 Where __FILE__ appears in the string, the `buffer-file-name' of the |
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1322 current buffer, without the directory portion, will be substituted." |
79545 | 1323 (interactive) |
1324 (cond | |
1325 ((or (file-exists-p "makefile") ;If there is a makefile, use it | |
1326 (file-exists-p "Makefile")) | |
1327 (make-local-variable 'compile-command) | |
1328 (setq compile-command "make ")) | |
1329 (t | |
1330 (make-local-variable 'compile-command) | |
1331 (setq compile-command | |
1332 (if verilog-tool | |
1333 (if (string-match "%s" (eval verilog-tool)) | |
1334 (format (eval verilog-tool) (or buffer-file-name "")) | |
1335 (concat (eval verilog-tool) " " (or buffer-file-name ""))) | |
1336 "")))) | |
1337 (verilog-modify-compile-command)) | |
1338 | |
1339 (defun verilog-modify-compile-command () | |
1340 "Replace meta-information in `compile-command'. | |
1341 Where __FILE__ appears in the string, the current buffer's file-name, | |
1342 without the directory portion, will be substituted." | |
1343 (when (and | |
1344 (stringp compile-command) | |
1345 (string-match "\\b__FILE__\\b" compile-command)) | |
1346 (make-local-variable 'compile-command) | |
1347 (setq compile-command | |
1348 (verilog-string-replace-matches | |
1349 "\\b__FILE__\\b" (file-name-nondirectory (buffer-file-name)) | |
1350 t t compile-command)))) | |
1351 | |
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1352 ;; Following code only gets called from compilation-mode-hook. |
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1353 (defvar compilation-error-regexp-alist) |
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1354 |
79545 | 1355 (defun verilog-error-regexp-add () |
1356 "Add the messages to the `compilation-error-regexp-alist'. | |
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1357 Called by `compilation-mode-hook'. This allows \\[next-error] to |
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1358 find the errors." |
79545 | 1359 (if (not verilog-error-regexp-add-didit) |
1360 (progn | |
1361 (setq verilog-error-regexp-add-didit t) | |
1362 (setq-default compilation-error-regexp-alist | |
1363 (append verilog-error-regexp | |
1364 (default-value 'compilation-error-regexp-alist))) | |
1365 ;; Could be buffer local at this point; maybe also in let; change all three | |
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1366 (setq compilation-error-regexp-alist |
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1367 (default-value 'compilation-error-regexp-alist)) |
79545 | 1368 (set (make-local-variable 'compilation-error-regexp-alist) |
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1369 (default-value 'compilation-error-regexp-alist))))) |
79545 | 1370 |
1371 (add-hook 'compilation-mode-hook 'verilog-error-regexp-add) | |
1372 | |
1373 (defconst verilog-directive-re | |
1374 ;; "`case" "`default" "`define" "`define" "`else" "`endfor" "`endif" | |
1375 ;; "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef" | |
1376 ;; "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale" | |
1377 ;; "`time_scale" "`undef" "`while" | |
1378 "\\<`\\(case\\|def\\(ault\\|ine\\(\\)?\\)\\|e\\(lse\\|nd\\(for\\|if\\|protect\\|switch\\|while\\)\\)\\|for\\(mat\\)?\\|i\\(f\\(def\\|ndef\\)?\\|nclude\\)\\|let\\|protect\\|switch\\|time\\(_scale\\|scale\\)\\|undef\\|while\\)\\>") | |
1379 | |
1380 (defconst verilog-directive-begin | |
1381 "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>") | |
1382 | |
1383 (defconst verilog-directive-middle | |
1384 "\\<`\\(else\\|default\\|case\\)\\>") | |
1385 | |
1386 (defconst verilog-directive-end | |
1387 "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>") | |
1388 | |
1389 (defconst verilog-directive-re-1 | |
1390 (concat "[ \t]*" verilog-directive-re)) | |
1391 | |
1392 ;; | |
1393 ;; Regular expressions used to calculate indent, etc. | |
1394 ;; | |
1395 (defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>") | |
1396 (defconst verilog-case-re "\\(\\<case[xz]?\\>\\|\\<randcase\\>\\)") | |
1397 ;; Want to match | |
1398 ;; aa : | |
1399 ;; aa,bb : | |
1400 ;; a[34:32] : | |
1401 ;; a, | |
1402 ;; b : | |
1403 | |
1404 (defconst verilog-no-indent-begin-re | |
1405 "\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>") | |
1406 | |
1407 (defconst verilog-ends-re | |
1408 ;; Parenthesis indicate type of keyword found | |
1409 (concat | |
1410 "\\(\\<else\\>\\)\\|" ; 1 | |
1411 "\\(\\<if\\>\\)\\|" ; 2 | |
1412 "\\(\\<end\\>\\)\\|" ; 3 | |
1413 "\\(\\<endcase\\>\\)\\|" ; 4 | |
1414 "\\(\\<endfunction\\>\\)\\|" ; 5 | |
1415 "\\(\\<endtask\\>\\)\\|" ; 6 | |
1416 "\\(\\<endspecify\\>\\)\\|" ; 7 | |
1417 "\\(\\<endtable\\>\\)\\|" ; 8 | |
1418 "\\(\\<endgenerate\\>\\)\\|" ; 9 | |
1419 "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10 | |
1420 "\\(\\<endclass\\>\\)\\|" ; 11 | |
1421 "\\(\\<endgroup\\>\\)" ; 12 | |
1422 )) | |
1423 | |
1424 (defconst verilog-auto-end-comment-lines-re | |
1425 ;; Matches to names in this list cause auto-end-commentation | |
1426 (concat "\\(" | |
1427 verilog-directive-re "\\)\\|\\(" | |
1428 (eval-when-compile | |
1429 (verilog-regexp-words | |
1430 `( "begin" | |
1431 "else" | |
1432 "end" | |
1433 "endcase" | |
1434 "endclass" | |
1435 "endclocking" | |
1436 "endgroup" | |
1437 "endfunction" | |
1438 "endmodule" | |
1439 "endprogram" | |
1440 "endprimitive" | |
1441 "endinterface" | |
1442 "endpackage" | |
1443 "endsequence" | |
1444 "endspecify" | |
1445 "endtable" | |
1446 "endtask" | |
1447 "join" | |
1448 "join_any" | |
1449 "join_none" | |
1450 "module" | |
1451 "macromodule" | |
1452 "primitive" | |
1453 "interface" | |
1454 "package"))) | |
1455 "\\)")) | |
1456 | |
1457 ;;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and | |
1458 ;;; verilog-end-block-ordered-re matches exactly the same strings. | |
1459 (defconst verilog-end-block-ordered-re | |
1460 ;; Parenthesis indicate type of keyword found | |
1461 (concat "\\(\\<endcase\\>\\)\\|" ; 1 | |
1462 "\\(\\<end\\>\\)\\|" ; 2 | |
1463 "\\(\\<end" ; 3, but not used | |
1464 "\\(" ; 4, but not used | |
1465 "\\(function\\)\\|" ; 5 | |
1466 "\\(task\\)\\|" ; 6 | |
1467 "\\(module\\)\\|" ; 7 | |
1468 "\\(primitive\\)\\|" ; 8 | |
1469 "\\(interface\\)\\|" ; 9 | |
1470 "\\(package\\)\\|" ; 10 | |
1471 "\\(class\\)\\|" ; 11 | |
1472 "\\(group\\)\\|" ; 12 | |
1473 "\\(program\\)\\|" ; 13 | |
1474 "\\(sequence\\)\\|" ; 14 | |
1475 "\\(clocking\\)\\|" ; 15 | |
1476 "\\)\\>\\)")) | |
1477 (defconst verilog-end-block-re | |
1478 (eval-when-compile | |
1479 (verilog-regexp-words | |
1480 | |
1481 `("end" ;; closes begin | |
1482 "endcase" ;; closes any of case, casex casez or randcase | |
1483 "join" "join_any" "join_none" ;; closes fork | |
1484 "endclass" | |
1485 "endtable" | |
1486 "endspecify" | |
1487 "endfunction" | |
1488 "endgenerate" | |
1489 "endtask" | |
1490 "endgroup" | |
1491 "endproperty" | |
1492 "endinterface" | |
1493 "endpackage" | |
1494 "endprogram" | |
1495 "endsequence" | |
1496 "endclocking" | |
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1497 )))) |
79545 | 1498 |
1499 | |
1500 (defconst verilog-endcomment-reason-re | |
1501 ;; Parenthesis indicate type of keyword found | |
1502 (concat | |
1503 "\\(\\<fork\\>\\)\\|" | |
1504 "\\(\\<begin\\>\\)\\|" | |
1505 "\\(\\<if\\>\\)\\|" | |
1506 "\\(\\<clocking\\>\\)\\|" | |
1507 "\\(\\<else\\>\\)\\|" | |
1508 "\\(\\<end\\>.*\\<else\\>\\)\\|" | |
1509 "\\(\\<task\\>\\)\\|" | |
1510 "\\(\\<function\\>\\)\\|" | |
1511 "\\(\\<initial\\>\\)\\|" | |
1512 "\\(\\<interface\\>\\)\\|" | |
1513 "\\(\\<package\\>\\)\\|" | |
1514 "\\(\\<final\\>\\)\\|" | |
1515 "\\(\\<always\\>\\(\[ \t\]*@\\)?\\)\\|" | |
1516 "\\(\\<always_comb\\>\\(\[ \t\]*@\\)?\\)\\|" | |
1517 "\\(\\<always_ff\\>\\(\[ \t\]*@\\)?\\)\\|" | |
1518 "\\(\\<always_latch\\>\\(\[ \t\]*@\\)?\\)\\|" | |
1519 "\\(@\\)\\|" | |
1520 "\\(\\<while\\>\\)\\|" | |
1521 "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|" | |
1522 "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|" | |
1523 "#")) | |
1524 | |
1525 (defconst verilog-named-block-re "begin[ \t]*:") | |
1526 | |
1527 ;; These words begin a block which can occur inside a module which should be indented, | |
1528 ;; and closed with the respective word from the end-block list | |
1529 | |
1530 (defconst verilog-beg-block-re | |
1531 (eval-when-compile | |
1532 (verilog-regexp-words | |
1533 `("begin" | |
1534 "case" "casex" "casez" "randcase" | |
1535 "clocking" | |
1536 "generate" | |
1537 "fork" | |
1538 "function" | |
1539 "property" | |
1540 "specify" | |
1541 "table" | |
1542 "task" | |
1543 )))) | |
1544 ;; These are the same words, in a specific order in the regular | |
1545 ;; expression so that matching will work nicely for | |
1546 ;; verilog-forward-sexp and verilog-calc-indent | |
1547 | |
1548 (defconst verilog-beg-block-re-ordered | |
1549 ( concat "\\<" | |
1550 "\\(begin\\)" ;1 | |
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1551 "\\|\\(randcase\\|\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)" ; 2,3 |
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1552 "\\|\\(\\(disable\\s-+\\)?fork\\)" ;4 |
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1553 "\\|\\(class\\)" ;5 |
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1554 "\\|\\(table\\)" ;6 |
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1555 "\\|\\(specify\\)" ;7 |
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1556 "\\|\\(function\\)" ;8 |
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1557 "\\|\\(task\\)" ;9 |
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1558 "\\|\\(generate\\)" ;10 |
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1559 "\\|\\(covergroup\\)" ;11 |
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1560 "\\|\\(property\\)" ;12 |
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1561 "\\|\\(\\(rand\\)?sequence\\)" ;13 |
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1562 "\\|\\(clocking\\)" ;14 |
79545 | 1563 "\\>")) |
1564 | |
1565 (defconst verilog-end-block-ordered-rry | |
1566 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" | |
1567 "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)" | |
1568 "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" | |
1569 "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" | |
1570 "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" | |
1571 "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" | |
1572 "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" | |
1573 "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" | |
1574 "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" | |
1575 "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" | |
1576 "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" | |
1577 "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" | |
1578 "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" | |
1579 ] ) | |
1580 | |
1581 (defconst verilog-nameable-item-re | |
1582 (eval-when-compile | |
1583 (verilog-regexp-words | |
1584 `("begin" | |
1585 "fork" | |
1586 "join" "join_any" "join_none" | |
1587 "end" | |
1588 "endcase" | |
1589 "endconfig" | |
1590 "endclass" | |
1591 "endclocking" | |
1592 "endfunction" | |
1593 "endgenerate" | |
1594 "endmodule" | |
1595 "endprimative" | |
1596 "endinterface" | |
1597 "endpackage" | |
1598 "endspecify" | |
1599 "endtable" | |
1600 "endtask" ) | |
1601 ))) | |
1602 | |
1603 (defconst verilog-declaration-opener | |
1604 (eval-when-compile | |
1605 (verilog-regexp-words | |
1606 `("module" "begin" "task" "function")))) | |
1607 | |
1608 (defconst verilog-declaration-prefix-re | |
1609 (eval-when-compile | |
1610 (verilog-regexp-words | |
1611 `( | |
1612 ;; port direction | |
79546 | 1613 "inout" "input" "output" "ref" |
79545 | 1614 ;; changeableness |
1615 "const" "static" "protected" "local" | |
1616 ;; parameters | |
79546 | 1617 "localparam" "parameter" "var" |
79545 | 1618 ;; type creation |
1619 "typedef" | |
1620 )))) | |
1621 (defconst verilog-declaration-core-re | |
1622 (eval-when-compile | |
1623 (verilog-regexp-words | |
1624 `( | |
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1625 ;; port direction (by themselves) |
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1626 "inout" "input" "output" |
79545 | 1627 ;; integer_atom_type |
1628 "byte" "shortint" "int" "longint" "integer" "time" | |
1629 ;; integer_vector_type | |
1630 "bit" "logic" "reg" | |
1631 ;; non_integer_type | |
1632 "shortreal" "real" "realtime" | |
1633 ;; net_type | |
1634 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor" | |
1635 ;; misc | |
1636 "string" "event" "chandle" "virtual" "enum" "genvar" | |
1637 "struct" "union" | |
1638 ;; builtin classes | |
79546 | 1639 "mailbox" "semaphore" |
79545 | 1640 )))) |
79546 | 1641 (defconst verilog-declaration-re |
79545 | 1642 (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re)) |
1643 (defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+") | |
1644 (defconst verilog-optional-signed-re "\\s-*\\(signed\\)?") | |
1645 (defconst verilog-optional-signed-range-re | |
1646 (concat | |
1647 "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?")) | |
1648 (defconst verilog-macroexp-re "`\\sw+") | |
1649 | |
1650 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)") | |
1651 (defconst verilog-declaration-re-2-no-macro | |
1652 (concat "\\s-*" verilog-declaration-re | |
1653 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)" | |
1654 "\\)?")) | |
1655 (defconst verilog-declaration-re-2-macro | |
1656 (concat "\\s-*" verilog-declaration-re | |
1657 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)" | |
1658 "\\|\\(" verilog-macroexp-re "\\)" | |
1659 "\\)?")) | |
1660 (defconst verilog-declaration-re-1-macro | |
1661 (concat "^" verilog-declaration-re-2-macro)) | |
1662 | |
1663 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro)) | |
1664 | |
1665 (defconst verilog-defun-re | |
1666 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config")))) | |
1667 (defconst verilog-end-defun-re | |
1668 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig")))) | |
1669 (defconst verilog-zero-indent-re | |
1670 (concat verilog-defun-re "\\|" verilog-end-defun-re)) | |
1671 | |
1672 (defconst verilog-behavioral-block-beg-re | |
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1673 (eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff" |
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1674 "function" "task")))) |
79545 | 1675 |
1676 (defconst verilog-indent-re | |
1677 (eval-when-compile | |
1678 (verilog-regexp-words | |
1679 `( | |
1680 "{" | |
1681 "always" "always_latch" "always_ff" "always_comb" | |
1682 "begin" "end" | |
1683 ; "unique" "priority" | |
1684 "case" "casex" "casez" "randcase" "endcase" | |
1685 "class" "endclass" | |
1686 "clocking" "endclocking" | |
1687 "config" "endconfig" | |
1688 "covergroup" "endgroup" | |
1689 "fork" "join" "join_any" "join_none" | |
1690 "function" "endfunction" | |
1691 "final" | |
1692 "generate" "endgenerate" | |
1693 "initial" | |
1694 "interface" "endinterface" | |
1695 "module" "macromodule" "endmodule" | |
1696 "package" "endpackage" | |
1697 "primitive" "endprimative" | |
1698 "program" "endprogram" | |
1699 "property" "endproperty" | |
1700 "sequence" "randsequence" "endsequence" | |
1701 "specify" "endspecify" | |
1702 "table" "endtable" | |
1703 "task" "endtask" | |
1704 "`case" | |
1705 "`default" | |
1706 "`define" "`undef" | |
1707 "`if" "`ifdef" "`ifndef" "`else" "`endif" | |
1708 "`while" "`endwhile" | |
1709 "`for" "`endfor" | |
1710 "`format" | |
1711 "`include" | |
1712 "`let" | |
1713 "`protect" "`endprotect" | |
1714 "`switch" "`endswitch" | |
1715 "`timescale" | |
1716 "`time_scale" | |
1717 )))) | |
1718 | |
1719 (defconst verilog-defun-level-re | |
1720 (eval-when-compile | |
1721 (verilog-regexp-words | |
1722 `( | |
1723 "module" "macromodule" "primitive" "class" "program" "initial" "final" "always" "always_comb" | |
1724 "always_ff" "always_latch" "endtask" "endfunction" "interface" "package" | |
1725 "config")))) | |
1726 | |
1727 (defconst verilog-defun-level-not-generate-re | |
1728 (eval-when-compile | |
1729 (verilog-regexp-words | |
1730 `( | |
1731 "module" "macromodule" "primitive" "class" "program" "interface" "package" "config")))) | |
1732 | |
1733 (defconst verilog-cpp-level-re | |
1734 (eval-when-compile | |
1735 (verilog-regexp-words | |
1736 `( | |
1737 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass" | |
1738 )))) | |
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1739 (defconst verilog-disable-fork-re "disable\\s-+fork") |
79545 | 1740 (defconst verilog-extended-case-re "\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?") |
1741 (defconst verilog-extended-complete-re | |
1742 (concat "\\(\\<extern\\s-+\\|\\<virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)" | |
1743 "\\|\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)" | |
1744 "\\|" verilog-extended-case-re )) | |
1745 (defconst verilog-basic-complete-re | |
1746 (eval-when-compile | |
1747 (verilog-regexp-words | |
1748 `( | |
1749 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint" | |
1750 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while" | |
1751 "if" "for" "forever" "foreach" "else" "parameter" "do" | |
1752 )))) | |
1753 (defconst verilog-complete-reg | |
1754 (concat | |
1755 verilog-extended-complete-re | |
1756 "\\|" | |
1757 verilog-basic-complete-re)) | |
1758 | |
1759 (defconst verilog-end-statement-re | |
1760 (concat "\\(" verilog-beg-block-re "\\)\\|\\(" | |
1761 verilog-end-block-re "\\)")) | |
1762 | |
1763 (defconst verilog-endcase-re | |
1764 (concat verilog-case-re "\\|" | |
1765 "\\(endcase\\)\\|" | |
1766 verilog-defun-re | |
1767 )) | |
1768 | |
1769 (defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----" | |
1770 "String used to mark beginning of excluded text.") | |
1771 (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */" | |
1772 "String used to mark end of excluded text.") | |
1773 (defconst verilog-preprocessor-re | |
1774 (eval-when-compile | |
1775 (verilog-regexp-words | |
1776 `( | |
1777 "`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else" | |
1778 )))) | |
1779 | |
1780 (defconst verilog-keywords | |
1781 '( "`case" "`default" "`define" "`else" "`endfor" "`endif" | |
1782 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef" | |
1783 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale" | |
1784 "`time_scale" "`undef" "`while" | |
1785 | |
1786 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and" | |
1787 "assert" "assign" "assume" "automatic" "before" "begin" "bind" | |
1788 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte" | |
1789 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos" | |
1790 "config" "const" "constraint" "context" "continue" "cover" | |
1791 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam" | |
1792 "design" "disable" "dist" "do" "edge" "else" "end" "endcase" | |
1793 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate" | |
1794 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive" | |
1795 "endprogram" "endproperty" "endspecify" "endsequence" "endtable" | |
1796 "endtask" "enum" "event" "expect" "export" "extends" "extern" | |
1797 "final" "first_match" "for" "force" "foreach" "forever" "fork" | |
1798 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if" | |
1799 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir" | |
1800 "include" "initial" "inout" "input" "inside" "instance" "int" | |
1801 "integer" "interface" "intersect" "join" "join_any" "join_none" | |
1802 "large" "liblist" "library" "local" "localparam" "logic" | |
1803 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module" | |
1804 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not" | |
1805 "notif0" "notif1" "null" "or" "output" "package" "packed" | |
1806 "parameter" "pmos" "posedge" "primitive" "priority" "program" | |
1807 "property" "protected" "pull0" "pull1" "pulldown" "pullup" | |
1808 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc" | |
1809 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg" | |
1810 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0" | |
1811 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal" | |
1812 "showcancelled" "signed" "small" "solve" "specify" "specparam" | |
1813 "static" "string" "strong0" "strong1" "struct" "super" "supply0" | |
1814 "supply1" "table" "tagged" "task" "this" "throughout" "time" | |
1815 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri" | |
1816 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union" | |
1817 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void" | |
1818 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard" | |
1819 "wire" "with" "within" "wor" "xnor" "xor" | |
1820 ) | |
1821 "List of Verilog keywords.") | |
1822 | |
1823 (defconst verilog-comment-start-regexp "//\\|/\\*" | |
1824 "Dual comment value for `comment-start-regexp'.") | |
1825 | |
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1826 (defvar verilog-mode-syntax-table |
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1827 (let ((table (make-syntax-table))) |
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1828 ;; Populate the syntax TABLE. |
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1829 (modify-syntax-entry ?\\ "\\" table) |
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1830 (modify-syntax-entry ?+ "." table) |
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1831 (modify-syntax-entry ?- "." table) |
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1832 (modify-syntax-entry ?= "." table) |
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1833 (modify-syntax-entry ?% "." table) |
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1834 (modify-syntax-entry ?< "." table) |
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1835 (modify-syntax-entry ?> "." table) |
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1836 (modify-syntax-entry ?& "." table) |
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1837 (modify-syntax-entry ?| "." table) |
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1838 (modify-syntax-entry ?` "w" table) |
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1839 (modify-syntax-entry ?_ "w" table) |
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1840 (modify-syntax-entry ?\' "." table) |
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1841 |
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1842 ;; Set up TABLE to handle block and line style comments. |
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1843 (if (featurep 'xemacs) |
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1844 (progn |
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1845 ;; XEmacs (formerly Lucid) has the best implementation |
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1846 (modify-syntax-entry ?/ ". 1456" table) |
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1847 (modify-syntax-entry ?* ". 23" table) |
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1848 (modify-syntax-entry ?\n "> b" table)) |
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1849 ;; Emacs 19 does things differently, but we can work with it |
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1850 (modify-syntax-entry ?/ ". 124b" table) |
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1851 (modify-syntax-entry ?* ". 23" table) |
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1852 (modify-syntax-entry ?\n "> b" table)) |
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1853 table) |
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1854 "Syntax table used in Verilog mode buffers.") |
79545 | 1855 |
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1856 (defvar verilog-font-lock-keywords nil |
79545 | 1857 "Default highlighting for Verilog mode.") |
1858 | |
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1859 (defvar verilog-font-lock-keywords-1 nil |
79545 | 1860 "Subdued level highlighting for Verilog mode.") |
1861 | |
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1862 (defvar verilog-font-lock-keywords-2 nil |
79545 | 1863 "Medium level highlighting for Verilog mode. |
1864 See also `verilog-font-lock-extra-types'.") | |
1865 | |
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1866 (defvar verilog-font-lock-keywords-3 nil |
79545 | 1867 "Gaudy level highlighting for Verilog mode. |
1868 See also `verilog-font-lock-extra-types'.") | |
1869 (defvar verilog-font-lock-translate-off-face | |
1870 'verilog-font-lock-translate-off-face | |
1871 "Font to use for translated off regions.") | |
1872 (defface verilog-font-lock-translate-off-face | |
1873 '((((class color) | |
1874 (background light)) | |
1875 (:background "gray90" :italic t )) | |
1876 (((class color) | |
1877 (background dark)) | |
1878 (:background "gray10" :italic t )) | |
1879 (((class grayscale) (background light)) | |
1880 (:foreground "DimGray" :italic t)) | |
1881 (((class grayscale) (background dark)) | |
1882 (:foreground "LightGray" :italic t)) | |
1883 (t (:italis t))) | |
1884 "Font lock mode face used to background highlight translate-off regions." | |
1885 :group 'font-lock-highlighting-faces) | |
1886 | |
1887 (defvar verilog-font-lock-p1800-face | |
1888 'verilog-font-lock-p1800-face | |
1889 "Font to use for p1800 keywords.") | |
1890 (defface verilog-font-lock-p1800-face | |
1891 '((((class color) | |
1892 (background light)) | |
1893 (:foreground "DarkOrange3" :bold t )) | |
1894 (((class color) | |
1895 (background dark)) | |
1896 (:foreground "orange1" :bold t )) | |
1897 (t (:italic t))) | |
1898 "Font lock mode face used to highlight P1800 keywords." | |
1899 :group 'font-lock-highlighting-faces) | |
1900 | |
1901 (defvar verilog-font-lock-ams-face | |
1902 'verilog-font-lock-ams-face | |
1903 "Font to use for Analog/Mixed Signal keywords.") | |
1904 (defface verilog-font-lock-ams-face | |
1905 '((((class color) | |
1906 (background light)) | |
1907 (:foreground "Purple" :bold t )) | |
1908 (((class color) | |
1909 (background dark)) | |
1910 (:foreground "orange1" :bold t )) | |
1911 (t (:italic t))) | |
1912 "Font lock mode face used to highlight AMS keywords." | |
1913 :group 'font-lock-highlighting-faces) | |
1914 | |
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1915 (defvar verilog-font-grouping-keywords-face |
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1916 'verilog-font-lock-grouping-keywords-face |
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1917 "Font to use for Verilog Grouping Keywords (such as begin..end).") |
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1918 (defface verilog-font-lock-grouping-keywords-face |
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1919 '((((class color) |
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1920 (background light)) |
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1921 (:foreground "red4" :bold t )) |
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1922 (((class color) |
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1923 (background dark)) |
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1924 (:foreground "red4" :bold t )) |
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1925 (t (:italic t))) |
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1926 "Font lock mode face used to highlight verilog grouping keywords." |
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1927 :group 'font-lock-highlighting-faces) |
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1928 |
79545 | 1929 (let* ((verilog-type-font-keywords |
1930 (eval-when-compile | |
1931 (verilog-regexp-opt | |
1932 '( | |
1933 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam" | |
1934 "event" "genvar" "inout" "input" "integer" "localparam" | |
1935 "logic" "mailbox" "nand" "nmos" "not" "notif0" "notif1" "or" | |
1936 "output" "parameter" "pmos" "pull0" "pull1" "pullup" | |
1937 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" | |
1938 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply" | |
1939 "supply0" "supply1" "time" "tran" "tranif0" "tranif1" | |
1940 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef" | |
1941 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor" | |
1942 ) nil ))) | |
1943 | |
1944 (verilog-pragma-keywords | |
1945 (eval-when-compile | |
1946 (verilog-regexp-opt | |
1947 '("surefire" "synopsys" "rtl_synthesis" "verilint" ) nil | |
1948 ))) | |
1949 | |
1950 (verilog-p1800-keywords | |
1951 (eval-when-compile | |
1952 (verilog-regexp-opt | |
1953 '("alias" "assert" "assume" "automatic" "before" "bind" | |
1954 "bins" "binsof" "break" "byte" "cell" "chandle" "class" | |
1955 "clocking" "config" "const" "constraint" "context" "continue" | |
1956 "cover" "covergroup" "coverpoint" "cross" "deassign" "design" | |
1957 "dist" "do" "edge" "endclass" "endclocking" "endconfig" | |
1958 "endgroup" "endprogram" "endproperty" "endsequence" "enum" | |
1959 "expect" "export" "extends" "extern" "first_match" "foreach" | |
1960 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins" | |
1961 "illegal_bins" "import" "incdir" "include" "inside" "instance" | |
1962 "int" "intersect" "large" "liblist" "library" "local" "longint" | |
1963 "matches" "medium" "modport" "new" "noshowcancelled" "null" | |
1964 "packed" "program" "property" "protected" "pull0" "pull1" | |
1965 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc" | |
1966 "randcase" "randsequence" "ref" "release" "return" "scalared" | |
1967 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve" | |
1968 "specparam" "static" "string" "strong0" "strong1" "struct" | |
1969 "super" "tagged" "this" "throughout" "timeprecision" "timeunit" | |
1970 "type" "union" "unsigned" "use" "var" "virtual" "void" | |
1971 "wait_order" "weak0" "weak1" "wildcard" "with" "within" | |
1972 ) nil ))) | |
1973 | |
1974 (verilog-ams-keywords | |
1975 (eval-when-compile | |
1976 (verilog-regexp-opt | |
1977 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim" | |
1978 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh" | |
1979 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt" | |
1980 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules" | |
1981 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise" | |
1982 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf" | |
1983 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp" | |
1984 "last_crossing" "limexp" "ln" "log" "max" "min" "nature" | |
1985 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin" | |
1986 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise" | |
1987 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil ))) | |
1988 | |
1989 (verilog-font-keywords | |
1990 (eval-when-compile | |
1991 (verilog-regexp-opt | |
1992 '( | |
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1993 "assign" "case" "casex" "casez" "randcase" "deassign" |
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1994 "default" "disable" "else" "endcase" "endfunction" |
79545 | 1995 "endgenerate" "endinterface" "endmodule" "endprimitive" |
1996 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break" | |
1997 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial" | |
1998 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge" | |
1999 "package" "endpackage" "always" "always_comb" "always_ff" | |
2000 "always_latch" "posedge" "primitive" "priority" "release" | |
2001 "repeat" "specify" "table" "task" "unique" "wait" "while" | |
2002 "class" "program" "endclass" "endprogram" | |
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2003 ) nil ))) |
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2004 |
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2005 (verilog-font-grouping-keywords |
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2006 (eval-when-compile |
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2007 (verilog-regexp-opt |
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2008 '( "begin" "end" ) nil )))) |
79545 | 2009 |
2010 (setq verilog-font-lock-keywords | |
2011 (list | |
2012 ;; Fontify all builtin keywords | |
2013 (concat "\\<\\(" verilog-font-keywords "\\|" | |
2014 ;; And user/system tasks and functions | |
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2015 "\\$[a-zA-Z][a-zA-Z0-9_\\$]*" |
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2016 "\\)\\>") |
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2017 ;; Fontify all types |
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2018 (if verilog-highlight-grouping-keywords |
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2019 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>") |
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2020 'verilog-font-lock-ams-face) |
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2021 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>") |
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2022 'font-lock-type-face)) |
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2023 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>") |
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2024 'font-lock-type-face) |
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2025 ;; Fontify IEEE-P1800 keywords appropriately |
79545 | 2026 (if verilog-highlight-p1800-keywords |
2027 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>") | |
2028 'verilog-font-lock-p1800-face) | |
2029 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>") | |
2030 'font-lock-type-face)) | |
2031 ;; Fontify Verilog-AMS keywords | |
2032 (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>") | |
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2033 'verilog-font-lock-ams-face))) |
79545 | 2034 |
2035 (setq verilog-font-lock-keywords-1 | |
2036 (append verilog-font-lock-keywords | |
2037 (list | |
2038 ;; Fontify module definitions | |
2039 (list | |
2040 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)" | |
2041 '(1 font-lock-keyword-face) | |
2042 '(3 font-lock-function-name-face 'prepend)) | |
2043 ;; Fontify function definitions | |
2044 (list | |
2045 (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" ) | |
2046 '(1 font-lock-keyword-face) | |
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2047 '(3 font-lock-reference-face prepend)) |
79545 | 2048 '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)" |
2049 (1 font-lock-keyword-face) | |
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2050 (2 font-lock-reference-face append)) |
79545 | 2051 '("\\<function\\>\\s-+\\(\\sw+\\)" |
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2052 1 'font-lock-reference-face append)))) |
79545 | 2053 |
2054 (setq verilog-font-lock-keywords-2 | |
2055 (append verilog-font-lock-keywords-1 | |
2056 (list | |
2057 ;; Fontify pragmas | |
2058 (concat "\\(//\\s-*" verilog-pragma-keywords "\\s-.*\\)") | |
2059 ;; Fontify escaped names | |
2060 '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face) | |
2061 ;; Fontify macro definitions/ uses | |
2062 '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face) | |
2063 'font-lock-preprocessor-face | |
2064 'font-lock-type-face)) | |
2065 ;; Fontify delays/numbers | |
2066 '("\\(@\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)" | |
2067 0 font-lock-type-face append) | |
2068 ;; Fontify instantiation names | |
2069 '("\\([A-Za-z][A-Za-z0-9_]+\\)\\s-*(" 1 font-lock-function-name-face) | |
2070 ))) | |
2071 | |
2072 (setq verilog-font-lock-keywords-3 | |
2073 (append verilog-font-lock-keywords-2 | |
2074 (when verilog-highlight-translate-off | |
2075 (list | |
2076 ;; Fontify things in translate off regions | |
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2077 '(verilog-match-translate-off |
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2078 (0 'verilog-font-lock-translate-off-face prepend)) |
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2079 ))))) |
79545 | 2080 |
2081 | |
2082 (defun verilog-inside-comment-p () | |
2083 "Check if point inside a nested comment." | |
2084 (save-excursion | |
2085 (let ((st-point (point)) hitbeg) | |
2086 (or (search-backward "//" (verilog-get-beg-of-line) t) | |
2087 (if (progn | |
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2088 ;; This is for tricky case //*, we keep searching if /* |
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2089 ;; is proceeded by // on same line. |
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2090 (while |
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2091 (and (setq hitbeg (search-backward "/*" nil t)) |
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2092 (progn |
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2093 (forward-char 1) |
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2094 (search-backward "//" (verilog-get-beg-of-line) t)))) |
79545 | 2095 hitbeg) |
2096 (not (search-forward "*/" st-point t))))))) | |
2097 | |
2098 (defun verilog-declaration-end () | |
2099 (search-forward ";")) | |
2100 | |
2101 (defun verilog-point-text (&optional pointnum) | |
2102 "Return text describing where POINTNUM or current point is (for errors). | |
2103 Use filename, if current buffer being edited shorten to just buffer name." | |
2104 (concat (or (and (equal (window-buffer (selected-window)) (current-buffer)) | |
2105 (buffer-name)) | |
2106 buffer-file-name | |
2107 (buffer-name)) | |
2108 ":" (int-to-string (count-lines (point-min) (or pointnum (point)))))) | |
2109 | |
2110 (defun electric-verilog-backward-sexp () | |
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2111 "Move backward over one balanced expression." |
79545 | 2112 (interactive) |
2113 ;; before that see if we are in a comment | |
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2114 (verilog-backward-sexp)) |
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2115 |
79545 | 2116 (defun electric-verilog-forward-sexp () |
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2117 "Move forward over one balanced expression." |
79545 | 2118 (interactive) |
2119 ;; before that see if we are in a comment | |
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2120 (verilog-forward-sexp)) |
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2121 |
79545 | 2122 ;;;used by hs-minor-mode |
2123 (defun verilog-forward-sexp-function (arg) | |
2124 (if (< arg 0) | |
2125 (verilog-backward-sexp) | |
2126 (verilog-forward-sexp))) | |
2127 | |
2128 | |
2129 (defun verilog-backward-sexp () | |
2130 (let ((reg) | |
2131 (elsec 1) | |
2132 (found nil) | |
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2133 (st (point))) |
79545 | 2134 (if (not (looking-at "\\<")) |
2135 (forward-word -1)) | |
2136 (cond | |
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2137 ((verilog-skip-backward-comment-or-string)) |
79545 | 2138 ((looking-at "\\<else\\>") |
2139 (setq reg (concat | |
2140 verilog-end-block-re | |
2141 "\\|\\(\\<else\\>\\)" | |
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2142 "\\|\\(\\<if\\>\\)")) |
79545 | 2143 (while (and (not found) |
2144 (verilog-re-search-backward reg nil 'move)) | |
2145 (cond | |
2146 ((match-end 1) ; matched verilog-end-block-re | |
2147 ; try to leap back to matching outward block by striding across | |
2148 ; indent level changing tokens then immediately | |
2149 ; previous line governs indentation. | |
2150 (verilog-leap-to-head)) | |
2151 ((match-end 2) ; else, we're in deep | |
2152 (setq elsec (1+ elsec))) | |
2153 ((match-end 3) ; found it | |
2154 (setq elsec (1- elsec)) | |
2155 (if (= 0 elsec) | |
2156 ;; Now previous line describes syntax | |
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2157 (setq found 't)))))) |
79545 | 2158 ((looking-at verilog-end-block-re) |
2159 (verilog-leap-to-head)) | |
2160 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)") | |
2161 (cond | |
2162 ((match-end 1) | |
2163 (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move)) | |
2164 ((match-end 2) | |
2165 (verilog-re-search-backward "\\<primitive\\>" nil 'move)) | |
2166 ((match-end 3) | |
2167 (verilog-re-search-backward "\\<class\\>" nil 'move)) | |
2168 ((match-end 4) | |
2169 (verilog-re-search-backward "\\<program\\>" nil 'move)) | |
2170 ((match-end 5) | |
2171 (verilog-re-search-backward "\\<interface\\>" nil 'move)) | |
2172 ((match-end 6) | |
2173 (verilog-re-search-backward "\\<package\\>" nil 'move)) | |
2174 (t | |
2175 (goto-char st) | |
2176 (backward-sexp 1)))) | |
2177 (t | |
2178 (goto-char st) | |
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2179 (backward-sexp))))) |
79545 | 2180 |
2181 (defun verilog-forward-sexp () | |
2182 (let ((reg) | |
2183 (md 2) | |
2184 (st (point))) | |
2185 (if (not (looking-at "\\<")) | |
2186 (forward-word -1)) | |
2187 (cond | |
2188 ((verilog-skip-forward-comment-or-string) | |
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2189 (verilog-forward-syntactic-ws)) |
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2190 ((looking-at verilog-beg-block-re-ordered) ;; begin|(case)|xx|(fork)|class|table|specify|function|task|generate|covergroup|property|sequence|clocking |
79545 | 2191 (cond |
2192 ((match-end 1) ; end | |
2193 ;; Search forward for matching begin | |
2194 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" )) | |
2195 ((match-end 2) ; endcase | |
2196 ;; Search forward for matching case | |
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2197 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ) |
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2198 (setq md 3) ;; ender is third item in regexp |
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2199 ) |
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2200 ((match-end 4) ; join |
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2201 ;; might be "disable fork" |
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2202 (if (or |
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2203 (looking-at verilog-disable-fork-re) |
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2204 (and (looking-at "fork") |
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2205 (progn |
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2206 (forward-word -1) |
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2207 (looking-at verilog-disable-fork-re)))) |
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2208 (progn |
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2209 (goto-char (match-end 0)) |
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2210 (forward-word) |
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2211 (setq reg nil)) |
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2212 (progn |
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2213 ;; Search forward for matching fork |
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2214 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))) |
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2215 ((match-end 5) ; endclass |
79545 | 2216 ;; Search forward for matching class |
2217 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" )) | |
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2218 ((match-end 6) ; endtable |
79545 | 2219 ;; Search forward for matching table |
2220 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" )) | |
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|
2221 ((match-end 7) ; endspecify |
79545 | 2222 ;; Search forward for matching specify |
2223 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" )) | |
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|
2224 ((match-end 8) ; endfunction |
79545 | 2225 ;; Search forward for matching function |
2226 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" )) | |
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2227 ((match-end 9) ; endtask |
79545 | 2228 ;; Search forward for matching task |
2229 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" )) | |
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2230 ((match-end 10) ; endgenerate |
79545 | 2231 ;; Search forward for matching generate |
2232 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" )) | |
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|
2233 ((match-end 11) ; endgroup |
79545 | 2234 ;; Search forward for matching covergroup |
2235 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )) | |
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2236 ((match-end 12) ; endproperty |
79545 | 2237 ;; Search forward for matching property |
2238 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" )) | |
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2239 ((match-end 13) ; endsequence |
79545 | 2240 ;; Search forward for matching sequence |
2241 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ) | |
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2242 (setq md 3)) ; 3 to get to endsequence in the reg above |
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2243 ((match-end 14) ; endclocking |
79545 | 2244 ;; Search forward for matching clocking |
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2245 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" ))) |
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2246 (if (and reg |
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2247 (forward-word 1)) |
79545 | 2248 (catch 'skip |
2249 (let ((nest 1)) | |
2250 (while (verilog-re-search-forward reg nil 'move) | |
2251 (cond | |
2252 ((match-end md) ; the closer in reg, so we are climbing out | |
2253 (setq nest (1- nest)) | |
2254 (if (= 0 nest) ; we are out! | |
2255 (throw 'skip 1))) | |
2256 ((match-end 1) ; the opener in reg, so we are deeper now | |
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2257 (setq nest (1+ nest))))))))) |
79545 | 2258 ((looking-at (concat |
2259 "\\(\\<\\(macro\\)?module\\>\\)\\|" | |
2260 "\\(\\<primitive\\>\\)\\|" | |
2261 "\\(\\<class\\>\\)\\|" | |
2262 "\\(\\<program\\>\\)\\|" | |
2263 "\\(\\<interface\\>\\)\\|" | |
2264 "\\(\\<package\\>\\)")) | |
2265 (cond | |
2266 ((match-end 1) | |
2267 (verilog-re-search-forward "\\<endmodule\\>" nil 'move)) | |
2268 ((match-end 2) | |
2269 (verilog-re-search-forward "\\<endprimitive\\>" nil 'move)) | |
2270 ((match-end 3) | |
2271 (verilog-re-search-forward "\\<endclass\\>" nil 'move)) | |
2272 ((match-end 4) | |
2273 (verilog-re-search-forward "\\<endprogram\\>" nil 'move)) | |
2274 ((match-end 5) | |
2275 (verilog-re-search-forward "\\<endinterface\\>" nil 'move)) | |
2276 ((match-end 6) | |
2277 (verilog-re-search-forward "\\<endpackage\\>" nil 'move)) | |
2278 (t | |
2279 (goto-char st) | |
2280 (if (= (following-char) ?\) ) | |
2281 (forward-char 1) | |
2282 (forward-sexp 1))))) | |
2283 (t | |
2284 (goto-char st) | |
2285 (if (= (following-char) ?\) ) | |
2286 (forward-char 1) | |
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2287 (forward-sexp 1)))))) |
79545 | 2288 |
2289 (defun verilog-declaration-beg () | |
2290 (verilog-re-search-backward verilog-declaration-re (bobp) t)) | |
2291 | |
2292 (defun verilog-font-lock-init () | |
2293 "Initialize fontification." | |
2294 ;; highlight keywords and standardized types, attributes, enumeration | |
2295 ;; values, and subprograms | |
2296 (setq verilog-font-lock-keywords-3 | |
2297 (append verilog-font-lock-keywords-2 | |
2298 (when verilog-highlight-translate-off | |
2299 (list | |
2300 ;; Fontify things in translate off regions | |
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|
2301 '(verilog-match-translate-off |
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2302 (0 'verilog-font-lock-translate-off-face prepend)))))) |
79545 | 2303 (put 'verilog-mode 'font-lock-defaults |
2304 '((verilog-font-lock-keywords | |
2305 verilog-font-lock-keywords-1 | |
2306 verilog-font-lock-keywords-2 | |
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2307 verilog-font-lock-keywords-3) |
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2308 nil ; nil means highlight strings & comments as well as keywords |
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2309 nil ; nil means keywords must match case |
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2310 nil ; syntax table handled elsewhere |
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2311 ;; Function to move to beginning of reasonable region to highlight |
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2312 verilog-beg-of-defun))) |
79545 | 2313 |
2314 ;; initialize fontification for Verilog Mode | |
2315 (verilog-font-lock-init) | |
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2316 |
79545 | 2317 ;; |
2318 ;; | |
2319 ;; Mode | |
2320 ;; | |
2321 (defvar verilog-which-tool 1) | |
79546 | 2322 ;;;###autoload |
79545 | 2323 (defun verilog-mode () |
2324 "Major mode for editing Verilog code. | |
2325 \\<verilog-mode-map> | |
2326 See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how | |
2327 AUTOs can improve coding efficiency. | |
2328 | |
2329 Use \\[verilog-faq] for a pointer to frequently asked questions. | |
2330 | |
2331 NEWLINE, TAB indents for Verilog code. | |
2332 Delete converts tabs to spaces as it moves back. | |
2333 | |
2334 Supports highlighting. | |
2335 | |
2336 Turning on Verilog mode calls the value of the variable `verilog-mode-hook' | |
2337 with no args, if that value is non-nil. | |
2338 | |
2339 Variables controlling indentation/edit style: | |
2340 | |
2341 variable `verilog-indent-level' (default 3) | |
2342 Indentation of Verilog statements with respect to containing block. | |
2343 `verilog-indent-level-module' (default 3) | |
2344 Absolute indentation of Module level Verilog statements. | |
2345 Set to 0 to get initial and always statements lined up | |
2346 on the left side of your screen. | |
2347 `verilog-indent-level-declaration' (default 3) | |
2348 Indentation of declarations with respect to containing block. | |
2349 Set to 0 to get them list right under containing block. | |
2350 `verilog-indent-level-behavioral' (default 3) | |
2351 Indentation of first begin in a task or function block | |
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2352 Set to 0 to get such code to lined up underneath the task or |
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2353 function keyword. |
79545 | 2354 `verilog-indent-level-directive' (default 1) |
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2355 Indentation of `ifdef/`endif blocks. |
79545 | 2356 `verilog-cexp-indent' (default 1) |
2357 Indentation of Verilog statements broken across lines i.e.: | |
2358 if (a) | |
2359 begin | |
2360 `verilog-case-indent' (default 2) | |
2361 Indentation for case statements. | |
2362 `verilog-auto-newline' (default nil) | |
2363 Non-nil means automatically newline after semicolons and the punctuation | |
2364 mark after an end. | |
2365 `verilog-auto-indent-on-newline' (default t) | |
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2366 Non-nil means automatically indent line after newline. |
79545 | 2367 `verilog-tab-always-indent' (default t) |
2368 Non-nil means TAB in Verilog mode should always reindent the current line, | |
2369 regardless of where in the line point is when the TAB command is used. | |
2370 `verilog-indent-begin-after-if' (default t) | |
2371 Non-nil means to indent begin statements following a preceding | |
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2372 if, else, while, for and repeat statements, if any. Otherwise, |
79545 | 2373 the begin is lined up with the preceding token. If t, you get: |
2374 if (a) | |
2375 begin // amount of indent based on `verilog-cexp-indent' | |
2376 otherwise you get: | |
2377 if (a) | |
2378 begin | |
2379 `verilog-auto-endcomments' (default t) | |
2380 Non-nil means a comment /* ... */ is set after the ends which ends | |
2381 cases, tasks, functions and modules. | |
2382 The type and name of the object will be set between the braces. | |
2383 `verilog-minimum-comment-distance' (default 10) | |
2384 Minimum distance (in lines) between begin and end required before a comment | |
2385 will be inserted. Setting this variable to zero results in every | |
2386 end acquiring a comment; the default avoids too many redundant | |
2387 comments in tight quarters. | |
2388 `verilog-auto-lineup' (default `(all)) | |
2389 List of contexts where auto lineup of code should be done. | |
2390 | |
2391 Variables controlling other actions: | |
2392 | |
2393 `verilog-linter' (default surelint) | |
2394 Unix program to call to run the lint checker. This is the default | |
2395 command for \\[compile-command] and \\[verilog-auto-save-compile]. | |
2396 | |
2397 See \\[customize] for the complete list of variables. | |
2398 | |
2399 AUTO expansion functions are, in part: | |
2400 | |
2401 \\[verilog-auto] Expand AUTO statements. | |
2402 \\[verilog-delete-auto] Remove the AUTOs. | |
2403 \\[verilog-inject-auto] Insert AUTOs for the first time. | |
2404 | |
2405 Some other functions are: | |
2406 | |
2407 \\[verilog-complete-word] Complete word with appropriate possibilities. | |
2408 \\[verilog-mark-defun] Mark function. | |
2409 \\[verilog-beg-of-defun] Move to beginning of current function. | |
2410 \\[verilog-end-of-defun] Move to end of current function. | |
2411 \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements. | |
2412 | |
2413 \\[verilog-comment-region] Put marked area in a comment. | |
2414 \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region]. | |
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2415 \\[verilog-insert-block] Insert begin ... end. |
79545 | 2416 \\[verilog-star-comment] Insert /* ... */. |
2417 | |
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2418 \\[verilog-sk-always] Insert an always @(AS) begin .. end block. |
79545 | 2419 \\[verilog-sk-begin] Insert a begin .. end block. |
2420 \\[verilog-sk-case] Insert a case block, prompting for details. | |
2421 \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details. | |
2422 \\[verilog-sk-generate] Insert a generate .. endgenerate block. | |
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2423 \\[verilog-sk-header] Insert a header block at the top of file. |
79545 | 2424 \\[verilog-sk-initial] Insert an initial begin .. end block. |
2425 \\[verilog-sk-fork] Insert a fork begin .. end .. join block. | |
2426 \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block. | |
2427 \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block. | |
2428 \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block. | |
2429 \\[verilog-sk-specify] Insert a specify .. endspecify block. | |
2430 \\[verilog-sk-task] Insert a task .. begin .. end endtask block. | |
2431 \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details. | |
2432 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details. | |
2433 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details. | |
2434 \\[verilog-sk-if] Insert an if (..) begin .. end block. | |
2435 \\[verilog-sk-else-if] Insert an else if (..) begin .. end block. | |
2436 \\[verilog-sk-comment] Insert a comment block. | |
2437 \\[verilog-sk-assign] Insert an assign .. = ..; statement. | |
2438 \\[verilog-sk-function] Insert a function .. begin .. end endfunction block. | |
2439 \\[verilog-sk-input] Insert an input declaration, prompting for details. | |
2440 \\[verilog-sk-output] Insert an output declaration, prompting for details. | |
2441 \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details. | |
2442 \\[verilog-sk-inout] Insert an inout declaration, prompting for details. | |
2443 \\[verilog-sk-wire] Insert a wire declaration, prompting for details. | |
2444 \\[verilog-sk-reg] Insert a register declaration, prompting for details. | |
2445 \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module. | |
2446 | |
2447 All key bindings can be seen in a Verilog-buffer with \\[describe-bindings]. | |
2448 Key bindings specific to `verilog-mode-map' are: | |
2449 | |
2450 \\{verilog-mode-map}" | |
2451 (interactive) | |
2452 (kill-all-local-variables) | |
2453 (use-local-map verilog-mode-map) | |
2454 (setq major-mode 'verilog-mode) | |
2455 (setq mode-name "Verilog") | |
2456 (setq local-abbrev-table verilog-mode-abbrev-table) | |
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2457 (set (make-local-variable 'beginning-of-defun-function) |
79546 | 2458 'verilog-beg-of-defun) |
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2459 (set (make-local-variable 'end-of-defun-function) |
79546 | 2460 'verilog-end-of-defun) |
79545 | 2461 (set-syntax-table verilog-mode-syntax-table) |
2462 (make-local-variable 'indent-line-function) | |
2463 (setq indent-line-function 'verilog-indent-line-relative) | |
2464 (setq comment-indent-function 'verilog-comment-indent) | |
2465 (make-local-variable 'parse-sexp-ignore-comments) | |
2466 (setq parse-sexp-ignore-comments nil) | |
2467 (make-local-variable 'comment-start) | |
2468 (make-local-variable 'comment-end) | |
2469 (make-local-variable 'comment-multi-line) | |
2470 (make-local-variable 'comment-start-skip) | |
2471 (setq comment-start "// " | |
2472 comment-end "" | |
2473 comment-start-skip "/\\*+ *\\|// *" | |
2474 comment-multi-line nil) | |
2475 ;; Set up for compilation | |
2476 (setq verilog-which-tool 1) | |
2477 (setq verilog-tool 'verilog-linter) | |
2478 (verilog-set-compile-command) | |
2479 (when (boundp 'hack-local-variables-hook) ;; Also modify any file-local-variables | |
2480 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t)) | |
2481 | |
2482 ;; Setting up menus | |
79546 | 2483 (when (featurep 'xemacs) |
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2484 (easy-menu-add verilog-stmt-menu) |
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2485 (easy-menu-add verilog-menu) |
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2486 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu))) |
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2487 |
79545 | 2488 ;; Stuff for GNU emacs |
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2489 (set (make-local-variable 'font-lock-defaults) |
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2490 '((verilog-font-lock-keywords verilog-font-lock-keywords-1 |
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2491 verilog-font-lock-keywords-2 |
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2492 verilog-font-lock-keywords-3) |
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2493 nil nil nil verilog-beg-of-defun)) |
79545 | 2494 ;;------------------------------------------------------------ |
2495 ;; now hook in 'verilog-colorize-include-files (eldo-mode.el&spice-mode.el) | |
2496 ;; all buffer local: | |
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2497 (when (featurep 'xemacs) |
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2498 (make-local-hook 'font-lock-mode-hook) |
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2499 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in emacs 20 |
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2500 (make-local-hook 'after-change-functions)) |
79545 | 2501 (add-hook 'font-lock-mode-hook 'verilog-colorize-include-files-buffer t t) |
2502 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-colorize-include-files-buffer t t) ; not in emacs 20 | |
2503 (add-hook 'after-change-functions 'verilog-colorize-include-files t t) | |
2504 | |
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2505 ;; Tell imenu how to handle Verilog. |
79545 | 2506 (make-local-variable 'imenu-generic-expression) |
2507 (setq imenu-generic-expression verilog-imenu-generic-expression) | |
2508 ;; hideshow support | |
2509 (unless (assq 'verilog-mode hs-special-modes-alist) | |
2510 (setq hs-special-modes-alist | |
2511 (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil | |
2512 verilog-forward-sexp-function) | |
2513 hs-special-modes-alist))) | |
2514 | |
2515 ;; Stuff for autos | |
2516 (add-hook 'write-contents-hooks 'verilog-auto-save-check) ; already local | |
2517 ;; (verilog-auto-reeval-locals t) ; Save locals in case user changes them | |
2518 ;; (verilog-getopt-flags) | |
2519 (run-hooks 'verilog-mode-hook)) | |
2520 | |
2521 | |
2522 ;; | |
2523 ;; Electric functions | |
2524 ;; | |
2525 (defun electric-verilog-terminate-line (&optional arg) | |
2526 "Terminate line and indent next line. | |
2527 With optional ARG, remove existing end of line comments." | |
2528 (interactive) | |
2529 ;; before that see if we are in a comment | |
2530 (let ((state | |
2531 (save-excursion | |
2532 (parse-partial-sexp (point-min) (point))))) | |
2533 (cond | |
2534 ((nth 7 state) ; Inside // comment | |
2535 (if (eolp) | |
2536 (progn | |
2537 (delete-horizontal-space) | |
2538 (newline)) | |
2539 (progn | |
2540 (newline) | |
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2541 (insert "// ") |
79545 | 2542 (beginning-of-line))) |
2543 (verilog-indent-line)) | |
2544 ((nth 4 state) ; Inside any comment (hence /**/) | |
2545 (newline) | |
2546 (verilog-more-comment)) | |
2547 ((eolp) | |
2548 ;; First, check if current line should be indented | |
2549 (if (save-excursion | |
2550 (delete-horizontal-space) | |
2551 (beginning-of-line) | |
2552 (skip-chars-forward " \t") | |
2553 (if (looking-at verilog-auto-end-comment-lines-re) | |
2554 (let ((indent-str (verilog-indent-line))) | |
2555 ;; Maybe we should set some endcomments | |
2556 (if verilog-auto-endcomments | |
2557 (verilog-set-auto-endcomments indent-str arg)) | |
2558 (end-of-line) | |
2559 (delete-horizontal-space) | |
2560 (if arg | |
2561 () | |
2562 (newline)) | |
2563 nil) | |
2564 (progn | |
2565 (end-of-line) | |
2566 (delete-horizontal-space) | |
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2567 't))) |
79545 | 2568 ;; see if we should line up assignments |
2569 (progn | |
2570 (if (or (memq 'all verilog-auto-lineup) | |
2571 (memq 'assignments verilog-auto-lineup)) | |
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2572 (verilog-pretty-expr)) |
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2573 (newline)) |
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2574 (forward-line 1)) |
79545 | 2575 ;; Indent next line |
2576 (if verilog-auto-indent-on-newline | |
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2577 (verilog-indent-line))) |
79545 | 2578 (t |
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2579 (newline))))) |
79545 | 2580 |
2581 (defun electric-verilog-terminate-and-indent () | |
2582 "Insert a newline and indent for the next statement." | |
2583 (interactive) | |
2584 (electric-verilog-terminate-line 1)) | |
2585 | |
2586 (defun electric-verilog-semi () | |
2587 "Insert `;' character and reindent the line." | |
2588 (interactive) | |
2589 (insert last-command-char) | |
2590 | |
2591 (if (or (verilog-in-comment-or-string-p) | |
2592 (verilog-in-escaped-name-p)) | |
2593 () | |
2594 (save-excursion | |
2595 (beginning-of-line) | |
2596 (verilog-forward-ws&directives) | |
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2597 (verilog-indent-line)) |
79545 | 2598 (if (and verilog-auto-newline |
2599 (not (verilog-parenthesis-depth))) | |
2600 (electric-verilog-terminate-line)))) | |
2601 | |
2602 (defun electric-verilog-semi-with-comment () | |
2603 "Insert `;' character, reindent the line and indent for comment." | |
2604 (interactive) | |
2605 (insert "\;") | |
2606 (save-excursion | |
2607 (beginning-of-line) | |
2608 (verilog-indent-line)) | |
2609 (indent-for-comment)) | |
2610 | |
2611 (defun electric-verilog-colon () | |
2612 "Insert `:' and do all indentations except line indent on this line." | |
2613 (interactive) | |
2614 (insert last-command-char) | |
2615 ;; Do nothing if within string. | |
2616 (if (or | |
2617 (verilog-within-string) | |
2618 (not (verilog-in-case-region-p))) | |
2619 () | |
2620 (save-excursion | |
2621 (let ((p (point)) | |
2622 (lim (progn (verilog-beg-of-statement) (point)))) | |
2623 (goto-char p) | |
2624 (verilog-backward-case-item lim) | |
2625 (verilog-indent-line))) | |
2626 ;; (let ((verilog-tab-always-indent nil)) | |
2627 ;; (verilog-indent-line)) | |
2628 )) | |
2629 | |
2630 ;;(defun electric-verilog-equal () | |
2631 ;; "Insert `=', and do indentation if within block." | |
2632 ;; (interactive) | |
2633 ;; (insert last-command-char) | |
2634 ;; Could auto line up expressions, but not yet | |
2635 ;; (if (eq (car (verilog-calculate-indent)) 'block) | |
2636 ;; (let ((verilog-tab-always-indent nil)) | |
2637 ;; (verilog-indent-command))) | |
2638 ;; ) | |
2639 | |
2640 (defun electric-verilog-tick () | |
2641 "Insert back-tick, and indent to column 0 if this is a CPP directive." | |
2642 (interactive) | |
2643 (insert last-command-char) | |
2644 (save-excursion | |
2645 (if (progn | |
2646 (beginning-of-line) | |
2647 (looking-at verilog-directive-re-1)) | |
2648 (verilog-indent-line)))) | |
2649 | |
2650 (defun electric-verilog-tab () | |
2651 "Function called when TAB is pressed in Verilog mode." | |
2652 (interactive) | |
2653 ;; If verilog-tab-always-indent, indent the beginning of the line. | |
2654 (if (or verilog-tab-always-indent | |
2655 (save-excursion | |
2656 (skip-chars-backward " \t") | |
2657 (bolp))) | |
2658 (let* ((oldpnt (point)) | |
2659 (boi-point | |
2660 (save-excursion | |
2661 (beginning-of-line) | |
2662 (skip-chars-forward " \t") | |
2663 (verilog-indent-line) | |
2664 (back-to-indentation) | |
2665 (point)))) | |
2666 (if (< (point) boi-point) | |
2667 (back-to-indentation) | |
2668 (cond ((not verilog-tab-to-comment)) | |
2669 ((not (eolp)) | |
2670 (end-of-line)) | |
2671 (t | |
2672 (indent-for-comment) | |
2673 (when (and (eolp) (= oldpnt (point))) | |
2674 ; kill existing comment | |
2675 (beginning-of-line) | |
2676 (re-search-forward comment-start-skip oldpnt 'move) | |
2677 (goto-char (match-beginning 0)) | |
2678 (skip-chars-backward " \t") | |
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|
2679 (kill-region (point) oldpnt)))))) |
79545 | 2680 (progn (insert "\t")))) |
2681 | |
2682 | |
2683 | |
2684 ;; | |
2685 ;; Interactive functions | |
2686 ;; | |
2687 | |
2688 (defun verilog-indent-buffer () | |
2689 "Indent-region the entire buffer as Verilog code. | |
2690 To call this from the command line, see \\[verilog-batch-indent]." | |
2691 (interactive) | |
2692 (verilog-mode) | |
2693 (indent-region (point-min) (point-max) nil)) | |
2694 | |
2695 (defun verilog-insert-block () | |
2696 "Insert Verilog begin ... end; block in the code with right indentation." | |
2697 (interactive) | |
2698 (verilog-indent-line) | |
2699 (insert "begin") | |
2700 (electric-verilog-terminate-line) | |
2701 (save-excursion | |
2702 (electric-verilog-terminate-line) | |
2703 (insert "end") | |
2704 (beginning-of-line) | |
2705 (verilog-indent-line))) | |
2706 | |
2707 (defun verilog-star-comment () | |
2708 "Insert Verilog star comment at point." | |
2709 (interactive) | |
2710 (verilog-indent-line) | |
2711 (insert "/*") | |
2712 (save-excursion | |
2713 (newline) | |
2714 (insert " */")) | |
2715 (newline) | |
2716 (insert " * ")) | |
2717 | |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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|
2718 (defun verilog-insert-1 (fmt max) |
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2719 "Use format string FMT to insert integers 0 to MAX - 1. |
79691
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2720 Inserts one integer per line, at the current column. Stops early |
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|
2721 if it reaches the end of the buffer." |
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|
2722 (let ((col (current-column)) |
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|
2723 (n 0)) |
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2724 (save-excursion |
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|
2725 (while (< n max) |
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2726 (insert (format fmt n)) |
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|
2727 (forward-line 1) |
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2728 ;; Note that this function does not bother to check for lines |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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2729 ;; shorter than col. |
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|
2730 (if (eobp) |
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|
2731 (setq n max) |
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|
2732 (setq n (1+ n)) |
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|
2733 (move-to-column col)))))) |
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2734 |
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|
2735 (defun verilog-insert-indices (max) |
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2736 "Insert a set of indices into a rectangle. |
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2737 The upper left corner is defined by point. Indices begin with 0 |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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|
2738 and extend to the MAX - 1. If no prefix arg is given, the user |
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|
2739 is prompted for a value. The indices are surrounded by square |
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2740 brackets \[]. For example, the following code with the point |
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|
2741 located after the first 'a' gives: |
79545 | 2742 |
2743 a = b a[ 0] = b | |
2744 a = b a[ 1] = b | |
2745 a = b a[ 2] = b | |
2746 a = b a[ 3] = b | |
2747 a = b ==> insert-indices ==> a[ 4] = b | |
2748 a = b a[ 5] = b | |
2749 a = b a[ 6] = b | |
2750 a = b a[ 7] = b | |
2751 a = b a[ 8] = b" | |
2752 | |
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2753 (interactive "NMAX: ") |
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|
2754 (verilog-insert-1 "[%3d]" max)) |
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|
2755 |
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|
2756 (defun verilog-generate-numbers (max) |
79545 | 2757 "Insert a set of generated numbers into a rectangle. |
2758 The upper left corner is defined by point. The numbers are padded to three | |
2759 digits, starting with 000 and extending to (MAX - 1). If no prefix argument | |
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|
2760 is supplied, then the user is prompted for the MAX number. Consider the |
79545 | 2761 following code fragment: |
2762 | |
79691
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|
2763 buf buf buf buf000 |
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|
2764 buf buf buf buf001 |
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|
2765 buf buf buf buf002 |
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|
2766 buf buf buf buf003 |
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2767 buf buf ==> generate-numbers ==> buf buf004 |
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|
2768 buf buf buf buf005 |
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|
2769 buf buf buf buf006 |
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|
2770 buf buf buf buf007 |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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|
2771 buf buf buf buf008" |
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|
2772 |
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|
2773 (interactive "NMAX: ") |
79691
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|
2774 (verilog-insert-1 "%3.3d" max)) |
79545 | 2775 |
2776 (defun verilog-mark-defun () | |
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Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
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80163
diff
changeset
|
2777 "Mark the current Verilog function (or procedure). |
79545 | 2778 This puts the mark at the end, and point at the beginning." |
2779 (interactive) | |
80172
7d8f87158250
(eval-when-compile): Don't define
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80171
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|
2780 (if (featurep 'xemacs) |
7d8f87158250
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80171
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changeset
|
2781 (progn |
7d8f87158250
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80171
diff
changeset
|
2782 (push-mark (point)) |
7d8f87158250
(eval-when-compile): Don't define
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80171
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changeset
|
2783 (verilog-end-of-defun) |
7d8f87158250
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diff
changeset
|
2784 (push-mark (point)) |
7d8f87158250
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|
2785 (verilog-beg-of-defun) |
7d8f87158250
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|
2786 (if (fboundp 'zmacs-activate-region) |
7d8f87158250
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diff
changeset
|
2787 (zmacs-activate-region))) |
7d8f87158250
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80171
diff
changeset
|
2788 (mark-defun))) |
79545 | 2789 |
2790 (defun verilog-comment-region (start end) | |
2791 ; checkdoc-params: (start end) | |
2792 "Put the region into a Verilog comment. | |
2793 The comments that are in this area are \"deformed\": | |
2794 `*)' becomes `!(*' and `}' becomes `!{'. | |
2795 These deformed comments are returned to normal if you use | |
2796 \\[verilog-uncomment-region] to undo the commenting. | |
2797 | |
2798 The commented area starts with `verilog-exclude-str-start', and ends with | |
2799 `verilog-exclude-str-end'. But if you change these variables, | |
2800 \\[verilog-uncomment-region] won't recognize the comments." | |
2801 (interactive "r") | |
2802 (save-excursion | |
2803 ;; Insert start and endcomments | |
2804 (goto-char end) | |
2805 (if (and (save-excursion (skip-chars-forward " \t") (eolp)) | |
2806 (not (save-excursion (skip-chars-backward " \t") (bolp)))) | |
2807 (forward-line 1) | |
2808 (beginning-of-line)) | |
2809 (insert verilog-exclude-str-end) | |
2810 (setq end (point)) | |
2811 (newline) | |
2812 (goto-char start) | |
2813 (beginning-of-line) | |
2814 (insert verilog-exclude-str-start) | |
2815 (newline) | |
2816 ;; Replace end-comments within commented area | |
2817 (goto-char end) | |
2818 (save-excursion | |
2819 (while (re-search-backward "\\*/" start t) | |
2820 (replace-match "*-/" t t))) | |
2821 (save-excursion | |
2822 (let ((s+1 (1+ start))) | |
2823 (while (re-search-backward "/\\*" s+1 t) | |
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changeset
|
2824 (replace-match "/-*" t t)))))) |
79545 | 2825 |
2826 (defun verilog-uncomment-region () | |
2827 "Uncomment a commented area; change deformed comments back to normal. | |
2828 This command does nothing if the pointer is not in a commented | |
2829 area. See also `verilog-comment-region'." | |
2830 (interactive) | |
2831 (save-excursion | |
2832 (let ((start (point)) | |
2833 (end (point))) | |
2834 ;; Find the boundaries of the comment | |
2835 (save-excursion | |
2836 (setq start (progn (search-backward verilog-exclude-str-start nil t) | |
2837 (point))) | |
2838 (setq end (progn (search-forward verilog-exclude-str-end nil t) | |
2839 (point)))) | |
2840 ;; Check if we're really inside a comment | |
2841 (if (or (equal start (point)) (<= end (point))) | |
2842 (message "Not standing within commented area.") | |
2843 (progn | |
2844 ;; Remove endcomment | |
2845 (goto-char end) | |
2846 (beginning-of-line) | |
2847 (let ((pos (point))) | |
2848 (end-of-line) | |
2849 (delete-region pos (1+ (point)))) | |
2850 ;; Change comments back to normal | |
2851 (save-excursion | |
2852 (while (re-search-backward "\\*-/" start t) | |
2853 (replace-match "*/" t t))) | |
2854 (save-excursion | |
2855 (while (re-search-backward "/-\\*" start t) | |
2856 (replace-match "/*" t t))) | |
2857 ;; Remove start comment | |
2858 (goto-char start) | |
2859 (beginning-of-line) | |
2860 (let ((pos (point))) | |
2861 (end-of-line) | |
2862 (delete-region pos (1+ (point))))))))) | |
2863 | |
2864 (defun verilog-beg-of-defun () | |
2865 "Move backward to the beginning of the current function or procedure." | |
2866 (interactive) | |
2867 (verilog-re-search-backward verilog-defun-re nil 'move)) | |
2868 | |
2869 (defun verilog-end-of-defun () | |
2870 "Move forward to the end of the current function or procedure." | |
2871 (interactive) | |
2872 (verilog-re-search-forward verilog-end-defun-re nil 'move)) | |
2873 | |
2874 (defun verilog-get-beg-of-defun (&optional warn) | |
2875 (save-excursion | |
2876 (cond ((verilog-re-search-forward-quick verilog-defun-re nil t) | |
2877 (point)) | |
2878 (t | |
2879 (error "%s: Can't find module beginning" (verilog-point-text)) | |
2880 (point-max))))) | |
2881 (defun verilog-get-end-of-defun (&optional warn) | |
2882 (save-excursion | |
2883 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t) | |
2884 (point)) | |
2885 (t | |
2886 (error "%s: Can't find endmodule" (verilog-point-text)) | |
2887 (point-max))))) | |
2888 | |
2889 (defun verilog-label-be (&optional arg) | |
2890 "Label matching begin ... end, fork ... join and case ... endcase statements. | |
2891 With ARG, first kill any existing labels." | |
2892 (interactive) | |
2893 (let ((cnt 0) | |
2894 (oldpos (point)) | |
2895 (b (progn | |
2896 (verilog-beg-of-defun) | |
2897 (point-marker))) | |
2898 (e (progn | |
2899 (verilog-end-of-defun) | |
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|
2900 (point-marker)))) |
79545 | 2901 (goto-char (marker-position b)) |
2902 (if (> (- e b) 200) | |
2903 (message "Relabeling module...")) | |
2904 (while (and | |
2905 (> (marker-position e) (point)) | |
2906 (verilog-re-search-forward | |
2907 (concat | |
2908 "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>" | |
2909 "\\|\\(`endif\\)\\|\\(`else\\)") | |
2910 nil 'move)) | |
2911 (goto-char (match-beginning 0)) | |
2912 (let ((indent-str (verilog-indent-line))) | |
2913 (verilog-set-auto-endcomments indent-str 't) | |
2914 (end-of-line) | |
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|
2915 (delete-horizontal-space)) |
79545 | 2916 (setq cnt (1+ cnt)) |
2917 (if (= 9 (% cnt 10)) | |
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|
2918 (message "%d..." cnt))) |
79545 | 2919 (goto-char oldpos) |
2920 (if (or | |
2921 (> (- e b) 200) | |
2922 (> cnt 20)) | |
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|
2923 (message "%d lines auto commented" cnt)))) |
79545 | 2924 |
2925 (defun verilog-beg-of-statement () | |
2926 "Move backward to beginning of statement." | |
2927 (interactive) | |
2928 ;; Move back token by token until we see the end | |
2929 ;; of some ealier line. | |
2930 (while | |
2931 ;; If the current point does not begin a new | |
2932 ;; statement, as in the character ahead of us is a ';', or SOF | |
2933 ;; or the string after us unambiguosly starts a statement, | |
2934 ;; or the token before us unambiguously ends a statement, | |
2935 ;; then move back a token and test again. | |
2936 (not (or | |
2937 (bolp) | |
2938 (= (preceding-char) ?\;) | |
2939 (not (or | |
2940 (looking-at "\\<") | |
2941 (forward-word -1))) | |
2942 (and | |
2943 (looking-at verilog-extended-complete-re) | |
2944 (not (save-excursion | |
2945 (verilog-backward-token) | |
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parents:
79717
diff
changeset
|
2946 (looking-at verilog-extended-complete-re)))) |
79545 | 2947 (looking-at verilog-basic-complete-re) |
2948 (save-excursion | |
2949 (verilog-backward-token) | |
2950 (or | |
2951 (looking-at verilog-end-block-re) | |
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(top-level): Fix spacing.
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diff
changeset
|
2952 (looking-at verilog-preprocessor-re))))) |
79545 | 2953 (verilog-backward-syntactic-ws) |
2954 (verilog-backward-token)) | |
2955 ;; Now point is where the previous line ended. | |
2956 (verilog-forward-syntactic-ws)) | |
2957 | |
2958 (defun verilog-beg-of-statement-1 () | |
2959 "Move backward to beginning of statement." | |
2960 (interactive) | |
2961 (let ((pt (point))) | |
2962 | |
2963 (while (and (not (looking-at verilog-complete-reg)) | |
2964 (setq pt (point)) | |
2965 (verilog-backward-token) | |
2966 (not (looking-at verilog-complete-reg)) | |
2967 (verilog-backward-syntactic-ws) | |
2968 (setq pt (point)) | |
2969 (not (bolp)) | |
2970 (not (= (preceding-char) ?\;)))) | |
2971 (goto-char pt) | |
2972 (verilog-forward-ws&directives))) | |
2973 | |
2974 (defun verilog-end-of-statement () | |
2975 "Move forward to end of current statement." | |
2976 (interactive) | |
2977 (let ((nest 0) pos) | |
2978 (or (looking-at verilog-beg-block-re) | |
2979 ;; Skip to end of statement | |
2980 (setq pos (catch 'found | |
2981 (while t | |
2982 (forward-sexp 1) | |
2983 (verilog-skip-forward-comment-or-string) | |
2984 (cond ((looking-at "[ \t]*;") | |
2985 (skip-chars-forward "^;") | |
2986 (forward-char 1) | |
2987 (throw 'found (point))) | |
2988 ((save-excursion | |
2989 (forward-sexp -1) | |
2990 (looking-at verilog-beg-block-re)) | |
2991 (goto-char (match-beginning 0)) | |
2992 (throw 'found nil)) | |
2993 ((looking-at "[ \t]*)") | |
79546 | 2994 (throw 'found (point))) |
79545 | 2995 ((eobp) |
2996 (throw 'found (point)))))))) | |
2997 (if (not pos) | |
2998 ;; Skip a whole block | |
2999 (catch 'found | |
3000 (while t | |
3001 (verilog-re-search-forward verilog-end-statement-re nil 'move) | |
3002 (setq nest (if (match-end 1) | |
3003 (1+ nest) | |
3004 (1- nest))) | |
3005 (cond ((eobp) | |
3006 (throw 'found (point))) | |
3007 ((= 0 nest) | |
3008 (throw 'found (verilog-end-of-statement)))))) | |
3009 pos))) | |
3010 | |
3011 (defun verilog-in-case-region-p () | |
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parents:
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diff
changeset
|
3012 "Return true if in a case region. |
411da0873a97
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parents:
80163
diff
changeset
|
3013 More specifically, point @ in the line foo : @ begin" |
79545 | 3014 (interactive) |
3015 (save-excursion | |
3016 (if (and | |
3017 (progn (verilog-forward-syntactic-ws) | |
3018 (looking-at "\\<begin\\>")) | |
3019 (progn (verilog-backward-syntactic-ws) | |
3020 (= (preceding-char) ?\:))) | |
3021 (catch 'found | |
3022 (let ((nest 1)) | |
3023 (while t | |
3024 (verilog-re-search-backward | |
3025 (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|" | |
3026 "\\(\\<endcase\\>\\)\\>") | |
3027 nil 'move) | |
3028 (cond | |
3029 ((match-end 3) | |
3030 (setq nest (1+ nest))) | |
3031 ((match-end 2) | |
3032 (if (= nest 1) | |
3033 (throw 'found 1)) | |
3034 (setq nest (1- nest))) | |
3035 (t | |
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parents:
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diff
changeset
|
3036 (throw 'found (= nest 0))))))) |
79545 | 3037 nil))) |
3038 (defun verilog-in-struct-region-p () | |
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Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
3039 "Return true if in a struct region. |
411da0873a97
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Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
3040 More specifically, in a list after a struct|union keyword." |
79545 | 3041 (interactive) |
3042 (save-excursion | |
3043 (let* ((state (parse-partial-sexp (point-min) (point))) | |
3044 (depth (nth 0 state))) | |
3045 (if depth | |
3046 (progn (backward-up-list depth) | |
3047 (verilog-beg-of-statement) | |
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parents:
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diff
changeset
|
3048 (looking-at "\\<typedef\\>?\\s-*\\<struct\\|union\\>")))))) |
79545 | 3049 |
3050 (defun verilog-in-generate-region-p () | |
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Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
3051 "Return true if in a generate region. |
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
3052 More specifically, after a generate and before an endgenerate." |
79545 | 3053 (interactive) |
3054 (let ((lim (save-excursion (verilog-beg-of-defun) (point))) | |
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parents:
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diff
changeset
|
3055 (nest 1)) |
79545 | 3056 (save-excursion |
3057 (while (and | |
3058 (/= nest 0) | |
3059 (verilog-re-search-backward "\\<\\(generate\\)\\|\\(endgenerate\\)\\>" lim 'move) | |
3060 (cond | |
3061 ((match-end 1) ; generate | |
3062 (setq nest (1- nest))) | |
3063 ((match-end 2) ; endgenerate | |
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parents:
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diff
changeset
|
3064 (setq nest (1+ nest))))))) |
79545 | 3065 (= nest 0) )) ; return nest |
3066 | |
3067 (defun verilog-in-fork-region-p () | |
3068 "Return true if between a fork and join." | |
3069 (interactive) | |
3070 (let ((lim (save-excursion (verilog-beg-of-defun) (point))) | |
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parents:
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diff
changeset
|
3071 (nest 1)) |
79545 | 3072 (save-excursion |
3073 (while (and | |
3074 (/= nest 0) | |
3075 (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move) | |
3076 (cond | |
3077 ((match-end 1) ; fork | |
3078 (setq nest (1- nest))) | |
3079 ((match-end 2) ; join | |
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parents:
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diff
changeset
|
3080 (setq nest (1+ nest))))))) |
79545 | 3081 (= nest 0) )) ; return nest |
3082 | |
3083 (defun verilog-backward-case-item (lim) | |
3084 "Skip backward to nearest enclosing case item. | |
3085 Limit search to point LIM." | |
3086 (interactive) | |
3087 (let ((str 'nil) | |
3088 (lim1 | |
3089 (progn | |
3090 (save-excursion | |
3091 (verilog-re-search-backward verilog-endcomment-reason-re | |
3092 lim 'move) | |
3093 (point))))) | |
3094 ;; Try to find the real : | |
3095 (if (save-excursion (search-backward ":" lim1 t)) | |
3096 (let ((colon 0) | |
3097 b e ) | |
3098 (while | |
3099 (and | |
3100 (< colon 1) | |
3101 (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)" | |
3102 lim1 'move)) | |
3103 (cond | |
3104 ((match-end 1) ;; [ | |
3105 (setq colon (1+ colon)) | |
3106 (if (>= colon 0) | |
3107 (error "%s: unbalanced [" (verilog-point-text)))) | |
3108 ((match-end 2) ;; ] | |
3109 (setq colon (1- colon))) | |
3110 | |
3111 ((match-end 3) ;; : | |
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Dan Nicolaescu <dann@ics.uci.edu>
parents:
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diff
changeset
|
3112 (setq colon (1+ colon))))) |
79545 | 3113 ;; Skip back to beginning of case item |
3114 (skip-chars-backward "\t ") | |
3115 (verilog-skip-backward-comment-or-string) | |
3116 (setq e (point)) | |
3117 (setq b | |
3118 (progn | |
3119 (if | |
3120 (verilog-re-search-backward | |
3121 "\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move) | |
3122 (progn | |
3123 (cond | |
3124 ((match-end 1) | |
3125 (goto-char (match-end 1)) | |
3126 (verilog-forward-ws&directives) | |
3127 (if (looking-at "(") | |
3128 (progn | |
3129 (forward-sexp) | |
3130 (verilog-forward-ws&directives))) | |
3131 (point)) | |
3132 (t | |
3133 (goto-char (match-end 0)) | |
3134 (verilog-forward-ws&directives) | |
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
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diff
changeset
|
3135 (point)))) |
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parents:
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diff
changeset
|
3136 (error "Malformed case item")))) |
79545 | 3137 (setq str (buffer-substring b e)) |
3138 (if | |
3139 (setq e | |
3140 (string-match | |
3141 "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str)) | |
3142 (setq str (concat (substring str 0 e) "..."))) | |
3143 str) | |
3144 'nil))) | |
3145 | |
3146 | |
3147 ;; | |
3148 ;; Other functions | |
3149 ;; | |
3150 | |
79554
bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79552
diff
changeset
|
3151 (defun verilog-kill-existing-comment () |
79545 | 3152 "Kill auto comment on this line." |
3153 (save-excursion | |
3154 (let* ( | |
3155 (e (progn | |
3156 (end-of-line) | |
3157 (point))) | |
3158 (b (progn | |
3159 (beginning-of-line) | |
3160 (search-forward "//" e t)))) | |
3161 (if b | |
3162 (delete-region (- b 2) e))))) | |
3163 | |
3164 (defconst verilog-directive-nest-re | |
3165 (concat "\\(`else\\>\\)\\|" | |
3166 "\\(`endif\\>\\)\\|" | |
3167 "\\(`if\\>\\)\\|" | |
3168 "\\(`ifdef\\>\\)\\|" | |
3169 "\\(`ifndef\\>\\)")) | |
3170 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment) | |
3171 "Add ending comment with given INDENT-STR. | |
3172 With KILL-EXISTING-COMMENT, remove what was there before. | |
3173 Insert `// case: 7 ' or `// NAME ' on this line if appropriate. | |
3174 Insert `// case expr ' if this line ends a case block. | |
3175 Insert `// ifdef FOO ' if this line ends code conditional on FOO. | |
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Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
3176 Insert `// NAME ' if this line ends a function, task, module, |
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
3177 primitive or interface named NAME." |
79545 | 3178 (save-excursion |
3179 (cond | |
3180 (; Comment close preprocessor directives | |
3181 (and | |
3182 (looking-at "\\(`endif\\)\\|\\(`else\\)") | |
3183 (or kill-existing-comment | |
3184 (not (save-excursion | |
3185 (end-of-line) | |
3186 (search-backward "//" (verilog-get-beg-of-line) t))))) | |
3187 (let ((nest 1) b e | |
3188 m | |
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3189 (else (if (match-end 2) "!" " "))) |
79545 | 3190 (end-of-line) |
3191 (if kill-existing-comment | |
79554
bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79552
diff
changeset
|
3192 (verilog-kill-existing-comment)) |
79545 | 3193 (delete-horizontal-space) |
3194 (save-excursion | |
3195 (backward-sexp 1) | |
3196 (while (and (/= nest 0) | |
3197 (verilog-re-search-backward verilog-directive-nest-re nil 'move)) | |
3198 (cond | |
3199 ((match-end 1) ; `else | |
3200 (if (= nest 1) | |
3201 (setq else "!"))) | |
3202 ((match-end 2) ; `endif | |
3203 (setq nest (1+ nest))) | |
3204 ((match-end 3) ; `if | |
3205 (setq nest (1- nest))) | |
3206 ((match-end 4) ; `ifdef | |
3207 (setq nest (1- nest))) | |
3208 ((match-end 5) ; `ifndef | |
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3209 (setq nest (1- nest))))) |
79545 | 3210 (if (match-end 0) |
3211 (setq | |
3212 m (buffer-substring | |
3213 (match-beginning 0) | |
3214 (match-end 0)) | |
3215 b (progn | |
3216 (skip-chars-forward "^ \t") | |
3217 (verilog-forward-syntactic-ws) | |
3218 (point)) | |
3219 e (progn | |
3220 (skip-chars-forward "a-zA-Z0-9_") | |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3221 (point))))) |
79545 | 3222 (if b |
3223 (if (> (count-lines (point) b) verilog-minimum-comment-distance) | |
3224 (insert (concat " // " else m " " (buffer-substring b e)))) | |
3225 (progn | |
3226 (insert " // unmatched `else or `endif") | |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3227 (ding 't))))) |
79545 | 3228 |
3229 (; Comment close case/class/function/task/module and named block | |
3230 (and (looking-at "\\<end") | |
3231 (or kill-existing-comment | |
3232 (not (save-excursion | |
3233 (end-of-line) | |
3234 (search-backward "//" (verilog-get-beg-of-line) t))))) | |
3235 (let ((type (car indent-str))) | |
3236 (unless (eq type 'declaration) | |
3237 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ;; ignore named ends | |
3238 (if (looking-at verilog-end-block-ordered-re) | |
3239 (cond | |
3240 (;- This is a case block; search back for the start of this case | |
3241 (match-end 1) ;; of verilog-end-block-ordered-re | |
3242 | |
3243 (let ((err 't) | |
3244 (str "UNMATCHED!!")) | |
3245 (save-excursion | |
3246 (verilog-leap-to-head) | |
3247 (cond | |
3248 ((looking-at "\\<randcase\\>") | |
3249 (setq str "randcase") | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3250 (setq err nil)) |
79545 | 3251 ((match-end 0) |
3252 (goto-char (match-end 1)) | |
3253 (if nil | |
3254 (let (s f) | |
3255 (setq s (match-beginning 1)) | |
3256 (setq f (progn (end-of-line) | |
3257 (point))) | |
3258 (setq str (buffer-substring s f))) | |
3259 (setq err nil)) | |
3260 (setq str (concat (buffer-substring (match-beginning 1) (match-end 1)) | |
3261 " " | |
3262 (verilog-get-expr)))))) | |
3263 (end-of-line) | |
3264 (if kill-existing-comment | |
79554
bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
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parents:
79552
diff
changeset
|
3265 (verilog-kill-existing-comment)) |
79545 | 3266 (delete-horizontal-space) |
3267 (insert (concat " // " str )) | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3268 (if err (ding 't)))) |
79545 | 3269 |
3270 (;- This is a begin..end block | |
3271 (match-end 2) ;; of verilog-end-block-ordered-re | |
3272 (let ((str " // UNMATCHED !!") | |
3273 (err 't) | |
3274 (here (point)) | |
3275 there | |
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(top-level): Fix spacing.
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parents:
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diff
changeset
|
3276 cntx) |
79545 | 3277 (save-excursion |
3278 (verilog-leap-to-head) | |
3279 (setq there (point)) | |
3280 (if (not (match-end 0)) | |
3281 (progn | |
3282 (goto-char here) | |
3283 (end-of-line) | |
3284 (if kill-existing-comment | |
79554
bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79552
diff
changeset
|
3285 (verilog-kill-existing-comment)) |
79545 | 3286 (delete-horizontal-space) |
3287 (insert str) | |
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
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diff
changeset
|
3288 (ding 't)) |
79545 | 3289 (let ((lim |
3290 (save-excursion (verilog-beg-of-defun) (point))) | |
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(top-level): Fix spacing.
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parents:
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diff
changeset
|
3291 (here (point))) |
79545 | 3292 (cond |
3293 (;-- handle named block differently | |
3294 (looking-at verilog-named-block-re) | |
3295 (search-forward ":") | |
3296 (setq there (point)) | |
3297 (setq str (verilog-get-expr)) | |
3298 (setq err nil) | |
3299 (setq str (concat " // block: " str ))) | |
3300 | |
3301 ((verilog-in-case-region-p) ;-- handle case item differently | |
3302 (goto-char here) | |
3303 (setq str (verilog-backward-case-item lim)) | |
3304 (setq there (point)) | |
3305 (setq err nil) | |
3306 (setq str (concat " // case: " str ))) | |
3307 | |
3308 (;- try to find "reason" for this begin | |
3309 (cond | |
3310 (; | |
3311 (eq here (progn | |
3312 (verilog-backward-token) | |
3313 (verilog-beg-of-statement-1) | |
3314 (point))) | |
3315 (setq err nil) | |
3316 (setq str "")) | |
3317 ((looking-at verilog-endcomment-reason-re) | |
3318 (setq there (match-end 0)) | |
3319 (setq cntx (concat | |
3320 (buffer-substring (match-beginning 0) (match-end 0)) " ")) | |
3321 (cond | |
3322 (;- begin | |
3323 (match-end 2) | |
3324 (setq err nil) | |
3325 (save-excursion | |
3326 (if (and (verilog-continued-line) | |
3327 (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>")) | |
3328 (progn | |
3329 (goto-char (match-end 0)) | |
3330 (setq there (point)) | |
3331 (setq str | |
3332 (concat " // " | |
3333 (buffer-substring (match-beginning 0) (match-end 0)) " " | |
3334 (verilog-get-expr)))) | |
3335 (setq str "")))) | |
3336 | |
3337 (;- else | |
3338 (match-end 4) | |
3339 (let ((nest 0) | |
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(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
3340 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)")) |
79545 | 3341 (catch 'skip |
3342 (while (verilog-re-search-backward reg nil 'move) | |
3343 (cond | |
3344 ((match-end 1) ; begin | |
3345 (setq nest (1- nest))) | |
3346 ((match-end 2) ; end | |
3347 (setq nest (1+ nest))) | |
3348 ((match-end 3) | |
3349 (if (= 0 nest) | |
3350 (progn | |
3351 (goto-char (match-end 0)) | |
3352 (setq there (point)) | |
3353 (setq err nil) | |
3354 (setq str (verilog-get-expr)) | |
3355 (setq str (concat " // else: !if" str )) | |
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diff
changeset
|
3356 (throw 'skip 1))))))))) |
79545 | 3357 |
3358 (;- end else | |
3359 (match-end 5) | |
3360 (goto-char there) | |
3361 (let ((nest 0) | |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3362 (reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)")) |
79545 | 3363 (catch 'skip |
3364 (while (verilog-re-search-backward reg nil 'move) | |
3365 (cond | |
3366 ((match-end 1) ; begin | |
3367 (setq nest (1- nest))) | |
3368 ((match-end 2) ; end | |
3369 (setq nest (1+ nest))) | |
3370 ((match-end 3) | |
3371 (if (= 0 nest) | |
3372 (progn | |
3373 (goto-char (match-end 0)) | |
3374 (setq there (point)) | |
3375 (setq err nil) | |
3376 (setq str (verilog-get-expr)) | |
3377 (setq str (concat " // else: !if" str )) | |
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(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
3378 (throw 'skip 1))))))))) |
79545 | 3379 |
3380 (;- task/function/initial et cetera | |
3381 t | |
3382 (match-end 0) | |
3383 (goto-char (match-end 0)) | |
3384 (setq there (point)) | |
3385 (setq err nil) | |
3386 (setq str (verilog-get-expr)) | |
3387 (setq str (concat " // " cntx str ))) | |
3388 | |
3389 (;-- otherwise... | |
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parents:
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diff
changeset
|
3390 (setq str " // auto-endcomment confused ")))) |
79545 | 3391 |
3392 ((and | |
3393 (verilog-in-case-region-p) ;-- handle case item differently | |
3394 (progn | |
3395 (setq there (point)) | |
3396 (goto-char here) | |
3397 (setq str (verilog-backward-case-item lim)))) | |
3398 (setq err nil) | |
3399 (setq str (concat " // case: " str ))) | |
3400 | |
3401 ((verilog-in-fork-region-p) | |
3402 (setq err nil) | |
3403 (setq str " // fork branch" )) | |
3404 | |
3405 ((looking-at "\\<end\\>") | |
3406 ;; HERE | |
3407 (forward-word 1) | |
3408 (verilog-forward-syntactic-ws) | |
3409 (setq err nil) | |
3410 (setq str (verilog-get-expr)) | |
3411 (setq str (concat " // " cntx str ))) | |
3412 | |
3413 )))) | |
3414 (goto-char here) | |
3415 (end-of-line) | |
3416 (if kill-existing-comment | |
79554
bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
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parents:
79552
diff
changeset
|
3417 (verilog-kill-existing-comment)) |
79545 | 3418 (delete-horizontal-space) |
3419 (if (or err | |
3420 (> (count-lines here there) verilog-minimum-comment-distance)) | |
3421 (insert str)) | |
3422 (if err (ding 't)) | |
3423 )))) | |
3424 (;- this is endclass, which can be nested | |
3425 (match-end 11) ;; of verilog-end-block-ordered-re | |
3426 ;;(goto-char there) | |
3427 (let ((nest 0) | |
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parents:
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diff
changeset
|
3428 (reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>") |
57956dd69d3f
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parents:
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diff
changeset
|
3429 string) |
79545 | 3430 (save-excursion |
3431 (catch 'skip | |
3432 (while (verilog-re-search-backward reg nil 'move) | |
3433 (cond | |
3434 ((match-end 3) ; endclass | |
3435 (ding 't) | |
3436 (setq string "unmatched endclass") | |
3437 (throw 'skip 1)) | |
3438 | |
3439 ((match-end 2) ; endclass | |
3440 (setq nest (1+ nest))) | |
3441 | |
3442 ((match-end 1) ; class | |
3443 (setq nest (1- nest)) | |
3444 (if (< nest 0) | |
3445 (progn | |
3446 (goto-char (match-end 0)) | |
3447 (let (b e) | |
3448 (setq b (progn | |
3449 (skip-chars-forward "^ \t") | |
3450 (verilog-forward-ws&directives) | |
3451 (point)) | |
3452 e (progn | |
3453 (skip-chars-forward "a-zA-Z0-9_") | |
3454 (point))) | |
3455 (setq string (buffer-substring b e))) | |
3456 (throw 'skip 1)))) | |
3457 )))) | |
3458 (end-of-line) | |
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parents:
79717
diff
changeset
|
3459 (insert (concat " // " string )))) |
79545 | 3460 |
3461 (;- this is end{function,generate,task,module,primitive,table,generate} | |
3462 ;- which can not be nested. | |
3463 t | |
3464 (let (string reg (width nil)) | |
3465 (end-of-line) | |
3466 (if kill-existing-comment | |
3467 (save-match-data | |
79554
bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79552
diff
changeset
|
3468 (verilog-kill-existing-comment))) |
79545 | 3469 (delete-horizontal-space) |
3470 (backward-sexp) | |
3471 (cond | |
3472 ((match-end 5) ;; of verilog-end-block-ordered-re | |
3473 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)") | |
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parents:
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diff
changeset
|
3474 (setq width "\\(\\s-*\\(\\[[^]]*\\]\\)\\|\\(real\\(time\\)?\\)\\|\\(integer\\)\\|\\(time\\)\\)?")) |
79545 | 3475 ((match-end 6) ;; of verilog-end-block-ordered-re |
3476 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")) | |
3477 ((match-end 7) ;; of verilog-end-block-ordered-re | |
3478 (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>")) | |
3479 ((match-end 8) ;; of verilog-end-block-ordered-re | |
3480 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)")) | |
3481 ((match-end 9) ;; of verilog-end-block-ordered-re | |
3482 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)")) | |
3483 ((match-end 10) ;; of verilog-end-block-ordered-re | |
3484 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)")) | |
3485 ((match-end 11) ;; of verilog-end-block-ordered-re | |
3486 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)")) | |
3487 ((match-end 12) ;; of verilog-end-block-ordered-re | |
3488 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)")) | |
3489 ((match-end 13) ;; of verilog-end-block-ordered-re | |
3490 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)")) | |
3491 ((match-end 14) ;; of verilog-end-block-ordered-re | |
3492 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)")) | |
3493 ((match-end 15) ;; of verilog-end-block-ordered-re | |
3494 (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>")) | |
3495 | |
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parents:
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diff
changeset
|
3496 (t (error "Problem in verilog-set-auto-endcomments"))) |
79545 | 3497 (let (b e) |
3498 (save-excursion | |
3499 (verilog-re-search-backward reg nil 'move) | |
3500 (cond | |
3501 ((match-end 1) | |
3502 (setq b (progn | |
3503 (skip-chars-forward "^ \t") | |
3504 (verilog-forward-ws&directives) | |
3505 (if (and width (looking-at width)) | |
3506 (progn | |
3507 (goto-char (match-end 0)) | |
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parents:
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diff
changeset
|
3508 (verilog-forward-ws&directives))) |
79545 | 3509 (point)) |
3510 e (progn | |
3511 (skip-chars-forward "a-zA-Z0-9_") | |
3512 (point))) | |
3513 (setq string (buffer-substring b e))) | |
3514 (t | |
3515 (ding 't) | |
3516 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)"))))) | |
3517 (end-of-line) | |
3518 (insert (concat " // " string ))) | |
3519 )))))))))) | |
3520 | |
3521 (defun verilog-get-expr() | |
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Juanma Barranquero <lekktu@gmail.com>
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80163
diff
changeset
|
3522 "Grab expression at point, e.g, case ( a | b & (c ^d))." |
79545 | 3523 (let* ((b (progn |
3524 (verilog-forward-syntactic-ws) | |
3525 (skip-chars-forward " \t") | |
3526 (point))) | |
3527 (e (let ((par 1)) | |
3528 (cond | |
3529 ((looking-at "@") | |
3530 (forward-char 1) | |
3531 (verilog-forward-syntactic-ws) | |
3532 (if (looking-at "(") | |
3533 (progn | |
3534 (forward-char 1) | |
3535 (while (and (/= par 0) | |
3536 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move)) | |
3537 (cond | |
3538 ((match-end 1) | |
3539 (setq par (1+ par))) | |
3540 ((match-end 2) | |
3541 (setq par (1- par))))))) | |
3542 (point)) | |
3543 ((looking-at "(") | |
3544 (forward-char 1) | |
3545 (while (and (/= par 0) | |
3546 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move)) | |
3547 (cond | |
3548 ((match-end 1) | |
3549 (setq par (1+ par))) | |
3550 ((match-end 2) | |
3551 (setq par (1- par))))) | |
3552 (point)) | |
3553 ((looking-at "\\[") | |
3554 (forward-char 1) | |
3555 (while (and (/= par 0) | |
3556 (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move)) | |
3557 (cond | |
3558 ((match-end 1) | |
3559 (setq par (1+ par))) | |
3560 ((match-end 2) | |
3561 (setq par (1- par))))) | |
3562 (verilog-forward-syntactic-ws) | |
3563 (skip-chars-forward "^ \t\n\f") | |
3564 (point)) | |
3565 ((looking-at "/[/\\*]") | |
3566 b) | |
3567 ('t | |
3568 (skip-chars-forward "^: \t\n\f") | |
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parents:
79717
diff
changeset
|
3569 (point))))) |
79545 | 3570 (str (buffer-substring b e))) |
3571 (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str)) | |
3572 (setq str (concat (substring str 0 e) "..."))) | |
3573 str)) | |
3574 | |
3575 (defun verilog-expand-vector () | |
3576 "Take a signal vector on the current line and expand it to multiple lines. | |
3577 Useful for creating tri's and other expanded fields." | |
3578 (interactive) | |
3579 (verilog-expand-vector-internal "[" "]")) | |
3580 | |
3581 (defun verilog-expand-vector-internal (bra ket) | |
3582 "Given BRA, the start brace and KET, the end brace, expand one line into many lines." | |
3583 (save-excursion | |
3584 (forward-line 0) | |
3585 (let ((signal-string (buffer-substring (point) | |
3586 (progn | |
3587 (end-of-line) (point))))) | |
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d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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79555
diff
changeset
|
3588 (if (string-match |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
3589 (concat "\\(.*\\)" |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
3590 (regexp-quote bra) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
3591 "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)" |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
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diff
changeset
|
3592 (regexp-quote ket) |
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(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
3593 "\\(.*\\)$") signal-string) |
79545 | 3594 (let* ((sig-head (match-string 1 signal-string)) |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3595 (vec-start (string-to-number (match-string 2 signal-string))) |
79545 | 3596 (vec-end (if (= (match-beginning 3) (match-end 3)) |
3597 vec-start | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
3598 (string-to-number |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3599 (substring signal-string (1+ (match-beginning 3)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
3600 (match-end 3))))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
3601 (vec-range |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
3602 (if (= (match-beginning 4) (match-end 4)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
3603 1 |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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79555
diff
changeset
|
3604 (string-to-number |
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79555
diff
changeset
|
3605 (substring signal-string (+ 2 (match-beginning 4)) |
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parents:
79555
diff
changeset
|
3606 (match-end 4))))) |
79545 | 3607 (sig-tail (match-string 5 signal-string)) |
3608 vec) | |
3609 ;; Decode vectors | |
3610 (setq vec nil) | |
3611 (if (< vec-range 0) | |
3612 (let ((tmp vec-start)) | |
3613 (setq vec-start vec-end | |
3614 vec-end tmp | |
3615 vec-range (- vec-range)))) | |
3616 (if (< vec-end vec-start) | |
3617 (while (<= vec-end vec-start) | |
3618 (setq vec (append vec (list vec-start))) | |
3619 (setq vec-start (- vec-start vec-range))) | |
3620 (while (<= vec-start vec-end) | |
3621 (setq vec (append vec (list vec-start))) | |
3622 (setq vec-start (+ vec-start vec-range)))) | |
3623 ;; | |
3624 ;; Delete current line | |
3625 (delete-region (point) (progn (forward-line 0) (point))) | |
3626 ;; | |
3627 ;; Expand vector | |
3628 (while vec | |
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diff
changeset
|
3629 (insert (concat sig-head bra |
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parents:
79555
diff
changeset
|
3630 (int-to-string (car vec)) ket sig-tail "\n")) |
79545 | 3631 (setq vec (cdr vec))) |
3632 (delete-char -1) | |
3633 ;; | |
3634 ))))) | |
3635 | |
3636 (defun verilog-strip-comments () | |
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diff
changeset
|
3637 "Strip all comments from the Verilog code." |
79545 | 3638 (interactive) |
3639 (goto-char (point-min)) | |
3640 (while (re-search-forward "//" nil t) | |
3641 (if (verilog-within-string) | |
3642 (re-search-forward "\"" nil t) | |
3643 (if (verilog-in-star-comment-p) | |
3644 (re-search-forward "\*/" nil t) | |
3645 (let ((bpt (- (point) 2))) | |
3646 (end-of-line) | |
3647 (delete-region bpt (point)))))) | |
3648 ;; | |
3649 (goto-char (point-min)) | |
3650 (while (re-search-forward "/\\*" nil t) | |
3651 (if (verilog-within-string) | |
3652 (re-search-forward "\"" nil t) | |
3653 (let ((bpt (- (point) 2))) | |
3654 (re-search-forward "\\*/") | |
3655 (delete-region bpt (point)))))) | |
3656 | |
3657 (defun verilog-one-line () | |
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diff
changeset
|
3658 "Convert structural Verilog instances to occupy one line." |
79545 | 3659 (interactive) |
3660 (goto-char (point-min)) | |
3661 (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t) | |
3662 (replace-match "\\1 " nil nil))) | |
3663 | |
3664 (defun verilog-linter-name () | |
3665 "Return name of linter, either surelint or verilint." | |
3666 (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil | |
3667 compile-command)) | |
3668 (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil | |
3669 verilog-linter))) | |
3670 (cond ((equal compile-word1 "surelint") `surelint) | |
3671 ((equal compile-word1 "verilint") `verilint) | |
3672 ((equal lint-word1 "surelint") `surelint) | |
3673 ((equal lint-word1 "verilint") `verilint) | |
3674 (t `surelint)))) ;; back compatibility | |
3675 | |
3676 (defun verilog-lint-off () | |
3677 "Convert a Verilog linter warning line into a disable statement. | |
3678 For example: | |
3679 pci_bfm_null.v, line 46: Unused input: pci_rst_ | |
3680 becomes a comment for the appropriate tool. | |
3681 | |
3682 The first word of the `compile-command' or `verilog-linter' | |
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diff
changeset
|
3683 variables is used to determine which product is being used. |
79545 | 3684 |
3685 See \\[verilog-surelint-off] and \\[verilog-verilint-off]." | |
3686 (interactive) | |
3687 (let ((linter (verilog-linter-name))) | |
3688 (cond ((equal linter `surelint) | |
3689 (verilog-surelint-off)) | |
3690 ((equal linter `verilint) | |
3691 (verilog-verilint-off)) | |
3692 (t (error "Linter name not set"))))) | |
3693 | |
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|
3694 (defvar compilation-last-buffer) |
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diff
changeset
|
3695 |
79545 | 3696 (defun verilog-surelint-off () |
3697 "Convert a SureLint warning line into a disable statement. | |
3698 Run from Verilog source window; assumes there is a *compile* buffer | |
3699 with point set appropriately. | |
3700 | |
3701 For example: | |
3702 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned. | |
3703 becomes: | |
3704 // surefire lint_line_off UDDONX" | |
3705 (interactive) | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3706 (let ((buff (if (boundp 'next-error-last-buffer) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3707 next-error-last-buffer |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3708 compilation-last-buffer))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3709 (when (buffer-live-p buff) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3710 ;; FIXME with-current-buffer? |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3711 (save-excursion |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3712 (switch-to-buffer buff) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3713 (beginning-of-line) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3714 (when |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3715 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$") |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3716 (let* ((code (match-string 2)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3717 (file (match-string 3)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3718 (line (match-string 4)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3719 (buffer (get-file-buffer file)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3720 dir filename) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3721 (unless buffer |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3722 (progn |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3723 (setq buffer |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3724 (and (file-exists-p file) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3725 (find-file-noselect file))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3726 (or buffer |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3727 (let* ((pop-up-windows t)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3728 (let ((name (expand-file-name |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3729 (read-file-name |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3730 (format "Find this error in: (default %s) " |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3731 file) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3732 dir file t)))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3733 (if (file-directory-p name) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3734 (setq name (expand-file-name filename name))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3735 (setq buffer |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3736 (and (file-exists-p name) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3737 (find-file-noselect name)))))))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3738 (switch-to-buffer buffer) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3739 (goto-line (string-to-number line)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3740 (end-of-line) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3741 (catch 'already |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3742 (cond |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3743 ((verilog-in-slash-comment-p) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3744 (re-search-backward "//") |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3745 (cond |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3746 ((looking-at "// surefire lint_off_line ") |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3747 (goto-char (match-end 0)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3748 (let ((lim (save-excursion (end-of-line) (point)))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3749 (if (re-search-forward code lim 'move) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3750 (throw 'already t) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3751 (insert (concat " " code))))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3752 (t |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3753 ))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3754 ((verilog-in-star-comment-p) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3755 (re-search-backward "/\*") |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3756 (insert (format " // surefire lint_off_line %6s" code ))) |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3757 (t |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3758 (insert (format " // surefire lint_off_line %6s" code )) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3759 ))))))))) |
79545 | 3760 |
3761 (defun verilog-verilint-off () | |
3762 "Convert a Verilint warning line into a disable statement. | |
3763 | |
3764 For example: | |
3765 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_ | |
3766 becomes: | |
3767 //Verilint 240 off // WARNING: Unused input" | |
3768 (interactive) | |
3769 (save-excursion | |
3770 (beginning-of-line) | |
3771 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$") | |
3772 (replace-match (format | |
3773 ;; %3s makes numbers 1-999 line up nicely | |
3774 "\\1//Verilint %3s off // WARNING: \\3" | |
3775 (match-string 2))) | |
3776 (beginning-of-line) | |
3777 (verilog-indent-line)))) | |
3778 | |
3779 (defun verilog-auto-save-compile () | |
3780 "Update automatics with \\[verilog-auto], save the buffer, and compile." | |
3781 (interactive) | |
3782 (verilog-auto) ; Always do it for safety | |
3783 (save-buffer) | |
3784 (compile compile-command)) | |
3785 | |
3786 | |
3787 | |
3788 ;; | |
3789 ;; Batch | |
3790 ;; | |
3791 | |
3792 (defmacro verilog-batch-error-wrapper (&rest body) | |
3793 "Execute BODY and add error prefix to any errors found. | |
3794 This lets programs calling batch mode to easily extract error messages." | |
79546 | 3795 `(condition-case err |
3796 (progn ,@body) | |
3797 (error | |
3798 (error "%%Error: %s%s" (error-message-string err) | |
3799 (if (featurep 'xemacs) "\n" ""))))) ;; xemacs forgets to add a newline | |
79545 | 3800 |
3801 (defun verilog-batch-execute-func (funref) | |
3802 "Internal processing of a batch command, running FUNREF on all command arguments." | |
3803 (verilog-batch-error-wrapper | |
3804 ;; General globals needed | |
3805 (setq make-backup-files nil) | |
3806 (setq-default make-backup-files nil) | |
3807 (setq enable-local-variables t) | |
3808 (setq enable-local-eval t) | |
3809 ;; Make sure any sub-files we read get proper mode | |
3810 (setq default-major-mode `verilog-mode) | |
3811 ;; Ditto files already read in | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3812 (mapc (lambda (buf) |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3813 (when (buffer-file-name buf) |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3814 (save-excursion |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3815 (set-buffer buf) |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3816 (verilog-mode)))) |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3817 (buffer-list)) |
79545 | 3818 ;; Process the files |
3819 (mapcar '(lambda (buf) | |
3820 (when (buffer-file-name buf) | |
3821 (save-excursion | |
3822 (if (not (file-exists-p (buffer-file-name buf))) | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3823 (error |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3824 (concat "File not found: " (buffer-file-name buf)))) |
79545 | 3825 (message (concat "Processing " (buffer-file-name buf))) |
3826 (set-buffer buf) | |
3827 (funcall funref) | |
3828 (save-buffer)))) | |
3829 (buffer-list)))) | |
3830 | |
3831 (defun verilog-batch-auto () | |
3832 "For use with --batch, perform automatic expansions as a stand-alone tool. | |
80165
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
3833 This sets up the appropriate Verilog mode environment, updates automatics |
79545 | 3834 with \\[verilog-auto] on all command-line files, and saves the buffers. |
3835 For proper results, multiple filenames need to be passed on the command | |
3836 line in bottom-up order." | |
3837 (unless noninteractive | |
3838 (error "Use verilog-batch-auto only with --batch")) ;; Otherwise we'd mess up buffer modes | |
3839 (verilog-batch-execute-func `verilog-auto)) | |
3840 | |
3841 (defun verilog-batch-delete-auto () | |
3842 "For use with --batch, perform automatic deletion as a stand-alone tool. | |
80165
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
3843 This sets up the appropriate Verilog mode environment, deletes automatics |
79545 | 3844 with \\[verilog-delete-auto] on all command-line files, and saves the buffers." |
3845 (unless noninteractive | |
3846 (error "Use verilog-batch-delete-auto only with --batch")) ;; Otherwise we'd mess up buffer modes | |
3847 (verilog-batch-execute-func `verilog-delete-auto)) | |
3848 | |
3849 (defun verilog-batch-inject-auto () | |
3850 "For use with --batch, perform automatic injection as a stand-alone tool. | |
80165
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
3851 This sets up the appropriate Verilog mode environment, injects new automatics |
79545 | 3852 with \\[verilog-inject-auto] on all command-line files, and saves the buffers. |
3853 For proper results, multiple filenames need to be passed on the command | |
3854 line in bottom-up order." | |
3855 (unless noninteractive | |
3856 (error "Use verilog-batch-inject-auto only with --batch")) ;; Otherwise we'd mess up buffer modes | |
3857 (verilog-batch-execute-func `verilog-inject-auto)) | |
3858 | |
3859 (defun verilog-batch-indent () | |
3860 "For use with --batch, reindent an a entire file as a stand-alone tool. | |
80165
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
3861 This sets up the appropriate Verilog mode environment, calls |
79545 | 3862 \\[verilog-indent-buffer] on all command-line files, and saves the buffers." |
3863 (unless noninteractive | |
3864 (error "Use verilog-batch-indent only with --batch")) ;; Otherwise we'd mess up buffer modes | |
3865 (verilog-batch-execute-func `verilog-indent-buffer)) | |
3866 | |
3867 | |
3868 ;; | |
3869 ;; Indentation | |
3870 ;; | |
3871 (defconst verilog-indent-alist | |
3872 '((block . (+ ind verilog-indent-level)) | |
3873 (case . (+ ind verilog-case-indent)) | |
3874 (cparenexp . (+ ind verilog-indent-level)) | |
3875 (cexp . (+ ind verilog-cexp-indent)) | |
3876 (defun . verilog-indent-level-module) | |
3877 (declaration . verilog-indent-level-declaration) | |
3878 (directive . (verilog-calculate-indent-directive)) | |
3879 (tf . verilog-indent-level) | |
3880 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module)) | |
3881 (statement . ind) | |
3882 (cpp . 0) | |
3883 (comment . (verilog-comment-indent)) | |
3884 (unknown . 3) | |
3885 (string . 0))) | |
3886 | |
3887 (defun verilog-continued-line-1 (lim) | |
3888 "Return true if this is a continued line. | |
3889 Set point to where line starts. Limit search to point LIM." | |
3890 (let ((continued 't)) | |
3891 (if (eq 0 (forward-line -1)) | |
3892 (progn | |
3893 (end-of-line) | |
3894 (verilog-backward-ws&directives lim) | |
3895 (if (bobp) | |
3896 (setq continued nil) | |
3897 (setq continued (verilog-backward-token)))) | |
3898 (setq continued nil)) | |
3899 continued)) | |
3900 | |
3901 (defun verilog-calculate-indent () | |
3902 "Calculate the indent of the current Verilog line. | |
3903 Examine previous lines. Once a line is found that is definitive as to the | |
80165
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
3904 type of the current line, return that lines' indent level and its type. |
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
3905 Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)." |
79545 | 3906 (save-excursion |
3907 (let* ((starting_position (point)) | |
3908 (par 0) | |
3909 (begin (looking-at "[ \t]*begin\\>")) | |
3910 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t))) | |
3911 (type (catch 'nesting | |
3912 ;; Keep working backwards until we can figure out | |
3913 ;; what type of statement this is. | |
3914 ;; Basically we need to figure out | |
3915 ;; 1) if this is a continuation of the previous line; | |
3916 ;; 2) are we in a block scope (begin..end) | |
3917 | |
3918 ;; if we are in a comment, done. | |
3919 (if (verilog-in-star-comment-p) | |
3920 (throw 'nesting 'comment)) | |
3921 | |
3922 ;; if we have a directive, done. | |
3923 (if (save-excursion (beginning-of-line) (looking-at verilog-directive-re-1)) | |
3924 (throw 'nesting 'directive)) | |
3925 | |
3926 ;; unless we are in the newfangled coverpoint or constraint blocks | |
3927 ;; if we are in a parenthesized list, and the user likes to indent these, return. | |
3928 (if (and | |
3929 verilog-indent-lists | |
3930 (not (verilog-in-coverage)) | |
3931 (verilog-in-paren)) | |
3932 (progn (setq par 1) | |
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parents:
79717
diff
changeset
|
3933 (throw 'nesting 'block))) |
79545 | 3934 |
3935 ;; See if we are continuing a previous line | |
3936 (while t | |
3937 ;; trap out if we crawl off the top of the buffer | |
3938 (if (bobp) (throw 'nesting 'cpp)) | |
3939 | |
3940 (if (verilog-continued-line-1 lim) | |
3941 (let ((sp (point))) | |
3942 (if (and | |
3943 (not (looking-at verilog-complete-reg)) | |
3944 (verilog-continued-line-1 lim)) | |
3945 (progn (goto-char sp) | |
3946 (throw 'nesting 'cexp)) | |
3947 | |
3948 (goto-char sp)) | |
3949 | |
3950 (if (and begin | |
3951 (not verilog-indent-begin-after-if) | |
3952 (looking-at verilog-no-indent-begin-re)) | |
3953 (progn | |
3954 (beginning-of-line) | |
3955 (skip-chars-forward " \t") | |
3956 (throw 'nesting 'statement)) | |
3957 (progn | |
3958 (throw 'nesting 'cexp)))) | |
3959 ;; not a continued line | |
3960 (goto-char starting_position)) | |
3961 | |
3962 (if (looking-at "\\<else\\>") | |
3963 ;; search back for governing if, striding across begin..end pairs | |
3964 ;; appropriately | |
3965 (let ((elsec 1)) | |
3966 (while (verilog-re-search-backward verilog-ends-re nil 'move) | |
3967 (cond | |
3968 ((match-end 1) ; else, we're in deep | |
3969 (setq elsec (1+ elsec))) | |
3970 ((match-end 2) ; if | |
3971 (setq elsec (1- elsec)) | |
3972 (if (= 0 elsec) | |
3973 (if verilog-align-ifelse | |
3974 (throw 'nesting 'statement) | |
3975 (progn ;; back up to first word on this line | |
3976 (beginning-of-line) | |
3977 (verilog-forward-syntactic-ws) | |
3978 (throw 'nesting 'statement))))) | |
3979 (t ; endblock | |
3980 ; try to leap back to matching outward block by striding across | |
3981 ; indent level changing tokens then immediately | |
3982 ; previous line governs indentation. | |
3983 (let (( reg) (nest 1)) | |
3984 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup | |
3985 (cond | |
3986 ((match-end 3) ; end | |
3987 ;; Search back for matching begin | |
3988 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" )) | |
3989 ((match-end 4) ; endcase | |
3990 ;; Search back for matching case | |
3991 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )) | |
3992 ((match-end 5) ; endfunction | |
3993 ;; Search back for matching function | |
3994 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" )) | |
3995 ((match-end 6) ; endtask | |
3996 ;; Search back for matching task | |
3997 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" )) | |
3998 ((match-end 7) ; endspecify | |
3999 ;; Search back for matching specify | |
4000 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" )) | |
4001 ((match-end 8) ; endtable | |
4002 ;; Search back for matching table | |
4003 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" )) | |
4004 ((match-end 9) ; endgenerate | |
4005 ;; Search back for matching generate | |
4006 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" )) | |
4007 ((match-end 10) ; joins | |
4008 ;; Search back for matching fork | |
4009 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" )) | |
4010 ((match-end 11) ; class | |
4011 ;; Search back for matching class | |
4012 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" )) | |
4013 ((match-end 12) ; covergroup | |
4014 ;; Search back for matching covergroup | |
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parents:
79717
diff
changeset
|
4015 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))) |
79545 | 4016 (catch 'skip |
4017 (while (verilog-re-search-backward reg nil 'move) | |
4018 (cond | |
4019 ((match-end 1) ; begin | |
4020 (setq nest (1- nest)) | |
4021 (if (= 0 nest) | |
4022 (throw 'skip 1))) | |
4023 ((match-end 2) ; end | |
4024 (setq nest (1+ nest))))) | |
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parents:
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diff
changeset
|
4025 ))))))) |
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parents:
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diff
changeset
|
4026 (throw 'nesting (verilog-calc-1))) |
79545 | 4027 );; catch nesting |
4028 );; type | |
4029 ) | |
4030 ;; Return type of block and indent level. | |
4031 (if (not type) | |
4032 (setq type 'cpp)) | |
4033 (if (> par 0) ; Unclosed Parenthesis | |
4034 (list 'cparenexp par) | |
4035 (cond | |
4036 ((eq type 'case) | |
4037 (list type (verilog-case-indent-level))) | |
4038 ((eq type 'statement) | |
4039 (list type (current-column))) | |
4040 ((eq type 'defun) | |
4041 (list type 0)) | |
4042 (t | |
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parents:
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diff
changeset
|
4043 (list type (verilog-current-indent-level)))))))) |
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parents:
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diff
changeset
|
4044 |
79545 | 4045 (defun verilog-wai () |
4046 "Show matching nesting block for debugging." | |
4047 (interactive) | |
4048 (save-excursion | |
4049 (let ((nesting (verilog-calc-1))) | |
4050 (message "You are at nesting %s" nesting)))) | |
4051 | |
4052 (defun verilog-calc-1 () | |
4053 (catch 'nesting | |
4054 (while (verilog-re-search-backward (concat "\\({\\|}\\|" verilog-indent-re "\\)") nil 'move) | |
4055 (cond | |
4056 ((equal (char-after) ?\{) | |
4057 (if (verilog-at-constraint-p) | |
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parents:
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diff
changeset
|
4058 (throw 'nesting 'block))) |
79545 | 4059 ((equal (char-after) ?\}) |
4060 | |
4061 (let ((there (verilog-at-close-constraint-p))) | |
4062 (if there (goto-char there)))) | |
4063 | |
4064 ((looking-at verilog-beg-block-re-ordered) | |
4065 (cond | |
4066 ((match-end 2) ; *sigh* could be "unique case" or "priority casex" | |
4067 (let ((here (point))) | |
4068 (verilog-beg-of-statement) | |
4069 (if (looking-at verilog-extended-case-re) | |
4070 (throw 'nesting 'case) | |
4071 (goto-char here))) | |
4072 (throw 'nesting 'case)) | |
80171
97019d686b43
* progmodes/verilog-mode.el (verilog-xemacs-menu): Remove XEmacs
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80165
diff
changeset
|
4073 |
97019d686b43
* progmodes/verilog-mode.el (verilog-xemacs-menu): Remove XEmacs
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80165
diff
changeset
|
4074 ((match-end 4) ; *sigh* could be "disable fork" |
97019d686b43
* progmodes/verilog-mode.el (verilog-xemacs-menu): Remove XEmacs
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80165
diff
changeset
|
4075 (let ((here (point))) |
97019d686b43
* progmodes/verilog-mode.el (verilog-xemacs-menu): Remove XEmacs
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80165
diff
changeset
|
4076 (verilog-beg-of-statement) |
97019d686b43
* progmodes/verilog-mode.el (verilog-xemacs-menu): Remove XEmacs
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80165
diff
changeset
|
4077 (if (looking-at verilog-disable-fork-re) |
97019d686b43
* progmodes/verilog-mode.el (verilog-xemacs-menu): Remove XEmacs
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80165
diff
changeset
|
4078 t ; is disable fork, this is a normal statement |
97019d686b43
* progmodes/verilog-mode.el (verilog-xemacs-menu): Remove XEmacs
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80165
diff
changeset
|
4079 (progn ; or is fork, starts a new block |
97019d686b43
* progmodes/verilog-mode.el (verilog-xemacs-menu): Remove XEmacs
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80165
diff
changeset
|
4080 (goto-char here) |
97019d686b43
* progmodes/verilog-mode.el (verilog-xemacs-menu): Remove XEmacs
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80165
diff
changeset
|
4081 (throw 'nesting 'block))))) |
97019d686b43
* progmodes/verilog-mode.el (verilog-xemacs-menu): Remove XEmacs
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80165
diff
changeset
|
4082 |
79545 | 4083 |
4084 ;; need to consider typedef struct here... | |
4085 ((looking-at "\\<class\\|struct\\|function\\|task\\|property\\>") | |
4086 ; *sigh* These words have an optional prefix: | |
4087 ; extern {virtual|protected}? function a(); | |
4088 ; assert property (p_1); | |
4089 ; typedef class foo; | |
4090 ; and we don't want to confuse this with | |
4091 ; function a(); | |
4092 ; property | |
4093 ; ... | |
4094 ; endfunction | |
4095 (let ((here (point))) | |
4096 (save-excursion | |
4097 (verilog-beg-of-statement) | |
4098 (if (= (point) here) | |
79691
d3e3c91e18f6
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Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
4099 (throw 'nesting 'block))))) |
79545 | 4100 (t (throw 'nesting 'block)))) |
4101 | |
4102 ((looking-at verilog-end-block-re) | |
4103 (verilog-leap-to-head) | |
4104 (if (verilog-in-case-region-p) | |
4105 (progn | |
4106 (verilog-leap-to-case-head) | |
4107 (if (looking-at verilog-case-re) | |
4108 (throw 'nesting 'case))))) | |
4109 | |
4110 ((looking-at (if (verilog-in-generate-region-p) | |
4111 verilog-defun-level-not-generate-re | |
4112 verilog-defun-level-re)) | |
4113 (throw 'nesting 'defun)) | |
4114 | |
4115 ((looking-at verilog-cpp-level-re) | |
4116 (throw 'nesting 'cpp)) | |
4117 | |
4118 ((bobp) | |
79691
d3e3c91e18f6
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Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
4119 (throw 'nesting 'cpp)))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
4120 (throw 'nesting 'cpp))) |
79545 | 4121 |
4122 (defun verilog-calculate-indent-directive () | |
4123 "Return indentation level for directive. | |
4124 For speed, the searcher looks at the last directive, not the indent | |
4125 of the appropriate enclosing block." | |
4126 (let ((base -1) ;; Indent of the line that determines our indentation | |
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parents:
79717
diff
changeset
|
4127 (ind 0)) ;; Relative offset caused by other directives (like `endif on same line as `else) |
79545 | 4128 ;; Start at current location, scan back for another directive |
4129 | |
4130 (save-excursion | |
4131 (beginning-of-line) | |
4132 (while (and (< base 0) | |
4133 (verilog-re-search-backward verilog-directive-re nil t)) | |
4134 (cond ((save-excursion (skip-chars-backward " \t") (bolp)) | |
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parents:
79717
diff
changeset
|
4135 (setq base (current-indentation)))) |
79545 | 4136 (cond ((and (looking-at verilog-directive-end) (< base 0)) ;; Only matters when not at BOL |
4137 (setq ind (- ind verilog-indent-level-directive))) | |
4138 ((and (looking-at verilog-directive-middle) (>= base 0)) ;; Only matters when at BOL | |
4139 (setq ind (+ ind verilog-indent-level-directive))) | |
4140 ((looking-at verilog-directive-begin) | |
4141 (setq ind (+ ind verilog-indent-level-directive))))) | |
4142 ;; Adjust indent to starting indent of critical line | |
4143 (setq ind (max 0 (+ ind base)))) | |
4144 | |
4145 (save-excursion | |
4146 (beginning-of-line) | |
4147 (skip-chars-forward " \t") | |
4148 (cond ((or (looking-at verilog-directive-middle) | |
4149 (looking-at verilog-directive-end)) | |
4150 (setq ind (max 0 (- ind verilog-indent-level-directive)))))) | |
4151 ind)) | |
4152 | |
4153 (defun verilog-leap-to-case-head () | |
4154 (let ((nest 1)) | |
4155 (while (/= 0 nest) | |
4156 (verilog-re-search-backward "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" nil 'move) | |
4157 (cond | |
4158 ((match-end 1) | |
4159 (setq nest (1- nest))) | |
4160 ((match-end 2) | |
4161 (setq nest (1+ nest))) | |
4162 ((bobp) | |
4163 (ding 't) | |
4164 (setq nest 0)))))) | |
4165 | |
4166 (defun verilog-leap-to-head () | |
80165
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
4167 "Move point to the head of this block. |
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
4168 Jump from end to matching begin, from endcase to matching case, and so on." |
79545 | 4169 (let ((reg nil) |
4170 snest | |
4171 (nest 1)) | |
4172 (cond | |
4173 ((looking-at "\\<end\\>") | |
4174 ;; 1: Search back for matching begin | |
4175 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|" | |
4176 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))) | |
4177 ((looking-at "\\<endcase\\>") | |
4178 ;; 2: Search back for matching case | |
4179 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)" )) | |
4180 ((looking-at "\\<join\\(_any\\|_none\\)?\\>") | |
4181 ;; 3: Search back for matching fork | |
4182 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )) | |
4183 ((looking-at "\\<endclass\\>") | |
4184 ;; 4: Search back for matching class | |
4185 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" )) | |
4186 ((looking-at "\\<endtable\\>") | |
4187 ;; 5: Search back for matching table | |
4188 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" )) | |
4189 ((looking-at "\\<endspecify\\>") | |
4190 ;; 6: Search back for matching specify | |
4191 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" )) | |
4192 ((looking-at "\\<endfunction\\>") | |
4193 ;; 7: Search back for matching function | |
4194 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" )) | |
4195 ((looking-at "\\<endgenerate\\>") | |
4196 ;; 8: Search back for matching generate | |
4197 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" )) | |
4198 ((looking-at "\\<endtask\\>") | |
4199 ;; 9: Search back for matching task | |
4200 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" )) | |
4201 ((looking-at "\\<endgroup\\>") | |
4202 ;; 10: Search back for matching covergroup | |
4203 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )) | |
4204 ((looking-at "\\<endproperty\\>") | |
4205 ;; 11: Search back for matching property | |
4206 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" )) | |
4207 ((looking-at "\\<endinterface\\>") | |
4208 ;; 12: Search back for matching interface | |
4209 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" )) | |
4210 ((looking-at "\\<endsequence\\>") | |
4211 ;; 12: Search back for matching sequence | |
4212 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )) | |
4213 ((looking-at "\\<endclocking\\>") | |
4214 ;; 12: Search back for matching clocking | |
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parents:
79717
diff
changeset
|
4215 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" ))) |
79545 | 4216 (if reg |
4217 (catch 'skip | |
4218 (let (sreg) | |
4219 (while (verilog-re-search-backward reg nil 'move) | |
4220 (cond | |
4221 ((match-end 1) ; begin | |
4222 (setq nest (1- nest)) | |
4223 (if (= 0 nest) | |
4224 ;; Now previous line describes syntax | |
4225 (throw 'skip 1)) | |
4226 (if (and snest | |
4227 (= snest nest)) | |
4228 (setq reg sreg))) | |
4229 ((match-end 2) ; end | |
4230 (setq nest (1+ nest))) | |
4231 ((match-end 3) | |
4232 ;; endcase, jump to case | |
4233 (setq snest nest) | |
4234 (setq nest (1+ nest)) | |
4235 (setq sreg reg) | |
4236 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )) | |
4237 ((match-end 4) | |
4238 ;; join, jump to fork | |
4239 (setq snest nest) | |
4240 (setq nest (1+ nest)) | |
4241 (setq sreg reg) | |
4242 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )) | |
4243 ))))))) | |
4244 | |
4245 (defun verilog-continued-line () | |
4246 "Return true if this is a continued line. | |
80165
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
4247 Set point to where line starts." |
79545 | 4248 (let ((continued 't)) |
4249 (if (eq 0 (forward-line -1)) | |
4250 (progn | |
4251 (end-of-line) | |
4252 (verilog-backward-ws&directives) | |
4253 (if (bobp) | |
4254 (setq continued nil) | |
4255 (while (and continued | |
4256 (save-excursion | |
4257 (skip-chars-backward " \t") | |
4258 (not (bolp)))) | |
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(top-level): Fix spacing.
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parents:
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diff
changeset
|
4259 (setq continued (verilog-backward-token))))) |
79545 | 4260 (setq continued nil)) |
4261 continued)) | |
4262 | |
4263 (defun verilog-backward-token () | |
4264 "Step backward token, returning true if we are now at an end of line token." | |
4265 (interactive) | |
4266 (verilog-backward-syntactic-ws) | |
4267 (cond | |
4268 ((bolp) | |
4269 nil) | |
4270 (;-- Anything ending in a ; is complete | |
4271 (= (preceding-char) ?\;) | |
4272 nil) | |
4273 (; If a "}" is prefixed by a ";", then this is a complete statement | |
4274 ; i.e.: constraint foo { a = b; } | |
4275 (= (preceding-char) ?\}) | |
4276 (progn | |
4277 (backward-char) | |
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(top-level): Fix spacing.
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parents:
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diff
changeset
|
4278 (verilog-at-close-constraint-p))) |
79545 | 4279 (;-- constraint foo { a = b } |
4280 ; is a complete statement. *sigh* | |
4281 (= (preceding-char) ?\{) | |
4282 (progn | |
4283 (backward-char) | |
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(top-level): Fix spacing.
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parents:
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diff
changeset
|
4284 (not (verilog-at-constraint-p)))) |
79545 | 4285 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete |
4286 ; also could be simply '@(foo)' | |
4287 ; or foo u1 #(a=8) | |
4288 ; (b, ... which ISN'T complete | |
4289 ;;;; Do we need this??? | |
4290 (= (preceding-char) ?\)) | |
4291 (progn | |
4292 (backward-char) | |
4293 (backward-up-list 1) | |
4294 (verilog-backward-syntactic-ws) | |
4295 (let ((back (point))) | |
4296 (forward-word -1) | |
4297 (cond | |
4298 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>") | |
4299 (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]"))) | |
4300 (t | |
4301 (goto-char back) | |
4302 (cond | |
4303 ((= (preceding-char) ?\@) | |
4304 (backward-char) | |
4305 (save-excursion | |
4306 (verilog-backward-token) | |
4307 (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>")))) | |
4308 ((= (preceding-char) ?\#) | |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4309 (backward-char)) |
57956dd69d3f
(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
4310 (t t))))))) |
79545 | 4311 |
4312 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete | |
4313 t | |
4314 (forward-word -1) | |
4315 (cond | |
4316 ((looking-at "\\<else\\>") | |
4317 t) | |
80171
97019d686b43
* progmodes/verilog-mode.el (verilog-xemacs-menu): Remove XEmacs
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80165
diff
changeset
|
4318 ((looking-at verilog-behavioral-block-beg-re) |
97019d686b43
* progmodes/verilog-mode.el (verilog-xemacs-menu): Remove XEmacs
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80165
diff
changeset
|
4319 t) |
79545 | 4320 ((looking-at verilog-indent-re) |
4321 nil) | |
4322 (t | |
4323 (let | |
4324 ((back (point))) | |
4325 (verilog-backward-syntactic-ws) | |
4326 (cond | |
4327 ((= (preceding-char) ?\:) | |
4328 (backward-char) | |
4329 (verilog-backward-syntactic-ws) | |
4330 (backward-sexp) | |
4331 (if (looking-at verilog-nameable-item-re ) | |
4332 nil | |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4333 t)) |
79545 | 4334 ((= (preceding-char) ?\#) |
4335 (backward-char) | |
4336 t) | |
4337 ((= (preceding-char) ?\`) | |
4338 (backward-char) | |
4339 t) | |
4340 | |
4341 (t | |
4342 (goto-char back) | |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4343 t)))))))) |
79545 | 4344 |
4345 (defun verilog-backward-syntactic-ws (&optional bound) | |
4346 "Backward skip over syntactic whitespace for Emacs 19. | |
4347 Optional BOUND limits search." | |
4348 (save-restriction | |
4349 (let* ((bound (or bound (point-min))) (here bound) ) | |
4350 (if (< bound (point)) | |
4351 (progn | |
4352 (narrow-to-region bound (point)) | |
4353 (while (/= here (point)) | |
4354 (setq here (point)) | |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4355 (verilog-skip-backward-comments)))))) |
79545 | 4356 t) |
4357 | |
4358 (defun verilog-forward-syntactic-ws (&optional bound) | |
4359 "Forward skip over syntactic whitespace for Emacs 19. | |
4360 Optional BOUND limits search." | |
4361 (save-restriction | |
4362 (let* ((bound (or bound (point-max))) | |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4363 (here bound)) |
79545 | 4364 (if (> bound (point)) |
4365 (progn | |
4366 (narrow-to-region (point) bound) | |
4367 (while (/= here (point)) | |
4368 (setq here (point)) | |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4369 (forward-comment (buffer-size)))))))) |
79545 | 4370 |
4371 (defun verilog-backward-ws&directives (&optional bound) | |
4372 "Backward skip over syntactic whitespace and compiler directives for Emacs 19. | |
4373 Optional BOUND limits search." | |
4374 (save-restriction | |
4375 (let* ((bound (or bound (point-min))) | |
4376 (here bound) | |
4377 (p nil) ) | |
4378 (if (< bound (point)) | |
4379 (progn | |
4380 (let ((state | |
4381 (save-excursion | |
4382 (parse-partial-sexp (point-min) (point))))) | |
4383 (cond | |
4384 ((nth 7 state) ;; in // comment | |
4385 (verilog-re-search-backward "//" nil 'move) | |
4386 (skip-chars-backward "/")) | |
4387 ((nth 4 state) ;; in /* */ comment | |
4388 (verilog-re-search-backward "/\*" nil 'move)))) | |
4389 (narrow-to-region bound (point)) | |
4390 (while (/= here (point)) | |
4391 (setq here (point)) | |
4392 (verilog-skip-backward-comments) | |
4393 (setq p | |
4394 (save-excursion | |
4395 (beginning-of-line) | |
4396 (cond | |
4397 ((verilog-within-translate-off) | |
4398 (verilog-back-to-start-translate-off (point-min))) | |
4399 ((looking-at verilog-directive-re-1) | |
4400 (point)) | |
4401 (t | |
4402 nil)))) | |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4403 (if p (goto-char p)))))))) |
79545 | 4404 |
4405 (defun verilog-forward-ws&directives (&optional bound) | |
4406 "Forward skip over syntactic whitespace and compiler directives for Emacs 19. | |
4407 Optional BOUND limits search." | |
4408 (save-restriction | |
4409 (let* ((bound (or bound (point-max))) | |
4410 (here bound) | |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4411 jump) |
79545 | 4412 (if (> bound (point)) |
4413 (progn | |
4414 (let ((state | |
4415 (save-excursion | |
4416 (parse-partial-sexp (point-min) (point))))) | |
4417 (cond | |
4418 ((nth 7 state) ;; in // comment | |
4419 (verilog-re-search-forward "//" nil 'move)) | |
4420 ((nth 4 state) ;; in /* */ comment | |
4421 (verilog-re-search-forward "/\*" nil 'move)))) | |
4422 (narrow-to-region (point) bound) | |
4423 (while (/= here (point)) | |
4424 (setq here (point) | |
4425 jump nil) | |
4426 (forward-comment (buffer-size)) | |
4427 (save-excursion | |
4428 (beginning-of-line) | |
4429 (if (looking-at verilog-directive-re-1) | |
4430 (setq jump t))) | |
4431 (if jump | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4432 (beginning-of-line 2)))))))) |
79545 | 4433 |
4434 (defun verilog-in-comment-p () | |
4435 "Return true if in a star or // comment." | |
4436 (let ((state | |
4437 (save-excursion | |
4438 (parse-partial-sexp (point-min) (point))))) | |
4439 (or (nth 4 state) (nth 7 state)))) | |
4440 | |
4441 (defun verilog-in-star-comment-p () | |
4442 "Return true if in a star comment." | |
4443 (let ((state | |
4444 (save-excursion | |
4445 (parse-partial-sexp (point-min) (point))))) | |
4446 (and | |
4447 (nth 4 state) ; t if in a comment of style a // or b /**/ | |
4448 (not | |
4449 (nth 7 state) ; t if in a comment of style b /**/ | |
4450 )))) | |
4451 | |
4452 (defun verilog-in-slash-comment-p () | |
4453 "Return true if in a slash comment." | |
4454 (let ((state | |
4455 (save-excursion | |
4456 (parse-partial-sexp (point-min) (point))))) | |
4457 (nth 7 state))) | |
4458 | |
4459 (defun verilog-in-comment-or-string-p () | |
4460 "Return true if in a string or comment." | |
4461 (let ((state | |
4462 (save-excursion | |
4463 (parse-partial-sexp (point-min) (point))))) | |
4464 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment) | |
4465 | |
4466 (defun verilog-in-escaped-name-p () | |
4467 "Return true if in an escaped name." | |
4468 (save-excursion | |
4469 (backward-char) | |
4470 (skip-chars-backward "^ \t\n\f") | |
4471 (if (equal (char-after (point) ) ?\\ ) | |
4472 t | |
4473 nil))) | |
4474 | |
4475 (defun verilog-in-paren () | |
4476 "Return true if in a parenthetical expression." | |
4477 (let ((state | |
4478 (save-excursion | |
4479 (parse-partial-sexp (point-min) (point))))) | |
4480 (> (nth 0 state) 0 ))) | |
4481 | |
4482 (defun verilog-in-coverage () | |
4483 "Return true if in a constraint or coverpoint expression." | |
4484 (interactive) | |
4485 (save-excursion | |
4486 (if (verilog-in-paren) | |
4487 (progn | |
4488 (backward-up-list 1) | |
4489 (verilog-at-constraint-p) | |
4490 ) | |
4491 nil))) | |
4492 (defun verilog-at-close-constraint-p () | |
4493 "If at the } that closes a constraint or covergroup, return true." | |
4494 (if (and | |
4495 (equal (char-after) ?\}) | |
4496 (verilog-in-paren)) | |
4497 | |
4498 (save-excursion | |
4499 (verilog-backward-ws&directives) | |
4500 (if (equal (char-before) ?\;) | |
4501 (point) | |
4502 nil)))) | |
4503 | |
4504 (defun verilog-at-constraint-p () | |
4505 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint." | |
4506 (if (save-excursion | |
4507 (and | |
4508 (equal (char-after) ?\{) | |
4509 (forward-list) | |
4510 (progn (backward-char 1) | |
4511 (verilog-backward-ws&directives) | |
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parents:
79717
diff
changeset
|
4512 (equal (char-before) ?\;)))) |
79545 | 4513 ;; maybe |
4514 (verilog-re-search-backward "\\<constraint\\|coverpoint\\|cross\\>" nil 'move) | |
4515 ;; not | |
79799
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parents:
79717
diff
changeset
|
4516 nil)) |
79545 | 4517 |
4518 (defun verilog-parenthesis-depth () | |
4519 "Return non zero if in parenthetical-expression." | |
4520 (save-excursion | |
4521 (nth 1 (parse-partial-sexp (point-min) (point))))) | |
4522 | |
4523 | |
4524 (defun verilog-skip-forward-comment-or-string () | |
4525 "Return true if in a string or comment." | |
4526 (let ((state | |
4527 (save-excursion | |
4528 (parse-partial-sexp (point-min) (point))))) | |
4529 (cond | |
4530 ((nth 3 state) ;Inside string | |
80355
35dfb85c0e6b
(verilog-easy-menu-filter): New function.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80342
diff
changeset
|
4531 (search-forward "\"") |
79545 | 4532 t) |
4533 ((nth 7 state) ;Inside // comment | |
4534 (forward-line 1) | |
4535 t) | |
4536 ((nth 4 state) ;Inside any comment (hence /**/) | |
4537 (search-forward "*/")) | |
4538 (t | |
4539 nil)))) | |
4540 | |
4541 (defun verilog-skip-backward-comment-or-string () | |
4542 "Return true if in a string or comment." | |
4543 (let ((state | |
4544 (save-excursion | |
4545 (parse-partial-sexp (point-min) (point))))) | |
4546 (cond | |
4547 ((nth 3 state) ;Inside string | |
4548 (search-backward "\"") | |
4549 t) | |
4550 ((nth 7 state) ;Inside // comment | |
4551 (search-backward "//") | |
4552 (skip-chars-backward "/") | |
4553 t) | |
4554 ((nth 4 state) ;Inside /* */ comment | |
4555 (search-backward "/*") | |
4556 t) | |
4557 (t | |
4558 nil)))) | |
4559 | |
4560 (defun verilog-skip-backward-comments () | |
4561 "Return true if a comment was skipped." | |
4562 (let ((more t)) | |
4563 (while more | |
4564 (setq more | |
4565 (let ((state | |
4566 (save-excursion | |
4567 (parse-partial-sexp (point-min) (point))))) | |
4568 (cond | |
4569 ((nth 7 state) ;Inside // comment | |
4570 (search-backward "//") | |
4571 (skip-chars-backward "/") | |
4572 (skip-chars-backward " \t\n\f") | |
4573 t) | |
4574 ((nth 4 state) ;Inside /* */ comment | |
4575 (search-backward "/*") | |
4576 (skip-chars-backward " \t\n\f") | |
4577 t) | |
4578 ((and (not (bobp)) | |
4579 (= (char-before) ?\/) | |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4580 (= (char-before (1- (point))) ?\*)) |
79545 | 4581 (goto-char (- (point) 2)) |
4582 t) | |
4583 (t | |
4584 (skip-chars-backward " \t\n\f") | |
4585 nil))))))) | |
4586 | |
4587 (defun verilog-skip-forward-comment-p () | |
4588 "If in comment, move to end and return true." | |
4589 (let (state) | |
4590 (progn | |
4591 (setq state | |
4592 (save-excursion | |
4593 (parse-partial-sexp (point-min) (point)))) | |
4594 (cond | |
4595 ((nth 3 state) | |
4596 t) | |
4597 ((nth 7 state) ;Inside // comment | |
4598 (end-of-line) | |
4599 (forward-char 1) | |
4600 t) | |
4601 ((nth 4 state) ;Inside any comment | |
4602 t) | |
4603 (t | |
4604 nil))))) | |
4605 | |
4606 (defun verilog-indent-line-relative () | |
4607 "Cheap version of indent line. | |
4608 Only look at a few lines to determine indent level." | |
4609 (interactive) | |
4610 (let ((indent-str) | |
4611 (sp (point))) | |
4612 (if (looking-at "^[ \t]*$") | |
4613 (cond ;- A blank line; No need to be too smart. | |
4614 ((bobp) | |
4615 (setq indent-str (list 'cpp 0))) | |
4616 ((verilog-continued-line) | |
4617 (let ((sp1 (point))) | |
4618 (if (verilog-continued-line) | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
4619 (progn |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
4620 (goto-char sp) |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4621 (setq indent-str |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4622 (list 'statement (verilog-current-indent-level)))) |
79545 | 4623 (goto-char sp1) |
4624 (setq indent-str (list 'block (verilog-current-indent-level))))) | |
4625 (goto-char sp)) | |
4626 ((goto-char sp) | |
4627 (setq indent-str (verilog-calculate-indent)))) | |
4628 (progn (skip-chars-forward " \t") | |
4629 (setq indent-str (verilog-calculate-indent)))) | |
4630 (verilog-do-indent indent-str))) | |
4631 | |
4632 (defun verilog-indent-line () | |
4633 "Indent for special part of code." | |
4634 (verilog-do-indent (verilog-calculate-indent))) | |
4635 | |
4636 (defun verilog-do-indent (indent-str) | |
4637 (let ((type (car indent-str)) | |
4638 (ind (car (cdr indent-str)))) | |
4639 (cond | |
4640 (; handle continued exp | |
4641 (eq type 'cexp) | |
4642 (let ((here (point))) | |
4643 (verilog-backward-syntactic-ws) | |
4644 (cond | |
4645 ((or | |
4646 (= (preceding-char) ?\,) | |
4647 (= (preceding-char) ?\]) | |
4648 (save-excursion | |
4649 (verilog-beg-of-statement-1) | |
4650 (looking-at verilog-declaration-re))) | |
4651 (let* ( fst | |
4652 (val | |
4653 (save-excursion | |
4654 (backward-char 1) | |
4655 (verilog-beg-of-statement-1) | |
4656 (setq fst (point)) | |
4657 (if (looking-at verilog-declaration-re) | |
4658 (progn ;; we have multiple words | |
4659 (goto-char (match-end 0)) | |
4660 (skip-chars-forward " \t") | |
4661 (cond | |
4662 ((and verilog-indent-declaration-macros | |
4663 (= (following-char) ?\`)) | |
4664 (progn | |
4665 (forward-char 1) | |
4666 (forward-word 1) | |
4667 (skip-chars-forward " \t"))) | |
4668 ((= (following-char) ?\[) | |
4669 (progn | |
4670 (forward-char 1) | |
4671 (backward-up-list -1) | |
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4672 (skip-chars-forward " \t")))) |
79545 | 4673 (current-column)) |
4674 (progn | |
4675 (goto-char fst) | |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4676 (+ (current-column) verilog-cexp-indent)))))) |
79545 | 4677 (goto-char here) |
79799
57956dd69d3f
(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
4678 (indent-line-to val))) |
79545 | 4679 ((= (preceding-char) ?\) ) |
4680 (goto-char here) | |
4681 (let ((val (eval (cdr (assoc type verilog-indent-alist))))) | |
4682 (indent-line-to val))) | |
4683 (t | |
4684 (goto-char here) | |
4685 (let ((val)) | |
4686 (verilog-beg-of-statement-1) | |
4687 (if (and (< (point) here) | |
4688 (verilog-re-search-forward "=[ \\t]*" here 'move)) | |
4689 (setq val (current-column)) | |
4690 (setq val (eval (cdr (assoc type verilog-indent-alist))))) | |
4691 (goto-char here) | |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4692 (indent-line-to val)))))) |
79545 | 4693 |
4694 (; handle inside parenthetical expressions | |
4695 (eq type 'cparenexp) | |
4696 (let ((val (save-excursion | |
4697 (backward-up-list 1) | |
4698 (forward-char 1) | |
4699 (skip-chars-forward " \t") | |
4700 (current-column)))) | |
4701 (indent-line-to val) | |
4702 (if (and (not (verilog-in-struct-region-p)) | |
4703 (looking-at verilog-declaration-re)) | |
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4704 (verilog-indent-declaration ind)))) |
79545 | 4705 |
4706 (;-- Handle the ends | |
4707 (or | |
4708 (looking-at verilog-end-block-re ) | |
4709 (verilog-at-close-constraint-p)) | |
4710 (let ((val (if (eq type 'statement) | |
4711 (- ind verilog-indent-level) | |
4712 ind))) | |
4713 (indent-line-to val))) | |
4714 | |
4715 (;-- Case -- maybe line 'em up | |
4716 (and (eq type 'case) (not (looking-at "^[ \t]*$"))) | |
4717 (progn | |
4718 (cond | |
4719 ((looking-at "\\<endcase\\>") | |
4720 (indent-line-to ind)) | |
4721 (t | |
4722 (let ((val (eval (cdr (assoc type verilog-indent-alist))))) | |
4723 (indent-line-to val)))))) | |
4724 | |
4725 (;-- defun | |
4726 (and (eq type 'defun) | |
4727 (looking-at verilog-zero-indent-re)) | |
4728 (indent-line-to 0)) | |
4729 | |
4730 (;-- declaration | |
4731 (and (or | |
4732 (eq type 'defun) | |
4733 (eq type 'block)) | |
4734 (looking-at verilog-declaration-re)) | |
4735 (verilog-indent-declaration ind)) | |
4736 | |
4737 (;-- Everything else | |
4738 t | |
4739 (let ((val (eval (cdr (assoc type verilog-indent-alist))))) | |
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(top-level): Fix spacing.
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parents:
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diff
changeset
|
4740 (indent-line-to val)))) |
57956dd69d3f
(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
4741 |
79545 | 4742 (if (looking-at "[ \t]+$") |
4743 (skip-chars-forward " \t")) | |
4744 indent-str ; Return indent data | |
4745 )) | |
4746 | |
4747 (defun verilog-current-indent-level () | |
80165
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
4748 "Return the indent-level of the current statement." |
79545 | 4749 (save-excursion |
4750 (let (par-pos) | |
4751 (beginning-of-line) | |
4752 (setq par-pos (verilog-parenthesis-depth)) | |
4753 (while par-pos | |
4754 (goto-char par-pos) | |
4755 (beginning-of-line) | |
4756 (setq par-pos (verilog-parenthesis-depth))) | |
4757 (skip-chars-forward " \t") | |
4758 (current-column)))) | |
4759 | |
4760 (defun verilog-case-indent-level () | |
80165
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
4761 "Return the indent-level of the current statement. |
79545 | 4762 Do not count named blocks or case-statements." |
4763 (save-excursion | |
4764 (skip-chars-forward " \t") | |
4765 (cond | |
4766 ((looking-at verilog-named-block-re) | |
4767 (current-column)) | |
4768 ((and (not (looking-at verilog-case-re)) | |
4769 (looking-at "^[^:;]+[ \t]*:")) | |
4770 (verilog-re-search-forward ":" nil t) | |
4771 (skip-chars-forward " \t") | |
4772 (current-column)) | |
4773 (t | |
4774 (current-column))))) | |
4775 | |
4776 (defun verilog-indent-comment () | |
4777 "Indent current line as comment." | |
4778 (let* ((stcol | |
4779 (cond | |
4780 ((verilog-in-star-comment-p) | |
4781 (save-excursion | |
4782 (re-search-backward "/\\*" nil t) | |
4783 (1+(current-column)))) | |
4784 (comment-column | |
4785 comment-column ) | |
4786 (t | |
4787 (save-excursion | |
4788 (re-search-backward "//" nil t) | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4789 (current-column)))))) |
79545 | 4790 (indent-line-to stcol) |
4791 stcol)) | |
4792 | |
4793 (defun verilog-more-comment () | |
4794 "Make more comment lines like the previous." | |
4795 (let* ((star 0) | |
4796 (stcol | |
4797 (cond | |
4798 ((verilog-in-star-comment-p) | |
4799 (save-excursion | |
4800 (setq star 1) | |
4801 (re-search-backward "/\\*" nil t) | |
4802 (1+(current-column)))) | |
4803 (comment-column | |
4804 comment-column ) | |
4805 (t | |
4806 (save-excursion | |
4807 (re-search-backward "//" nil t) | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4808 (current-column)))))) |
79545 | 4809 (progn |
4810 (indent-to stcol) | |
4811 (if (and star | |
4812 (save-excursion | |
4813 (forward-line -1) | |
4814 (skip-chars-forward " \t") | |
4815 (looking-at "\*"))) | |
4816 (insert "* "))))) | |
4817 | |
4818 (defun verilog-comment-indent (&optional arg) | |
4819 "Return the column number the line should be indented to. | |
4820 ARG is ignored, for `comment-indent-function' compatibility." | |
4821 (cond | |
4822 ((verilog-in-star-comment-p) | |
4823 (save-excursion | |
4824 (re-search-backward "/\\*" nil t) | |
4825 (1+(current-column)))) | |
4826 ( comment-column | |
4827 comment-column ) | |
4828 (t | |
4829 (save-excursion | |
4830 (re-search-backward "//" nil t) | |
4831 (current-column))))) | |
4832 | |
4833 ;; | |
4834 | |
80024
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* progmodes/verilog-mode.el (verilog-declaration-core-re):
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parents:
79986
diff
changeset
|
4835 (defun verilog-pretty-declarations (&optional quiet) |
79545 | 4836 "Line up declarations around point." |
4837 (interactive) | |
4838 (save-excursion | |
4839 (if (progn | |
4840 (verilog-beg-of-statement-1) | |
4841 (looking-at verilog-declaration-re)) | |
4842 (let* ((m1 (make-marker)) | |
4843 (e) (r) | |
4844 (here (point)) | |
4845 ;; Start of declaration range | |
4846 (start | |
4847 (progn | |
4848 (verilog-beg-of-statement-1) | |
4849 (while (looking-at verilog-declaration-re) | |
4850 (beginning-of-line) | |
4851 (setq e (point)) | |
4852 (verilog-backward-syntactic-ws) | |
4853 (backward-char) | |
4854 (verilog-beg-of-statement-1)) ;Ack, need to grok `define | |
4855 e)) | |
4856 ;; End of declaration range | |
4857 (end | |
4858 (progn | |
4859 (goto-char here) | |
4860 (verilog-end-of-statement) | |
4861 (setq e (point)) ;Might be on last line | |
4862 (verilog-forward-syntactic-ws) | |
4863 (while (looking-at verilog-declaration-re) | |
4864 (beginning-of-line) | |
4865 (verilog-end-of-statement) | |
4866 (setq e (point)) | |
4867 (verilog-forward-syntactic-ws)) | |
4868 e)) | |
4869 (edpos (set-marker (make-marker) end)) | |
4870 (ind) | |
4871 (base-ind | |
4872 (progn | |
4873 (goto-char start) | |
4874 (verilog-do-indent (verilog-calculate-indent)) | |
4875 (verilog-forward-ws&directives) | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4876 (current-column)))) |
79545 | 4877 (goto-char end) |
4878 (goto-char start) | |
80024
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* progmodes/verilog-mode.el (verilog-declaration-core-re):
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parents:
79986
diff
changeset
|
4879 (if (and (not quiet) |
9231505e5076
* progmodes/verilog-mode.el (verilog-declaration-core-re):
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parents:
79986
diff
changeset
|
4880 (> (- end start) 100)) |
79545 | 4881 (message "Lining up declarations..(please stand by)")) |
4882 ;; Get the beginning of line indent first | |
4883 (while (progn (setq e (marker-position edpos)) | |
4884 (< (point) e)) | |
4885 (cond | |
4886 ( (save-excursion (skip-chars-backward " \t") | |
4887 (bolp)) | |
4888 (verilog-forward-ws&directives) | |
4889 (indent-line-to base-ind) | |
4890 (verilog-forward-ws&directives) | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4891 (verilog-re-search-forward "[ \t\n\f]" e 'move)) |
79545 | 4892 (t |
4893 (just-one-space) | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4894 (verilog-re-search-forward "[ \t\n\f]" e 'move))) |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4895 ;;(forward-line) |
79545 | 4896 ) |
4897 ;; Now find biggest prefix | |
4898 (setq ind (verilog-get-lineup-indent start edpos)) | |
4899 ;; Now indent each line. | |
4900 (goto-char start) | |
4901 (while (progn (setq e (marker-position edpos)) | |
4902 (setq r (- e (point))) | |
4903 (> r 0)) | |
4904 (setq e (point)) | |
80024
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parents:
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diff
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|
4905 (unless quiet (message "%d" r)) |
79545 | 4906 (cond |
4907 ((or (and verilog-indent-declaration-macros | |
4908 (looking-at verilog-declaration-re-1-macro)) | |
4909 (looking-at verilog-declaration-re-1-no-macro)) | |
4910 (let ((p (match-end 0))) | |
4911 (set-marker m1 p) | |
4912 (if (verilog-re-search-forward "[[#`]" p 'move) | |
4913 (progn | |
4914 (forward-char -1) | |
4915 (just-one-space) | |
4916 (goto-char (marker-position m1)) | |
4917 (just-one-space) | |
4918 (indent-to ind)) | |
4919 (progn | |
4920 (just-one-space) | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4921 (indent-to ind))))) |
79545 | 4922 ((verilog-continued-line-1 start) |
4923 (goto-char e) | |
4924 (indent-line-to ind)) | |
4925 (t ; Must be comment or white space | |
4926 (goto-char e) | |
4927 (verilog-forward-ws&directives) | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
4928 (forward-line -1))) |
79545 | 4929 (forward-line 1)) |
80024
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diff
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|
4930 (unless quiet (message "")))))) |
9231505e5076
* progmodes/verilog-mode.el (verilog-declaration-core-re):
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|
4931 |
9231505e5076
* progmodes/verilog-mode.el (verilog-declaration-core-re):
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parents:
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|
4932 (defun verilog-pretty-expr (&optional quiet myre) |
79799
57956dd69d3f
(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
4933 "Line up expressions around point, or optional regexp MYRE." |
79545 | 4934 (interactive "sRegular Expression: ((<|:)?=) ") |
4935 (save-excursion | |
4936 (if (or (eq myre nil) | |
4937 (string-equal myre "")) | |
4938 (setq myre "\\(<\\|:\\)?=")) | |
80024
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* progmodes/verilog-mode.el (verilog-declaration-core-re):
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parents:
79986
diff
changeset
|
4939 (setq myre (concat "\\(^[^;#:<=>]*\\)\\(" myre "\\)")) |
9231505e5076
* progmodes/verilog-mode.el (verilog-declaration-core-re):
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parents:
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diff
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|
4940 (let ((rexp(concat "^\\s-*" verilog-complete-reg))) |
9231505e5076
* progmodes/verilog-mode.el (verilog-declaration-core-re):
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|
4941 (beginning-of-line) |
9231505e5076
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|
4942 (if (and (not (looking-at rexp )) |
9231505e5076
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|
4943 (looking-at myre)) |
9231505e5076
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parents:
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|
4944 (let* ((here (point)) |
9231505e5076
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|
4945 (e) (r) |
9231505e5076
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parents:
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|
4946 (start |
9231505e5076
* progmodes/verilog-mode.el (verilog-declaration-core-re):
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parents:
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|
4947 (progn |
9231505e5076
* progmodes/verilog-mode.el (verilog-declaration-core-re):
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parents:
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diff
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|
4948 (beginning-of-line) |
79545 | 4949 (setq e (point)) |
4950 (verilog-backward-syntactic-ws) | |
4951 (beginning-of-line) | |
80024
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|
4952 (while (and (not (looking-at rexp )) |
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* progmodes/verilog-mode.el (verilog-declaration-core-re):
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|
4953 (looking-at myre) |
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* progmodes/verilog-mode.el (verilog-declaration-core-re):
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|
4954 (not (bobp)) |
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|
4955 ) |
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parents:
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|
4956 (setq e (point)) |
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|
4957 (verilog-backward-syntactic-ws) |
9231505e5076
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|
4958 (beginning-of-line) |
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* progmodes/verilog-mode.el (verilog-declaration-core-re):
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|
4959 ) ;Ack, need to grok `define |
9231505e5076
* progmodes/verilog-mode.el (verilog-declaration-core-re):
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parents:
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|
4960 e)) |
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|
4961 (end |
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|
4962 (progn |
9231505e5076
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|
4963 (goto-char here) |
79545 | 4964 (end-of-line) |
80024
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parents:
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|
4965 (setq e (point)) ;Might be on last line |
79545 | 4966 (verilog-forward-syntactic-ws) |
80024
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|
4967 (beginning-of-line) |
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4968 (while (and (not (looking-at rexp )) |
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4969 (looking-at myre)) |
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|
4970 (end-of-line) |
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4971 (setq e (point)) |
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4972 (verilog-forward-syntactic-ws) |
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4973 (beginning-of-line) |
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4974 ) |
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4975 e)) |
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4976 (edpos (set-marker (make-marker) end)) |
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4977 (ind) |
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4978 ) |
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4979 (goto-char start) |
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4980 (verilog-do-indent (verilog-calculate-indent)) |
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4981 (if (and (not quiet) |
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4982 (> (- end start) 100)) |
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4983 (message "Lining up expressions..(please stand by)")) |
80141
00b853b0f933
(customize): Fix typo in error message.
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parents:
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4984 |
80024
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4985 ;; Set indent to minimum throughout region |
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4986 (while (< (point) (marker-position edpos)) |
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4987 (beginning-of-line) |
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4988 (verilog-just-one-space myre) |
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4989 (end-of-line) |
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4990 (verilog-forward-syntactic-ws) |
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4991 ) |
80141
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4992 |
80024
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4993 ;; Now find biggest prefix |
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4994 (setq ind (verilog-get-lineup-indent-2 myre start edpos)) |
80141
00b853b0f933
(customize): Fix typo in error message.
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4995 |
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4996 ;; Now indent each line. |
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4997 (goto-char start) |
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|
4998 (while (progn (setq e (marker-position edpos)) |
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|
4999 (setq r (- e (point))) |
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|
5000 (> r 0)) |
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|
5001 (setq e (point)) |
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|
5002 (if (not quiet) (message "%d" r)) |
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5003 (cond |
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5004 ((looking-at myre) |
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|
5005 (goto-char (match-end 1)) |
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|
5006 (if (not (verilog-parenthesis-depth)) ;; ignore parenthsized exprs |
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|
5007 (if (eq (char-after) ?=) |
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|
5008 (indent-to (1+ ind)) ; line up the = of the <= with surrounding = |
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|
5009 (indent-to ind) |
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5010 ))) |
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5011 ((verilog-continued-line-1 start) |
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|
5012 (goto-char e) |
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|
5013 (indent-line-to ind)) |
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|
5014 (t ; Must be comment or white space |
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|
5015 (goto-char e) |
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|
5016 (verilog-forward-ws&directives) |
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|
5017 (forward-line -1)) |
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* progmodes/verilog-mode.el (verilog-declaration-core-re):
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|
5018 ) |
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* progmodes/verilog-mode.el (verilog-declaration-core-re):
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|
5019 (forward-line 1)) |
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|
5020 (unless quiet (message "")) |
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5021 ))))) |
79545 | 5022 |
5023 (defun verilog-just-one-space (myre) | |
5024 "Remove extra spaces around regular expression MYRE." | |
5025 (interactive) | |
5026 (if (and (not(looking-at verilog-complete-reg)) | |
5027 (looking-at myre)) | |
5028 (let ((p1 (match-end 1)) | |
5029 (p2 (match-end 2))) | |
5030 (progn | |
5031 (goto-char p2) | |
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(top-level): Fix spacing.
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diff
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|
5032 (if (looking-at "\\s-") (just-one-space)) |
79545 | 5033 (goto-char p1) |
5034 (forward-char -1) | |
80024
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|
5035 (if (looking-at "\\s-") (just-one-space)) |
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|
5036 )))) |
79545 | 5037 |
5038 (defun verilog-indent-declaration (baseind) | |
5039 "Indent current lines as declaration. | |
5040 Line up the variable names based on previous declaration's indentation. | |
5041 BASEIND is the base indent to offset everything." | |
5042 (interactive) | |
5043 (let ((pos (point-marker)) | |
5044 (lim (save-excursion | |
5045 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move) | |
5046 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move) | |
5047 (point))) | |
5048 (ind) | |
5049 (val) | |
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changeset
|
5050 (m1 (make-marker))) |
79691
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79555
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|
5051 (setq val |
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|
5052 (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist))))) |
79545 | 5053 (indent-line-to val) |
5054 | |
5055 ;; Use previous declaration (in this module) as template. | |
5056 (if (or (memq 'all verilog-auto-lineup) | |
5057 (memq 'declaration verilog-auto-lineup)) | |
79546 | 5058 (if (verilog-re-search-backward |
79545 | 5059 (or (and verilog-indent-declaration-macros |
5060 verilog-declaration-re-1-macro) | |
5061 verilog-declaration-re-1-no-macro) lim t) | |
5062 (progn | |
5063 (goto-char (match-end 0)) | |
5064 (skip-chars-forward " \t") | |
5065 (setq ind (current-column)) | |
5066 (goto-char pos) | |
79691
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changeset
|
5067 (setq val |
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|
5068 (+ baseind |
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changeset
|
5069 (eval (cdr (assoc 'declaration verilog-indent-alist))))) |
79545 | 5070 (indent-line-to val) |
5071 (if (and verilog-indent-declaration-macros | |
5072 (looking-at verilog-declaration-re-2-macro)) | |
5073 (let ((p (match-end 0))) | |
5074 (set-marker m1 p) | |
5075 (if (verilog-re-search-forward "[[#`]" p 'move) | |
5076 (progn | |
5077 (forward-char -1) | |
5078 (just-one-space) | |
5079 (goto-char (marker-position m1)) | |
5080 (just-one-space) | |
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79717
diff
changeset
|
5081 (indent-to ind)) |
79545 | 5082 (if (/= (current-column) ind) |
5083 (progn | |
5084 (just-one-space) | |
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(top-level): Fix spacing.
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diff
changeset
|
5085 (indent-to ind))))) |
79545 | 5086 (if (looking-at verilog-declaration-re-2-no-macro) |
5087 (let ((p (match-end 0))) | |
5088 (set-marker m1 p) | |
5089 (if (verilog-re-search-forward "[[`#]" p 'move) | |
5090 (progn | |
5091 (forward-char -1) | |
5092 (just-one-space) | |
5093 (goto-char (marker-position m1)) | |
5094 (just-one-space) | |
5095 (indent-to ind)) | |
5096 (if (/= (current-column) ind) | |
5097 (progn | |
5098 (just-one-space) | |
79691
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changeset
|
5099 (indent-to ind)))))))))) |
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|
5100 (goto-char pos))) |
79545 | 5101 |
5102 (defun verilog-get-lineup-indent (b edpos) | |
5103 "Return the indent level that will line up several lines within the region. | |
5104 Region is defined by B and EDPOS." | |
5105 (save-excursion | |
5106 (let ((ind 0) e) | |
5107 (goto-char b) | |
5108 ;; Get rightmost position | |
5109 (while (progn (setq e (marker-position edpos)) | |
5110 (< (point) e)) | |
79546 | 5111 (if (verilog-re-search-forward |
79545 | 5112 (or (and verilog-indent-declaration-macros |
5113 verilog-declaration-re-1-macro) | |
5114 verilog-declaration-re-1-no-macro) e 'move) | |
5115 (progn | |
5116 (goto-char (match-end 0)) | |
5117 (verilog-backward-syntactic-ws) | |
5118 (if (> (current-column) ind) | |
5119 (setq ind (current-column))) | |
5120 (goto-char (match-end 0))))) | |
5121 (if (> ind 0) | |
5122 (1+ ind) | |
5123 ;; No lineup-string found | |
5124 (goto-char b) | |
5125 (end-of-line) | |
5126 (skip-chars-backward " \t") | |
5127 (1+ (current-column)))))) | |
5128 | |
5129 (defun verilog-get-lineup-indent-2 (myre b edpos) | |
5130 "Return the indent level that will line up several lines within the region." | |
5131 (save-excursion | |
5132 (let ((ind 0) e) | |
5133 (goto-char b) | |
5134 ;; Get rightmost position | |
5135 (while (progn (setq e (marker-position edpos)) | |
5136 (< (point) e)) | |
80024
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|
5137 (if (and (verilog-re-search-forward myre e 'move) |
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|
5138 (not (verilog-parenthesis-depth))) ;; skip parenthsized exprs |
79545 | 5139 (progn |
80024
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changeset
|
5140 (goto-char (match-beginning 2)) |
79545 | 5141 (verilog-backward-syntactic-ws) |
5142 (if (> (current-column) ind) | |
5143 (setq ind (current-column))) | |
80024
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* progmodes/verilog-mode.el (verilog-declaration-core-re):
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|
5144 (goto-char (match-end 0))) |
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|
5145 )) |
79545 | 5146 (if (> ind 0) |
5147 (1+ ind) | |
5148 ;; No lineup-string found | |
5149 (goto-char b) | |
5150 (end-of-line) | |
5151 (skip-chars-backward " \t") | |
5152 (1+ (current-column)))))) | |
5153 | |
5154 (defun verilog-comment-depth (type val) | |
5155 "A useful mode debugging aide. TYPE and VAL are comments for insertion." | |
5156 (save-excursion | |
5157 (let | |
5158 ((b (prog2 | |
5159 (beginning-of-line) | |
5160 (point-marker) | |
5161 (end-of-line))) | |
5162 (e (point-marker))) | |
5163 (if (re-search-backward " /\\* \[#-\]# \[a-zA-Z\]+ \[0-9\]+ ## \\*/" b t) | |
5164 (progn | |
5165 (replace-match " /* -# ## */") | |
5166 (end-of-line)) | |
5167 (progn | |
5168 (end-of-line) | |
5169 (insert " /* ## ## */")))) | |
5170 (backward-char 6) | |
5171 (insert | |
5172 (format "%s %d" type val)))) | |
5173 | |
5174 ;; | |
5175 ;; | |
5176 ;; Completion | |
5177 ;; | |
5178 (defvar verilog-str nil) | |
5179 (defvar verilog-all nil) | |
5180 (defvar verilog-pred nil) | |
5181 (defvar verilog-buffer-to-use nil) | |
5182 (defvar verilog-flag nil) | |
5183 (defvar verilog-toggle-completions nil | |
5184 "*True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one. | |
5185 Repeated use of \\[verilog-complete-word] will show you all of them. | |
5186 Normally, when there is more than one possible completion, | |
5187 it displays a list of all possible completions.") | |
5188 | |
5189 | |
5190 (defvar verilog-type-keywords | |
5191 '( | |
5192 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input" | |
5193 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0" | |
5194 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pullup" | |
5195 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0" | |
5196 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1" | |
5197 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor" | |
5198 ) | |
5199 "*Keywords for types used when completing a word in a declaration or parmlist. | |
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|
5200 \(Eg. integer, real, reg...)") |
79545 | 5201 |
5202 (defvar verilog-cpp-keywords | |
5203 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else" | |
5204 "endif") | |
5205 "*Keywords to complete when at first word of a line in declarative scope. | |
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|
5206 \(Eg. initial, always, begin, assign.) |
79545 | 5207 The procedures and variables defined within the Verilog program |
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|
5208 will be completed at runtime and should not be added to this list.") |
79545 | 5209 |
5210 (defvar verilog-defun-keywords | |
5211 (append | |
5212 '( | |
5213 "always" "always_comb" "always_ff" "always_latch" "assign" | |
5214 "begin" "end" "generate" "endgenerate" "module" "endmodule" | |
5215 "specify" "endspecify" "function" "endfunction" "initial" "final" | |
5216 "task" "endtask" "primitive" "endprimitive" | |
5217 ) | |
5218 verilog-type-keywords) | |
5219 "*Keywords to complete when at first word of a line in declarative scope. | |
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|
5220 \(Eg. initial, always, begin, assign.) |
79545 | 5221 The procedures and variables defined within the Verilog program |
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|
5222 will be completed at runtime and should not be added to this list.") |
79545 | 5223 |
5224 (defvar verilog-block-keywords | |
5225 '( | |
5226 "begin" "break" "case" "continue" "else" "end" "endfunction" | |
5227 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask" | |
5228 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return" | |
5229 "while") | |
5230 "*Keywords to complete when at first word of a line in behavioral scope. | |
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|
5231 \(Eg. begin, if, then, else, for, fork.) |
79545 | 5232 The procedures and variables defined within the Verilog program |
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|
5233 will be completed at runtime and should not be added to this list.") |
79545 | 5234 |
5235 (defvar verilog-tf-keywords | |
5236 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat") | |
5237 "*Keywords to complete when at first word of a line in a task or function. | |
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|
5238 \(Eg. begin, if, then, else, for, fork.) |
79545 | 5239 The procedures and variables defined within the Verilog program |
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|
5240 will be completed at runtime and should not be added to this list.") |
79545 | 5241 |
5242 (defvar verilog-case-keywords | |
5243 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat") | |
5244 "*Keywords to complete when at first word of a line in case scope. | |
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|
5245 \(Eg. begin, if, then, else, for, fork.) |
79545 | 5246 The procedures and variables defined within the Verilog program |
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|
5247 will be completed at runtime and should not be added to this list.") |
79545 | 5248 |
5249 (defvar verilog-separator-keywords | |
5250 '("else" "then" "begin") | |
5251 "*Keywords to complete when NOT standing at the first word of a statement. | |
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|
5252 \(Eg. else, then.) |
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|
5253 Variables and function names defined within the Verilog program |
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|
5254 will be completed at runtime and should not be added to this list.") |
79545 | 5255 |
5256 (defun verilog-string-diff (str1 str2) | |
5257 "Return index of first letter where STR1 and STR2 differs." | |
5258 (catch 'done | |
5259 (let ((diff 0)) | |
5260 (while t | |
5261 (if (or (> (1+ diff) (length str1)) | |
5262 (> (1+ diff) (length str2))) | |
5263 (throw 'done diff)) | |
5264 (or (equal (aref str1 diff) (aref str2 diff)) | |
5265 (throw 'done diff)) | |
5266 (setq diff (1+ diff)))))) | |
5267 | |
5268 ;; Calculate all possible completions for functions if argument is `function', | |
5269 ;; completions for procedures if argument is `procedure' or both functions and | |
5270 ;; procedures otherwise. | |
5271 | |
5272 (defun verilog-func-completion (type) | |
5273 "Build regular expression for module/task/function names. | |
5274 TYPE is 'module, 'tf for task or function, or t if unknown." | |
5275 (if (string= verilog-str "") | |
5276 (setq verilog-str "[a-zA-Z_]")) | |
5277 (let ((verilog-str (concat (cond | |
5278 ((eq type 'module) "\\<\\(module\\)\\s +") | |
5279 ((eq type 'tf) "\\<\\(task\\|function\\)\\s +") | |
5280 (t "\\<\\(task\\|function\\|module\\)\\s +")) | |
5281 "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>")) | |
5282 match) | |
5283 | |
5284 (if (not (looking-at verilog-defun-re)) | |
5285 (verilog-re-search-backward verilog-defun-re nil t)) | |
5286 (forward-char 1) | |
5287 | |
5288 ;; Search through all reachable functions | |
5289 (goto-char (point-min)) | |
5290 (while (verilog-re-search-forward verilog-str (point-max) t) | |
5291 (progn (setq match (buffer-substring (match-beginning 2) | |
5292 (match-end 2))) | |
5293 (if (or (null verilog-pred) | |
5294 (funcall verilog-pred match)) | |
5295 (setq verilog-all (cons match verilog-all))))) | |
5296 (if (match-beginning 0) | |
5297 (goto-char (match-beginning 0))))) | |
5298 | |
5299 (defun verilog-get-completion-decl (end) | |
5300 "Macro for searching through current declaration (var, type or const) | |
5301 for matches of `str' and adding the occurrence tp `all' through point END." | |
5302 (let ((re (or (and verilog-indent-declaration-macros | |
5303 verilog-declaration-re-2-macro) | |
5304 verilog-declaration-re-2-no-macro)) | |
5305 decl-end match) | |
5306 ;; Traverse lines | |
5307 (while (and (< (point) end) | |
5308 (verilog-re-search-forward re end t)) | |
5309 ;; Traverse current line | |
5310 (setq decl-end (save-excursion (verilog-declaration-end))) | |
5311 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t) | |
5312 (not (match-end 1))) | |
5313 (setq match (buffer-substring (match-beginning 0) (match-end 0))) | |
5314 (if (string-match (concat "\\<" verilog-str) match) | |
5315 (if (or (null verilog-pred) | |
5316 (funcall verilog-pred match)) | |
5317 (setq verilog-all (cons match verilog-all))))) | |
79799
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Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
5318 (forward-line 1))) |
57956dd69d3f
(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
5319 verilog-all) |
79545 | 5320 |
5321 (defun verilog-type-completion () | |
5322 "Calculate all possible completions for types." | |
5323 (let ((start (point)) | |
5324 goon) | |
5325 ;; Search for all reachable type declarations | |
5326 (while (or (verilog-beg-of-defun) | |
5327 (setq goon (not goon))) | |
5328 (save-excursion | |
5329 (if (and (< start (prog1 (save-excursion (verilog-end-of-defun) | |
5330 (point)) | |
5331 (forward-char 1))) | |
5332 (verilog-re-search-forward | |
5333 "\\<type\\>\\|\\<\\(begin\\|function\\|procedure\\)\\>" | |
5334 start t) | |
5335 (not (match-end 1))) | |
5336 ;; Check current type declaration | |
5337 (verilog-get-completion-decl start)))))) | |
5338 | |
5339 (defun verilog-var-completion () | |
5340 "Calculate all possible completions for variables (or constants)." | |
5341 (let ((start (point))) | |
5342 ;; Search for all reachable var declarations | |
5343 (verilog-beg-of-defun) | |
5344 (save-excursion | |
5345 ;; Check var declarations | |
5346 (verilog-get-completion-decl start)))) | |
5347 | |
5348 (defun verilog-keyword-completion (keyword-list) | |
5349 "Give list of all possible completions of keywords in KEYWORD-LIST." | |
5350 (mapcar '(lambda (s) | |
5351 (if (string-match (concat "\\<" verilog-str) s) | |
5352 (if (or (null verilog-pred) | |
5353 (funcall verilog-pred s)) | |
5354 (setq verilog-all (cons s verilog-all))))) | |
5355 keyword-list)) | |
5356 | |
5357 | |
5358 (defun verilog-completion (verilog-str verilog-pred verilog-flag) | |
5359 "Function passed to `completing-read', `try-completion' or `all-completions'. | |
5360 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it | |
5361 must be a function to be called for every match to check if this should | |
80165
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
5362 really be a match. If VERILOG-FLAG is t, the function returns a list of |
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
5363 all possible completions. If VERILOG-FLAG is nil it returns a string, |
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
5364 the longest possible completion, or t if VERILOG-STR is an exact match. |
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
5365 If VERILOG-FLAG is 'lambda, the function returns t if VERILOG-STR is an |
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
5366 exact match, nil otherwise." |
79545 | 5367 (save-excursion |
5368 (let ((verilog-all nil)) | |
5369 ;; Set buffer to use for searching labels. This should be set | |
5370 ;; within functions which use verilog-completions | |
5371 (set-buffer verilog-buffer-to-use) | |
5372 | |
5373 ;; Determine what should be completed | |
5374 (let ((state (car (verilog-calculate-indent)))) | |
5375 (cond ((eq state 'defun) | |
5376 (save-excursion (verilog-var-completion)) | |
5377 (verilog-func-completion 'module) | |
5378 (verilog-keyword-completion verilog-defun-keywords)) | |
5379 | |
5380 ((eq state 'behavioral) | |
5381 (save-excursion (verilog-var-completion)) | |
5382 (verilog-func-completion 'module) | |
5383 (verilog-keyword-completion verilog-defun-keywords)) | |
5384 | |
5385 ((eq state 'block) | |
5386 (save-excursion (verilog-var-completion)) | |
5387 (verilog-func-completion 'tf) | |
5388 (verilog-keyword-completion verilog-block-keywords)) | |
5389 | |
5390 ((eq state 'case) | |
5391 (save-excursion (verilog-var-completion)) | |
5392 (verilog-func-completion 'tf) | |
5393 (verilog-keyword-completion verilog-case-keywords)) | |
5394 | |
5395 ((eq state 'tf) | |
5396 (save-excursion (verilog-var-completion)) | |
5397 (verilog-func-completion 'tf) | |
5398 (verilog-keyword-completion verilog-tf-keywords)) | |
5399 | |
5400 ((eq state 'cpp) | |
5401 (save-excursion (verilog-var-completion)) | |
5402 (verilog-keyword-completion verilog-cpp-keywords)) | |
5403 | |
5404 ((eq state 'cparenexp) | |
5405 (save-excursion (verilog-var-completion))) | |
5406 | |
5407 (t;--Anywhere else | |
5408 (save-excursion (verilog-var-completion)) | |
5409 (verilog-func-completion 'both) | |
5410 (verilog-keyword-completion verilog-separator-keywords)))) | |
5411 | |
5412 ;; Now we have built a list of all matches. Give response to caller | |
5413 (verilog-completion-response)))) | |
5414 | |
5415 (defun verilog-completion-response () | |
5416 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag)) | |
5417 ;; This was not called by all-completions | |
5418 (if (null verilog-all) | |
5419 ;; Return nil if there was no matching label | |
5420 nil | |
5421 ;; Get longest string common in the labels | |
5422 (let* ((elm (cdr verilog-all)) | |
5423 (match (car verilog-all)) | |
5424 (min (length match)) | |
5425 tmp) | |
5426 (if (string= match verilog-str) | |
5427 ;; Return t if first match was an exact match | |
5428 (setq match t) | |
5429 (while (not (null elm)) | |
5430 ;; Find longest common string | |
5431 (if (< (setq tmp (verilog-string-diff match (car elm))) min) | |
5432 (progn | |
5433 (setq min tmp) | |
5434 (setq match (substring match 0 min)))) | |
5435 ;; Terminate with match=t if this is an exact match | |
5436 (if (string= (car elm) verilog-str) | |
5437 (progn | |
5438 (setq match t) | |
5439 (setq elm nil)) | |
5440 (setq elm (cdr elm))))) | |
5441 ;; If this is a test just for exact match, return nil ot t | |
5442 (if (and (equal verilog-flag 'lambda) (not (equal match 't))) | |
5443 nil | |
5444 match)))) | |
5445 ;; If flag is t, this was called by all-completions. Return | |
5446 ;; list of all possible completions | |
5447 (verilog-flag | |
5448 verilog-all))) | |
5449 | |
5450 (defvar verilog-last-word-numb 0) | |
5451 (defvar verilog-last-word-shown nil) | |
5452 (defvar verilog-last-completions nil) | |
5453 | |
5454 (defun verilog-complete-word () | |
5455 "Complete word at current point. | |
5456 \(See also `verilog-toggle-completions', `verilog-type-keywords', | |
5457 and `verilog-separator-keywords'.)" | |
5458 (interactive) | |
5459 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point))) | |
5460 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point))) | |
5461 (verilog-str (buffer-substring b e)) | |
5462 ;; The following variable is used in verilog-completion | |
5463 (verilog-buffer-to-use (current-buffer)) | |
5464 (allcomp (if (and verilog-toggle-completions | |
5465 (string= verilog-last-word-shown verilog-str)) | |
5466 verilog-last-completions | |
5467 (all-completions verilog-str 'verilog-completion))) | |
5468 (match (if verilog-toggle-completions | |
5469 "" (try-completion | |
5470 verilog-str (mapcar '(lambda (elm) | |
5471 (cons elm 0)) allcomp))))) | |
5472 ;; Delete old string | |
5473 (delete-region b e) | |
5474 | |
5475 ;; Toggle-completions inserts whole labels | |
5476 (if verilog-toggle-completions | |
5477 (progn | |
5478 ;; Update entry number in list | |
5479 (setq verilog-last-completions allcomp | |
5480 verilog-last-word-numb | |
5481 (if (>= verilog-last-word-numb (1- (length allcomp))) | |
5482 0 | |
5483 (1+ verilog-last-word-numb))) | |
5484 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb)) | |
5485 ;; Display next match or same string if no match was found | |
5486 (if (not (null allcomp)) | |
5487 (insert "" verilog-last-word-shown) | |
5488 (insert "" verilog-str) | |
5489 (message "(No match)"))) | |
5490 ;; The other form of completion does not necessarily do that. | |
5491 | |
5492 ;; Insert match if found, or the original string if no match | |
5493 (if (or (null match) (equal match 't)) | |
5494 (progn (insert "" verilog-str) | |
5495 (message "(No match)")) | |
5496 (insert "" match)) | |
5497 ;; Give message about current status of completion | |
5498 (cond ((equal match 't) | |
5499 (if (not (null (cdr allcomp))) | |
5500 (message "(Complete but not unique)") | |
5501 (message "(Sole completion)"))) | |
5502 ;; Display buffer if the current completion didn't help | |
5503 ;; on completing the label. | |
5504 ((and (not (null (cdr allcomp))) (= (length verilog-str) | |
5505 (length match))) | |
5506 (with-output-to-temp-buffer "*Completions*" | |
5507 (display-completion-list allcomp)) | |
5508 ;; Wait for a key press. Then delete *Completion* window | |
5509 (momentary-string-display "" (point)) | |
5510 (delete-window (get-buffer-window (get-buffer "*Completions*"))) | |
5511 ))))) | |
5512 | |
5513 (defun verilog-show-completions () | |
5514 "Show all possible completions at current point." | |
5515 (interactive) | |
5516 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point))) | |
5517 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point))) | |
5518 (verilog-str (buffer-substring b e)) | |
5519 ;; The following variable is used in verilog-completion | |
5520 (verilog-buffer-to-use (current-buffer)) | |
5521 (allcomp (if (and verilog-toggle-completions | |
5522 (string= verilog-last-word-shown verilog-str)) | |
5523 verilog-last-completions | |
5524 (all-completions verilog-str 'verilog-completion)))) | |
5525 ;; Show possible completions in a temporary buffer. | |
5526 (with-output-to-temp-buffer "*Completions*" | |
5527 (display-completion-list allcomp)) | |
5528 ;; Wait for a key press. Then delete *Completion* window | |
5529 (momentary-string-display "" (point)) | |
5530 (delete-window (get-buffer-window (get-buffer "*Completions*"))))) | |
5531 | |
5532 | |
5533 (defun verilog-get-default-symbol () | |
5534 "Return symbol around current point as a string." | |
5535 (save-excursion | |
5536 (buffer-substring (progn | |
5537 (skip-chars-backward " \t") | |
5538 (skip-chars-backward "a-zA-Z0-9_") | |
5539 (point)) | |
5540 (progn | |
5541 (skip-chars-forward "a-zA-Z0-9_") | |
5542 (point))))) | |
5543 | |
5544 (defun verilog-build-defun-re (str &optional arg) | |
5545 "Return function/task/module starting with STR as regular expression. | |
5546 With optional second ARG non-nil, STR is the complete name of the instruction." | |
5547 (if arg | |
5548 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>") | |
5549 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>"))) | |
5550 | |
5551 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag) | |
5552 "Function passed to `completing-read', `try-completion' or `all-completions'. | |
5553 Returns a completion on any function name based on VERILOG-STR prefix. If | |
5554 VERILOG-PRED is non-nil, it must be a function to be called for every match | |
5555 to check if this should really be a match. If VERILOG-FLAG is t, the | |
5556 function returns a list of all possible completions. If it is nil it | |
5557 returns a string, the longest possible completion, or t if VERILOG-STR is | |
5558 an exact match. If VERILOG-FLAG is 'lambda, the function returns t if | |
5559 VERILOG-STR is an exact match, nil otherwise." | |
5560 (save-excursion | |
5561 (let ((verilog-all nil) | |
5562 match) | |
5563 | |
5564 ;; Set buffer to use for searching labels. This should be set | |
5565 ;; within functions which use verilog-completions | |
5566 (set-buffer verilog-buffer-to-use) | |
5567 | |
5568 (let ((verilog-str verilog-str)) | |
5569 ;; Build regular expression for functions | |
5570 (if (string= verilog-str "") | |
5571 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]")) | |
5572 (setq verilog-str (verilog-build-defun-re verilog-str))) | |
5573 (goto-char (point-min)) | |
5574 | |
5575 ;; Build a list of all possible completions | |
5576 (while (verilog-re-search-forward verilog-str nil t) | |
5577 (setq match (buffer-substring (match-beginning 2) (match-end 2))) | |
5578 (if (or (null verilog-pred) | |
5579 (funcall verilog-pred match)) | |
5580 (setq verilog-all (cons match verilog-all))))) | |
5581 | |
5582 ;; Now we have built a list of all matches. Give response to caller | |
5583 (verilog-completion-response)))) | |
5584 | |
5585 (defun verilog-goto-defun () | |
5586 "Move to specified Verilog module/task/function. | |
5587 The default is a name found in the buffer around point. | |
5588 If search fails, other files are checked based on | |
5589 `verilog-library-flags'." | |
5590 (interactive) | |
5591 (let* ((default (verilog-get-default-symbol)) | |
5592 ;; The following variable is used in verilog-comp-function | |
5593 (verilog-buffer-to-use (current-buffer)) | |
5594 (label (if (not (string= default "")) | |
5595 ;; Do completion with default | |
5596 (completing-read (concat "Label: (default " default ") ") | |
5597 'verilog-comp-defun nil nil "") | |
5598 ;; There is no default value. Complete without it | |
5599 (completing-read "Label: " | |
5600 'verilog-comp-defun nil nil ""))) | |
5601 pt) | |
5602 ;; If there was no response on prompt, use default value | |
5603 (if (string= label "") | |
5604 (setq label default)) | |
5605 ;; Goto right place in buffer if label is not an empty string | |
5606 (or (string= label "") | |
5607 (progn | |
5608 (save-excursion | |
5609 (goto-char (point-min)) | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
5610 (setq pt |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
5611 (re-search-forward (verilog-build-defun-re label t) nil t))) |
79545 | 5612 (when pt |
5613 (goto-char pt) | |
5614 (beginning-of-line)) | |
5615 pt) | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
5616 (verilog-goto-defun-file label)))) |
79545 | 5617 |
5618 ;; Eliminate compile warning | |
80172
7d8f87158250
(eval-when-compile): Don't define
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parents:
80171
diff
changeset
|
5619 (defvar occur-pos-list) |
79545 | 5620 |
5621 (defun verilog-showscopes () | |
5622 "List all scopes in this module." | |
5623 (interactive) | |
5624 (let ((buffer (current-buffer)) | |
5625 (linenum 1) | |
5626 (nlines 0) | |
5627 (first 1) | |
5628 (prevpos (point-min)) | |
5629 (final-context-start (make-marker)) | |
79799
57956dd69d3f
(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
5630 (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)")) |
79545 | 5631 (with-output-to-temp-buffer "*Occur*" |
5632 (save-excursion | |
5633 (message (format "Searching for %s ..." regexp)) | |
5634 ;; Find next match, but give up if prev match was at end of buffer. | |
5635 (while (and (not (= prevpos (point-max))) | |
5636 (verilog-re-search-forward regexp nil t)) | |
5637 (goto-char (match-beginning 0)) | |
5638 (beginning-of-line) | |
5639 (save-match-data | |
5640 (setq linenum (+ linenum (count-lines prevpos (point))))) | |
5641 (setq prevpos (point)) | |
5642 (goto-char (match-end 0)) | |
5643 (let* ((start (save-excursion | |
5644 (goto-char (match-beginning 0)) | |
5645 (forward-line (if (< nlines 0) nlines (- nlines))) | |
5646 (point))) | |
5647 (end (save-excursion | |
5648 (goto-char (match-end 0)) | |
5649 (if (> nlines 0) | |
5650 (forward-line (1+ nlines)) | |
5651 (forward-line 1)) | |
5652 (point))) | |
5653 (tag (format "%3d" linenum)) | |
5654 (empty (make-string (length tag) ?\ )) | |
5655 tem) | |
5656 (save-excursion | |
5657 (setq tem (make-marker)) | |
5658 (set-marker tem (point)) | |
5659 (set-buffer standard-output) | |
5660 (setq occur-pos-list (cons tem occur-pos-list)) | |
5661 (or first (zerop nlines) | |
5662 (insert "--------\n")) | |
5663 (setq first nil) | |
5664 (insert-buffer-substring buffer start end) | |
5665 (backward-char (- end start)) | |
5666 (setq tem (if (< nlines 0) (- nlines) nlines)) | |
5667 (while (> tem 0) | |
5668 (insert empty ?:) | |
5669 (forward-line 1) | |
5670 (setq tem (1- tem))) | |
5671 (let ((this-linenum linenum)) | |
5672 (set-marker final-context-start | |
5673 (+ (point) (- (match-end 0) (match-beginning 0)))) | |
5674 (while (< (point) final-context-start) | |
5675 (if (null tag) | |
5676 (setq tag (format "%3d" this-linenum))) | |
5677 (insert tag ?:))))))) | |
5678 (set-buffer-modified-p nil)))) | |
5679 | |
5680 | |
5681 ;; Highlight helper functions | |
5682 (defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_") | |
5683 (defun verilog-within-translate-off () | |
5684 "Return point if within translate-off region, else nil." | |
5685 (and (save-excursion | |
5686 (re-search-backward | |
5687 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>") | |
5688 nil t)) | |
5689 (equal "off" (match-string 2)) | |
5690 (point))) | |
5691 | |
5692 (defun verilog-start-translate-off (limit) | |
5693 "Return point before translate-off directive if before LIMIT, else nil." | |
5694 (when (re-search-forward | |
5695 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>") | |
5696 limit t) | |
5697 (match-beginning 0))) | |
5698 | |
5699 (defun verilog-back-to-start-translate-off (limit) | |
5700 "Return point before translate-off directive if before LIMIT, else nil." | |
5701 (when (re-search-backward | |
5702 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>") | |
5703 limit t) | |
5704 (match-beginning 0))) | |
5705 | |
5706 (defun verilog-end-translate-off (limit) | |
5707 "Return point after translate-on directive if before LIMIT, else nil." | |
5708 | |
5709 (re-search-forward (concat | |
5710 "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t)) | |
5711 | |
5712 (defun verilog-match-translate-off (limit) | |
5713 "Match a translate-off block, setting `match-data' and returning t, else nil. | |
5714 Bound search by LIMIT." | |
5715 (when (< (point) limit) | |
5716 (let ((start (or (verilog-within-translate-off) | |
5717 (verilog-start-translate-off limit))) | |
5718 (case-fold-search t)) | |
5719 (when start | |
5720 (let ((end (or (verilog-end-translate-off limit) limit))) | |
5721 (set-match-data (list start end)) | |
5722 (goto-char end)))))) | |
5723 | |
5724 (defun verilog-font-lock-match-item (limit) | |
5725 "Match, and move over, any declaration item after point. | |
5726 Bound search by LIMIT. Adapted from | |
5727 `font-lock-match-c-style-declaration-item-and-skip-to-next'." | |
5728 (condition-case nil | |
5729 (save-restriction | |
5730 (narrow-to-region (point-min) limit) | |
5731 ;; match item | |
5732 (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)") | |
5733 (save-match-data | |
5734 (goto-char (match-end 1)) | |
5735 ;; move to next item | |
5736 (if (looking-at "\\(\\s-*,\\)") | |
5737 (goto-char (match-end 1)) | |
5738 (end-of-line) t)))) | |
5739 (error nil))) | |
5740 | |
5741 | |
5742 ;; Added by Subbu Meiyappan for Header | |
5743 | |
5744 (defun verilog-header () | |
5745 "Insert a standard Verilog file header." | |
5746 (interactive) | |
5747 (let ((start (point))) | |
5748 (insert "\ | |
5749 //----------------------------------------------------------------------------- | |
5750 // Title : <title> | |
5751 // Project : <project> | |
5752 //----------------------------------------------------------------------------- | |
5753 // File : <filename> | |
5754 // Author : <author> | |
5755 // Created : <credate> | |
5756 // Last modified : <moddate> | |
5757 //----------------------------------------------------------------------------- | |
5758 // Description : | |
5759 // <description> | |
5760 //----------------------------------------------------------------------------- | |
5761 // Copyright (c) <copydate> by <company> This model is the confidential and | |
5762 // proprietary property of <company> and the possession or use of this | |
5763 // file requires a written license from <company>. | |
5764 //------------------------------------------------------------------------------ | |
5765 // Modification history : | |
5766 // <modhist> | |
5767 //----------------------------------------------------------------------------- | |
5768 | |
5769 ") | |
5770 (goto-char start) | |
5771 (search-forward "<filename>") | |
5772 (replace-match (buffer-name) t t) | |
5773 (search-forward "<author>") (replace-match "" t t) | |
5774 (insert (user-full-name)) | |
5775 (insert " <" (user-login-name) "@" (system-name) ">") | |
5776 (search-forward "<credate>") (replace-match "" t t) | |
79554
bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
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parents:
79552
diff
changeset
|
5777 (verilog-insert-date) |
79545 | 5778 (search-forward "<moddate>") (replace-match "" t t) |
79554
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(verilog-kill-existing-comment, verilog-insert-date)
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parents:
79552
diff
changeset
|
5779 (verilog-insert-date) |
79545 | 5780 (search-forward "<copydate>") (replace-match "" t t) |
79554
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(verilog-kill-existing-comment, verilog-insert-date)
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parents:
79552
diff
changeset
|
5781 (verilog-insert-year) |
79545 | 5782 (search-forward "<modhist>") (replace-match "" t t) |
79554
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(verilog-kill-existing-comment, verilog-insert-date)
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parents:
79552
diff
changeset
|
5783 (verilog-insert-date) |
79545 | 5784 (insert " : created") |
5785 (goto-char start) | |
5786 (let (string) | |
5787 (setq string (read-string "title: ")) | |
5788 (search-forward "<title>") | |
5789 (replace-match string t t) | |
5790 (setq string (read-string "project: " verilog-project)) | |
5791 (setq verilog-project string) | |
5792 (search-forward "<project>") | |
5793 (replace-match string t t) | |
5794 (setq string (read-string "Company: " verilog-company)) | |
5795 (setq verilog-company string) | |
5796 (search-forward "<company>") | |
5797 (replace-match string t t) | |
5798 (search-forward "<company>") | |
5799 (replace-match string t t) | |
5800 (search-forward "<company>") | |
5801 (replace-match string t t) | |
5802 (search-backward "<description>") | |
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diff
changeset
|
5803 (replace-match "" t t)))) |
79545 | 5804 |
79554
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(verilog-kill-existing-comment, verilog-insert-date)
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parents:
79552
diff
changeset
|
5805 ;; verilog-header Uses the verilog-insert-date function |
bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
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parents:
79552
diff
changeset
|
5806 |
bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
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parents:
79552
diff
changeset
|
5807 (defun verilog-insert-date () |
79545 | 5808 "Insert date from the system." |
5809 (interactive) | |
5810 (let ((timpos)) | |
5811 (setq timpos (point)) | |
5812 (if verilog-date-scientific-format | |
5813 (shell-command "date \"+@%Y/%m/%d\"" t) | |
5814 (shell-command "date \"+@%d.%m.%Y\"" t)) | |
5815 (search-forward "@") | |
5816 (delete-region timpos (point)) | |
5817 (end-of-line)) | |
5818 (delete-char 1)) | |
5819 | |
79554
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(verilog-kill-existing-comment, verilog-insert-date)
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parents:
79552
diff
changeset
|
5820 (defun verilog-insert-year () |
79545 | 5821 "Insert year from the system." |
5822 (interactive) | |
5823 (let ((timpos)) | |
5824 (setq timpos (point)) | |
5825 (shell-command "date \"+@%Y\"" t) | |
5826 (search-forward "@") | |
5827 (delete-region timpos (point)) | |
5828 (end-of-line)) | |
5829 (delete-char 1)) | |
5830 | |
5831 | |
5832 ;; | |
5833 ;; Signal list parsing | |
5834 ;; | |
5835 | |
5836 ;; Elements of a signal list | |
5837 (defsubst verilog-sig-name (sig) | |
5838 (car sig)) | |
5839 (defsubst verilog-sig-bits (sig) | |
5840 (nth 1 sig)) | |
5841 (defsubst verilog-sig-comment (sig) | |
5842 (nth 2 sig)) | |
5843 (defsubst verilog-sig-memory (sig) | |
5844 (nth 3 sig)) | |
5845 (defsubst verilog-sig-enum (sig) | |
5846 (nth 4 sig)) | |
5847 (defsubst verilog-sig-signed (sig) | |
5848 (nth 5 sig)) | |
5849 (defsubst verilog-sig-type (sig) | |
5850 (nth 6 sig)) | |
5851 (defsubst verilog-sig-multidim (sig) | |
5852 (nth 7 sig)) | |
5853 (defsubst verilog-sig-multidim-string (sig) | |
5854 (if (verilog-sig-multidim sig) | |
5855 (let ((str "") (args (verilog-sig-multidim sig))) | |
5856 (while args | |
5857 (setq str (concat str (car args))) | |
5858 (setq args (cdr args))) | |
5859 str))) | |
5860 (defsubst verilog-sig-width (sig) | |
5861 (verilog-make-width-expression (verilog-sig-bits sig))) | |
5862 | |
5863 (defsubst verilog-alw-get-inputs (sigs) | |
5864 (nth 2 sigs)) | |
5865 (defsubst verilog-alw-get-outputs (sigs) | |
5866 (nth 0 sigs)) | |
5867 (defsubst verilog-alw-get-uses-delayed (sigs) | |
5868 (nth 3 sigs)) | |
5869 | |
5870 (defun verilog-signals-not-in (in-list not-list) | |
80165
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
5871 "Return list of signals in IN-LIST that aren't also in NOT-LIST. |
411da0873a97
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Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
5872 Also remove any duplicates in IN-LIST. |
79545 | 5873 Signals must be in standard (base vector) form." |
5874 (let (out-list) | |
5875 (while in-list | |
5876 (if (not (or (assoc (car (car in-list)) not-list) | |
5877 (assoc (car (car in-list)) out-list))) | |
5878 (setq out-list (cons (car in-list) out-list))) | |
5879 (setq in-list (cdr in-list))) | |
5880 (nreverse out-list))) | |
5881 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" ""))) | |
5882 | |
5883 (defun verilog-signals-in (in-list other-list) | |
5884 "Return list of signals in IN-LIST that are also in OTHER-LIST. | |
5885 Signals must be in standard (base vector) form." | |
5886 (let (out-list) | |
5887 (while in-list | |
5888 (if (assoc (car (car in-list)) other-list) | |
5889 (setq out-list (cons (car in-list) out-list))) | |
5890 (setq in-list (cdr in-list))) | |
5891 (nreverse out-list))) | |
5892 ;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" ""))) | |
5893 | |
5894 (defun verilog-signals-memory (in-list) | |
5895 "Return list of signals in IN-LIST that are memoried (multidimensional)." | |
5896 (let (out-list) | |
5897 (while in-list | |
5898 (if (nth 3 (car in-list)) | |
5899 (setq out-list (cons (car in-list) out-list))) | |
5900 (setq in-list (cdr in-list))) | |
5901 out-list)) | |
5902 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil))) | |
5903 | |
5904 (defun verilog-signals-sort-compare (a b) | |
5905 "Compare signal A and B for sorting." | |
5906 (string< (car a) (car b))) | |
5907 | |
5908 (defun verilog-signals-not-params (in-list) | |
5909 "Return list of signals in IN-LIST that aren't parameters or numeric constants." | |
5910 (let (out-list) | |
5911 (while in-list | |
5912 (unless (boundp (intern (concat "vh-" (car (car in-list))))) | |
5913 (setq out-list (cons (car in-list) out-list))) | |
5914 (setq in-list (cdr in-list))) | |
5915 (nreverse out-list))) | |
5916 | |
5917 (defun verilog-signals-combine-bus (in-list) | |
5918 "Return a list of signals in IN-LIST, with busses combined. | |
5919 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]." | |
5920 (let (combo buswarn | |
5921 out-list | |
5922 sig highbit lowbit ; Temp information about current signal | |
5923 sv-name sv-highbit sv-lowbit ; Details about signal we are forming | |
5924 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring | |
5925 bus) | |
5926 ;; Shove signals so duplicated signals will be adjacent | |
5927 (setq in-list (sort in-list `verilog-signals-sort-compare)) | |
5928 (while in-list | |
5929 (setq sig (car in-list)) | |
5930 ;; No current signal; form from existing details | |
5931 (unless sv-name | |
5932 (setq sv-name (verilog-sig-name sig) | |
5933 sv-highbit nil | |
5934 sv-busstring nil | |
5935 sv-comment (verilog-sig-comment sig) | |
5936 sv-memory (verilog-sig-memory sig) | |
5937 sv-enum (verilog-sig-enum sig) | |
5938 sv-signed (verilog-sig-signed sig) | |
5939 sv-type (verilog-sig-type sig) | |
5940 sv-multidim (verilog-sig-multidim sig) | |
5941 combo "" | |
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diff
changeset
|
5942 buswarn "")) |
79545 | 5943 ;; Extract bus details |
5944 (setq bus (verilog-sig-bits sig)) | |
5945 (cond ((and bus | |
5946 (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus) | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
5947 (setq highbit (string-to-number (match-string 1 bus)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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diff
changeset
|
5948 lowbit (string-to-number |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
5949 (match-string 2 bus)))) |
79545 | 5950 (and (string-match "\\[\\([0-9]+\\)\\]" bus) |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
5951 (setq highbit (string-to-number (match-string 1 bus)) |
79545 | 5952 lowbit highbit)))) |
5953 ;; Combine bits in bus | |
5954 (if sv-highbit | |
5955 (setq sv-highbit (max highbit sv-highbit) | |
5956 sv-lowbit (min lowbit sv-lowbit)) | |
5957 (setq sv-highbit highbit | |
5958 sv-lowbit lowbit))) | |
5959 (bus | |
5960 ;; String, probably something like `preproc:0 | |
5961 (setq sv-busstring bus))) | |
5962 ;; Peek ahead to next signal | |
5963 (setq in-list (cdr in-list)) | |
5964 (setq sig (car in-list)) | |
5965 (cond ((and sig (equal sv-name (verilog-sig-name sig))) | |
5966 ;; Combine with this signal | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
5967 (when (and sv-busstring |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
5968 (not (equal sv-busstring (verilog-sig-bits sig)))) |
79545 | 5969 (when nil ;; Debugging |
5970 (message (concat "Warning, can't merge into single bus " | |
5971 sv-name bus | |
5972 ", the AUTOs may be wrong"))) | |
5973 (setq buswarn ", Couldn't Merge")) | |
5974 (if (verilog-sig-comment sig) (setq combo ", ...")) | |
5975 (setq sv-memory (or sv-memory (verilog-sig-memory sig)) | |
5976 sv-enum (or sv-enum (verilog-sig-enum sig)) | |
5977 sv-signed (or sv-signed (verilog-sig-signed sig)) | |
5978 sv-type (or sv-type (verilog-sig-type sig)) | |
5979 sv-multidim (or sv-multidim (verilog-sig-multidim sig)))) | |
5980 ;; Doesn't match next signal, add to queue, zero in prep for next | |
5981 ;; Note sig may also be nil for the last signal in the list | |
5982 (t | |
5983 (setq out-list | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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79555
diff
changeset
|
5984 (cons |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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79555
diff
changeset
|
5985 (list sv-name |
d3e3c91e18f6
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79555
diff
changeset
|
5986 (or sv-busstring |
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79555
diff
changeset
|
5987 (if sv-highbit |
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79555
diff
changeset
|
5988 (concat "[" (int-to-string sv-highbit) ":" |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
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79555
diff
changeset
|
5989 (int-to-string sv-lowbit) "]"))) |
79799
57956dd69d3f
(top-level): Fix spacing.
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parents:
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diff
changeset
|
5990 (concat sv-comment combo buswarn) |
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diff
changeset
|
5991 sv-memory sv-enum sv-signed sv-type sv-multidim) |
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(top-level): Fix spacing.
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diff
changeset
|
5992 out-list) |
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(top-level): Fix spacing.
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diff
changeset
|
5993 sv-name nil)))) |
79545 | 5994 ;; |
5995 out-list)) | |
5996 | |
5997 (defun verilog-sig-tieoff (sig &optional no-width) | |
79799
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(top-level): Fix spacing.
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diff
changeset
|
5998 "Return tieoff expression for given SIG, with appropriate width. |
79545 | 5999 Ignore width if optional NO-WIDTH is set." |
6000 (let* ((width (if no-width nil (verilog-sig-width sig)))) | |
6001 (concat | |
6002 (if (and verilog-active-low-regexp | |
6003 (string-match verilog-active-low-regexp (verilog-sig-name sig))) | |
6004 "~" "") | |
6005 (cond ((not width) | |
6006 "0") | |
6007 ((string-match "^[0-9]+$" width) | |
6008 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0"))) | |
6009 (t | |
6010 (concat "{" width "{1'b0}}")))))) | |
6011 | |
6012 ;; | |
6013 ;; Port/Wire/Etc Reading | |
6014 ;; | |
6015 | |
6016 (defun verilog-read-inst-backward-name () | |
6017 "Internal. Move point back to beginning of inst-name." | |
6018 (verilog-backward-open-paren) | |
6019 (let (done) | |
6020 (while (not done) | |
6021 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil) ; ] isn't word boundary | |
6022 (cond ((looking-at ")") | |
6023 (verilog-backward-open-paren)) | |
6024 (t (setq done t))))) | |
6025 (while (looking-at "\\]") | |
6026 (verilog-backward-open-bracket) | |
6027 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil)) | |
6028 (skip-chars-backward "a-zA-Z0-9`_$")) | |
6029 | |
6030 (defun verilog-read-inst-module () | |
6031 "Return module_name when point is inside instantiation." | |
6032 (save-excursion | |
6033 (verilog-read-inst-backward-name) | |
6034 ;; Skip over instantiation name | |
6035 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary | |
6036 ;; Check for parameterized instantiations | |
6037 (when (looking-at ")") | |
6038 (verilog-backward-open-paren) | |
6039 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil)) | |
6040 (skip-chars-backward "a-zA-Z0-9'_$") | |
6041 (looking-at "[a-zA-Z0-9`_\$]+") | |
6042 ;; Important: don't use match string, this must work with emacs 19 font-lock on | |
6043 (buffer-substring-no-properties (match-beginning 0) (match-end 0)))) | |
6044 | |
6045 (defun verilog-read-inst-name () | |
6046 "Return instance_name when point is inside instantiation." | |
6047 (save-excursion | |
6048 (verilog-read-inst-backward-name) | |
6049 (looking-at "[a-zA-Z0-9`_\$]+") | |
6050 ;; Important: don't use match string, this must work with emacs 19 font-lock on | |
6051 (buffer-substring-no-properties (match-beginning 0) (match-end 0)))) | |
6052 | |
6053 (defun verilog-read-module-name () | |
6054 "Return module name when after its ( or ;." | |
6055 (save-excursion | |
6056 (re-search-backward "[(;]") | |
6057 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil) | |
6058 (skip-chars-backward "a-zA-Z0-9`_$") | |
6059 (looking-at "[a-zA-Z0-9`_\$]+") | |
6060 ;; Important: don't use match string, this must work with emacs 19 font-lock on | |
6061 (buffer-substring-no-properties (match-beginning 0) (match-end 0)))) | |
6062 | |
6063 (defun verilog-read-auto-params (num-param &optional max-param) | |
6064 "Return parameter list inside auto. | |
6065 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters." | |
6066 (let ((olist)) | |
6067 (save-excursion | |
6068 ;; /*AUTOPUNT("parameter", "parameter")*/ | |
6069 (search-backward "(") | |
6070 (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?") | |
6071 (setq olist (cons (match-string 1) olist)) | |
6072 (goto-char (match-end 0)))) | |
6073 (or (eq nil num-param) | |
6074 (<= num-param (length olist)) | |
6075 (error "%s: Expected %d parameters" (verilog-point-text) num-param)) | |
6076 (if (eq max-param nil) (setq max-param num-param)) | |
6077 (or (eq nil max-param) | |
6078 (>= max-param (length olist)) | |
6079 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param)) | |
6080 (nreverse olist))) | |
6081 | |
6082 (defun verilog-read-decls () | |
6083 "Compute signal declaration information for the current module at point. | |
6084 Return a array of [outputs inouts inputs wire reg assign const]." | |
6085 (let ((end-mod-point (or (verilog-get-end-of-defun t) (point-max))) | |
6086 (functask 0) (paren 0) (sig-paren 0) | |
6087 sigs-in sigs-out sigs-inout sigs-wire sigs-reg sigs-assign sigs-const sigs-gparam | |
6088 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim) | |
6089 (save-excursion | |
6090 (verilog-beg-of-defun) | |
6091 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point)) | |
6092 (while (< (point) end-mod-point) | |
6093 ;;(if dbg (setq dbg (cons (format "Pt %s Vec %s Kwd'%s'\n" (point) vec keywd) dbg))) | |
6094 (cond | |
6095 ((looking-at "//") | |
6096 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)") | |
6097 (setq enum (match-string 1))) | |
6098 (search-forward "\n")) | |
6099 ((looking-at "/\\*") | |
6100 (forward-char 2) | |
6101 (if (looking-at "[^*]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)") | |
6102 (setq enum (match-string 1))) | |
6103 (or (search-forward "*/") | |
6104 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point)))) | |
6105 ((looking-at "(\\*") | |
6106 (forward-char 2) | |
6107 (or (looking-at "\\s-*)") ; It's a "always @ (*)" | |
6108 (search-forward "*)") | |
6109 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point)))) | |
6110 ((eq ?\" (following-char)) | |
6111 (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first | |
6112 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point)))) | |
6113 ((eq ?\; (following-char)) | |
6114 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil) | |
6115 (forward-char 1)) | |
6116 ((eq ?= (following-char)) | |
6117 (setq rvalue t newsig nil) | |
6118 (forward-char 1)) | |
6119 ((and (or rvalue sig-paren) | |
6120 (cond ((and (eq ?, (following-char)) | |
6121 (eq paren sig-paren)) | |
6122 (setq rvalue nil) | |
6123 (forward-char 1) | |
6124 t) | |
6125 ;; ,'s can occur inside {} & funcs | |
6126 ((looking-at "[{(]") | |
6127 (setq paren (1+ paren)) | |
6128 (forward-char 1) | |
6129 t) | |
6130 ((looking-at "[})]") | |
6131 (setq paren (1- paren)) | |
6132 (forward-char 1) | |
6133 (when (< paren sig-paren) | |
6134 (setq expect-signal nil)) ; ) that ends variables inside v2k arg list | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
6135 t)))) |
79545 | 6136 ((looking-at "\\s-*\\(\\[[^]]+\\]\\)") |
6137 (goto-char (match-end 0)) | |
6138 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3) | |
6139 (setcar (cdr (cdr (cdr newsig))) (match-string 1))) | |
6140 (vec ;; Multidimensional | |
6141 (setq multidim (cons vec multidim)) | |
6142 (setq vec (verilog-string-replace-matches | |
6143 "\\s-+" "" nil nil (match-string 1)))) | |
6144 (t ;; Bit width | |
6145 (setq vec (verilog-string-replace-matches | |
6146 "\\s-+" "" nil nil (match-string 1)))))) | |
6147 ;; Normal or escaped identifier -- note we remember the \ if escaped | |
6148 ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)") | |
6149 (goto-char (match-end 0)) | |
6150 (setq keywd (match-string 1)) | |
6151 (when (string-match "^\\\\" keywd) | |
6152 (setq keywd (concat keywd " "))) ;; Escaped ID needs space at end | |
6153 (cond ((equal keywd "input") | |
6154 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren | |
6155 expect-signal 'sigs-in io t)) | |
6156 ((equal keywd "output") | |
6157 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren | |
6158 expect-signal 'sigs-out io t)) | |
6159 ((equal keywd "inout") | |
6160 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren | |
6161 expect-signal 'sigs-inout io t)) | |
6162 ((or (equal keywd "wire") | |
6163 (equal keywd "tri") | |
6164 (equal keywd "tri0") | |
6165 (equal keywd "tri1")) | |
6166 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren | |
6167 expect-signal 'sigs-wire))) | |
6168 ((or (equal keywd "reg") | |
6169 (equal keywd "trireg")) | |
6170 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren | |
6171 expect-signal 'sigs-reg))) | |
6172 ((equal keywd "assign") | |
6173 (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren | |
6174 expect-signal 'sigs-assign)) | |
6175 ((or (equal keywd "supply0") | |
6176 (equal keywd "supply1") | |
6177 (equal keywd "supply") | |
80342
b7bed0a77336
(verilog-read-decls): Fix AUTOINPUT/AUTOOUTPUT mis-including genvars.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80270
diff
changeset
|
6178 (equal keywd "localparam") |
b7bed0a77336
(verilog-read-decls): Fix AUTOINPUT/AUTOOUTPUT mis-including genvars.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
80270
diff
changeset
|
6179 (equal keywd "genvar")) |
79545 | 6180 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren |
6181 expect-signal 'sigs-const))) | |
6182 ((or (equal keywd "parameter")) | |
6183 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren | |
6184 expect-signal 'sigs-gparam))) | |
6185 ((equal keywd "signed") | |
6186 (setq signed "signed")) | |
6187 ((or (equal keywd "function") | |
6188 (equal keywd "task")) | |
6189 (setq functask (1+ functask))) | |
6190 ((or (equal keywd "endfunction") | |
6191 (equal keywd "endtask")) | |
6192 (setq functask (1- functask))) | |
6193 ((or (equal keywd "`ifdef") | |
6194 (equal keywd "`ifndef")) | |
6195 (setq rvalue t)) | |
6196 ((verilog-typedef-name-p keywd) | |
6197 (setq typedefed keywd)) | |
6198 ((and expect-signal | |
6199 (eq functask 0) | |
6200 (not rvalue) | |
6201 (eq paren sig-paren) | |
6202 (not (member keywd verilog-keywords))) | |
6203 ;; Add new signal to expect-signal's variable | |
6204 (setq newsig (list keywd vec nil nil enum signed typedefed multidim)) | |
6205 (set expect-signal (cons newsig | |
6206 (symbol-value expect-signal)))))) | |
6207 (t | |
6208 (forward-char 1))) | |
6209 (skip-syntax-forward " ")) | |
6210 ;; Return arguments | |
6211 (vector (nreverse sigs-out) | |
6212 (nreverse sigs-inout) | |
6213 (nreverse sigs-in) | |
6214 (nreverse sigs-wire) | |
6215 (nreverse sigs-reg) | |
6216 (nreverse sigs-assign) | |
6217 (nreverse sigs-const) | |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
6218 (nreverse sigs-gparam))))) |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
6219 |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
6220 (eval-when-compile |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
6221 ;; Prevent compile warnings; these are let's, not globals |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
6222 ;; Do not remove the eval-when-compile |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
6223 ;; - we want a error when we are debugging this code if they are refed. |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
6224 (defvar sigs-in) |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
6225 (defvar sigs-inout) |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
6226 (defvar sigs-out)) |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6227 |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6228 |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6229 (defsubst verilog-modi-get-decls (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6230 (verilog-modi-cache-results modi 'verilog-read-decls)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6231 |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6232 (defsubst verilog-modi-get-sub-decls (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6233 (verilog-modi-cache-results modi 'verilog-read-sub-decls)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6234 |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6235 |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6236 ;; Signal reading for given module |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6237 ;; Note these all take modi's - as returned from the |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6238 ;; verilog-modi-current function. |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6239 (defsubst verilog-modi-get-outputs (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6240 (aref (verilog-modi-get-decls modi) 0)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6241 (defsubst verilog-modi-get-inouts (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6242 (aref (verilog-modi-get-decls modi) 1)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6243 (defsubst verilog-modi-get-inputs (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6244 (aref (verilog-modi-get-decls modi) 2)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6245 (defsubst verilog-modi-get-wires (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6246 (aref (verilog-modi-get-decls modi) 3)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6247 (defsubst verilog-modi-get-regs (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6248 (aref (verilog-modi-get-decls modi) 4)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6249 (defsubst verilog-modi-get-assigns (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6250 (aref (verilog-modi-get-decls modi) 5)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6251 (defsubst verilog-modi-get-consts (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6252 (aref (verilog-modi-get-decls modi) 6)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6253 (defsubst verilog-modi-get-gparams (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6254 (aref (verilog-modi-get-decls modi) 7)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6255 (defsubst verilog-modi-get-sub-outputs (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6256 (aref (verilog-modi-get-sub-decls modi) 0)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6257 (defsubst verilog-modi-get-sub-inouts (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6258 (aref (verilog-modi-get-sub-decls modi) 1)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
6259 (defsubst verilog-modi-get-sub-inputs (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6260 (aref (verilog-modi-get-sub-decls modi) 2)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6261 |
79545 | 6262 |
6263 (defun verilog-read-sub-decls-sig (submodi comment port sig vec multidim) | |
80165
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
6264 "For `verilog-read-sub-decls-line', add a signal." |
79545 | 6265 (let (portdata) |
6266 (when sig | |
6267 (setq port (verilog-symbol-detick-denumber port)) | |
6268 (setq sig (verilog-symbol-detick-denumber sig)) | |
6269 (if sig (setq sig (verilog-string-replace-matches "^[---+~!|&]+" "" nil nil sig))) | |
6270 (if vec (setq vec (verilog-symbol-detick-denumber vec))) | |
6271 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim))) | |
6272 (unless (or (not sig) | |
6273 (equal sig "")) ;; Ignore .foo(1'b1) assignments | |
6274 (cond ((setq portdata (assoc port (verilog-modi-get-inouts submodi))) | |
6275 (setq sigs-inout (cons (list sig vec (concat "To/From " comment) nil nil | |
6276 (verilog-sig-signed portdata) | |
6277 (verilog-sig-type portdata) | |
6278 multidim) | |
6279 sigs-inout))) | |
6280 ((setq portdata (assoc port (verilog-modi-get-outputs submodi))) | |
6281 (setq sigs-out (cons (list sig vec (concat "From " comment) nil nil | |
6282 (verilog-sig-signed portdata) | |
6283 (verilog-sig-type portdata) | |
6284 multidim) | |
6285 sigs-out))) | |
6286 ((setq portdata (assoc port (verilog-modi-get-inputs submodi))) | |
6287 (setq sigs-in (cons (list sig vec (concat "To " comment) nil nil | |
6288 (verilog-sig-signed portdata) | |
6289 (verilog-sig-type portdata) | |
6290 multidim) | |
6291 sigs-in))) | |
6292 ;; (t -- warning pin isn't defined.) ; Leave for lint tool | |
6293 ))))) | |
6294 | |
6295 (defun verilog-read-sub-decls-line (submodi comment) | |
80165
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
6296 "For `verilog-read-sub-decls', read lines of port defs until none match anymore. |
79545 | 6297 Return the list of signals found, using submodi to look up each port." |
6298 (let (done port sig vec multidim) | |
6299 (save-excursion | |
6300 (forward-line 1) | |
6301 (while (not done) | |
6302 ;; Get port name | |
6303 (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*") | |
6304 (setq port (match-string 1)) | |
6305 (goto-char (match-end 0))) | |
6306 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*") | |
6307 (setq port (concat (match-string 1) " ")) ;; escaped id's need trailing space | |
6308 (goto-char (match-end 0))) | |
6309 ((looking-at "\\s-*\\.[^(]*(") | |
6310 (setq port nil) ;; skip this line | |
6311 (goto-char (match-end 0))) | |
6312 (t | |
6313 (setq port nil done t))) ;; Unknown, ignore rest of line | |
6314 ;; Get signal name | |
6315 (when port | |
6316 (setq multidim nil) | |
6317 (cond ((looking-at "\\(\\\\[^ \t\n\f]*\\)\\s-*)") | |
6318 (setq sig (concat (match-string 1) " ") ;; escaped id's need trailing space | |
6319 vec nil)) | |
6320 ; We intentionally ignore (non-escaped) signals with .s in them | |
6321 ; this prevents AUTOWIRE etc from noticing hierarchical sigs. | |
6322 ((looking-at "\\([^[({).]*\\)\\s-*)") | |
6323 (setq sig (verilog-string-remove-spaces (match-string 1)) | |
6324 vec nil)) | |
6325 ((looking-at "\\([^[({).]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)") | |
6326 (setq sig (verilog-string-remove-spaces (match-string 1)) | |
6327 vec (match-string 2))) | |
6328 ((looking-at "\\([^[({).]*\\)\\s-*/\\*\\(\\[[^*]+\\]\\)\\*/\\s-*)") | |
6329 (setq sig (verilog-string-remove-spaces (match-string 1)) | |
6330 vec nil) | |
6331 (let ((parse (match-string 2))) | |
6332 (while (string-match "^\\(\\[[^]]+\\]\\)\\(.*\\)$" parse) | |
6333 (when vec (setq multidim (cons vec multidim))) | |
6334 (setq vec (match-string 1 parse)) | |
6335 (setq parse (match-string 2 parse))))) | |
6336 ((looking-at "{\\(.*\\)}.*\\s-*)") | |
6337 (let ((mlst (split-string (match-string 1) ",")) | |
6338 mstr) | |
6339 (while (setq mstr (pop mlst)) | |
6340 ;;(unless noninteractive (message "sig: %s " mstr)) | |
6341 (cond | |
6342 ((string-match "\\(['`a-zA-Z0-9_$]+\\)\\s-*$" mstr) | |
6343 (setq sig (verilog-string-remove-spaces (match-string 1 mstr)) | |
6344 vec nil) | |
6345 ;;(unless noninteractive (message "concat sig1: %s %s" mstr (match-string 1 mstr))) | |
6346 ) | |
6347 ((string-match "\\([^[({).]+\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*" mstr) | |
6348 (setq sig (verilog-string-remove-spaces (match-string 1 mstr)) | |
6349 vec (match-string 2 mstr)) | |
6350 ;;(unless noninteractive (message "concat sig2: '%s' '%s' '%s'" mstr (match-string 1 mstr) (match-string 2 mstr))) | |
6351 ) | |
6352 (t | |
6353 (setq sig nil))) | |
6354 ;; Process signals | |
6355 (verilog-read-sub-decls-sig submodi comment port sig vec multidim)))) | |
6356 (t | |
6357 (setq sig nil))) | |
6358 ;; Process signals | |
6359 (verilog-read-sub-decls-sig submodi comment port sig vec multidim)) | |
6360 ;; | |
6361 (forward-line 1))))) | |
6362 | |
6363 (defun verilog-read-sub-decls () | |
6364 "Internally parse signals going to modules under this module. | |
6365 Return a array of [ outputs inouts inputs ] signals for modules that are | |
6366 instantiated in this module. For example if declare A A (.B(SIG)) and SIG | |
6367 is a output, then SIG will be included in the list. | |
6368 | |
6369 This only works on instantiations created with /*AUTOINST*/ converted by | |
6370 \\[verilog-auto-inst]. Otherwise, it would have to read in the whole | |
6371 component library to determine connectivity of the design. | |
6372 | |
6373 One work around for this problem is to manually create // Inputs and // | |
6374 Outputs comments above subcell signals, for example: | |
6375 | |
6376 module1 instance1x ( | |
6377 // Outputs | |
6378 .out (out), | |
6379 // Inputs | |
6380 .in (in));" | |
6381 (save-excursion | |
6382 (let ((end-mod-point (verilog-get-end-of-defun t)) | |
6383 st-point end-inst-point | |
6384 ;; below 3 modified by verilog-read-sub-decls-line | |
6385 sigs-out sigs-inout sigs-in) | |
6386 (verilog-beg-of-defun) | |
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|
6387 (while (verilog-re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t) |
79545 | 6388 (save-excursion |
6389 (goto-char (match-beginning 0)) | |
6390 (unless (verilog-inside-comment-p) | |
6391 ;; Attempt to snarf a comment | |
6392 (let* ((submod (verilog-read-inst-module)) | |
6393 (inst (verilog-read-inst-name)) | |
6394 (comment (concat inst " of " submod ".v")) submodi) | |
6395 (when (setq submodi (verilog-modi-lookup submod t)) | |
6396 ;; This could have used a list created by verilog-auto-inst | |
6397 ;; However I want it to be runnable even on user's manually added signals | |
6398 (verilog-backward-open-paren) | |
6399 (setq end-inst-point (save-excursion (forward-sexp 1) (point)) | |
6400 st-point (point)) | |
6401 (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t) | |
6402 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-out | |
6403 (goto-char st-point) | |
6404 (while (re-search-forward "\\s *// Inouts" end-inst-point t) | |
6405 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-inout | |
6406 (goto-char st-point) | |
6407 (while (re-search-forward "\\s *// Inputs" end-inst-point t) | |
6408 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-in | |
6409 ))))) | |
6410 ;; Combine duplicate bits | |
6411 ;;(setq rr (vector sigs-out sigs-inout sigs-in)) | |
6412 (vector (verilog-signals-combine-bus (nreverse sigs-out)) | |
6413 (verilog-signals-combine-bus (nreverse sigs-inout)) | |
6414 (verilog-signals-combine-bus (nreverse sigs-in)))))) | |
6415 | |
6416 (defun verilog-read-inst-pins () | |
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diff
changeset
|
6417 "Return an array of [ pins ] for the current instantiation at point. |
79545 | 6418 For example if declare A A (.B(SIG)) then B will be included in the list." |
6419 (save-excursion | |
6420 (let ((end-mod-point (point)) ;; presume at /*AUTOINST*/ point | |
6421 pins pin) | |
6422 (verilog-backward-open-paren) | |
6423 (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t) | |
6424 (setq pin (match-string 1)) | |
6425 (unless (verilog-inside-comment-p) | |
6426 (setq pins (cons (list pin) pins)) | |
6427 (when (looking-at "(") | |
6428 (forward-sexp 1)))) | |
6429 (vector pins)))) | |
6430 | |
6431 (defun verilog-read-arg-pins () | |
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80163
diff
changeset
|
6432 "Return an array of [ pins ] for the current argument declaration at point." |
79545 | 6433 (save-excursion |
6434 (let ((end-mod-point (point)) ;; presume at /*AUTOARG*/ point | |
6435 pins pin) | |
6436 (verilog-backward-open-paren) | |
6437 (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t) | |
6438 (setq pin (match-string 1)) | |
6439 (unless (verilog-inside-comment-p) | |
6440 (setq pins (cons (list pin) pins)))) | |
6441 (vector pins)))) | |
6442 | |
6443 (defun verilog-read-auto-constants (beg end-mod-point) | |
6444 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT." | |
6445 ;; Insert new | |
6446 (save-excursion | |
6447 (let (sig-list tpl-end-pt) | |
6448 (goto-char beg) | |
6449 (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t) | |
6450 (if (not (looking-at "\\s *(")) | |
6451 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text))) | |
6452 (search-forward "(" end-mod-point) | |
6453 (setq tpl-end-pt (save-excursion | |
6454 (backward-char 1) | |
6455 (forward-sexp 1) ;; Moves to paren that closes argdecl's | |
6456 (backward-char 1) | |
6457 (point))) | |
6458 (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t) | |
6459 (setq sig-list (cons (list (match-string 1) nil nil) sig-list)))) | |
6460 sig-list))) | |
6461 | |
6462 (defun verilog-read-auto-lisp (start end) | |
6463 "Look for and evaluate a AUTO_LISP between START and END." | |
6464 (save-excursion | |
6465 (goto-char start) | |
6466 (while (re-search-forward "\\<AUTO_LISP(" end t) | |
6467 (backward-char) | |
6468 (let* ((beg-pt (prog1 (point) | |
6469 (forward-sexp 1))) ;; Closing paren | |
6470 (end-pt (point))) | |
6471 (eval-region beg-pt end-pt nil))))) | |
6472 | |
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diff
changeset
|
6473 (eval-when-compile |
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parents:
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diff
changeset
|
6474 ;; Prevent compile warnings; these are let's, not globals |
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parents:
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diff
changeset
|
6475 ;; Do not remove the eval-when-compile |
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diff
changeset
|
6476 ;; - we want a error when we are debugging this code if they are refed. |
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parents:
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diff
changeset
|
6477 (defvar sigs-in) |
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parents:
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diff
changeset
|
6478 (defvar sigs-out) |
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parents:
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diff
changeset
|
6479 (defvar got-sig) |
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parents:
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diff
changeset
|
6480 (defvar got-rvalue) |
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parents:
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diff
changeset
|
6481 (defvar uses-delayed) |
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diff
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|
6482 (defvar vector-skip-list)) |
79545 | 6483 |
6484 (defun verilog-read-always-signals-recurse | |
6485 (exit-keywd rvalue ignore-next) | |
6486 "Recursive routine for parentheses/bracket matching. | |
6487 EXIT-KEYWD is expression to stop at, nil if top level. | |
6488 RVALUE is true if at right hand side of equal. | |
6489 IGNORE-NEXT is true to ignore next token, fake from inside case statement." | |
6490 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ;; true if after a ; we are looking for rvalue | |
6491 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-rvalue end-else-check) | |
6492 ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue ignore-next)))) | |
6493 (while (not (or (eobp) gotend)) | |
6494 (cond | |
6495 ((looking-at "//") | |
6496 (search-forward "\n")) | |
6497 ((looking-at "/\\*") | |
6498 (or (search-forward "*/") | |
6499 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point)))) | |
6500 ((looking-at "(\\*") | |
6501 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)" | |
6502 (search-forward "*)") | |
6503 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point)))) | |
6504 (t (setq keywd (buffer-substring-no-properties | |
6505 (point) | |
6506 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`")) | |
6507 (forward-char 1)) | |
6508 (point))) | |
6509 sig-last-tolk sig-tolk | |
6510 sig-tolk nil) | |
6511 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S\n" (point) keywd rvalue ignore-next end-else-check)))) | |
6512 (cond | |
6513 ((equal keywd "\"") | |
6514 (or (re-search-forward "[^\\]\"" nil t) | |
6515 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point)))) | |
6516 ;; else at top level loop, keep parsing | |
6517 ((and end-else-check (equal keywd "else")) | |
6518 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd)))) | |
6519 ;; no forward movement, want to see else in lower loop | |
6520 (setq end-else-check nil)) | |
6521 ;; End at top level loop | |
6522 ((and end-else-check (looking-at "[^ \t\n\f]")) | |
6523 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd)))) | |
6524 (setq gotend t)) | |
6525 ;; Final statement? | |
6526 ((and exit-keywd (equal keywd exit-keywd)) | |
6527 (setq gotend t) | |
6528 (forward-char (length keywd))) | |
6529 ;; Standard tokens... | |
6530 ((equal keywd ";") | |
6531 (setq ignore-next nil rvalue semi-rvalue) | |
6532 ;; Final statement at top level loop? | |
6533 (when (not exit-keywd) | |
6534 ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd)))) | |
6535 (setq end-else-check t)) | |
6536 (forward-char 1)) | |
6537 ((equal keywd "'") | |
6538 (if (looking-at "'s?[hdxbo][0-9a-fA-F_xz? \t]*") | |
6539 (goto-char (match-end 0)) | |
6540 (forward-char 1))) | |
6541 ((equal keywd ":") ;; Case statement, begin/end label, x?y:z | |
6542 (cond ((equal "endcase" exit-keywd) ;; case x: y=z; statement next | |
6543 (setq ignore-next nil rvalue nil)) | |
6544 ((equal "?" exit-keywd) ;; x?y:z rvalue | |
6545 ) ;; NOP | |
6546 (got-sig ;; label: statement | |
6547 (setq ignore-next nil rvalue semi-rvalue got-sig nil)) | |
6548 ((not rvalue) ;; begin label | |
6549 (setq ignore-next t rvalue nil))) | |
6550 (forward-char 1)) | |
6551 ((equal keywd "=") | |
6552 (if (eq (char-before) ?< ) | |
6553 (setq uses-delayed 1)) | |
6554 (setq ignore-next nil rvalue t) | |
6555 (forward-char 1)) | |
6556 ((equal keywd "?") | |
6557 (forward-char 1) | |
6558 (verilog-read-always-signals-recurse ":" rvalue nil)) | |
6559 ((equal keywd "[") | |
6560 (forward-char 1) | |
6561 (verilog-read-always-signals-recurse "]" t nil)) | |
6562 ((equal keywd "(") | |
6563 (forward-char 1) | |
6564 (cond (sig-last-tolk ;; Function call; zap last signal | |
6565 (setq got-sig nil))) | |
6566 (cond ((equal last-keywd "for") | |
6567 (verilog-read-always-signals-recurse ";" nil nil) | |
6568 (verilog-read-always-signals-recurse ";" t nil) | |
6569 (verilog-read-always-signals-recurse ")" nil nil)) | |
6570 (t (verilog-read-always-signals-recurse ")" t nil)))) | |
6571 ((equal keywd "begin") | |
6572 (skip-syntax-forward "w_") | |
6573 (verilog-read-always-signals-recurse "end" nil nil) | |
6574 ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd)))) | |
6575 (setq ignore-next nil rvalue semi-rvalue) | |
6576 (if (not exit-keywd) (setq end-else-check t))) | |
6577 ((or (equal keywd "case") | |
6578 (equal keywd "casex") | |
6579 (equal keywd "casez")) | |
6580 (skip-syntax-forward "w_") | |
6581 (verilog-read-always-signals-recurse "endcase" t nil) | |
6582 (setq ignore-next nil rvalue semi-rvalue) | |
6583 (if (not exit-keywd) (setq gotend t))) ;; top level begin/end | |
6584 ((string-match "^[$`a-zA-Z_]" keywd) ;; not exactly word constituent | |
6585 (cond ((or (equal keywd "`ifdef") | |
6586 (equal keywd "`ifndef")) | |
6587 (setq ignore-next t)) | |
6588 ((or ignore-next | |
6589 (member keywd verilog-keywords) | |
6590 (string-match "^\\$" keywd)) ;; PLI task | |
6591 (setq ignore-next nil)) | |
6592 (t | |
6593 (setq keywd (verilog-symbol-detick-denumber keywd)) | |
6594 (when got-sig | |
6595 (if got-rvalue (setq sigs-in (cons got-sig sigs-in)) | |
6596 (setq sigs-out (cons got-sig sigs-out))) | |
6597 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue)))) | |
6598 ) | |
6599 (setq got-rvalue rvalue | |
6600 got-sig (if (or (not keywd) | |
6601 (assoc keywd (if got-rvalue sigs-in sigs-out))) | |
6602 nil (list keywd nil nil)) | |
6603 sig-tolk t))) | |
6604 (skip-chars-forward "a-zA-Z0-9$_.%`")) | |
6605 (t | |
6606 (forward-char 1))) | |
6607 ;; End of non-comment token | |
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parents:
79717
diff
changeset
|
6608 (setq last-keywd keywd))) |
79545 | 6609 (skip-syntax-forward " ")) |
6610 ;; Append the final pending signal | |
6611 (when got-sig | |
6612 (if got-rvalue (setq sigs-in (cons got-sig sigs-in)) | |
6613 (setq sigs-out (cons got-sig sigs-out))) | |
6614 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue)))) | |
6615 (setq got-sig nil)) | |
6616 ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd)))) | |
6617 )) | |
6618 | |
6619 (defun verilog-read-always-signals () | |
6620 "Parse always block at point and return list of (outputs inout inputs)." | |
6621 ;; Insert new | |
6622 (save-excursion | |
6623 (let* (;;(dbg "") | |
6624 sigs-in sigs-out | |
6625 uses-delayed) ;; Found signal/rvalue; push if not function | |
6626 (search-forward ")") | |
6627 (verilog-read-always-signals-recurse nil nil nil) | |
6628 ;;(if dbg (save-excursion (set-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg ""))) | |
6629 ;; Return what was found | |
6630 (list sigs-out nil sigs-in uses-delayed)))) | |
6631 | |
6632 (defun verilog-read-instants () | |
6633 "Parse module at point and return list of ( ( file instance ) ... )." | |
6634 (verilog-beg-of-defun) | |
6635 (let* ((end-mod-point (verilog-get-end-of-defun t)) | |
6636 (state nil) | |
6637 (instants-list nil)) | |
6638 (save-excursion | |
6639 (while (< (point) end-mod-point) | |
6640 ;; Stay at level 0, no comments | |
6641 (while (progn | |
6642 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil)) | |
6643 (or (> (car state) 0) ; in parens | |
6644 (nth 5 state) ; comment | |
6645 )) | |
6646 (forward-line 1)) | |
6647 (beginning-of-line) | |
6648 (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(") | |
6649 ;;(if (looking-at "^\\(.+\\)$") | |
6650 (let ((module (match-string 1)) | |
6651 (instant (match-string 2))) | |
6652 (if (not (member module verilog-keywords)) | |
6653 (setq instants-list (cons (list module instant) instants-list))))) | |
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parents:
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diff
changeset
|
6654 (forward-line 1))) |
79545 | 6655 instants-list)) |
6656 | |
6657 | |
6658 (defun verilog-read-auto-template (module) | |
6659 "Look for a auto_template for the instantiation of the given MODULE. | |
6660 If found returns the signal name connections. Return REGEXP and | |
80165
411da0873a97
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diff
changeset
|
6661 list of ( (signal_name connection_name)... )." |
79545 | 6662 (save-excursion |
6663 ;; Find beginning | |
6664 (let ((tpl-regexp "\\([0-9]+\\)") | |
6665 (lineno 0) | |
6666 (templateno 0) | |
6667 tpl-sig-list tpl-wild-list tpl-end-pt rep) | |
6668 (cond ((or | |
6669 (re-search-backward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t) | |
6670 (progn | |
6671 (goto-char (point-min)) | |
6672 (re-search-forward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t))) | |
6673 (goto-char (match-end 0)) | |
6674 ;; Parse "REGEXP" | |
6675 ;; We reserve @"..." for future lisp expressions that evaluate once-per-AUTOINST | |
6676 (when (looking-at "\\s-*\"\\([^\"]*)\\)\"") | |
6677 (setq tpl-regexp (match-string 1)) | |
6678 (goto-char (match-end 0))) | |
6679 (search-forward "(") | |
6680 ;; Parse lines in the template | |
6681 (when verilog-auto-inst-template-numbers | |
6682 (save-excursion | |
6683 (goto-char (point-min)) | |
6684 (while (search-forward "AUTO_TEMPLATE" nil t) | |
6685 (setq templateno (1+ templateno))))) | |
6686 (setq tpl-end-pt (save-excursion | |
6687 (backward-char 1) | |
6688 (forward-sexp 1) ;; Moves to paren that closes argdecl's | |
6689 (backward-char 1) | |
6690 (point))) | |
6691 ;; | |
6692 (while (< (point) tpl-end-pt) | |
6693 (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)") | |
6694 (setq tpl-sig-list (cons (list | |
6695 (match-string-no-properties 1) | |
6696 (match-string-no-properties 2) | |
6697 templateno lineno) | |
6698 tpl-sig-list)) | |
6699 (goto-char (match-end 0))) | |
6700 ;; Regexp form?? | |
6701 ((looking-at | |
6702 ;; Regexp bug in xemacs disallows ][ inside [], and wants + last | |
6703 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)") | |
6704 (setq rep (match-string-no-properties 3)) | |
6705 (goto-char (match-end 0)) | |
6706 (setq tpl-wild-list | |
6707 (cons (list | |
6708 (concat "^" | |
6709 (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil | |
6710 (match-string 1)) | |
6711 "$") | |
6712 rep | |
6713 templateno lineno) | |
6714 tpl-wild-list))) | |
6715 ((looking-at "[ \t\f]+") | |
6716 (goto-char (match-end 0))) | |
6717 ((looking-at "\n") | |
6718 (setq lineno (1+ lineno)) | |
6719 (goto-char (match-end 0))) | |
6720 ((looking-at "//") | |
6721 (search-forward "\n")) | |
6722 ((looking-at "/\\*") | |
6723 (forward-char 2) | |
6724 (or (search-forward "*/") | |
6725 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point)))) | |
6726 (t | |
6727 (error "%s: AUTO_TEMPLATE parsing error: %s" | |
6728 (verilog-point-text) | |
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6729 (progn (looking-at ".*$") (match-string 0)))))) |
79545 | 6730 ;; Return |
6731 (vector tpl-regexp | |
6732 (list tpl-sig-list tpl-wild-list))) | |
6733 ;; If no template found | |
6734 (t (vector tpl-regexp nil)))))) | |
6735 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry")) | |
6736 | |
6737 (defun verilog-set-define (defname defvalue &optional buffer enumname) | |
6738 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER. | |
6739 Optionally associate it with the specified enumeration ENUMNAME." | |
6740 (save-excursion | |
6741 (set-buffer (or buffer (current-buffer))) | |
6742 (let ((mac (intern (concat "vh-" defname)))) | |
6743 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1) | |
6744 ;; Need to define to a constant if no value given | |
6745 (set (make-variable-buffer-local mac) | |
6746 (if (equal defvalue "") "1" defvalue))) | |
6747 (if enumname | |
6748 (let ((enumvar (intern (concat "venum-" enumname)))) | |
6749 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1) | |
6750 (make-variable-buffer-local enumvar) | |
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|
6751 (add-to-list enumvar defname))))) |
79545 | 6752 |
6753 (defun verilog-read-defines (&optional filename recurse subcall) | |
6754 "Read `defines and parameters for the current file, or optional FILENAME. | |
6755 If the filename is provided, `verilog-library-flags' will be used to | |
6756 resolve it. If optional RECURSE is non-nil, recurse through `includes. | |
6757 | |
6758 Parameters must be simple assignments to constants, or have their own | |
6759 \"parameter\" label rather than a list of parameters. Thus: | |
6760 | |
6761 parameter X = 5, Y = 10; // Ok | |
6762 parameter X = {1'b1, 2'h2}; // Ok | |
6763 parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines | |
6764 | |
6765 Defines must be simple text substitutions, one on a line, starting | |
6766 at the beginning of the line. Any ifdefs or multiline comments around the | |
6767 define are ignored. | |
6768 | |
6769 Defines are stored inside Emacs variables using the name vh-{definename}. | |
6770 | |
6771 This function is useful for setting vh-* variables. The file variables | |
6772 feature can be used to set defines that `verilog-mode' can see; put at the | |
6773 *END* of your file something like: | |
6774 | |
6775 // Local Variables: | |
6776 // vh-macro:\"macro_definition\" | |
6777 // End: | |
6778 | |
6779 If macros are defined earlier in the same file and you want their values, | |
6780 you can read them automatically (provided `enable-local-eval' is on): | |
6781 | |
6782 // Local Variables: | |
6783 // eval:(verilog-read-defines) | |
6784 // eval:(verilog-read-defines \"group_standard_includes.v\") | |
6785 // End: | |
6786 | |
6787 Note these are only read when the file is first visited, you must use | |
6788 \\[find-alternate-file] RET to have these take effect after editing them! | |
6789 | |
6790 If you want to disable the \"Process `eval' or hook local variables\" | |
6791 warning message, you need to add to your .emacs file: | |
6792 | |
6793 (setq enable-local-eval t)" | |
6794 (let ((origbuf (current-buffer))) | |
6795 (save-excursion | |
6796 (unless subcall (verilog-getopt-flags)) | |
6797 (when filename | |
6798 (let ((fns (verilog-library-filenames filename (buffer-file-name)))) | |
6799 (if fns | |
6800 (set-buffer (find-file-noselect (car fns))) | |
6801 (error (concat (verilog-point-text) | |
6802 ": Can't find verilog-read-defines file: " filename))))) | |
6803 (when recurse | |
6804 (goto-char (point-min)) | |
6805 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t) | |
6806 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string-no-properties 1)))) | |
6807 (unless (verilog-inside-comment-p) | |
6808 (verilog-read-defines inc recurse t))))) | |
6809 ;; Read `defines | |
6810 ;; note we don't use verilog-re... it's faster this way, and that | |
6811 ;; function has problems when comments are at the end of the define | |
6812 (goto-char (point-min)) | |
6813 (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t) | |
6814 (let ((defname (match-string-no-properties 1)) | |
6815 (defvalue (match-string-no-properties 2))) | |
6816 (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue)) | |
6817 (verilog-set-define defname defvalue origbuf))) | |
6818 ;; Hack: Read parameters | |
6819 (goto-char (point-min)) | |
6820 (while (re-search-forward | |
6821 "^\\s-*\\(parameter\\|localparam\\)\\(\\(\\s-*\\[[^]]*\\]\\|\\)\\s-+\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\|\\)\\s-*" nil t) | |
6822 (let ((var (match-string-no-properties 4)) | |
6823 (val (match-string-no-properties 5)) | |
6824 enumname) | |
6825 ;; The primary way of getting defines is verilog-read-decls | |
6826 ;; However, that isn't called yet for included files, so we'll add another scheme | |
6827 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)") | |
6828 (setq enumname (match-string-no-properties 1))) | |
6829 (if var | |
6830 (verilog-set-define var val origbuf enumname)) | |
6831 (forward-comment 999) | |
6832 (while (looking-at "\\s-*,?\\s-*\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\s-*") | |
6833 (verilog-set-define (match-string-no-properties 1) (match-string-no-properties 2) origbuf enumname) | |
6834 (goto-char (match-end 0)) | |
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diff
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|
6835 (forward-comment 999))))))) |
79545 | 6836 |
6837 (defun verilog-read-includes () | |
6838 "Read `includes for the current file. | |
6839 This will find all of the `includes which are at the beginning of lines, | |
6840 ignoring any ifdefs or multiline comments around them. | |
6841 `verilog-read-defines' is then performed on the current and each included | |
6842 file. | |
6843 | |
6844 It is often useful put at the *END* of your file something like: | |
6845 | |
6846 // Local Variables: | |
6847 // eval:(verilog-read-defines) | |
6848 // eval:(verilog-read-includes) | |
6849 // End: | |
6850 | |
6851 Note includes are only read when the file is first visited, you must use | |
6852 \\[find-alternate-file] RET to have these take effect after editing them! | |
6853 | |
6854 It is good to get in the habit of including all needed files in each .v | |
6855 file that needs it, rather than waiting for compile time. This will aid | |
6856 this process, Verilint, and readability. To prevent defining the same | |
6857 variable over and over when many modules are compiled together, put a test | |
6858 around the inside each include file: | |
6859 | |
6860 foo.v (a include): | |
6861 `ifdef _FOO_V // include if not already included | |
6862 `else | |
6863 `define _FOO_V | |
6864 ... contents of file | |
6865 `endif // _FOO_V" | |
6866 ;;slow: (verilog-read-defines nil t)) | |
6867 (save-excursion | |
6868 (verilog-getopt-flags) | |
6869 (goto-char (point-min)) | |
6870 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t) | |
6871 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1)))) | |
6872 (verilog-read-defines inc nil t))))) | |
6873 | |
6874 (defun verilog-read-signals (&optional start end) | |
6875 "Return a simple list of all possible signals in the file. | |
6876 Bounded by optional region from START to END. Overly aggressive but fast. | |
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|
6877 Some macros and such are also found and included. For dinotrace.el." |
79545 | 6878 (let (sigs-all keywd) |
6879 (progn;save-excursion | |
6880 (goto-char (or start (point-min))) | |
6881 (setq end (or end (point-max))) | |
6882 (while (re-search-forward "[\"/a-zA-Z_.%`]" end t) | |
6883 (forward-char -1) | |
6884 (cond | |
6885 ((looking-at "//") | |
6886 (search-forward "\n")) | |
6887 ((looking-at "/\\*") | |
6888 (search-forward "*/")) | |
6889 ((looking-at "(\\*") | |
6890 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)" | |
6891 (search-forward "*)"))) | |
6892 ((eq ?\" (following-char)) | |
6893 (re-search-forward "[^\\]\"")) ;; don't forward-char first, since we look for a non backslash first | |
6894 ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)") | |
6895 (goto-char (match-end 0)) | |
6896 (setq keywd (match-string-no-properties 1)) | |
6897 (or (member keywd verilog-keywords) | |
6898 (member keywd sigs-all) | |
6899 (setq sigs-all (cons keywd sigs-all)))) | |
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6900 (t (forward-char 1)))) |
79545 | 6901 ;; Return list |
6902 sigs-all))) | |
6903 | |
6904 ;; | |
6905 ;; Argument file parsing | |
6906 ;; | |
6907 | |
6908 (defun verilog-getopt (arglist) | |
6909 "Parse -f, -v etc arguments in ARGLIST list or string." | |
6910 (unless (listp arglist) (setq arglist (list arglist))) | |
6911 (let ((space-args '()) | |
6912 arg next-param) | |
6913 ;; Split on spaces, so users can pass whole command lines | |
6914 (while arglist | |
6915 (setq arg (car arglist) | |
6916 arglist (cdr arglist)) | |
6917 (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg) | |
6918 (setq space-args (append space-args | |
6919 (list (match-string-no-properties 1 arg)))) | |
6920 (setq arg (match-string 2 arg)))) | |
6921 ;; Parse arguments | |
6922 (while space-args | |
6923 (setq arg (car space-args) | |
6924 space-args (cdr space-args)) | |
6925 (cond | |
6926 ;; Need another arg | |
6927 ((equal arg "-f") | |
6928 (setq next-param arg)) | |
6929 ((equal arg "-v") | |
6930 (setq next-param arg)) | |
6931 ((equal arg "-y") | |
6932 (setq next-param arg)) | |
6933 ;; +libext+(ext1)+(ext2)... | |
6934 ((string-match "^\\+libext\\+\\(.*\\)" arg) | |
6935 (setq arg (match-string 1 arg)) | |
6936 (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg) | |
6937 (verilog-add-list-unique `verilog-library-extensions | |
6938 (match-string 1 arg)) | |
6939 (setq arg (match-string 2 arg)))) | |
6940 ;; | |
6941 ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; -Ddefine=val | |
6942 (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ;; -Ddefine | |
6943 (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; +define+val | |
6944 (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ;; +define+define | |
6945 (verilog-set-define (match-string 1 arg) (match-string 2 arg))) | |
6946 ;; | |
6947 ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ;; +incdir+dir | |
6948 (string-match "^-I\\(.*\\)" arg)) ;; -Idir | |
6949 (verilog-add-list-unique `verilog-library-directories | |
6950 (match-string 1 arg))) | |
6951 ;; Ignore | |
6952 ((equal "+librescan" arg)) | |
6953 ((string-match "^-U\\(.*\\)" arg)) ;; -Udefine | |
6954 ;; Second parameters | |
6955 ((equal next-param "-f") | |
6956 (setq next-param nil) | |
6957 (verilog-getopt-file arg)) | |
6958 ((equal next-param "-v") | |
6959 (setq next-param nil) | |
6960 (verilog-add-list-unique `verilog-library-files arg)) | |
6961 ((equal next-param "-y") | |
6962 (setq next-param nil) | |
6963 (verilog-add-list-unique `verilog-library-directories arg)) | |
6964 ;; Filename | |
6965 ((string-match "^[^-+]" arg) | |
6966 (verilog-add-list-unique `verilog-library-files arg)) | |
6967 ;; Default - ignore; no warning | |
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|
6968 )))) |
79545 | 6969 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir")) |
6970 | |
6971 (defun verilog-getopt-file (filename) | |
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diff
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|
6972 "Read Verilog options from the specified FILENAME." |
79545 | 6973 (save-excursion |
6974 (let ((fns (verilog-library-filenames filename (buffer-file-name))) | |
6975 (orig-buffer (current-buffer)) | |
6976 line) | |
6977 (if fns | |
6978 (set-buffer (find-file-noselect (car fns))) | |
6979 (error (concat (verilog-point-text) | |
6980 "Can't find verilog-getopt-file -f file: " filename))) | |
6981 (goto-char (point-min)) | |
6982 (while (not (eobp)) | |
6983 (setq line (buffer-substring (point) | |
6984 (save-excursion (end-of-line) (point)))) | |
6985 (forward-line 1) | |
6986 (when (string-match "//" line) | |
6987 (setq line (substring line 0 (match-beginning 0)))) | |
6988 (save-excursion | |
6989 (set-buffer orig-buffer) ; Variables are buffer-local, so need right context. | |
6990 (verilog-getopt line)))))) | |
6991 | |
6992 (defun verilog-getopt-flags () | |
6993 "Convert `verilog-library-flags' into standard library variables." | |
6994 ;; If the flags are local, then all the outputs should be local also | |
6995 (when (local-variable-p `verilog-library-flags (current-buffer)) | |
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79555
diff
changeset
|
6996 (mapc 'make-local-variable '(verilog-library-extensions |
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79555
diff
changeset
|
6997 verilog-library-directories |
d3e3c91e18f6
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79555
diff
changeset
|
6998 verilog-library-files |
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changeset
|
6999 verilog-library-flags))) |
79545 | 7000 ;; Allow user to customize |
7001 (run-hooks 'verilog-before-getopt-flags-hook) | |
7002 ;; Process arguments | |
7003 (verilog-getopt verilog-library-flags) | |
7004 ;; Allow user to customize | |
7005 (run-hooks 'verilog-getopt-flags-hook)) | |
7006 | |
7007 (defun verilog-add-list-unique (varref object) | |
7008 "Append to VARREF list the given OBJECT, | |
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changeset
|
7009 unless it is already a member of the variable's list." |
79545 | 7010 (unless (member object (symbol-value varref)) |
7011 (set varref (append (symbol-value varref) (list object)))) | |
7012 varref) | |
7013 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l) | |
7014 | |
7015 | |
7016 ;; | |
7017 ;; Module name lookup | |
7018 ;; | |
7019 | |
7020 (defun verilog-module-inside-filename-p (module filename) | |
7021 "Return point if MODULE is specified inside FILENAME, else nil. | |
7022 Allows version control to check out the file if need be." | |
7023 (and (or (file-exists-p filename) | |
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79555
diff
changeset
|
7024 (and (fboundp 'vc-backend) |
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diff
changeset
|
7025 (vc-backend filename))) |
79545 | 7026 (let (pt) |
7027 (save-excursion | |
7028 (set-buffer (find-file-noselect filename)) | |
7029 (goto-char (point-min)) | |
7030 (while (and | |
7031 ;; It may be tempting to look for verilog-defun-re, don't, it slows things down a lot! | |
7032 (verilog-re-search-forward-quick "\\<module\\>" nil t) | |
7033 (verilog-re-search-forward-quick "[(;]" nil t)) | |
7034 (if (equal module (verilog-read-module-name)) | |
7035 (setq pt (point)))) | |
7036 pt)))) | |
7037 | |
7038 (defun verilog-is-number (symbol) | |
7039 "Return true if SYMBOL is number-like." | |
7040 (or (string-match "^[0-9 \t:]+$" symbol) | |
7041 (string-match "^[---]*[0-9]+$" symbol) | |
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7042 (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol))) |
79545 | 7043 |
7044 (defun verilog-symbol-detick (symbol wing-it) | |
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diff
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|
7045 "Return an expanded SYMBOL name without any defines. |
79545 | 7046 If the variable vh-{symbol} is defined, return that value. |
7047 If undefined, and WING-IT, return just SYMBOL without the tick, else nil." | |
7048 (while (and symbol (string-match "^`" symbol)) | |
7049 (setq symbol (substring symbol 1)) | |
7050 (setq symbol | |
7051 (if (boundp (intern (concat "vh-" symbol))) | |
7052 ;; Emacs has a bug where boundp on a buffer-local | |
7053 ;; variable in only one buffer returns t in another. | |
7054 ;; This can confuse, so check for nil. | |
7055 (let ((val (eval (intern (concat "vh-" symbol))))) | |
7056 (if (eq val nil) | |
7057 (if wing-it symbol nil) | |
7058 val)) | |
7059 (if wing-it symbol nil)))) | |
7060 symbol) | |
7061 ;;(verilog-symbol-detick "`mod" nil) | |
7062 | |
7063 (defun verilog-symbol-detick-denumber (symbol) | |
7064 "Return SYMBOL with defines converted and any numbers dropped to nil." | |
7065 (when (string-match "^`" symbol) | |
7066 ;; This only will work if the define is a simple signal, not | |
7067 ;; something like a[b]. Sorry, it should be substituted into the parser | |
7068 (setq symbol | |
7069 (verilog-string-replace-matches | |
7070 "\[[^0-9: \t]+\]" "" nil nil | |
7071 (or (verilog-symbol-detick symbol nil) | |
7072 (if verilog-auto-sense-defines-constant | |
7073 "0" | |
7074 symbol))))) | |
7075 (if (verilog-is-number symbol) | |
7076 nil | |
7077 symbol)) | |
7078 | |
7079 (defun verilog-symbol-detick-text (text) | |
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diff
changeset
|
7080 "Return TEXT without any known defines. |
79545 | 7081 If the variable vh-{symbol} is defined, substitute that value." |
7082 (let ((ok t) symbol val) | |
7083 (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text)) | |
7084 (setq symbol (match-string 1 text)) | |
7085 (message symbol) | |
7086 (cond ((and | |
7087 (boundp (intern (concat "vh-" symbol))) | |
7088 ;; Emacs has a bug where boundp on a buffer-local | |
7089 ;; variable in only one buffer returns t in another. | |
7090 ;; This can confuse, so check for nil. | |
7091 (setq val (eval (intern (concat "vh-" symbol))))) | |
7092 (setq text (replace-match val nil nil text))) | |
7093 (t (setq ok nil))))) | |
7094 text) | |
7095 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed")) | |
7096 | |
7097 (defun verilog-expand-dirnames (&optional dirnames) | |
7098 "Return a list of existing directories given a list of wildcarded DIRNAMES. | |
7099 Or, just the existing dirnames themselves if there are no wildcards." | |
7100 (interactive) | |
7101 (unless dirnames (error "`verilog-library-directories' should include at least '.'")) | |
7102 (setq dirnames (reverse dirnames)) ; not nreverse | |
7103 (let ((dirlist nil) | |
7104 pattern dirfile dirfiles dirname root filename rest) | |
7105 (while dirnames | |
7106 (setq dirname (substitute-in-file-name (car dirnames)) | |
7107 dirnames (cdr dirnames)) | |
7108 (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ;; root | |
7109 "\\([^/\\]*[*?][^/\\]*\\)" ;; filename with *? | |
7110 "\\(.*\\)") ;; rest | |
7111 dirname) | |
7112 (setq root (match-string 1 dirname) | |
7113 filename (match-string 2 dirname) | |
7114 rest (match-string 3 dirname) | |
7115 pattern filename) | |
7116 ;; now replace those * and ? with .+ and . | |
7117 ;; use ^ and /> to get only whole file names | |
7118 ;;verilog-string-replace-matches | |
7119 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern) | |
7120 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern) | |
7121 | |
7122 ;; Unfortunately allows abc/*/rtl to match abc/rtl | |
7123 ;; because abc/.. shows up in dirfiles. Solutions welcome. | |
7124 dirfiles (if (file-directory-p root) ; Ignore version control external | |
7125 (directory-files root t pattern nil))) | |
7126 (while dirfiles | |
7127 (setq dirfile (expand-file-name (concat (car dirfiles) rest)) | |
7128 dirfiles (cdr dirfiles)) | |
7129 (if (file-directory-p dirfile) | |
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7130 (setq dirlist (cons dirfile dirlist))))) |
79545 | 7131 ;; Defaults |
7132 (t | |
7133 (if (file-directory-p dirname) | |
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7134 (setq dirlist (cons dirname dirlist)))))) |
79545 | 7135 dirlist)) |
7136 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v")) | |
7137 | |
7138 (defun verilog-library-filenames (filename current &optional check-ext) | |
7139 "Return a search path to find the given FILENAME name. | |
7140 Uses the CURRENT filename, `verilog-library-directories' and | |
7141 `verilog-library-extensions' variables to build the path. | |
7142 With optional CHECK-EXT also check `verilog-library-extensions'." | |
7143 (let ((ckdir (verilog-expand-dirnames verilog-library-directories)) | |
7144 fn outlist) | |
7145 (while ckdir | |
7146 (let ((ckext (if check-ext verilog-library-extensions `("")))) | |
7147 (while ckext | |
7148 (setq fn (expand-file-name | |
7149 (concat filename (car ckext)) | |
7150 (expand-file-name (car ckdir) (file-name-directory current)))) | |
7151 (if (file-exists-p fn) | |
7152 (setq outlist (cons fn outlist))) | |
7153 (setq ckext (cdr ckext)))) | |
7154 (setq ckdir (cdr ckdir))) | |
7155 (nreverse outlist))) | |
7156 | |
7157 (defun verilog-module-filenames (module current) | |
7158 "Return a search path to find the given MODULE name. | |
7159 Uses the CURRENT filename, `verilog-library-extensions', | |
7160 `verilog-library-directories' and `verilog-library-files' | |
7161 variables to build the path." | |
7162 ;; Return search locations for it | |
7163 (append (list current) ; first, current buffer | |
7164 (verilog-library-filenames module current t) | |
7165 verilog-library-files)) ; finally, any libraries | |
7166 | |
7167 ;; | |
7168 ;; Module Information | |
7169 ;; | |
7170 ;; Many of these functions work on "modi" a module information structure | |
7171 ;; A modi is: [module-name-string file-name begin-point] | |
7172 | |
7173 (defvar verilog-cache-enabled t | |
7174 "If true, enable caching of signals, etc. Set to nil for debugging to make things SLOW!") | |
7175 | |
7176 (defvar verilog-modi-cache-list nil | |
7177 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)... | |
7178 For speeding up verilog-modi-get-* commands. | |
7179 Buffer-local.") | |
7180 | |
79691
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7181 (make-variable-buffer-local 'verilog-modi-cache-list) |
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7182 |
79545 | 7183 (defvar verilog-modi-cache-preserve-tick nil |
7184 "Modification tick after which the cache is still considered valid. | |
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7185 Use `verilog-preserve-cache' to set it.") |
79545 | 7186 (defvar verilog-modi-cache-preserve-buffer nil |
7187 "Modification tick after which the cache is still considered valid. | |
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7188 Use `verilog-preserve-cache' to set it.") |
79545 | 7189 |
7190 (defun verilog-modi-current () | |
7191 "Return the modi structure for the module currently at point." | |
7192 (let* (name pt) | |
7193 ;; read current module's name | |
7194 (save-excursion | |
7195 (verilog-re-search-backward-quick verilog-defun-re nil nil) | |
7196 (verilog-re-search-forward-quick "(" nil nil) | |
7197 (setq name (verilog-read-module-name)) | |
7198 (setq pt (point))) | |
7199 ;; return | |
7200 (vector name (or (buffer-file-name) (current-buffer)) pt))) | |
7201 | |
7202 (defvar verilog-modi-lookup-last-mod nil "Cache of last module looked up.") | |
7203 (defvar verilog-modi-lookup-last-modi nil "Cache of last modi returned.") | |
7204 (defvar verilog-modi-lookup-last-current nil "Cache of last `current-buffer' looked up.") | |
7205 (defvar verilog-modi-lookup-last-tick nil "Cache of last `buffer-modified-tick' looked up.") | |
7206 | |
7207 (defun verilog-modi-lookup (module allow-cache &optional ignore-error) | |
7208 "Find the file and point at which MODULE is defined. | |
7209 If ALLOW-CACHE is set, check and remember cache of previous lookups. | |
7210 Return modi if successful, else print message unless IGNORE-ERROR is true." | |
7211 (let* ((current (or (buffer-file-name) (current-buffer)))) | |
7212 (cond ((and verilog-modi-lookup-last-modi | |
7213 verilog-cache-enabled | |
7214 allow-cache | |
7215 (equal verilog-modi-lookup-last-mod module) | |
7216 (equal verilog-modi-lookup-last-current current) | |
7217 (equal verilog-modi-lookup-last-tick (buffer-modified-tick))) | |
7218 ;; ok as is | |
7219 ) | |
7220 (t (let* ((realmod (verilog-symbol-detick module t)) | |
7221 (orig-filenames (verilog-module-filenames realmod current)) | |
7222 (filenames orig-filenames) | |
7223 pt) | |
7224 (while (and filenames (not pt)) | |
7225 (if (not (setq pt (verilog-module-inside-filename-p realmod (car filenames)))) | |
7226 (setq filenames (cdr filenames)))) | |
7227 (cond (pt (setq verilog-modi-lookup-last-modi | |
7228 (vector realmod (car filenames) pt))) | |
7229 (t (setq verilog-modi-lookup-last-modi nil) | |
7230 (or ignore-error | |
7231 (error (concat (verilog-point-text) | |
7232 ": Can't locate " module " module definition" | |
7233 (if (not (equal module realmod)) | |
7234 (concat " (Expanded macro to " realmod ")") | |
7235 "") | |
7236 "\n Check the verilog-library-directories variable." | |
7237 "\n I looked in (if not listed, doesn't exist):\n\t" | |
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7238 (mapconcat 'concat orig-filenames "\n\t")))))) |
79545 | 7239 (setq verilog-modi-lookup-last-mod module |
7240 verilog-modi-lookup-last-current current | |
7241 verilog-modi-lookup-last-tick (buffer-modified-tick))))) | |
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7242 verilog-modi-lookup-last-modi)) |
79545 | 7243 |
7244 (defsubst verilog-modi-name (modi) | |
7245 (aref modi 0)) | |
7246 (defsubst verilog-modi-file-or-buffer (modi) | |
7247 (aref modi 1)) | |
7248 (defsubst verilog-modi-point (modi) | |
7249 (aref modi 2)) | |
7250 | |
7251 (defun verilog-modi-filename (modi) | |
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diff
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|
7252 "Filename of MODI, or name of buffer if it's never been saved." |
79545 | 7253 (if (bufferp (verilog-modi-file-or-buffer modi)) |
7254 (or (buffer-file-name (verilog-modi-file-or-buffer modi)) | |
7255 (buffer-name (verilog-modi-file-or-buffer modi))) | |
7256 (verilog-modi-file-or-buffer modi))) | |
7257 | |
7258 (defun verilog-modi-goto (modi) | |
7259 "Move point/buffer to specified MODI." | |
7260 (or modi (error "Passed unfound modi to goto, check earlier")) | |
7261 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi)) | |
7262 (verilog-modi-file-or-buffer modi) | |
7263 (find-file-noselect (verilog-modi-file-or-buffer modi)))) | |
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parents:
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diff
changeset
|
7264 (or (equal major-mode `verilog-mode) ;; Put into Verilog mode to get syntax |
79545 | 7265 (verilog-mode)) |
7266 (goto-char (verilog-modi-point modi))) | |
7267 | |
7268 (defun verilog-goto-defun-file (module) | |
7269 "Move point to the file at which a given MODULE is defined." | |
7270 (interactive "sGoto File for Module: ") | |
7271 (let* ((modi (verilog-modi-lookup module nil))) | |
7272 (when modi | |
7273 (verilog-modi-goto modi) | |
7274 (switch-to-buffer (current-buffer))))) | |
7275 | |
7276 (defun verilog-modi-cache-results (modi function) | |
7277 "Run on MODI the given FUNCTION. Locate the module in a file. | |
7278 Cache the output of function so next call may have faster access." | |
7279 (let (func-returns fass) | |
7280 (save-excursion | |
7281 (verilog-modi-goto modi) | |
7282 (if (and (setq fass (assoc (list (verilog-modi-name modi) function) | |
7283 verilog-modi-cache-list)) | |
7284 ;; Destroy caching when incorrect; Modified or file changed | |
7285 (not (and verilog-cache-enabled | |
7286 (or (equal (buffer-modified-tick) (nth 1 fass)) | |
7287 (and verilog-modi-cache-preserve-tick | |
7288 (<= verilog-modi-cache-preserve-tick (nth 1 fass)) | |
7289 (equal verilog-modi-cache-preserve-buffer (current-buffer)))) | |
7290 (equal (visited-file-modtime) (nth 2 fass))))) | |
7291 (setq verilog-modi-cache-list nil | |
7292 fass nil)) | |
7293 (cond (fass | |
7294 ;; Found | |
7295 (setq func-returns (nth 3 fass))) | |
7296 (t | |
7297 ;; Read from file | |
7298 ;; Clear then restore any hilighting to make emacs19 happy | |
7299 (let ((fontlocked (when (and (boundp 'font-lock-mode) | |
7300 font-lock-mode) | |
7301 (font-lock-mode nil) | |
7302 t))) | |
7303 (setq func-returns (funcall function)) | |
7304 (when fontlocked (font-lock-mode t))) | |
7305 ;; Cache for next time | |
7306 (setq verilog-modi-cache-list | |
7307 (cons (list (list (verilog-modi-name modi) function) | |
7308 (buffer-modified-tick) | |
7309 (visited-file-modtime) | |
7310 func-returns) | |
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|
7311 verilog-modi-cache-list))))) |
79545 | 7312 ;; |
7313 func-returns)) | |
7314 | |
7315 (defun verilog-modi-cache-add (modi function element sig-list) | |
7316 "Add function return results to the module cache. | |
7317 Update MODI's cache for given FUNCTION so that the return ELEMENT of that | |
7318 function now contains the additional SIG-LIST parameters." | |
7319 (let (fass) | |
7320 (save-excursion | |
7321 (verilog-modi-goto modi) | |
7322 (if (setq fass (assoc (list (verilog-modi-name modi) function) | |
7323 verilog-modi-cache-list)) | |
7324 (let ((func-returns (nth 3 fass))) | |
7325 (aset func-returns element | |
7326 (append sig-list (aref func-returns element)))))))) | |
7327 | |
7328 (defmacro verilog-preserve-cache (&rest body) | |
7329 "Execute the BODY forms, allowing cache preservation within BODY. | |
7330 This means that changes to the buffer will not result in the cache being | |
7331 flushed. If the changes affect the modsig state, they must call the | |
7332 modsig-cache-add-* function, else the results of later calls may be | |
7333 incorrect. Without this, changes are assumed to be adding/removing signals | |
7334 and invalidating the cache." | |
7335 `(let ((verilog-modi-cache-preserve-tick (buffer-modified-tick)) | |
7336 (verilog-modi-cache-preserve-buffer (current-buffer))) | |
7337 (progn ,@body))) | |
7338 | |
7339 | |
7340 (defun verilog-signals-matching-enum (in-list enum) | |
7341 "Return all signals in IN-LIST matching the given ENUM." | |
7342 (let (out-list) | |
7343 (while in-list | |
7344 (if (equal (verilog-sig-enum (car in-list)) enum) | |
7345 (setq out-list (cons (car in-list) out-list))) | |
7346 (setq in-list (cdr in-list))) | |
7347 ;; New scheme | |
7348 (let* ((enumvar (intern (concat "venum-" enum))) | |
7349 (enumlist (and (boundp enumvar) (eval enumvar)))) | |
7350 (while enumlist | |
7351 (add-to-list 'out-list (list (car enumlist))) | |
7352 (setq enumlist (cdr enumlist)))) | |
7353 (nreverse out-list))) | |
7354 | |
7355 (defun verilog-signals-not-matching-regexp (in-list regexp) | |
7356 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil." | |
7357 (if (not regexp) | |
7358 in-list | |
7359 (let (out-list) | |
7360 (while in-list | |
7361 (if (not (string-match regexp (verilog-sig-name (car in-list)))) | |
7362 (setq out-list (cons (car in-list) out-list))) | |
7363 (setq in-list (cdr in-list))) | |
7364 (nreverse out-list)))) | |
7365 | |
7366 ;; Combined | |
7367 (defun verilog-modi-get-signals (modi) | |
7368 (append | |
7369 (verilog-modi-get-outputs modi) | |
7370 (verilog-modi-get-inouts modi) | |
7371 (verilog-modi-get-inputs modi) | |
7372 (verilog-modi-get-wires modi) | |
7373 (verilog-modi-get-regs modi) | |
7374 (verilog-modi-get-assigns modi) | |
7375 (verilog-modi-get-consts modi) | |
7376 (verilog-modi-get-gparams modi))) | |
7377 | |
7378 (defun verilog-modi-get-ports (modi) | |
7379 (append | |
7380 (verilog-modi-get-outputs modi) | |
7381 (verilog-modi-get-inouts modi) | |
7382 (verilog-modi-get-inputs modi))) | |
7383 | |
7384 (defsubst verilog-modi-cache-add-outputs (modi sig-list) | |
7385 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list)) | |
7386 (defsubst verilog-modi-cache-add-inouts (modi sig-list) | |
7387 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list)) | |
7388 (defsubst verilog-modi-cache-add-inputs (modi sig-list) | |
7389 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list)) | |
7390 (defsubst verilog-modi-cache-add-wires (modi sig-list) | |
7391 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list)) | |
7392 (defsubst verilog-modi-cache-add-regs (modi sig-list) | |
7393 (verilog-modi-cache-add modi 'verilog-read-decls 4 sig-list)) | |
7394 | |
7395 (defun verilog-signals-from-signame (signame-list) | |
7396 "Return signals in standard form from SIGNAME-LIST, a simple list of signal names." | |
7397 (mapcar (function (lambda (name) (list name nil nil))) | |
7398 signame-list)) | |
7399 | |
7400 ;; | |
7401 ;; Auto creation utilities | |
7402 ;; | |
7403 | |
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|
7404 (defun verilog-auto-re-search-do (search-for func) |
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changeset
|
7405 "Search for the given auto text regexp SEARCH-FOR, and perform FUNC where it occurs." |
35dfb85c0e6b
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diff
changeset
|
7406 (goto-char (point-min)) |
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diff
changeset
|
7407 (while (verilog-re-search-forward search-for nil t) |
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|
7408 (funcall func))) |
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diff
changeset
|
7409 |
79545 | 7410 (defun verilog-auto-search-do (search-for func) |
7411 "Search for the given auto text SEARCH-FOR, and perform FUNC where it occurs." | |
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|
7412 (verilog-auto-re-search-do (regexp-quote search-for) func)) |
79545 | 7413 |
7414 (defun verilog-insert-one-definition (sig type indent-pt) | |
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7415 "Print out a definition for SIG of the given TYPE, |
79545 | 7416 with appropriate INDENT-PT indentation." |
7417 (indent-to indent-pt) | |
7418 (insert type) | |
7419 (when (verilog-sig-signed sig) | |
7420 (insert " " (verilog-sig-signed sig))) | |
7421 (when (verilog-sig-multidim sig) | |
7422 (insert " " (verilog-sig-multidim-string sig))) | |
7423 (when (verilog-sig-bits sig) | |
7424 (insert " " (verilog-sig-bits sig))) | |
7425 (indent-to (max 24 (+ indent-pt 16))) | |
7426 (unless (= (char-syntax (preceding-char)) ?\ ) | |
7427 (insert " ")) ; Need space between "]name" if indent-to did nothing | |
7428 (insert (verilog-sig-name sig))) | |
7429 | |
7430 (defun verilog-insert-definition (sigs direction indent-pt v2k &optional dont-sort) | |
7431 "Print out a definition for a list of SIGS of the given DIRECTION, | |
7432 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O | |
7433 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output." | |
7434 (or dont-sort | |
7435 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare))) | |
7436 (while sigs | |
7437 (let ((sig (car sigs))) | |
7438 (verilog-insert-one-definition | |
7439 sig | |
7440 ;; Want "type x" or "output type x", not "wire type x" | |
7441 (cond ((verilog-sig-type sig) | |
7442 (concat | |
7443 (if (not (equal direction "wire")) | |
7444 (concat direction " ")) | |
7445 (verilog-sig-type sig))) | |
7446 (t direction)) | |
7447 indent-pt) | |
7448 (insert (if v2k "," ";")) | |
7449 (if (or (not (verilog-sig-comment sig)) | |
7450 (equal "" (verilog-sig-comment sig))) | |
7451 (insert "\n") | |
7452 (indent-to (max 48 (+ indent-pt 40))) | |
7453 (insert (concat "// " (verilog-sig-comment sig) "\n"))) | |
7454 (setq sigs (cdr sigs))))) | |
7455 | |
7456 (eval-when-compile | |
7457 (if (not (boundp 'indent-pt)) | |
7458 (defvar indent-pt nil "Local used by insert-indent"))) | |
7459 | |
7460 (defun verilog-insert-indent (&rest stuff) | |
7461 "Indent to position stored in local `indent-pt' variable, then insert STUFF. | |
7462 Presumes that any newlines end a list element." | |
7463 (let ((need-indent t)) | |
7464 (while stuff | |
7465 (if need-indent (indent-to indent-pt)) | |
7466 (setq need-indent nil) | |
7467 (insert (car stuff)) | |
7468 (setq need-indent (string-match "\n$" (car stuff)) | |
7469 stuff (cdr stuff))))) | |
7470 ;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n")) | |
7471 | |
7472 (defun verilog-repair-open-comma () | |
7473 "If backwards-from-point is other than a open parenthesis insert comma." | |
7474 (save-excursion | |
7475 (verilog-backward-syntactic-ws) | |
7476 (when (save-excursion | |
7477 (backward-char 1) | |
7478 (and (not (looking-at "[(,]")) | |
7479 (progn | |
7480 (verilog-re-search-backward "[(`]" nil t) | |
7481 (looking-at "(")))) | |
7482 (insert ",")))) | |
7483 | |
7484 (defun verilog-repair-close-comma () | |
7485 "If point is at a comma followed by a close parenthesis, fix it. | |
7486 This repairs those mis-inserted by a AUTOARG." | |
7487 ;; It would be much nicer if Verilog allowed extra commas like Perl does! | |
7488 (save-excursion | |
7489 (verilog-forward-close-paren) | |
7490 (backward-char 1) | |
7491 (verilog-backward-syntactic-ws) | |
7492 (backward-char 1) | |
7493 (when (looking-at ",") | |
7494 (delete-char 1)))) | |
7495 | |
7496 (defun verilog-get-list (start end) | |
7497 "Return the elements of a comma separated list between START and END." | |
7498 (interactive) | |
7499 (let ((my-list (list)) | |
7500 my-string) | |
7501 (save-excursion | |
7502 (while (< (point) end) | |
7503 (when (re-search-forward "\\([^,{]+\\)" end t) | |
7504 (setq my-string (verilog-string-remove-spaces (match-string 1))) | |
7505 (setq my-list (nconc my-list (list my-string) )) | |
7506 (goto-char (match-end 0)))) | |
7507 my-list))) | |
7508 | |
7509 (defun verilog-make-width-expression (range-exp) | |
7510 "Return an expression calculating the length of a range [x:y] in RANGE-EXP." | |
7511 ;; strip off the [] | |
7512 (cond ((not range-exp) | |
7513 "1") | |
7514 (t | |
7515 (if (string-match "^\\[\\(.*\\)\\]$" range-exp) | |
7516 (setq range-exp (match-string 1 range-exp))) | |
7517 (cond ((not range-exp) | |
7518 "1") | |
79691
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
7519 ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$" |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
7520 range-exp) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
7521 (int-to-string |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
7522 (1+ (abs (- (string-to-number (match-string 1 range-exp)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
7523 (string-to-number (match-string 2 range-exp))))))) |
79545 | 7524 ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp) |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
7525 (concat "(1+(" (match-string 1 range-exp) ")" |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
7526 (if (equal "0" (match-string 2 range-exp)) |
57956dd69d3f
(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
7527 "" ;; Don't bother with -(0) |
79545 | 7528 (concat "-(" (match-string 2 range-exp) ")")) |
7529 ")")) | |
7530 (t nil))))) | |
7531 ;;(verilog-make-width-expression "`A:`B") | |
7532 | |
7533 (defun verilog-typedef-name-p (variable-name) | |
7534 "Return true if the VARIABLE-NAME is a type definition." | |
7535 (when verilog-typedef-regexp | |
7536 (string-match verilog-typedef-regexp variable-name))) | |
7537 | |
7538 ;; | |
7539 ;; Auto deletion | |
7540 ;; | |
7541 | |
7542 (defun verilog-delete-autos-lined () | |
7543 "Delete autos that occupy multiple lines, between begin and end comments." | |
7544 (let ((pt (point))) | |
7545 (forward-line 1) | |
7546 (when (and | |
7547 (looking-at "\\s-*// Beginning") | |
7548 (search-forward "// End of automatic" nil t)) | |
7549 ;; End exists | |
7550 (end-of-line) | |
7551 (delete-region pt (point)) | |
79799
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79717
diff
changeset
|
7552 (forward-line 1)))) |
79545 | 7553 |
7554 (defun verilog-forward-close-paren () | |
80165
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parents:
80163
diff
changeset
|
7555 "Find the close parenthesis that match the current point. |
411da0873a97
Re-commit doc fixes accidentally reverted.
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parents:
80163
diff
changeset
|
7556 Ignore other close parenthesis with matching open parens." |
79545 | 7557 (let ((parens 1)) |
7558 (while (> parens 0) | |
7559 (unless (verilog-re-search-forward-quick "[()]" nil t) | |
7560 (error "%s: Mismatching ()" (verilog-point-text))) | |
7561 (cond ((= (preceding-char) ?\( ) | |
7562 (setq parens (1+ parens))) | |
7563 ((= (preceding-char) ?\) ) | |
7564 (setq parens (1- parens))))))) | |
7565 | |
7566 (defun verilog-backward-open-paren () | |
80165
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Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
7567 "Find the open parenthesis that match the current point. |
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
7568 Ignore other open parenthesis with matching close parens." |
79545 | 7569 (let ((parens 1)) |
7570 (while (> parens 0) | |
7571 (unless (verilog-re-search-backward-quick "[()]" nil t) | |
7572 (error "%s: Mismatching ()" (verilog-point-text))) | |
7573 (cond ((= (following-char) ?\) ) | |
7574 (setq parens (1+ parens))) | |
7575 ((= (following-char) ?\( ) | |
7576 (setq parens (1- parens))))))) | |
7577 | |
7578 (defun verilog-backward-open-bracket () | |
80165
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Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
7579 "Find the open bracket that match the current point. |
411da0873a97
Re-commit doc fixes accidentally reverted.
Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
7580 Ignore other open bracket with matching close bracket." |
79545 | 7581 (let ((parens 1)) |
7582 (while (> parens 0) | |
7583 (unless (verilog-re-search-backward-quick "[][]" nil t) | |
7584 (error "%s: Mismatching []" (verilog-point-text))) | |
7585 (cond ((= (following-char) ?\] ) | |
7586 (setq parens (1+ parens))) | |
7587 ((= (following-char) ?\[ ) | |
7588 (setq parens (1- parens))))))) | |
7589 | |
7590 (defun verilog-delete-to-paren () | |
7591 "Delete the automatic inst/sense/arg created by autos. | |
7592 Deletion stops at the matching end parenthesis." | |
7593 (delete-region (point) | |
7594 (save-excursion | |
7595 (verilog-backward-open-paren) | |
7596 (forward-sexp 1) ;; Moves to paren that closes argdecl's | |
7597 (backward-char 1) | |
7598 (point)))) | |
7599 | |
7600 (defun verilog-auto-star-safe () | |
7601 "Return if a .* AUTOINST is safe to delete or expand. | |
7602 It was created by the AUTOS themselves, or by the user." | |
7603 (and verilog-auto-star-expand | |
7604 (looking-at "[ \t\n\f,]*\\([)]\\|// \\(Outputs\\|Inouts\\|Inputs\\)\\)"))) | |
7605 | |
7606 (defun verilog-delete-auto-star-all () | |
7607 "Delete a .* AUTOINST, if it is safe." | |
7608 (when (verilog-auto-star-safe) | |
7609 (verilog-delete-to-paren))) | |
7610 | |
7611 (defun verilog-delete-auto-star-implicit () | |
7612 "Delete all .* implicit connections created by `verilog-auto-star'. | |
7613 This function will be called automatically at save unless | |
7614 `verilog-auto-star-save' is set, any non-templated expanded pins will be | |
7615 removed." | |
7616 (interactive) | |
7617 (let (paren-pt indent have-close-paren) | |
7618 (save-excursion | |
7619 (goto-char (point-min)) | |
7620 ;; We need to match these even outside of comments. | |
7621 ;; For reasonable performance, we don't check if inside comments, sorry. | |
7622 (while (re-search-forward "// Implicit \\.\\*" nil t) | |
7623 (setq paren-pt (point)) | |
7624 (beginning-of-line) | |
7625 (setq have-close-paren | |
7626 (save-excursion | |
7627 (when (search-forward ");" paren-pt t) | |
7628 (setq indent (current-indentation)) | |
7629 t))) | |
7630 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR | |
7631 (when have-close-paren | |
7632 ;; Delete extra commentary | |
7633 (save-excursion | |
7634 (while (progn | |
7635 (forward-line -1) | |
7636 (looking-at "\\s *//\\s *\\(Outputs\\|Inouts\\|Inputs\\)\n")) | |
7637 (delete-region (match-beginning 0) (match-end 0)))) | |
7638 ;; If it is simple, we can put the ); on the same line as the last text | |
7639 (let ((rtn-pt (point))) | |
7640 (save-excursion | |
7641 (while (progn (backward-char 1) | |
7642 (looking-at "[ \t\n\f]"))) | |
7643 (when (looking-at ",") | |
7644 (delete-region (+ 1 (point)) rtn-pt)))) | |
7645 (when (bolp) | |
7646 (indent-to indent)) | |
7647 (insert ");\n") | |
7648 ;; Still need to kill final comma - always is one as we put one after the .* | |
7649 (re-search-backward ",") | |
7650 (delete-char 1)))))) | |
7651 | |
7652 (defun verilog-delete-auto () | |
7653 "Delete the automatic outputs, regs, and wires created by \\[verilog-auto]. | |
7654 Use \\[verilog-auto] to re-insert the updated AUTOs. | |
7655 | |
7656 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are | |
7657 called before and after this function, respectively." | |
7658 (interactive) | |
7659 (save-excursion | |
7660 (if (buffer-file-name) | |
7661 (find-file-noselect (buffer-file-name))) ;; To check we have latest version | |
7662 ;; Allow user to customize | |
7663 (run-hooks 'verilog-before-delete-auto-hook) | |
7664 | |
7665 ;; Remove those that have multi-line insertions | |
7666 (verilog-auto-re-search-do "/\\*AUTO\\(OUTPUTEVERY\\|CONCATCOMMENT\\|WIRE\\|REG\\|DEFINEVALUE\\|REGINPUT\\|INPUT\\|OUTPUT\\|INOUT\\|RESET\\|TIEOFF\\|UNUSED\\)\\*/" | |
7667 'verilog-delete-autos-lined) | |
7668 ;; Remove those that have multi-line insertions with parameters | |
7669 (verilog-auto-re-search-do "/\\*AUTO\\(INOUTMODULE\\|ASCIIENUM\\)([^)]*)\\*/" | |
7670 'verilog-delete-autos-lined) | |
7671 ;; Remove those that are in parenthesis | |
7672 (verilog-auto-re-search-do "/\\*\\(AS\\|AUTO\\(ARG\\|CONCATWIDTH\\|INST\\|INSTPARAM\\|SENSE\\)\\)\\*/" | |
7673 'verilog-delete-to-paren) | |
7674 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments | |
7675 (verilog-auto-re-search-do "\\.\\*" | |
7676 'verilog-delete-auto-star-all) | |
7677 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed | |
7678 (goto-char (point-min)) | |
7679 (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)[ \tLT0-9]*$" nil t) | |
7680 (replace-match "")) | |
7681 | |
7682 ;; Final customize | |
7683 (run-hooks 'verilog-delete-auto-hook))) | |
7684 | |
7685 ;; | |
7686 ;; Auto inject | |
7687 ;; | |
7688 | |
7689 (defun verilog-inject-auto () | |
7690 "Examine legacy non-AUTO code and insert AUTOs in appropriate places. | |
7691 | |
7692 Any always @ blocks with sensitivity lists that match computed lists will | |
7693 be replaced with /*AS*/ comments. | |
7694 | |
80165
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parents:
80163
diff
changeset
|
7695 Any cells will get /*AUTOINST*/ added to the end of the pin list. |
411da0873a97
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Juanma Barranquero <lekktu@gmail.com>
parents:
80163
diff
changeset
|
7696 Pins with have identical names will be deleted. |
79545 | 7697 |
7698 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to | |
7699 support adding new ports. You may wish to delete older ports yourself. | |
7700 | |
7701 For example: | |
7702 | |
7703 module ex_inject (i, o); | |
7704 input i; | |
7705 input j; | |
7706 output o; | |
7707 always @ (i or j) | |
7708 o = i | j; | |
7709 cell cell (.foobar(baz), | |
7710 .j(j)); | |
7711 endmodule | |
7712 | |
7713 Typing \\[verilog-inject-auto] will make this into: | |
7714 | |
7715 module ex_inject (i, o/*AUTOARG*/ | |
7716 // Inputs | |
7717 j); | |
7718 input i; | |
7719 output o; | |
7720 always @ (/*AS*/i or j) | |
7721 o = i | j; | |
7722 cell cell (.foobar(baz), | |
7723 /*AUTOINST*/ | |
7724 // Outputs | |
7725 .j(j)); | |
7726 endmodule" | |
7727 (interactive) | |
7728 (verilog-auto t)) | |
7729 | |
7730 (defun verilog-inject-arg () | |
7731 "Inject AUTOARG into new code. See `verilog-inject-auto'." | |
7732 ;; Presume one module per file. | |
7733 (save-excursion | |
7734 (goto-char (point-min)) | |
7735 (while (verilog-re-search-forward-quick "\\<module\\>" nil t) | |
7736 (let ((endmodp (save-excursion | |
7737 (verilog-re-search-forward-quick "\\<endmodule\\>" nil t) | |
7738 (point)))) | |
7739 ;; See if there's already a comment .. inside a comment so not verilog-re-search | |
7740 (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t)) | |
7741 (verilog-re-search-forward-quick ";" nil t) | |
7742 (backward-char 1) | |
7743 (verilog-backward-syntactic-ws) | |
7744 (backward-char 1) ; Moves to paren that closes argdecl's | |
7745 (when (looking-at ")") | |
7746 (insert "/*AUTOARG*/"))))))) | |
7747 | |
7748 (defun verilog-inject-sense () | |
7749 "Inject AUTOSENSE into new code. See `verilog-inject-auto'." | |
7750 (save-excursion | |
7751 (goto-char (point-min)) | |
7752 (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t) | |
7753 (let ((start-pt (point)) | |
7754 (modi (verilog-modi-current)) | |
7755 pre-sigs | |
7756 got-sigs) | |
7757 (backward-char 1) | |
7758 (forward-sexp 1) | |
7759 (backward-char 1) ;; End ) | |
7760 (when (not (verilog-re-search-backward "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t)) | |
7761 (setq pre-sigs (verilog-signals-from-signame | |
7762 (verilog-read-signals start-pt (point))) | |
7763 got-sigs (verilog-auto-sense-sigs modi nil)) | |
7764 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal? | |
7765 (verilog-signals-not-in got-sigs pre-sigs))) | |
7766 (delete-region start-pt (point)) | |
7767 (insert "/*AS*/"))))))) | |
7768 | |
7769 (defun verilog-inject-inst () | |
7770 "Inject AUTOINST into new code. See `verilog-inject-auto'." | |
7771 (save-excursion | |
7772 (goto-char (point-min)) | |
7773 ;; It's hard to distinguish modules; we'll instead search for pins. | |
7774 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_\$]+\\s *(\\s *[a-zA-Z0-9`_\$]+\\s *)" nil t) | |
7775 (verilog-backward-open-paren) ;; Inst start | |
7776 (cond | |
7777 ((= (preceding-char) ?\#) ;; #(...) parameter section, not pin. Skip. | |
7778 (forward-char 1) | |
7779 (verilog-forward-close-paren)) ;; Parameters done | |
7780 (t | |
7781 (forward-char 1) | |
7782 (let ((indent-pt (+ (current-column))) | |
7783 (end-pt (save-excursion (verilog-forward-close-paren) (point)))) | |
7784 (cond ((verilog-re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t) | |
7785 (goto-char end-pt)) ;; Already there, continue search with next instance | |
7786 (t | |
7787 ;; Delete identical interconnect | |
7788 (let ((case-fold-search nil)) ;; So we don't convert upper-to-lower, etc | |
7789 (while (verilog-re-search-forward "\\.\\s *\\([a-zA-Z0-9`_\$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t) | |
7790 (delete-region (match-beginning 0) (match-end 0)) | |
7791 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ;; Keep it correct | |
7792 (while (or (looking-at "[ \t\n\f,]+") | |
7793 (looking-at "//[^\n]*")) | |
7794 (delete-region (match-beginning 0) (match-end 0)) | |
7795 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0))))))) | |
7796 (verilog-forward-close-paren) | |
7797 (backward-char 1) | |
7798 ;; Not verilog-re-search, as we don't want to strip comments | |
7799 (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t) | |
7800 (delete-region (match-beginning 0) (match-end 0))) | |
7801 (insert "\n") | |
7802 (indent-to indent-pt) | |
7803 (insert "/*AUTOINST*/"))))))))) | |
7804 | |
7805 ;; | |
7806 ;; Auto save | |
7807 ;; | |
7808 | |
7809 (defun verilog-auto-save-check () | |
7810 "On saving see if we need auto update." | |
7811 (cond ((not verilog-auto-save-policy)) ; disabled | |
7812 ((not (save-excursion | |
7813 (save-match-data | |
7814 (let ((case-fold-search nil)) | |
7815 (goto-char (point-min)) | |
7816 (re-search-forward "AUTO" nil t)))))) | |
7817 ((eq verilog-auto-save-policy 'force) | |
7818 (verilog-auto)) | |
7819 ((not (buffer-modified-p))) | |
7820 ((eq verilog-auto-update-tick (buffer-modified-tick))) ; up-to-date | |
7821 ((eq verilog-auto-save-policy 'detect) | |
7822 (verilog-auto)) | |
7823 (t | |
7824 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ") | |
7825 (verilog-auto)) | |
7826 ;; Don't ask again if didn't update | |
79799
57956dd69d3f
(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
7827 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick)))) |
79545 | 7828 (when (not verilog-auto-star-save) |
7829 (verilog-delete-auto-star-implicit)) | |
7830 nil) ;; Always return nil -- we don't write the file ourselves | |
7831 | |
7832 (defun verilog-auto-read-locals () | |
7833 "Return file local variable segment at bottom of file." | |
7834 (save-excursion | |
7835 (goto-char (point-max)) | |
7836 (if (re-search-backward "Local Variables:" nil t) | |
7837 (buffer-substring-no-properties (point) (point-max)) | |
7838 ""))) | |
7839 | |
7840 (defun verilog-auto-reeval-locals (&optional force) | |
7841 "Read file local variable segment at bottom of file if it has changed. | |
7842 If FORCE, always reread it." | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
7843 (make-local-variable 'verilog-auto-last-file-locals) |
79545 | 7844 (let ((curlocal (verilog-auto-read-locals))) |
7845 (when (or force (not (equal verilog-auto-last-file-locals curlocal))) | |
7846 (setq verilog-auto-last-file-locals curlocal) | |
7847 ;; Note this may cause this function to be recursively invoked. | |
7848 ;; The above when statement will prevent it from recursing forever. | |
7849 (hack-local-variables) | |
7850 t))) | |
7851 | |
7852 ;; | |
7853 ;; Auto creation | |
7854 ;; | |
7855 | |
7856 (defun verilog-auto-arg-ports (sigs message indent-pt) | |
7857 "Print a list of ports for a AUTOINST. | |
7858 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT." | |
7859 (when sigs | |
7860 (insert "\n") | |
7861 (indent-to indent-pt) | |
7862 (insert message) | |
7863 (insert "\n") | |
7864 (let ((space "")) | |
7865 (indent-to indent-pt) | |
7866 (while sigs | |
7867 (cond ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column) | |
7868 (insert "\n") | |
7869 (indent-to indent-pt)) | |
7870 (t (insert space))) | |
7871 (insert (verilog-sig-name (car sigs)) ",") | |
7872 (setq sigs (cdr sigs) | |
7873 space " "))))) | |
7874 | |
7875 (defun verilog-auto-arg () | |
7876 "Expand AUTOARG statements. | |
7877 Replace the argument declarations at the beginning of the | |
7878 module with ones automatically derived from input and output | |
7879 statements. This can be dangerous if the module is instantiated | |
7880 using position-based connections, so use only name-based when | |
7881 instantiating the resulting module. Long lines are split based | |
7882 on the `fill-column', see \\[set-fill-column]. | |
7883 | |
7884 Limitations: | |
7885 Concatenation and outputting partial busses is not supported. | |
7886 | |
7887 Typedefs must match `verilog-typedef-regexp', which is disabled by default. | |
7888 | |
7889 For example: | |
7890 | |
7891 module ex_arg (/*AUTOARG*/); | |
7892 input i; | |
7893 output o; | |
7894 endmodule | |
7895 | |
7896 Typing \\[verilog-auto] will make this into: | |
7897 | |
7898 module ex_arg (/*AUTOARG*/ | |
7899 // Outputs | |
7900 o, | |
7901 // Inputs | |
7902 i | |
7903 ); | |
7904 input i; | |
7905 output o; | |
7906 endmodule | |
7907 | |
7908 Any ports declared between the ( and /*AUTOARG*/ are presumed to be | |
7909 predeclared and are not redeclared by AUTOARG. AUTOARG will make a | |
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7910 conservative guess on adding a comma for the first signal, if you have |
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7911 any ifdefs or complicated expressions before the AUTOARG you will need |
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|
7912 to choose the comma yourself. |
79545 | 7913 |
7914 Avoid declaring ports manually, as it makes code harder to maintain." | |
7915 (save-excursion | |
7916 (let ((modi (verilog-modi-current)) | |
7917 (skip-pins (aref (verilog-read-arg-pins) 0))) | |
7918 (verilog-repair-open-comma) | |
7919 (verilog-auto-arg-ports (verilog-signals-not-in | |
7920 (verilog-modi-get-outputs modi) | |
7921 skip-pins) | |
7922 "// Outputs" | |
7923 verilog-indent-level-declaration) | |
7924 (verilog-auto-arg-ports (verilog-signals-not-in | |
7925 (verilog-modi-get-inouts modi) | |
7926 skip-pins) | |
7927 "// Inouts" | |
7928 verilog-indent-level-declaration) | |
7929 (verilog-auto-arg-ports (verilog-signals-not-in | |
7930 (verilog-modi-get-inputs modi) | |
7931 skip-pins) | |
7932 "// Inputs" | |
7933 verilog-indent-level-declaration) | |
7934 (verilog-repair-close-comma) | |
7935 (unless (eq (char-before) ?/ ) | |
7936 (insert "\n")) | |
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7937 (indent-to verilog-indent-level-declaration)))) |
79545 | 7938 |
7939 (defun verilog-auto-inst-port-map (port-st) | |
7940 nil) | |
7941 | |
7942 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning | |
7943 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning | |
7944 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning | |
7945 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning | |
7946 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning | |
7947 | |
7948 (defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star) | |
7949 "Print out a instantiation connection for this PORT-ST. | |
7950 Insert to INDENT-PT, use template TPL-LIST. | |
7951 @ are instantiation numbers, replaced with TPL-NUM. | |
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7952 @\"(expression @)\" are evaluated, with @ as a variable. |
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7953 If FOR-STAR add comment it is a .* expansion." |
79545 | 7954 (let* ((port (verilog-sig-name port-st)) |
7955 (tpl-ass (or (assoc port (car tpl-list)) | |
7956 (verilog-auto-inst-port-map port-st))) | |
7957 ;; vl-* are documented for user use | |
7958 (vl-name (verilog-sig-name port-st)) | |
7959 (vl-width (verilog-sig-width port-st)) | |
7960 (vl-bits (if (or verilog-auto-inst-vector | |
7961 (not (assoc port vector-skip-list)) | |
7962 (not (equal (verilog-sig-bits port-st) | |
7963 (verilog-sig-bits (assoc port vector-skip-list))))) | |
7964 (or (verilog-sig-bits port-st) "") | |
7965 "")) | |
7966 ;; Default if not found | |
7967 (tpl-net (if (verilog-sig-multidim port-st) | |
7968 (concat port "/*" (verilog-sig-multidim-string port-st) | |
7969 vl-bits "*/") | |
7970 (concat port vl-bits))) | |
7971 (case-fold-search nil)) | |
7972 ;; Find template | |
7973 (cond (tpl-ass ; Template of exact port name | |
7974 (setq tpl-net (nth 1 tpl-ass))) | |
7975 ((nth 1 tpl-list) ; Wildcards in template, search them | |
7976 (let ((wildcards (nth 1 tpl-list))) | |
7977 (while wildcards | |
7978 (when (string-match (nth 0 (car wildcards)) port) | |
7979 (setq tpl-ass (car wildcards) ; so allow @ parsing | |
7980 tpl-net (replace-match (nth 1 (car wildcards)) | |
7981 t nil port))) | |
7982 (setq wildcards (cdr wildcards)))))) | |
7983 ;; Parse Templated variable | |
7984 (when tpl-ass | |
7985 ;; Evaluate @"(lispcode)" | |
7986 (when (string-match "@\".*[^\\]\"" tpl-net) | |
7987 (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net) | |
7988 (setq tpl-net | |
7989 (concat | |
7990 (substring tpl-net 0 (match-beginning 0)) | |
7991 (save-match-data | |
7992 (let* ((expr (match-string 1 tpl-net)) | |
7993 (value | |
7994 (progn | |
7995 (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr)) | |
7996 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr)) | |
7997 (prin1 (eval (car (read-from-string expr))) | |
7998 (lambda (ch) ()))))) | |
7999 (if (numberp value) (setq value (number-to-string value))) | |
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8000 value)) |
79545 | 8001 (substring tpl-net (match-end 0)))))) |
8002 ;; Replace @ and [] magic variables in final output | |
8003 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net)) | |
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8004 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net))) |
79545 | 8005 (indent-to indent-pt) |
8006 (insert "." port) | |
8007 (indent-to verilog-auto-inst-column) | |
8008 (insert "(" tpl-net "),") | |
8009 (cond (tpl-ass | |
8010 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16) | |
8011 verilog-auto-inst-column)) | |
8012 (insert " // Templated") | |
8013 (when verilog-auto-inst-template-numbers | |
8014 (insert " T" (int-to-string (nth 2 tpl-ass)) | |
8015 " L" (int-to-string (nth 3 tpl-ass))))) | |
8016 (for-star | |
8017 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16) | |
8018 verilog-auto-inst-column)) | |
8019 (insert " // Implicit .\*"))) ;For some reason the . or * must be escaped... | |
8020 (insert "\n"))) | |
8021 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3") | |
8022 ;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]") | |
8023 ;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));") | |
8024 | |
8025 (defun verilog-auto-inst-first () | |
8026 "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]." | |
8027 ;; Do we need a trailing comma? | |
8028 ;; There maybe a ifdef or something similar before us. What a mess. Thus | |
8029 ;; to avoid trouble we only insert on preceeding ) or *. | |
8030 ;; Insert first port on new line | |
8031 (insert "\n") ;; Must insert before search, so point will move forward if insert comma | |
8032 (save-excursion | |
8033 (verilog-re-search-backward "[^ \t\n\f]" nil nil) | |
8034 (when (looking-at ")\\|\\*") ;; Generally don't insert, unless we are fairly sure | |
8035 (forward-char 1) | |
8036 (insert ",")))) | |
8037 | |
8038 (defun verilog-auto-star () | |
8039 "Expand SystemVerilog .* pins, as part of \\[verilog-auto]. | |
8040 | |
8041 If `verilog-auto-star-expand' is set, .* pins are treated if they were | |
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8042 AUTOINST statements, otherwise they are ignored. For safety, Verilog mode |
79545 | 8043 will also ignore any .* that are not last in your pin list (this prevents |
8044 it from deleting pins following the .* when it expands the AUTOINST.) | |
8045 | |
8046 On writing your file, unless `verilog-auto-star-save' is set, any | |
8047 non-templated expanded pins will be removed. You may do this at any time | |
8048 with \\[verilog-delete-auto-star-implicit]. | |
8049 | |
8050 If you are converting a module to use .* for the first time, you may wish | |
8051 to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*. | |
8052 | |
8053 See `verilog-auto-inst' for examples, templates, and more information." | |
8054 (when (verilog-auto-star-safe) | |
8055 (verilog-auto-inst))) | |
8056 | |
8057 (defun verilog-auto-inst () | |
8058 "Expand AUTOINST statements, as part of \\[verilog-auto]. | |
8059 Replace the pin connections to an instantiation with ones | |
8060 automatically derived from the module header of the instantiated netlist. | |
8061 | |
8062 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports, | |
8063 and delete them before saving unless `verilog-auto-star-save' is set. | |
8064 See `verilog-auto-star' for more information. | |
8065 | |
8066 Limitations: | |
8067 Module names must be resolvable to filenames by adding a | |
8068 `verilog-library-extensions', and being found in the same directory, or | |
8069 by changing the variable `verilog-library-flags' or | |
8070 `verilog-library-directories'. Macros `modname are translated through the | |
8071 vh-{name} Emacs variable, if that is not found, it just ignores the `. | |
8072 | |
8073 In templates you must have one signal per line, ending in a ), or ));, | |
8074 and have proper () nesting, including a final ); to end the template. | |
8075 | |
8076 Typedefs must match `verilog-typedef-regexp', which is disabled by default. | |
8077 | |
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8078 SystemVerilog multidimensional input/output has only experimental support. |
79545 | 8079 |
8080 For example, first take the submodule inst.v: | |
8081 | |
8082 module inst (o,i) | |
8083 output [31:0] o; | |
8084 input i; | |
8085 wire [31:0] o = {32{i}}; | |
8086 endmodule | |
8087 | |
8088 This is then used in a upper level module: | |
8089 | |
8090 module ex_inst (o,i) | |
8091 output o; | |
8092 input i; | |
8093 inst inst (/*AUTOINST*/); | |
8094 endmodule | |
8095 | |
8096 Typing \\[verilog-auto] will make this into: | |
8097 | |
8098 module ex_inst (o,i) | |
8099 output o; | |
8100 input i; | |
8101 inst inst (/*AUTOINST*/ | |
8102 // Outputs | |
8103 .ov (ov[31:0]), | |
8104 // Inputs | |
8105 .i (i)); | |
8106 endmodule | |
8107 | |
8108 Where the list of inputs and outputs came from the inst module. | |
8109 | |
8110 Exceptions: | |
8111 | |
8112 Unless you are instantiating a module multiple times, or the module is | |
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8113 something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY. |
79545 | 8114 It just makes for unmaintainable code. To sanitize signal names, try |
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8115 vrename from http://www.veripool.com. |
79545 | 8116 |
8117 When you need to violate this suggestion there are two ways to list | |
8118 exceptions, placing them before the AUTOINST, or using templates. | |
8119 | |
8120 Any ports defined before the /*AUTOINST*/ are not included in the list of | |
8121 automatics. This is similar to making a template as described below, but | |
8122 is restricted to simple connections just like you normally make. Also note | |
8123 that any signals before the AUTOINST will only be picked up by AUTOWIRE if | |
8124 you have the appropriate // Input or // Output comment, and exactly the | |
8125 same line formatting as AUTOINST itself uses. | |
8126 | |
8127 inst inst (// Inputs | |
8128 .i (my_i_dont_mess_with_it), | |
8129 /*AUTOINST*/ | |
8130 // Outputs | |
8131 .ov (ov[31:0])); | |
8132 | |
8133 | |
8134 Templates: | |
8135 | |
8136 For multiple instantiations based upon a single template, create a | |
8137 commented out template: | |
8138 | |
8139 /* instantiating_module_name AUTO_TEMPLATE ( | |
8140 .sig3 (sigz[]), | |
8141 ); | |
8142 */ | |
8143 | |
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8144 Templates go ABOVE the instantiation(s). When an instantiation is |
79545 | 8145 expanded `verilog-mode' simply searches up for the closest template. |
8146 Thus you can have multiple templates for the same module, just alternate | |
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8147 between the template for an instantiation and the instantiation itself. |
79545 | 8148 |
8149 The module name must be the same as the name of the module in the | |
8150 instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact | |
8151 words and capitalized. Only signals that must be different for each | |
8152 instantiation need to be listed. | |
8153 | |
8154 Inside a template, a [] in a connection name (with nothing else inside | |
8155 the brackets) will be replaced by the same bus subscript as it is being | |
8156 connected to, or the [] will be removed if it is a single bit signal. | |
8157 Generally it is a good idea to do this for all connections in a template, | |
8158 as then they will work for any width signal, and with AUTOWIRE. See | |
8159 PTL_BUS becoming PTL_BUSNEW below. | |
8160 | |
8161 If you have a complicated template, set `verilog-auto-inst-template-numbers' | |
8162 to see which regexps are matching. Don't leave that mode set after | |
8163 debugging is completed though, it will result in lots of extra differences | |
8164 and merge conflicts. | |
8165 | |
8166 For example: | |
8167 | |
8168 /* psm_mas AUTO_TEMPLATE ( | |
8169 .ptl_bus (ptl_busnew[]), | |
8170 ); | |
8171 */ | |
8172 psm_mas ms2m (/*AUTOINST*/); | |
8173 | |
8174 Typing \\[verilog-auto] will make this into: | |
8175 | |
8176 psm_mas ms2m (/*AUTOINST*/ | |
8177 // Outputs | |
8178 .NotInTemplate (NotInTemplate), | |
8179 .ptl_bus (ptl_busnew[3:0]), // Templated | |
8180 .... | |
8181 | |
8182 @ Templates: | |
8183 | |
8184 It is common to instantiate a cell multiple times, so templates make it | |
8185 trivial to substitute part of the cell name into the connection name. | |
8186 | |
8187 /* cell_type AUTO_TEMPLATE <optional \"REGEXP\"> ( | |
8188 .sig1 (sigx[@]), | |
8189 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]), | |
8190 ); | |
8191 */ | |
8192 | |
8193 If no regular expression is provided immediately after the AUTO_TEMPLATE | |
8194 keyword, then the @ character in any connection names will be replaced | |
8195 with the instantiation number; the first digits found in the cell's | |
8196 instantiation name. | |
8197 | |
8198 If a regular expression is provided, the @ character will be replaced | |
8199 with the first \(\) grouping that matches against the cell name. Using a | |
8200 regexp of \"\\([0-9]+\\)\" provides identical values for @ as when no | |
8201 regexp is provided. If you use multiple layers of parenthesis, | |
8202 \"test\\([^0-9]+\\)_\\([0-9]+\\)\" would replace @ with non-number | |
8203 characters after test and before _, whereas | |
8204 \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire | |
8205 match. | |
8206 | |
8207 For example: | |
8208 | |
8209 /* psm_mas AUTO_TEMPLATE ( | |
8210 .ptl_mapvalidx (ptl_mapvalid[@]), | |
8211 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]), | |
8212 ); | |
8213 */ | |
8214 psm_mas ms2m (/*AUTOINST*/); | |
8215 | |
8216 Typing \\[verilog-auto] will make this into: | |
8217 | |
8218 psm_mas ms2m (/*AUTOINST*/ | |
8219 // Outputs | |
8220 .ptl_mapvalidx (ptl_mapvalid[2]), | |
8221 .ptl_mapvalidp1x (ptl_mapvalid[3])); | |
8222 | |
8223 Note the @ character was replaced with the 2 from \"ms2m\". | |
8224 | |
8225 Alternatively, using a regular expression for @: | |
8226 | |
8227 /* psm_mas AUTO_TEMPLATE \"_\\([a-z]+\\)\" ( | |
8228 .ptl_mapvalidx (@_ptl_mapvalid), | |
8229 .ptl_mapvalidp1x (ptl_mapvalid_@), | |
8230 ); | |
8231 */ | |
8232 psm_mas ms2_FOO (/*AUTOINST*/); | |
8233 psm_mas ms2_BAR (/*AUTOINST*/); | |
8234 | |
8235 Typing \\[verilog-auto] will make this into: | |
8236 | |
8237 psm_mas ms2_FOO (/*AUTOINST*/ | |
8238 // Outputs | |
8239 .ptl_mapvalidx (FOO_ptl_mapvalid), | |
8240 .ptl_mapvalidp1x (ptl_mapvalid_FOO)); | |
8241 psm_mas ms2_BAR (/*AUTOINST*/ | |
8242 // Outputs | |
8243 .ptl_mapvalidx (BAR_ptl_mapvalid), | |
8244 .ptl_mapvalidp1x (ptl_mapvalid_BAR)); | |
8245 | |
8246 | |
8247 Regexp Templates: | |
8248 | |
8249 A template entry of the form | |
8250 | |
8251 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]), | |
8252 | |
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8253 will apply an Emacs style regular expression search for any port beginning |
79545 | 8254 in pci_req followed by numbers and ending in _l and connecting that to |
8255 the pci_req_jtag_[] net, with the bus subscript coming from what matches | |
8256 inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2]. | |
8257 | |
8258 Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name | |
8259 does the same thing. (Note a @ in the connection/replacement text is | |
8260 completely different -- still use \\1 there!) Thus this is the same as | |
8261 the above template: | |
8262 | |
8263 .pci_req@_l (pci_req_jtag_[\\1]), | |
8264 | |
8265 Here's another example to remove the _l, useful when naming conventions | |
8266 specify _ alone to mean active low. Note the use of [] to keep the bus | |
8267 subscript: | |
8268 | |
8269 .\\(.*\\)_l (\\1_[]), | |
8270 | |
8271 Lisp Templates: | |
8272 | |
8273 First any regular expression template is expanded. | |
8274 | |
8275 If the syntax @\"( ... )\" is found in a connection, the expression in | |
8276 quotes will be evaluated as a Lisp expression, with @ replaced by the | |
8277 instantiation number. The MAPVALIDP1X example above would put @+1 modulo | |
8278 4 into the brackets. Quote all double-quotes inside the expression with | |
8279 a leading backslash (\\\"). There are special variables defined that are | |
8280 useful in these Lisp functions: | |
8281 | |
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8282 vl-name Name portion of the input/output port. |
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8283 vl-bits Bus bits portion of the input/output port ('[2:0]'). |
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8284 vl-width Width of the input/output port ('3' for [2:0]). |
79545 | 8285 May be a (...) expression if bits isn't a constant. |
8286 vl-dir Direction of the pin input/output/inout. | |
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8287 vl-cell-type Module name/type of the cell ('psm_mas'). |
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8288 vl-cell-name Instance name of the cell ('ms2m'). |
79545 | 8289 |
8290 Normal Lisp variables may be used in expressions. See | |
8291 `verilog-read-defines' which can set vh-{definename} variables for use | |
8292 here. Also, any comments of the form: | |
8293 | |
8294 /*AUTO_LISP(setq foo 1)*/ | |
8295 | |
8296 will evaluate any Lisp expression inside the parenthesis between the | |
8297 beginning of the buffer and the point of the AUTOINST. This allows | |
8298 functions to be defined or variables to be changed between instantiations. | |
8299 | |
8300 Note that when using lisp expressions errors may occur when @ is not a | |
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8301 number; you may need to use the standard Emacs Lisp functions |
79545 | 8302 `number-to-string' and `string-to-number'. |
8303 | |
8304 After the evaluation is completed, @ substitution and [] substitution | |
8305 occur." | |
8306 (save-excursion | |
8307 ;; Find beginning | |
8308 (let* ((pt (point)) | |
8309 (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*"))) | |
8310 (indent-pt (save-excursion (verilog-backward-open-paren) | |
8311 (1+ (current-column)))) | |
8312 (verilog-auto-inst-column (max verilog-auto-inst-column | |
8313 (+ 16 (* 8 (/ (+ indent-pt 7) 8))))) | |
8314 (modi (verilog-modi-current)) | |
8315 (vector-skip-list (unless verilog-auto-inst-vector | |
8316 (verilog-modi-get-signals modi))) | |
8317 submod submodi inst skip-pins tpl-list tpl-num did-first) | |
8318 ;; Find module name that is instantiated | |
8319 (setq submod (verilog-read-inst-module) | |
8320 inst (verilog-read-inst-name) | |
8321 vl-cell-type submod | |
8322 vl-cell-name inst | |
8323 skip-pins (aref (verilog-read-inst-pins) 0)) | |
8324 | |
8325 ;; Parse any AUTO_LISP() before here | |
8326 (verilog-read-auto-lisp (point-min) pt) | |
8327 | |
8328 ;; Lookup position, etc of submodule | |
8329 ;; Note this may raise an error | |
8330 (when (setq submodi (verilog-modi-lookup submod t)) | |
8331 ;; If there's a number in the instantiation, it may be a argument to the | |
8332 ;; automatic variable instantiation program. | |
8333 (let* ((tpl-info (verilog-read-auto-template submod)) | |
8334 (tpl-regexp (aref tpl-info 0))) | |
8335 (setq tpl-num (if (string-match tpl-regexp inst) | |
8336 (match-string 1 inst) | |
8337 "") | |
8338 tpl-list (aref tpl-info 1))) | |
8339 ;; Find submodule's signals and dump | |
8340 (let ((sig-list (verilog-signals-not-in | |
8341 (verilog-modi-get-outputs submodi) | |
8342 skip-pins)) | |
8343 (vl-dir "output")) | |
8344 (when sig-list | |
8345 (when (not did-first) (verilog-auto-inst-first) (setq did-first t)) | |
8346 (indent-to indent-pt) | |
79691
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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79555
diff
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|
8347 ;; Note these are searched for in verilog-read-sub-decls. |
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changeset
|
8348 (insert "// Outputs\n") |
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parents:
79555
diff
changeset
|
8349 (mapc (lambda (port) |
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parents:
79555
diff
changeset
|
8350 (verilog-auto-inst-port port indent-pt |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
8351 tpl-list tpl-num for-star)) |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
8352 sig-list))) |
79545 | 8353 (let ((sig-list (verilog-signals-not-in |
8354 (verilog-modi-get-inouts submodi) | |
8355 skip-pins)) | |
8356 (vl-dir "inout")) | |
8357 (when sig-list | |
8358 (when (not did-first) (verilog-auto-inst-first) (setq did-first t)) | |
8359 (indent-to indent-pt) | |
8360 (insert "// Inouts\n") | |
79691
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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79555
diff
changeset
|
8361 (mapc (lambda (port) |
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|
8362 (verilog-auto-inst-port port indent-pt |
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|
8363 tpl-list tpl-num for-star)) |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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79555
diff
changeset
|
8364 sig-list))) |
79545 | 8365 (let ((sig-list (verilog-signals-not-in |
8366 (verilog-modi-get-inputs submodi) | |
8367 skip-pins)) | |
8368 (vl-dir "input")) | |
8369 (when sig-list | |
8370 (when (not did-first) (verilog-auto-inst-first) (setq did-first t)) | |
8371 (indent-to indent-pt) | |
8372 (insert "// Inputs\n") | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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changeset
|
8373 (mapc (lambda (port) |
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parents:
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changeset
|
8374 (verilog-auto-inst-port port indent-pt |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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changeset
|
8375 tpl-list tpl-num for-star)) |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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diff
changeset
|
8376 sig-list))) |
79545 | 8377 ;; Kill extra semi |
8378 (save-excursion | |
8379 (cond (did-first | |
8380 (re-search-backward "," pt t) | |
8381 (delete-char 1) | |
8382 (insert ");") | |
8383 (search-forward "\n") ;; Added by inst-port | |
8384 (delete-backward-char 1) | |
8385 (if (search-forward ")" nil t) ;; From user, moved up a line | |
8386 (delete-backward-char 1)) | |
8387 (if (search-forward ";" nil t) ;; Don't error if user had syntax error and forgot it | |
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(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
8388 (delete-backward-char 1))))))))) |
79545 | 8389 |
8390 (defun verilog-auto-inst-param () | |
8391 "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto]. | |
8392 Replace the parameter connections to an instantiation with ones | |
8393 automatically derived from the module header of the instantiated netlist. | |
8394 | |
8395 See \\[verilog-auto-inst] for limitations, and templates to customize the | |
8396 output. | |
8397 | |
8398 For example, first take the submodule inst.v: | |
8399 | |
8400 module inst (o,i) | |
8401 parameter PAR; | |
8402 endmodule | |
8403 | |
8404 This is then used in a upper level module: | |
8405 | |
8406 module ex_inst (o,i) | |
8407 parameter PAR; | |
8408 inst #(/*AUTOINSTPARAM*/) | |
8409 inst (/*AUTOINST*/); | |
8410 endmodule | |
8411 | |
8412 Typing \\[verilog-auto] will make this into: | |
8413 | |
8414 module ex_inst (o,i) | |
8415 output o; | |
8416 input i; | |
8417 inst (/*AUTOINSTPARAM*/ | |
8418 // Parameters | |
8419 .PAR (PAR)); | |
8420 inst (/*AUTOINST*/); | |
8421 endmodule | |
8422 | |
8423 Where the list of parameter connections come from the inst module. | |
8424 | |
8425 Templates: | |
8426 | |
8427 You can customize the parameter connections using AUTO_TEMPLATEs, | |
8428 just as you would with \\[verilog-auto-inst]." | |
8429 (save-excursion | |
8430 ;; Find beginning | |
8431 (let* ((pt (point)) | |
8432 (indent-pt (save-excursion (verilog-backward-open-paren) | |
8433 (1+ (current-column)))) | |
8434 (verilog-auto-inst-column (max verilog-auto-inst-column | |
8435 (+ 16 (* 8 (/ (+ indent-pt 7) 8))))) | |
8436 (modi (verilog-modi-current)) | |
8437 (vector-skip-list (unless verilog-auto-inst-vector | |
8438 (verilog-modi-get-signals modi))) | |
8439 submod submodi inst skip-pins tpl-list tpl-num did-first) | |
8440 ;; Find module name that is instantiated | |
8441 (setq submod (save-excursion | |
8442 ;; Get to the point where AUTOINST normally is to read the module | |
8443 (verilog-re-search-forward-quick "[(;]" nil nil) | |
8444 (verilog-read-inst-module)) | |
8445 inst (save-excursion | |
8446 ;; Get to the point where AUTOINST normally is to read the module | |
8447 (verilog-re-search-forward-quick "[(;]" nil nil) | |
8448 (verilog-read-inst-name)) | |
8449 vl-cell-type submod | |
8450 vl-cell-name inst | |
8451 skip-pins (aref (verilog-read-inst-pins) 0)) | |
8452 | |
8453 ;; Parse any AUTO_LISP() before here | |
8454 (verilog-read-auto-lisp (point-min) pt) | |
8455 | |
8456 ;; Lookup position, etc of submodule | |
8457 ;; Note this may raise an error | |
8458 (when (setq submodi (verilog-modi-lookup submod t)) | |
8459 ;; If there's a number in the instantiation, it may be a argument to the | |
8460 ;; automatic variable instantiation program. | |
8461 (let* ((tpl-info (verilog-read-auto-template submod)) | |
8462 (tpl-regexp (aref tpl-info 0))) | |
8463 (setq tpl-num (if (string-match tpl-regexp inst) | |
8464 (match-string 1 inst) | |
8465 "") | |
8466 tpl-list (aref tpl-info 1))) | |
8467 ;; Find submodule's signals and dump | |
8468 (let ((sig-list (verilog-signals-not-in | |
8469 (verilog-modi-get-gparams submodi) | |
8470 skip-pins)) | |
8471 (vl-dir "parameter")) | |
8472 (when sig-list | |
8473 (when (not did-first) (verilog-auto-inst-first) (setq did-first t)) | |
8474 (indent-to indent-pt) | |
79691
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parents:
79555
diff
changeset
|
8475 ;; Note these are searched for in verilog-read-sub-decls. |
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parents:
79555
diff
changeset
|
8476 (insert "// Parameters\n") |
d3e3c91e18f6
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79555
diff
changeset
|
8477 (mapc (lambda (port) |
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parents:
79555
diff
changeset
|
8478 (verilog-auto-inst-port port indent-pt |
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parents:
79555
diff
changeset
|
8479 tpl-list tpl-num nil)) |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
8480 sig-list))) |
79545 | 8481 ;; Kill extra semi |
8482 (save-excursion | |
8483 (cond (did-first | |
8484 (re-search-backward "," pt t) | |
8485 (delete-char 1) | |
8486 (insert ")") | |
8487 (search-forward "\n") ;; Added by inst-port | |
8488 (delete-backward-char 1) | |
8489 (if (search-forward ")" nil t) ;; From user, moved up a line | |
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parents:
79717
diff
changeset
|
8490 (delete-backward-char 1))))))))) |
79545 | 8491 |
8492 (defun verilog-auto-reg () | |
8493 "Expand AUTOREG statements, as part of \\[verilog-auto]. | |
8494 Make reg statements for any output that isn't already declared, | |
8495 and isn't a wire output from a block. | |
8496 | |
8497 Limitations: | |
8498 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'). | |
8499 | |
8500 This does NOT work on memories, declare those yourself. | |
8501 | |
8502 An example: | |
8503 | |
8504 module ex_reg (o,i) | |
8505 output o; | |
8506 input i; | |
8507 /*AUTOREG*/ | |
8508 always o = i; | |
8509 endmodule | |
8510 | |
8511 Typing \\[verilog-auto] will make this into: | |
8512 | |
8513 module ex_reg (o,i) | |
8514 output o; | |
8515 input i; | |
8516 /*AUTOREG*/ | |
8517 // Beginning of automatic regs (for this module's undeclared outputs) | |
8518 reg o; | |
8519 // End of automatics | |
8520 always o = i; | |
8521 endmodule" | |
8522 (save-excursion | |
8523 ;; Point must be at insertion point. | |
8524 (let* ((indent-pt (current-indentation)) | |
8525 (modi (verilog-modi-current)) | |
8526 (sig-list (verilog-signals-not-in | |
8527 (verilog-modi-get-outputs modi) | |
8528 (append (verilog-modi-get-wires modi) | |
8529 (verilog-modi-get-regs modi) | |
8530 (verilog-modi-get-assigns modi) | |
8531 (verilog-modi-get-consts modi) | |
8532 (verilog-modi-get-gparams modi) | |
8533 (verilog-modi-get-sub-outputs modi) | |
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parents:
79717
diff
changeset
|
8534 (verilog-modi-get-sub-inouts modi))))) |
79545 | 8535 (forward-line 1) |
8536 (when sig-list | |
8537 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n") | |
8538 (verilog-insert-definition sig-list "reg" indent-pt nil) | |
8539 (verilog-modi-cache-add-regs modi sig-list) | |
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parents:
79717
diff
changeset
|
8540 (verilog-insert-indent "// End of automatics\n"))))) |
79545 | 8541 |
8542 (defun verilog-auto-reg-input () | |
8543 "Expand AUTOREGINPUT statements, as part of \\[verilog-auto]. | |
8544 Make reg statements instantiation inputs that aren't already declared. | |
8545 This is useful for making a top level shell for testing the module that is | |
8546 to be instantiated. | |
8547 | |
8548 Limitations: | |
8549 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls'). | |
8550 | |
8551 This does NOT work on memories, declare those yourself. | |
8552 | |
8553 An example (see `verilog-auto-inst' for what else is going on here): | |
8554 | |
8555 module ex_reg_input (o,i) | |
8556 output o; | |
8557 input i; | |
8558 /*AUTOREGINPUT*/ | |
8559 inst inst (/*AUTOINST*/); | |
8560 endmodule | |
8561 | |
8562 Typing \\[verilog-auto] will make this into: | |
8563 | |
8564 module ex_reg_input (o,i) | |
8565 output o; | |
8566 input i; | |
8567 /*AUTOREGINPUT*/ | |
8568 // Beginning of automatic reg inputs (for undeclared ... | |
8569 reg [31:0] iv; // From inst of inst.v | |
8570 // End of automatics | |
8571 inst inst (/*AUTOINST*/ | |
8572 // Outputs | |
8573 .o (o[31:0]), | |
8574 // Inputs | |
8575 .iv (iv)); | |
8576 endmodule" | |
8577 (save-excursion | |
8578 ;; Point must be at insertion point. | |
8579 (let* ((indent-pt (current-indentation)) | |
8580 (modi (verilog-modi-current)) | |
8581 (sig-list (verilog-signals-combine-bus | |
8582 (verilog-signals-not-in | |
8583 (append (verilog-modi-get-sub-inputs modi) | |
8584 (verilog-modi-get-sub-inouts modi)) | |
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parents:
79717
diff
changeset
|
8585 (verilog-modi-get-signals modi))))) |
79545 | 8586 (forward-line 1) |
8587 (when sig-list | |
8588 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n") | |
8589 (verilog-insert-definition sig-list "reg" indent-pt nil) | |
8590 (verilog-modi-cache-add-regs modi sig-list) | |
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diff
changeset
|
8591 (verilog-insert-indent "// End of automatics\n"))))) |
79545 | 8592 |
8593 (defun verilog-auto-wire () | |
8594 "Expand AUTOWIRE statements, as part of \\[verilog-auto]. | |
8595 Make wire statements for instantiations outputs that aren't | |
8596 already declared. | |
8597 | |
8598 Limitations: | |
8599 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'), | |
8600 and all busses must have widths, such as those from AUTOINST, or using [] | |
8601 in AUTO_TEMPLATEs. | |
8602 | |
8603 This does NOT work on memories or SystemVerilog .name connections, | |
8604 declare those yourself. | |
8605 | |
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80163
diff
changeset
|
8606 Verilog mode will add \"Couldn't Merge\" comments to signals it cannot |
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80163
diff
changeset
|
8607 determine how to bus together. This occurs when you have ports with |
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diff
changeset
|
8608 non-numeric or non-sequential bus subscripts. If Verilog mode |
79545 | 8609 mis-guessed, you'll have to declare them yourself. |
8610 | |
8611 An example (see `verilog-auto-inst' for what else is going on here): | |
8612 | |
8613 module ex_wire (o,i) | |
8614 output o; | |
8615 input i; | |
8616 /*AUTOWIRE*/ | |
8617 inst inst (/*AUTOINST*/); | |
8618 endmodule | |
8619 | |
8620 Typing \\[verilog-auto] will make this into: | |
8621 | |
8622 module ex_wire (o,i) | |
8623 output o; | |
8624 input i; | |
8625 /*AUTOWIRE*/ | |
8626 // Beginning of automatic wires | |
8627 wire [31:0] ov; // From inst of inst.v | |
8628 // End of automatics | |
8629 inst inst (/*AUTOINST*/ | |
8630 // Outputs | |
8631 .ov (ov[31:0]), | |
8632 // Inputs | |
8633 .i (i)); | |
8634 wire o = | ov; | |
8635 endmodule" | |
8636 (save-excursion | |
8637 ;; Point must be at insertion point. | |
8638 (let* ((indent-pt (current-indentation)) | |
8639 (modi (verilog-modi-current)) | |
8640 (sig-list (verilog-signals-combine-bus | |
8641 (verilog-signals-not-in | |
8642 (append (verilog-modi-get-sub-outputs modi) | |
8643 (verilog-modi-get-sub-inouts modi)) | |
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diff
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|
8644 (verilog-modi-get-signals modi))))) |
79545 | 8645 (forward-line 1) |
8646 (when sig-list | |
8647 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n") | |
8648 (verilog-insert-definition sig-list "wire" indent-pt nil) | |
8649 (verilog-modi-cache-add-wires modi sig-list) | |
8650 (verilog-insert-indent "// End of automatics\n") | |
8651 (when nil ;; Too slow on huge modules, plus makes everyone's module change | |
8652 (beginning-of-line) | |
8653 (setq pnt (point)) | |
80024
9231505e5076
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79986
diff
changeset
|
8654 (verilog-pretty-declarations quiet) |
79545 | 8655 (goto-char pnt) |
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diff
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|
8656 (verilog-pretty-expr "//")))))) |
79545 | 8657 |
8658 (defun verilog-auto-output () | |
8659 "Expand AUTOOUTPUT statements, as part of \\[verilog-auto]. | |
8660 Make output statements for any output signal from an /*AUTOINST*/ that | |
8661 isn't a input to another AUTOINST. This is useful for modules which | |
8662 only instantiate other modules. | |
8663 | |
8664 Limitations: | |
8665 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'). | |
8666 | |
8667 If placed inside the parenthesis of a module declaration, it creates | |
8668 Verilog 2001 style, else uses Verilog 1995 style. | |
8669 | |
8670 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's | |
8671 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE). | |
8672 | |
8673 Typedefs must match `verilog-typedef-regexp', which is disabled by default. | |
8674 | |
8675 Signals matching `verilog-auto-output-ignore-regexp' are not included. | |
8676 | |
8677 An example (see `verilog-auto-inst' for what else is going on here): | |
8678 | |
8679 module ex_output (ov,i) | |
8680 input i; | |
8681 /*AUTOOUTPUT*/ | |
8682 inst inst (/*AUTOINST*/); | |
8683 endmodule | |
8684 | |
8685 Typing \\[verilog-auto] will make this into: | |
8686 | |
8687 module ex_output (ov,i) | |
8688 input i; | |
8689 /*AUTOOUTPUT*/ | |
8690 // Beginning of automatic outputs (from unused autoinst outputs) | |
8691 output [31:0] ov; // From inst of inst.v | |
8692 // End of automatics | |
8693 inst inst (/*AUTOINST*/ | |
8694 // Outputs | |
8695 .ov (ov[31:0]), | |
8696 // Inputs | |
8697 .i (i)); | |
8698 endmodule" | |
8699 (save-excursion | |
8700 ;; Point must be at insertion point. | |
8701 (let* ((indent-pt (current-indentation)) | |
8702 (v2k (verilog-in-paren)) | |
8703 (modi (verilog-modi-current)) | |
8704 (sig-list (verilog-signals-not-in | |
8705 (verilog-modi-get-sub-outputs modi) | |
8706 (append (verilog-modi-get-outputs modi) | |
8707 (verilog-modi-get-inouts modi) | |
8708 (verilog-modi-get-sub-inputs modi) | |
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8709 (verilog-modi-get-sub-inouts modi))))) |
79545 | 8710 (setq sig-list (verilog-signals-not-matching-regexp |
8711 sig-list verilog-auto-output-ignore-regexp)) | |
8712 (forward-line 1) | |
8713 (when v2k (verilog-repair-open-comma)) | |
8714 (when sig-list | |
8715 (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n") | |
8716 (verilog-insert-definition sig-list "output" indent-pt v2k) | |
8717 (verilog-modi-cache-add-outputs modi sig-list) | |
8718 (verilog-insert-indent "// End of automatics\n")) | |
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8719 (when v2k (verilog-repair-close-comma))))) |
79545 | 8720 |
8721 (defun verilog-auto-output-every () | |
8722 "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto]. | |
8723 Make output statements for any signals that aren't primary inputs or | |
8724 outputs already. This makes every signal in the design a output. This is | |
8725 useful to get Synopsys to preserve every signal in the design, since it | |
8726 won't optimize away the outputs. | |
8727 | |
8728 An example: | |
8729 | |
8730 module ex_output_every (o,i,tempa,tempb) | |
8731 output o; | |
8732 input i; | |
8733 /*AUTOOUTPUTEVERY*/ | |
8734 wire tempa = i; | |
8735 wire tempb = tempa; | |
8736 wire o = tempb; | |
8737 endmodule | |
8738 | |
8739 Typing \\[verilog-auto] will make this into: | |
8740 | |
8741 module ex_output_every (o,i,tempa,tempb) | |
8742 output o; | |
8743 input i; | |
8744 /*AUTOOUTPUTEVERY*/ | |
8745 // Beginning of automatic outputs (every signal) | |
8746 output tempb; | |
8747 output tempa; | |
8748 // End of automatics | |
8749 wire tempa = i; | |
8750 wire tempb = tempa; | |
8751 wire o = tempb; | |
8752 endmodule" | |
8753 (save-excursion | |
8754 ;;Point must be at insertion point | |
8755 (let* ((indent-pt (current-indentation)) | |
8756 (v2k (verilog-in-paren)) | |
8757 (modi (verilog-modi-current)) | |
8758 (sig-list (verilog-signals-combine-bus | |
8759 (verilog-signals-not-in | |
8760 (verilog-modi-get-signals modi) | |
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8761 (verilog-modi-get-ports modi))))) |
79545 | 8762 (forward-line 1) |
8763 (when v2k (verilog-repair-open-comma)) | |
8764 (when sig-list | |
8765 (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n") | |
8766 (verilog-insert-definition sig-list "output" indent-pt v2k) | |
8767 (verilog-modi-cache-add-outputs modi sig-list) | |
8768 (verilog-insert-indent "// End of automatics\n")) | |
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|
8769 (when v2k (verilog-repair-close-comma))))) |
79545 | 8770 |
8771 (defun verilog-auto-input () | |
8772 "Expand AUTOINPUT statements, as part of \\[verilog-auto]. | |
8773 Make input statements for any input signal into an /*AUTOINST*/ that | |
8774 isn't declared elsewhere inside the module. This is useful for modules which | |
8775 only instantiate other modules. | |
8776 | |
8777 Limitations: | |
8778 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'). | |
8779 | |
8780 If placed inside the parenthesis of a module declaration, it creates | |
8781 Verilog 2001 style, else uses Verilog 1995 style. | |
8782 | |
8783 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's | |
8784 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE). | |
8785 | |
8786 Typedefs must match `verilog-typedef-regexp', which is disabled by default. | |
8787 | |
8788 Signals matching `verilog-auto-input-ignore-regexp' are not included. | |
8789 | |
8790 An example (see `verilog-auto-inst' for what else is going on here): | |
8791 | |
8792 module ex_input (ov,i) | |
8793 output [31:0] ov; | |
8794 /*AUTOINPUT*/ | |
8795 inst inst (/*AUTOINST*/); | |
8796 endmodule | |
8797 | |
8798 Typing \\[verilog-auto] will make this into: | |
8799 | |
8800 module ex_input (ov,i) | |
8801 output [31:0] ov; | |
8802 /*AUTOINPUT*/ | |
8803 // Beginning of automatic inputs (from unused autoinst inputs) | |
8804 input i; // From inst of inst.v | |
8805 // End of automatics | |
8806 inst inst (/*AUTOINST*/ | |
8807 // Outputs | |
8808 .ov (ov[31:0]), | |
8809 // Inputs | |
8810 .i (i)); | |
8811 endmodule" | |
8812 (save-excursion | |
8813 (let* ((indent-pt (current-indentation)) | |
8814 (v2k (verilog-in-paren)) | |
8815 (modi (verilog-modi-current)) | |
8816 (sig-list (verilog-signals-not-in | |
8817 (verilog-modi-get-sub-inputs modi) | |
8818 (append (verilog-modi-get-inputs modi) | |
8819 (verilog-modi-get-inouts modi) | |
8820 (verilog-modi-get-wires modi) | |
8821 (verilog-modi-get-regs modi) | |
8822 (verilog-modi-get-consts modi) | |
8823 (verilog-modi-get-gparams modi) | |
8824 (verilog-modi-get-sub-outputs modi) | |
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8825 (verilog-modi-get-sub-inouts modi))))) |
79545 | 8826 (setq sig-list (verilog-signals-not-matching-regexp |
8827 sig-list verilog-auto-input-ignore-regexp)) | |
8828 (forward-line 1) | |
8829 (when v2k (verilog-repair-open-comma)) | |
8830 (when sig-list | |
8831 (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n") | |
8832 (verilog-insert-definition sig-list "input" indent-pt v2k) | |
8833 (verilog-modi-cache-add-inputs modi sig-list) | |
8834 (verilog-insert-indent "// End of automatics\n")) | |
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8835 (when v2k (verilog-repair-close-comma))))) |
79545 | 8836 |
8837 (defun verilog-auto-inout () | |
8838 "Expand AUTOINOUT statements, as part of \\[verilog-auto]. | |
8839 Make inout statements for any inout signal in an /*AUTOINST*/ that | |
8840 isn't declared elsewhere inside the module. | |
8841 | |
8842 Limitations: | |
8843 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'). | |
8844 | |
8845 If placed inside the parenthesis of a module declaration, it creates | |
8846 Verilog 2001 style, else uses Verilog 1995 style. | |
8847 | |
8848 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's | |
8849 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE). | |
8850 | |
8851 Typedefs must match `verilog-typedef-regexp', which is disabled by default. | |
8852 | |
8853 Signals matching `verilog-auto-inout-ignore-regexp' are not included. | |
8854 | |
8855 An example (see `verilog-auto-inst' for what else is going on here): | |
8856 | |
8857 module ex_inout (ov,i) | |
8858 input i; | |
8859 /*AUTOINOUT*/ | |
8860 inst inst (/*AUTOINST*/); | |
8861 endmodule | |
8862 | |
8863 Typing \\[verilog-auto] will make this into: | |
8864 | |
8865 module ex_inout (ov,i) | |
8866 input i; | |
8867 /*AUTOINOUT*/ | |
8868 // Beginning of automatic inouts (from unused autoinst inouts) | |
8869 inout [31:0] ov; // From inst of inst.v | |
8870 // End of automatics | |
8871 inst inst (/*AUTOINST*/ | |
8872 // Inouts | |
8873 .ov (ov[31:0]), | |
8874 // Inputs | |
8875 .i (i)); | |
8876 endmodule" | |
8877 (save-excursion | |
8878 ;; Point must be at insertion point. | |
8879 (let* ((indent-pt (current-indentation)) | |
8880 (v2k (verilog-in-paren)) | |
8881 (modi (verilog-modi-current)) | |
8882 (sig-list (verilog-signals-not-in | |
8883 (verilog-modi-get-sub-inouts modi) | |
8884 (append (verilog-modi-get-outputs modi) | |
8885 (verilog-modi-get-inouts modi) | |
8886 (verilog-modi-get-inputs modi) | |
8887 (verilog-modi-get-sub-inputs modi) | |
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8888 (verilog-modi-get-sub-outputs modi))))) |
79545 | 8889 (setq sig-list (verilog-signals-not-matching-regexp |
8890 sig-list verilog-auto-inout-ignore-regexp)) | |
8891 (forward-line 1) | |
8892 (when v2k (verilog-repair-open-comma)) | |
8893 (when sig-list | |
8894 (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n") | |
8895 (verilog-insert-definition sig-list "inout" indent-pt v2k) | |
8896 (verilog-modi-cache-add-inouts modi sig-list) | |
8897 (verilog-insert-indent "// End of automatics\n")) | |
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8898 (when v2k (verilog-repair-close-comma))))) |
79545 | 8899 |
8900 (defun verilog-auto-inout-module () | |
8901 "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto]. | |
8902 Take input/output/inout statements from the specified module and insert | |
8903 into the current module. This is useful for making null templates and | |
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8904 shell modules which need to have identical I/O with another module. |
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8905 Any I/O which are already defined in this module will not be redefined. |
79545 | 8906 |
8907 Limitations: | |
8908 If placed inside the parenthesis of a module declaration, it creates | |
8909 Verilog 2001 style, else uses Verilog 1995 style. | |
8910 | |
8911 Concatenation and outputting partial busses is not supported. | |
8912 | |
8913 Module names must be resolvable to filenames. See `verilog-auto-inst'. | |
8914 | |
8915 Signals are not inserted in the same order as in the original module, | |
8916 though they will appear to be in the same order to a AUTOINST | |
8917 instantiating either module. | |
8918 | |
8919 An example: | |
8920 | |
8921 module ex_shell (/*AUTOARG*/) | |
8922 /*AUTOINOUTMODULE(\"ex_main\")*/ | |
8923 endmodule | |
8924 | |
8925 module ex_main (i,o,io) | |
8926 input i; | |
8927 output o; | |
8928 inout io; | |
8929 endmodule | |
8930 | |
8931 Typing \\[verilog-auto] will make this into: | |
8932 | |
8933 module ex_shell (/*AUTOARG*/i,o,io) | |
8934 /*AUTOINOUTMODULE(\"ex_main\")*/ | |
8935 // Beginning of automatic in/out/inouts (from specific module) | |
8936 input i; | |
8937 output o; | |
8938 inout io; | |
8939 // End of automatics | |
8940 endmodule" | |
8941 (save-excursion | |
8942 (let* ((submod (car (verilog-read-auto-params 1))) submodi) | |
8943 ;; Lookup position, etc of co-module | |
8944 ;; Note this may raise an error | |
8945 (when (setq submodi (verilog-modi-lookup submod t)) | |
8946 (let* ((indent-pt (current-indentation)) | |
8947 (v2k (verilog-in-paren)) | |
8948 (modi (verilog-modi-current)) | |
8949 (sig-list-i (verilog-signals-not-in | |
8950 (verilog-modi-get-inputs submodi) | |
8951 (append (verilog-modi-get-inputs modi)))) | |
8952 (sig-list-o (verilog-signals-not-in | |
8953 (verilog-modi-get-outputs submodi) | |
8954 (append (verilog-modi-get-outputs modi)))) | |
8955 (sig-list-io (verilog-signals-not-in | |
8956 (verilog-modi-get-inouts submodi) | |
8957 (append (verilog-modi-get-inouts modi))))) | |
8958 (forward-line 1) | |
8959 (when v2k (verilog-repair-open-comma)) | |
8960 (when (or sig-list-i sig-list-o sig-list-io) | |
8961 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n") | |
8962 ;; Don't sort them so a upper AUTOINST will match the main module | |
8963 (verilog-insert-definition sig-list-o "output" indent-pt v2k t) | |
8964 (verilog-insert-definition sig-list-io "inout" indent-pt v2k t) | |
8965 (verilog-insert-definition sig-list-i "input" indent-pt v2k t) | |
8966 (verilog-modi-cache-add-inputs modi sig-list-i) | |
8967 (verilog-modi-cache-add-outputs modi sig-list-o) | |
8968 (verilog-modi-cache-add-inouts modi sig-list-io) | |
8969 (verilog-insert-indent "// End of automatics\n")) | |
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8970 (when v2k (verilog-repair-close-comma))))))) |
79545 | 8971 |
8972 (defun verilog-auto-sense-sigs (modi presense-sigs) | |
8973 "Return list of signals for current AUTOSENSE block." | |
8974 (let* ((sigss (verilog-read-always-signals)) | |
8975 (sig-list (verilog-signals-not-params | |
8976 (verilog-signals-not-in (verilog-alw-get-inputs sigss) | |
8977 (append (and (not verilog-auto-sense-include-inputs) | |
8978 (verilog-alw-get-outputs sigss)) | |
8979 (verilog-modi-get-consts modi) | |
8980 (verilog-modi-get-gparams modi) | |
8981 presense-sigs))))) | |
8982 sig-list)) | |
8983 | |
8984 (defun verilog-auto-sense () | |
8985 "Expand AUTOSENSE statements, as part of \\[verilog-auto]. | |
8986 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short) | |
8987 with one automatically derived from all inputs declared in the always | |
8988 statement. Signals that are generated within the same always block are NOT | |
8989 placed into the sensitivity list (see `verilog-auto-sense-include-inputs'). | |
8990 Long lines are split based on the `fill-column', see \\[set-fill-column]. | |
8991 | |
8992 Limitations: | |
8993 Verilog does not allow memories (multidimensional arrays) in sensitivity | |
8994 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment. | |
8995 | |
8996 Constant signals: | |
8997 AUTOSENSE cannot always determine if a `define is a constant or a signal | |
8998 (it could be in a include file for example). If a `define or other signal | |
8999 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT | |
9000 declaration anywhere in the module (parenthesis are required): | |
9001 | |
9002 /* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */ | |
9003 | |
9004 Better yet, use a parameter, which will be understood to be constant | |
9005 automatically. | |
9006 | |
9007 OOps! | |
9008 If AUTOSENSE makes a mistake, please report it. (First try putting | |
9009 a begin/end after your always!) As a workaround, if a signal that | |
9010 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above. | |
9011 If a signal should be in the sensitivity list wasn't, placing it before | |
9012 the /*AUTOSENSE*/ comment will prevent it from being deleted when the | |
9013 autos are updated (or added if it occurs there already). | |
9014 | |
9015 An example: | |
9016 | |
9017 always @ (/*AUTOSENSE*/) begin | |
9018 /* AUTO_CONSTANT (`constant) */ | |
9019 outin = ina | inb | `constant; | |
9020 out = outin; | |
9021 end | |
9022 | |
9023 Typing \\[verilog-auto] will make this into: | |
9024 | |
9025 always @ (/*AUTOSENSE*/ina or inb) begin | |
9026 /* AUTO_CONSTANT (`constant) */ | |
9027 outin = ina | inb | `constant; | |
9028 out = outin; | |
9029 end" | |
9030 (save-excursion | |
9031 ;; Find beginning | |
9032 (let* ((start-pt (save-excursion | |
9033 (verilog-re-search-backward "(" nil t) | |
9034 (point))) | |
9035 (indent-pt (save-excursion | |
9036 (or (and (goto-char start-pt) (1+ (current-column))) | |
9037 (current-indentation)))) | |
9038 (modi (verilog-modi-current)) | |
9039 (sig-memories (verilog-signals-memory | |
9040 (append | |
9041 (verilog-modi-get-regs modi) | |
9042 (verilog-modi-get-wires modi)))) | |
9043 sig-list not-first presense-sigs) | |
9044 ;; Read signals in always, eliminate outputs from sense list | |
9045 (setq presense-sigs (verilog-signals-from-signame | |
9046 (save-excursion | |
9047 (verilog-read-signals start-pt (point))))) | |
9048 (setq sig-list (verilog-auto-sense-sigs modi presense-sigs)) | |
9049 (when sig-memories | |
9050 (let ((tlen (length sig-list))) | |
9051 (setq sig-list (verilog-signals-not-in sig-list sig-memories)) | |
9052 (if (not (eq tlen (length sig-list))) (insert " /*memory or*/ ")))) | |
9053 (if (and presense-sigs ;; Add a "or" if not "(.... or /*AUTOSENSE*/" | |
9054 (save-excursion (goto-char (point)) | |
9055 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t) | |
9056 (verilog-re-search-backward "\\s-" start-pt t) | |
9057 (while (looking-at "\\s-`endif") | |
9058 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t) | |
9059 (verilog-re-search-backward "\\s-" start-pt t)) | |
9060 (not (looking-at "\\s-or\\b")))) | |
9061 (setq not-first t)) | |
9062 (setq sig-list (sort sig-list `verilog-signals-sort-compare)) | |
9063 (while sig-list | |
9064 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or | |
9065 (insert "\n") | |
9066 (indent-to indent-pt) | |
9067 (if not-first (insert "or "))) | |
9068 (not-first (insert " or "))) | |
9069 (insert (verilog-sig-name (car sig-list))) | |
9070 (setq sig-list (cdr sig-list) | |
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9071 not-first t))))) |
79545 | 9072 |
9073 (defun verilog-auto-reset () | |
9074 "Expand AUTORESET statements, as part of \\[verilog-auto]. | |
9075 Replace the /*AUTORESET*/ comment with code to initialize all | |
9076 registers set elsewhere in the always block. | |
9077 | |
9078 Limitations: | |
9079 AUTORESET will not clear memories. | |
9080 | |
9081 AUTORESET uses <= if there are any <= in the block, else it uses =. | |
9082 | |
9083 /*AUTORESET*/ presumes that any signals mentioned between the previous | |
9084 begin/case/if statement and the AUTORESET comment are being reset manually | |
9085 and should not be automatically reset. This includes omitting any signals | |
9086 used on the right hand side of assignments. | |
9087 | |
9088 By default, AUTORESET will include the width of the signal in the autos, | |
9089 this is a recent change. To control this behavior, see | |
9090 `verilog-auto-reset-widths'. | |
9091 | |
9092 AUTORESET ties signals to deasserted, which is presumed to be zero. | |
9093 Signals that match `verilog-active-low-regexp' will be deasserted by tieing | |
9094 them to a one. | |
9095 | |
9096 An example: | |
9097 | |
9098 always @(posedge clk or negedge reset_l) begin | |
9099 if (!reset_l) begin | |
9100 c <= 1; | |
9101 /*AUTORESET*/ | |
9102 end | |
9103 else begin | |
9104 a <= in_a; | |
9105 b <= in_b; | |
9106 c <= in_c; | |
9107 end | |
9108 end | |
9109 | |
9110 Typing \\[verilog-auto] will make this into: | |
9111 | |
9112 always @(posedge core_clk or negedge reset_l) begin | |
9113 if (!reset_l) begin | |
9114 c <= 1; | |
9115 /*AUTORESET*/ | |
9116 // Beginning of autoreset for uninitialized flops | |
9117 a <= 0; | |
9118 b <= 0; | |
9119 // End of automatics | |
9120 end | |
9121 else begin | |
9122 a <= in_a; | |
9123 b <= in_b; | |
9124 c <= in_c; | |
9125 end | |
9126 end" | |
9127 | |
9128 (interactive) | |
9129 (save-excursion | |
9130 ;; Find beginning | |
9131 (let* ((indent-pt (current-indentation)) | |
9132 (modi (verilog-modi-current)) | |
9133 (all-list (verilog-modi-get-signals modi)) | |
9134 sigss sig-list prereset-sigs assignment-str) | |
9135 ;; Read signals in always, eliminate outputs from reset list | |
9136 (setq prereset-sigs (verilog-signals-from-signame | |
9137 (save-excursion | |
9138 (verilog-read-signals | |
9139 (save-excursion | |
9140 (verilog-re-search-backward "\\(@\\|\\<begin\\>\\|\\<if\\>\\|\\<case\\>\\)" nil t) | |
9141 (point)) | |
9142 (point))))) | |
9143 (save-excursion | |
9144 (verilog-re-search-backward "@" nil t) | |
9145 (setq sigss (verilog-read-always-signals))) | |
9146 (setq assignment-str (if (verilog-alw-get-uses-delayed sigss) | |
9147 (concat " <= " verilog-assignment-delay) | |
9148 " = ")) | |
9149 (setq sig-list (verilog-signals-not-in (verilog-alw-get-outputs sigss) | |
9150 prereset-sigs)) | |
9151 (setq sig-list (sort sig-list `verilog-signals-sort-compare)) | |
9152 (when sig-list | |
9153 (insert "\n"); | |
9154 (indent-to indent-pt) | |
9155 (insert "// Beginning of autoreset for uninitialized flops\n"); | |
9156 (indent-to indent-pt) | |
9157 (while sig-list | |
9158 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ;; As sig-list has no widths | |
9159 (car sig-list)))) | |
9160 (insert (verilog-sig-name sig) | |
9161 assignment-str | |
9162 (verilog-sig-tieoff sig (not verilog-auto-reset-widths)) | |
9163 ";\n") | |
9164 (indent-to indent-pt) | |
9165 (setq sig-list (cdr sig-list)))) | |
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9166 (insert "// End of automatics"))))) |
79545 | 9167 |
9168 (defun verilog-auto-tieoff () | |
9169 "Expand AUTOTIEOFF statements, as part of \\[verilog-auto]. | |
9170 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output | |
9171 signals to deasserted. | |
9172 | |
9173 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same | |
9174 input/output list as another module, but no internals. Specifically, it | |
9175 finds all outputs in the module, and if that input is not otherwise declared | |
9176 as a register or wire, creates a tieoff. | |
9177 | |
9178 AUTORESET ties signals to deasserted, which is presumed to be zero. | |
9179 Signals that match `verilog-active-low-regexp' will be deasserted by tieing | |
9180 them to a one. | |
9181 | |
9182 An example of making a stub for another module: | |
9183 | |
9184 module FooStub (/*AUTOINST*/); | |
9185 /*AUTOINOUTMODULE(\"Foo\")*/ | |
9186 /*AUTOTIEOFF*/ | |
9187 // verilator lint_off UNUSED | |
9188 wire _unused_ok = &{1'b0, | |
9189 /*AUTOUNUSED*/ | |
9190 1'b0}; | |
9191 // verilator lint_on UNUSED | |
9192 endmodule | |
9193 | |
9194 Typing \\[verilog-auto] will make this into: | |
9195 | |
9196 module FooStub (/*AUTOINST*/...); | |
9197 /*AUTOINOUTMODULE(\"Foo\")*/ | |
9198 // Beginning of autotieoff | |
9199 output [2:0] foo; | |
9200 // End of automatics | |
9201 | |
9202 /*AUTOTIEOFF*/ | |
9203 // Beginning of autotieoff | |
9204 wire [2:0] foo = 3'b0; | |
9205 // End of automatics | |
9206 ... | |
9207 endmodule" | |
9208 (interactive) | |
9209 (save-excursion | |
9210 ;; Find beginning | |
9211 (let* ((indent-pt (current-indentation)) | |
9212 (modi (verilog-modi-current)) | |
9213 (sig-list (verilog-signals-not-in | |
9214 (verilog-modi-get-outputs modi) | |
9215 (append (verilog-modi-get-wires modi) | |
9216 (verilog-modi-get-regs modi) | |
9217 (verilog-modi-get-assigns modi) | |
9218 (verilog-modi-get-consts modi) | |
9219 (verilog-modi-get-gparams modi) | |
9220 (verilog-modi-get-sub-outputs modi) | |
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9221 (verilog-modi-get-sub-inouts modi))))) |
79545 | 9222 (when sig-list |
9223 (forward-line 1) | |
9224 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n") | |
9225 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare)) | |
9226 (verilog-modi-cache-add-wires modi sig-list) ; Before we trash list | |
9227 (while sig-list | |
9228 (let ((sig (car sig-list))) | |
9229 (verilog-insert-one-definition sig "wire" indent-pt) | |
9230 (indent-to (max 48 (+ indent-pt 40))) | |
9231 (insert "= " (verilog-sig-tieoff sig) | |
9232 ";\n") | |
9233 (setq sig-list (cdr sig-list)))) | |
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|
9234 (verilog-insert-indent "// End of automatics\n"))))) |
79545 | 9235 |
9236 (defun verilog-auto-unused () | |
9237 "Expand AUTOUNUSED statements, as part of \\[verilog-auto]. | |
9238 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused | |
9239 input and inout signals. | |
9240 | |
9241 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same | |
9242 input/output list as another module, but no internals. Specifically, it | |
9243 finds all inputs and inouts in the module, and if that input is not otherwise | |
9244 used, adds it to a comma separated list. | |
9245 | |
9246 The comma separated list is intended to be used to create a _unused_ok | |
9247 signal. Using the exact name \"_unused_ok\" for name of the temporary | |
9248 signal is recommended as it will insure maximum forward compatibility, it | |
9249 also makes lint warnings easy to understand; ignore any unused warnings | |
9250 with \"unused\" in the signal name. | |
9251 | |
9252 To reduce simulation time, the _unused_ok signal should be forced to a | |
9253 constant to prevent wiggling. The easiest thing to do is use a | |
9254 reduction-and with 1'b0 as shown. | |
9255 | |
9256 This way all unused signals are in one place, making it convenient to add | |
9257 your tool's specific pragmas around the assignment to disable any unused | |
9258 warnings. | |
9259 | |
9260 You can add signals you do not want included in AUTOUNUSED with | |
9261 `verilog-auto-unused-ignore-regexp'. | |
9262 | |
9263 An example of making a stub for another module: | |
9264 | |
9265 module FooStub (/*AUTOINST*/); | |
9266 /*AUTOINOUTMODULE(\"Foo\")*/ | |
9267 /*AUTOTIEOFF*/ | |
9268 // verilator lint_off UNUSED | |
9269 wire _unused_ok = &{1'b0, | |
9270 /*AUTOUNUSED*/ | |
9271 1'b0}; | |
9272 // verilator lint_on UNUSED | |
9273 endmodule | |
9274 | |
9275 Typing \\[verilog-auto] will make this into: | |
9276 | |
9277 ... | |
9278 // verilator lint_off UNUSED | |
9279 wire _unused_ok = &{1'b0, | |
9280 /*AUTOUNUSED*/ | |
9281 // Beginning of automatics | |
9282 unused_input_a, | |
9283 unused_input_b, | |
9284 unused_input_c, | |
9285 // End of automatics | |
9286 1'b0}; | |
9287 // verilator lint_on UNUSED | |
9288 endmodule" | |
9289 (interactive) | |
9290 (save-excursion | |
9291 ;; Find beginning | |
9292 (let* ((indent-pt (progn (search-backward "/*") (current-column))) | |
9293 (modi (verilog-modi-current)) | |
9294 (sig-list (verilog-signals-not-in | |
9295 (append (verilog-modi-get-inputs modi) | |
9296 (verilog-modi-get-inouts modi)) | |
9297 (append (verilog-modi-get-sub-inputs modi) | |
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9298 (verilog-modi-get-sub-inouts modi))))) |
79545 | 9299 (setq sig-list (verilog-signals-not-matching-regexp |
9300 sig-list verilog-auto-unused-ignore-regexp)) | |
9301 (when sig-list | |
9302 (forward-line 1) | |
9303 (verilog-insert-indent "// Beginning of automatic unused inputs\n") | |
9304 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare)) | |
9305 (while sig-list | |
9306 (let ((sig (car sig-list))) | |
9307 (indent-to indent-pt) | |
9308 (insert (verilog-sig-name sig) ",\n") | |
9309 (setq sig-list (cdr sig-list)))) | |
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diff
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|
9310 (verilog-insert-indent "// End of automatics\n"))))) |
79545 | 9311 |
9312 (defun verilog-enum-ascii (signm elim-regexp) | |
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9313 "Convert an enum name SIGNM to an ascii string for insertion. |
79545 | 9314 Remove user provided prefix ELIM-REGEXP." |
9315 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_")) | |
9316 (let ((case-fold-search t)) | |
9317 ;; All upper becomes all lower for readability | |
9318 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm)))) | |
9319 | |
9320 (defun verilog-auto-ascii-enum () | |
9321 "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto]. | |
9322 Create a register to contain the ASCII decode of a enumerated signal type. | |
9323 This will allow trace viewers to show the ASCII name of states. | |
9324 | |
9325 First, parameters are built into a enumeration using the synopsys enum | |
9326 comment. The comment must be between the keyword and the symbol. | |
79546 | 9327 \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.) |
79545 | 9328 |
9329 Next, registers which that enum applies to are also tagged with the same | |
9330 enum. Synopsys also suggests labeling state vectors, but `verilog-mode' | |
9331 doesn't care. | |
9332 | |
9333 Finally, a AUTOASCIIENUM command is used. | |
9334 | |
9335 The first parameter is the name of the signal to be decoded. | |
9336 | |
9337 The second parameter is the name to store the ASCII code into. For the | |
9338 signal foo, I suggest the name _foo__ascii, where the leading _ indicates | |
9339 a signal that is just for simulation, and the magic characters _ascii | |
9340 tell viewers like Dinotrace to display in ASCII format. | |
9341 | |
9342 The final optional parameter is a string which will be removed from the | |
9343 state names. | |
9344 | |
9345 An example: | |
9346 | |
9347 //== State enumeration | |
9348 parameter [2:0] // synopsys enum state_info | |
9349 SM_IDLE = 3'b000, | |
9350 SM_SEND = 3'b001, | |
9351 SM_WAIT1 = 3'b010; | |
9352 //== State variables | |
9353 reg [2:0] /* synopsys enum state_info */ | |
9354 state_r; /* synopsys state_vector state_r */ | |
9355 reg [2:0] /* synopsys enum state_info */ | |
9356 state_e1; | |
9357 | |
9358 //== ASCII state decoding | |
9359 | |
9360 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/ | |
9361 | |
9362 Typing \\[verilog-auto] will make this into: | |
9363 | |
9364 ... same front matter ... | |
9365 | |
9366 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/ | |
9367 // Beginning of automatic ASCII enum decoding | |
9368 reg [39:0] state_ascii_r; // Decode of state_r | |
9369 always @(state_r) begin | |
9370 case ({state_r}) | |
9371 SM_IDLE: state_ascii_r = \"idle \"; | |
9372 SM_SEND: state_ascii_r = \"send \"; | |
9373 SM_WAIT1: state_ascii_r = \"wait1\"; | |
9374 default: state_ascii_r = \"%Erro\"; | |
9375 endcase | |
9376 end | |
9377 // End of automatics" | |
9378 (save-excursion | |
9379 (let* ((params (verilog-read-auto-params 2 3)) | |
9380 (undecode-name (nth 0 params)) | |
9381 (ascii-name (nth 1 params)) | |
9382 (elim-regexp (nth 2 params)) | |
9383 ;; | |
9384 (indent-pt (current-indentation)) | |
9385 (modi (verilog-modi-current)) | |
9386 ;; | |
9387 (sig-list-consts (append (verilog-modi-get-consts modi) | |
9388 (verilog-modi-get-gparams modi))) | |
9389 (sig-list-all (append (verilog-modi-get-regs modi) | |
9390 (verilog-modi-get-outputs modi) | |
9391 (verilog-modi-get-inouts modi) | |
9392 (verilog-modi-get-inputs modi) | |
9393 (verilog-modi-get-wires modi))) | |
9394 ;; | |
9395 (undecode-sig (or (assoc undecode-name sig-list-all) | |
9396 (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name))) | |
9397 (undecode-enum (or (verilog-sig-enum undecode-sig) | |
9398 (error "%s: Signal %s does not have a enum tag" (verilog-point-text) undecode-name))) | |
9399 ;; | |
9400 (enum-sigs (or (verilog-signals-matching-enum sig-list-consts undecode-enum) | |
9401 (error "%s: No state definitions for %s" (verilog-point-text) undecode-enum))) | |
9402 ;; | |
9403 (enum-chars 0) | |
9404 (ascii-chars 0)) | |
9405 ;; | |
9406 ;; Find number of ascii chars needed | |
9407 (let ((tmp-sigs enum-sigs)) | |
9408 (while tmp-sigs | |
9409 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs)))) | |
9410 ascii-chars (max ascii-chars (length (verilog-enum-ascii | |
9411 (verilog-sig-name (car tmp-sigs)) | |
9412 elim-regexp))) | |
9413 tmp-sigs (cdr tmp-sigs)))) | |
9414 ;; | |
9415 (forward-line 1) | |
9416 (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n") | |
9417 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1)) | |
9418 (concat "Decode of " undecode-name) nil nil)))) | |
9419 (verilog-insert-definition decode-sig-list "reg" indent-pt nil) | |
9420 (verilog-modi-cache-add-regs modi decode-sig-list)) | |
9421 ;; | |
9422 (verilog-insert-indent "always @(" undecode-name ") begin\n") | |
9423 (setq indent-pt (+ indent-pt verilog-indent-level)) | |
9424 (indent-to indent-pt) | |
9425 (insert "case ({" undecode-name "})\n") | |
9426 (setq indent-pt (+ indent-pt verilog-case-indent)) | |
9427 ;; | |
9428 (let ((tmp-sigs enum-sigs) | |
9429 (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n" (1+ (max 8 enum-chars)) | |
9430 ascii-name ascii-chars)) | |
9431 (errname (substring "%Error" 0 (min 6 ascii-chars)))) | |
9432 (while tmp-sigs | |
9433 (verilog-insert-indent | |
9434 (format chrfmt (concat (verilog-sig-name (car tmp-sigs)) ":") | |
9435 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs)) | |
9436 elim-regexp))) | |
9437 (setq tmp-sigs (cdr tmp-sigs))) | |
9438 (verilog-insert-indent (format chrfmt "default:" errname))) | |
9439 ;; | |
9440 (setq indent-pt (- indent-pt verilog-case-indent)) | |
9441 (verilog-insert-indent "endcase\n") | |
9442 (setq indent-pt (- indent-pt verilog-indent-level)) | |
9443 (verilog-insert-indent "end\n" | |
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|
9444 "// End of automatics\n")))) |
79545 | 9445 |
9446 (defun verilog-auto-templated-rel () | |
9447 "Replace Templated relative line numbers with absolute line numbers. | |
9448 Internal use only. This hacks around the line numbers in AUTOINST Templates | |
9449 being different from the final output's line numbering." | |
9450 (let ((templateno 0) (template-line (list 0))) | |
9451 ;; Find line number each template is on | |
9452 (goto-char (point-min)) | |
9453 (while (search-forward "AUTO_TEMPLATE" nil t) | |
9454 (setq templateno (1+ templateno)) | |
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79555
diff
changeset
|
9455 (setq template-line |
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parents:
79555
diff
changeset
|
9456 (cons (count-lines (point-min) (point)) template-line))) |
79545 | 9457 (setq template-line (nreverse template-line)) |
9458 ;; Replace T# L# with absolute line number | |
9459 (goto-char (point-min)) | |
9460 (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t) | |
79691
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parents:
79555
diff
changeset
|
9461 (replace-match |
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parents:
79555
diff
changeset
|
9462 (concat " Templated " |
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parents:
79555
diff
changeset
|
9463 (int-to-string (+ (nth (string-to-number (match-string 1)) |
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79555
diff
changeset
|
9464 template-line) |
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diff
changeset
|
9465 (string-to-number (match-string 2))))) |
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diff
changeset
|
9466 t t)))) |
79545 | 9467 |
9468 | |
9469 ;; | |
9470 ;; Auto top level | |
9471 ;; | |
9472 | |
9473 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing a arg | |
9474 "Expand AUTO statements. | |
9475 Look for any /*AUTO...*/ commands in the code, as used in | |
9476 instantiations or argument headers. Update the list of signals | |
9477 following the /*AUTO...*/ command. | |
9478 | |
9479 Use \\[verilog-delete-auto] to remove the AUTOs. | |
9480 | |
9481 Use \\[verilog-inject-auto] to insert AUTOs for the first time. | |
9482 | |
9483 Use \\[verilog-faq] for a pointer to frequently asked questions. | |
9484 | |
9485 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are | |
9486 called before and after this function, respectively. | |
9487 | |
9488 For example: | |
9489 module (/*AUTOARG*/) | |
9490 /*AUTOINPUT*/ | |
9491 /*AUTOOUTPUT*/ | |
9492 /*AUTOWIRE*/ | |
9493 /*AUTOREG*/ | |
9494 somesub sub #(/*AUTOINSTPARAM*/) (/*AUTOINST*/); | |
9495 | |
9496 You can also update the AUTOs from the shell using: | |
9497 emacs --batch <filenames.v> -f verilog-batch-auto | |
9498 Or fix indentation with: | |
9499 emacs --batch <filenames.v> -f verilog-batch-indent | |
9500 Likewise, you can delete or inject AUTOs with: | |
9501 emacs --batch <filenames.v> -f verilog-batch-delete-auto | |
9502 emacs --batch <filenames.v> -f verilog-batch-inject-auto | |
9503 | |
9504 Using \\[describe-function], see also: | |
9505 `verilog-auto-arg' for AUTOARG module instantiations | |
9506 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding | |
9507 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere | |
9508 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts | |
9509 `verilog-auto-input' for AUTOINPUT making hierarchy inputs | |
9510 `verilog-auto-inst' for AUTOINST instantiation pins | |
9511 `verilog-auto-star' for AUTOINST .* SystemVerilog pins | |
9512 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params | |
9513 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs | |
9514 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs | |
9515 `verilog-auto-reg' for AUTOREG registers | |
9516 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers | |
9517 `verilog-auto-reset' for AUTORESET flop resets | |
9518 `verilog-auto-sense' for AUTOSENSE always sensitivity lists | |
9519 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs | |
9520 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts | |
9521 `verilog-auto-wire' for AUTOWIRE instantiation wires | |
9522 | |
9523 `verilog-read-defines' for reading `define values | |
9524 `verilog-read-includes' for reading `includes | |
9525 | |
9526 If you have bugs with these autos, try contacting the AUTOAUTHOR | |
9527 Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.com." | |
9528 (interactive) | |
9529 (unless noninteractive (message "Updating AUTOs...")) | |
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79555
diff
changeset
|
9530 (if (fboundp 'dinotrace-unannotate-all) |
79545 | 9531 (dinotrace-unannotate-all)) |
9532 (let ((oldbuf (if (not (buffer-modified-p)) | |
9533 (buffer-string))) | |
9534 ;; Before version 20, match-string with font-lock returns a | |
9535 ;; vector that is not equal to the string. IE if on "input" | |
9536 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0))) | |
9537 (fontlocked (when (and (boundp 'font-lock-mode) | |
9538 font-lock-mode) | |
9539 (font-lock-mode nil) | |
9540 t))) | |
9541 (unwind-protect | |
9542 (save-excursion | |
9543 ;; If we're not in verilog-mode, change syntax table so parsing works right | |
9544 (unless (eq major-mode `verilog-mode) (verilog-mode)) | |
9545 ;; Allow user to customize | |
9546 (run-hooks 'verilog-before-auto-hook) | |
9547 ;; Try to save the user from needing to revert-file to reread file local-variables | |
9548 (verilog-auto-reeval-locals) | |
9549 (verilog-read-auto-lisp (point-min) (point-max)) | |
9550 (verilog-getopt-flags) | |
9551 ;; These two may seem obvious to do always, but on large includes it can be way too slow | |
9552 (when verilog-auto-read-includes | |
9553 (verilog-read-includes) | |
9554 (verilog-read-defines nil nil t)) | |
9555 ;; This particular ordering is important | |
9556 ;; INST: Lower modules correct, no internal dependencies, FIRST | |
9557 (verilog-preserve-cache | |
9558 ;; Clear existing autos else we'll be screwed by existing ones | |
9559 (verilog-delete-auto) | |
9560 ;; Injection if appropriate | |
9561 (when inject | |
9562 (verilog-inject-inst) | |
9563 (verilog-inject-sense) | |
9564 (verilog-inject-arg)) | |
9565 ;; | |
9566 (verilog-auto-search-do "/*AUTOINSTPARAM*/" 'verilog-auto-inst-param) | |
9567 (verilog-auto-search-do "/*AUTOINST*/" 'verilog-auto-inst) | |
9568 (verilog-auto-search-do ".*" 'verilog-auto-star) | |
9569 ;; Doesn't matter when done, but combine it with a common changer | |
9570 (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense) | |
9571 (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset) | |
9572 ;; Must be done before autoin/out as creates a reg | |
9573 (verilog-auto-re-search-do "/\\*AUTOASCIIENUM([^)]*)\\*/" 'verilog-auto-ascii-enum) | |
9574 ;; | |
9575 ;; first in/outs from other files | |
9576 (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE([^)]*)\\*/" 'verilog-auto-inout-module) | |
9577 ;; next in/outs which need previous sucked inputs first | |
9578 (verilog-auto-search-do "/*AUTOOUTPUT*/" 'verilog-auto-output) | |
9579 (verilog-auto-search-do "/*AUTOINPUT*/" 'verilog-auto-input) | |
9580 (verilog-auto-search-do "/*AUTOINOUT*/" 'verilog-auto-inout) | |
9581 ;; Then tie off those in/outs | |
9582 (verilog-auto-search-do "/*AUTOTIEOFF*/" 'verilog-auto-tieoff) | |
9583 ;; Wires/regs must be after inputs/outputs | |
9584 (verilog-auto-search-do "/*AUTOWIRE*/" 'verilog-auto-wire) | |
9585 (verilog-auto-search-do "/*AUTOREG*/" 'verilog-auto-reg) | |
9586 (verilog-auto-search-do "/*AUTOREGINPUT*/" 'verilog-auto-reg-input) | |
9587 ;; outputevery needs AUTOOUTPUTs done first | |
9588 (verilog-auto-search-do "/*AUTOOUTPUTEVERY*/" 'verilog-auto-output-every) | |
9589 ;; After we've created all new variables | |
9590 (verilog-auto-search-do "/*AUTOUNUSED*/" 'verilog-auto-unused) | |
9591 ;; Must be after all inputs outputs are generated | |
9592 (verilog-auto-search-do "/*AUTOARG*/" 'verilog-auto-arg) | |
9593 ;; Fix line numbers (comments only) | |
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9594 (verilog-auto-templated-rel)) |
79545 | 9595 ;; |
9596 (run-hooks 'verilog-auto-hook) | |
9597 ;; | |
9598 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick)) | |
9599 ;; | |
9600 ;; If end result is same as when started, clear modified flag | |
9601 (cond ((and oldbuf (equal oldbuf (buffer-string))) | |
9602 (set-buffer-modified-p nil) | |
9603 (unless noninteractive (message "Updating AUTOs...done (no changes)"))) | |
9604 (t (unless noninteractive (message "Updating AUTOs...done"))))) | |
9605 ;; Unwind forms | |
9606 (progn | |
9607 ;; Restore font-lock | |
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9608 (when fontlocked (font-lock-mode t)))))) |
79545 | 9609 |
9610 | |
9611 ;; | |
9612 ;; Skeleton based code insertion | |
9613 ;; | |
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9614 (defvar verilog-template-map |
79546 | 9615 (let ((map (make-sparse-keymap))) |
9616 (define-key map "a" 'verilog-sk-always) | |
9617 (define-key map "b" 'verilog-sk-begin) | |
9618 (define-key map "c" 'verilog-sk-case) | |
9619 (define-key map "f" 'verilog-sk-for) | |
9620 (define-key map "g" 'verilog-sk-generate) | |
9621 (define-key map "h" 'verilog-sk-header) | |
9622 (define-key map "i" 'verilog-sk-initial) | |
9623 (define-key map "j" 'verilog-sk-fork) | |
9624 (define-key map "m" 'verilog-sk-module) | |
9625 (define-key map "p" 'verilog-sk-primitive) | |
9626 (define-key map "r" 'verilog-sk-repeat) | |
9627 (define-key map "s" 'verilog-sk-specify) | |
9628 (define-key map "t" 'verilog-sk-task) | |
9629 (define-key map "w" 'verilog-sk-while) | |
9630 (define-key map "x" 'verilog-sk-casex) | |
9631 (define-key map "z" 'verilog-sk-casez) | |
9632 (define-key map "?" 'verilog-sk-if) | |
9633 (define-key map ":" 'verilog-sk-else-if) | |
9634 (define-key map "/" 'verilog-sk-comment) | |
9635 (define-key map "A" 'verilog-sk-assign) | |
9636 (define-key map "F" 'verilog-sk-function) | |
9637 (define-key map "I" 'verilog-sk-input) | |
9638 (define-key map "O" 'verilog-sk-output) | |
9639 (define-key map "S" 'verilog-sk-state-machine) | |
9640 (define-key map "=" 'verilog-sk-inout) | |
9641 (define-key map "W" 'verilog-sk-wire) | |
9642 (define-key map "R" 'verilog-sk-reg) | |
79550
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* progmodes/verilog-mode.el (verilog-mode-map)
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79549
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9643 (define-key map "D" 'verilog-sk-define-signal) |
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* progmodes/verilog-mode.el (verilog-mode-map)
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9644 map) |
79545 | 9645 "Keymap used in Verilog mode for smart template operations.") |
9646 | |
9647 | |
9648 ;; | |
9649 ;; Place the templates into Verilog Mode. They may be inserted under any key. | |
9650 ;; C-c C-t will be the default. If you use templates a lot, you | |
9651 ;; may want to consider moving the binding to another key in your .emacs | |
9652 ;; file. | |
9653 ;; | |
9654 ;(define-key verilog-mode-map "\C-ct" verilog-template-map) | |
9655 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map) | |
9656 | |
9657 ;;; ---- statement skeletons ------------------------------------------ | |
9658 | |
9659 (define-skeleton verilog-sk-prompt-condition | |
9660 "Prompt for the loop condition." | |
9661 "[condition]: " str ) | |
9662 | |
9663 (define-skeleton verilog-sk-prompt-init | |
9664 "Prompt for the loop init statement." | |
9665 "[initial statement]: " str ) | |
9666 | |
9667 (define-skeleton verilog-sk-prompt-inc | |
9668 "Prompt for the loop increment statement." | |
9669 "[increment statement]: " str ) | |
9670 | |
9671 (define-skeleton verilog-sk-prompt-name | |
9672 "Prompt for the name of something." | |
9673 "[name]: " str) | |
9674 | |
9675 (define-skeleton verilog-sk-prompt-clock | |
9676 "Prompt for the name of something." | |
9677 "name and edge of clock(s): " str) | |
9678 | |
9679 (defvar verilog-sk-reset nil) | |
9680 (defun verilog-sk-prompt-reset () | |
9681 "Prompt for the name of a state machine reset." | |
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9682 (setq verilog-sk-reset (read-string "name of reset: " "rst"))) |
79545 | 9683 |
9684 | |
9685 (define-skeleton verilog-sk-prompt-state-selector | |
9686 "Prompt for the name of a state machine selector." | |
9687 "name of selector (eg {a,b,c,d}): " str ) | |
9688 | |
9689 (define-skeleton verilog-sk-prompt-output | |
9690 "Prompt for the name of something." | |
9691 "output: " str) | |
9692 | |
9693 (define-skeleton verilog-sk-prompt-msb | |
9694 "Prompt for least significant bit specification." | |
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9695 "msb:" str & ?: & '(verilog-sk-prompt-lsb) | -1 ) |
79545 | 9696 |
9697 (define-skeleton verilog-sk-prompt-lsb | |
9698 "Prompt for least significant bit specification." | |
9699 "lsb:" str ) | |
9700 | |
9701 (defvar verilog-sk-p nil) | |
9702 (define-skeleton verilog-sk-prompt-width | |
9703 "Prompt for a width specification." | |
9704 () | |
9705 (progn | |
9706 (setq verilog-sk-p (point)) | |
9707 (verilog-sk-prompt-msb) | |
9708 (if (> (point) verilog-sk-p) "] " " "))) | |
9709 | |
9710 (defun verilog-sk-header () | |
9711 "Insert a descriptive header at the top of the file." | |
9712 (interactive "*") | |
9713 (save-excursion | |
9714 (goto-char (point-min)) | |
9715 (verilog-sk-header-tmpl))) | |
9716 | |
9717 (define-skeleton verilog-sk-header-tmpl | |
9718 "Insert a comment block containing the module title, author, etc." | |
9719 "[Description]: " | |
9720 "// -*- Mode: Verilog -*-" | |
9721 "\n// Filename : " (buffer-name) | |
9722 "\n// Description : " str | |
9723 "\n// Author : " (user-full-name) | |
9724 "\n// Created On : " (current-time-string) | |
9725 "\n// Last Modified By: ." | |
9726 "\n// Last Modified On: ." | |
9727 "\n// Update Count : 0" | |
9728 "\n// Status : Unknown, Use with caution!" | |
9729 "\n") | |
9730 | |
9731 (define-skeleton verilog-sk-module | |
9732 "Insert a module definition." | |
9733 () | |
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9734 > "module " '(verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n |
79545 | 9735 > _ \n |
9736 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil)) | |
9737 | |
9738 (define-skeleton verilog-sk-primitive | |
9739 "Insert a task definition." | |
9740 () | |
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9741 > "primitive " '(verilog-sk-prompt-name) " ( " '(verilog-sk-prompt-output) ("input:" ", " str ) " );"\n |
79545 | 9742 > _ \n |
9743 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil)) | |
9744 | |
9745 (define-skeleton verilog-sk-task | |
9746 "Insert a task definition." | |
9747 () | |
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9748 > "task " '(verilog-sk-prompt-name) & ?; \n |
79545 | 9749 > _ \n |
9750 > "begin" \n | |
9751 > \n | |
9752 > (- verilog-indent-level-behavioral) "end" \n | |
9753 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil)) | |
9754 | |
9755 (define-skeleton verilog-sk-function | |
9756 "Insert a function definition." | |
9757 () | |
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9758 > "function [" '(verilog-sk-prompt-width) | -1 '(verilog-sk-prompt-name) ?; \n |
79545 | 9759 > _ \n |
9760 > "begin" \n | |
9761 > \n | |
9762 > (- verilog-indent-level-behavioral) "end" \n | |
9763 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil)) | |
9764 | |
9765 (define-skeleton verilog-sk-always | |
9766 "Insert always block. Uses the minibuffer to prompt | |
9767 for sensitivity list." | |
9768 () | |
9769 > "always @ ( /*AUTOSENSE*/ ) begin\n" | |
9770 > _ \n | |
9771 > (- verilog-indent-level-behavioral) "end" \n > | |
9772 ) | |
9773 | |
9774 (define-skeleton verilog-sk-initial | |
9775 "Insert an initial block." | |
9776 () | |
9777 > "initial begin\n" | |
9778 > _ \n | |
9779 > (- verilog-indent-level-behavioral) "end" \n > ) | |
9780 | |
9781 (define-skeleton verilog-sk-specify | |
9782 "Insert specify block. " | |
9783 () | |
9784 > "specify\n" | |
9785 > _ \n | |
9786 > (- verilog-indent-level-behavioral) "endspecify" \n > ) | |
9787 | |
9788 (define-skeleton verilog-sk-generate | |
9789 "Insert generate block. " | |
9790 () | |
9791 > "generate\n" | |
9792 > _ \n | |
9793 > (- verilog-indent-level-behavioral) "endgenerate" \n > ) | |
9794 | |
9795 (define-skeleton verilog-sk-begin | |
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|
9796 "Insert begin end block. Uses the minibuffer to prompt for name." |
79545 | 9797 () |
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9798 > "begin" '(verilog-sk-prompt-name) \n |
79545 | 9799 > _ \n |
9800 > (- verilog-indent-level-behavioral) "end" | |
9801 ) | |
9802 | |
9803 (define-skeleton verilog-sk-fork | |
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|
9804 "Insert a fork join block." |
79545 | 9805 () |
9806 > "fork\n" | |
9807 > "begin" \n | |
9808 > _ \n | |
9809 > (- verilog-indent-level-behavioral) "end" \n | |
9810 > "begin" \n | |
9811 > \n | |
9812 > (- verilog-indent-level-behavioral) "end" \n | |
9813 > (- verilog-indent-level-behavioral) "join" \n | |
9814 > ) | |
9815 | |
9816 | |
9817 (define-skeleton verilog-sk-case | |
9818 "Build skeleton case statement, prompting for the selector expression, | |
9819 and the case items." | |
9820 "[selector expression]: " | |
9821 > "case (" str ") " \n | |
9822 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n ) | |
9823 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)) | |
9824 | |
9825 (define-skeleton verilog-sk-casex | |
9826 "Build skeleton casex statement, prompting for the selector expression, | |
9827 and the case items." | |
9828 "[selector expression]: " | |
9829 > "casex (" str ") " \n | |
9830 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n ) | |
9831 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)) | |
9832 | |
9833 (define-skeleton verilog-sk-casez | |
9834 "Build skeleton casez statement, prompting for the selector expression, | |
9835 and the case items." | |
9836 "[selector expression]: " | |
9837 > "casez (" str ") " \n | |
9838 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n ) | |
9839 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)) | |
9840 | |
9841 (define-skeleton verilog-sk-if | |
9842 "Insert a skeleton if statement." | |
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|
9843 > "if (" '(verilog-sk-prompt-condition) & ")" " begin" \n |
79545 | 9844 > _ \n |
9845 > (- verilog-indent-level-behavioral) "end " \n ) | |
9846 | |
9847 (define-skeleton verilog-sk-else-if | |
9848 "Insert a skeleton else if statement." | |
9849 > (verilog-indent-line) "else if (" | |
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changeset
|
9850 (progn (setq verilog-sk-p (point)) nil) '(verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n |
79545 | 9851 > _ \n |
9852 > "end" (progn (electric-verilog-terminate-line) nil)) | |
9853 | |
9854 (define-skeleton verilog-sk-datadef | |
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|
9855 "Common routine to get data definition." |
79545 | 9856 () |
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|
9857 '(verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n) |
79545 | 9858 |
9859 (define-skeleton verilog-sk-input | |
9860 "Insert an input definition." | |
9861 () | |
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9862 > "input [" '(verilog-sk-datadef)) |
79545 | 9863 |
9864 (define-skeleton verilog-sk-output | |
9865 "Insert an output definition." | |
9866 () | |
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9867 > "output [" '(verilog-sk-datadef)) |
79545 | 9868 |
9869 (define-skeleton verilog-sk-inout | |
9870 "Insert an inout definition." | |
9871 () | |
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changeset
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9872 > "inout [" '(verilog-sk-datadef)) |
79545 | 9873 |
9874 (defvar verilog-sk-signal nil) | |
9875 (define-skeleton verilog-sk-def-reg | |
9876 "Insert a reg definition." | |
9877 () | |
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9878 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations) ) |
79545 | 9879 |
9880 (defun verilog-sk-define-signal () | |
9881 "Insert a definition of signal under point at top of module." | |
9882 (interactive "*") | |
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9883 (let* ((sig-re "[a-zA-Z0-9_]*") |
79545 | 9884 (v1 (buffer-substring |
9885 (save-excursion | |
9886 (skip-chars-backward sig-re) | |
9887 (point)) | |
9888 (save-excursion | |
9889 (skip-chars-forward sig-re) | |
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9890 (point))))) |
79545 | 9891 (if (not (member v1 verilog-keywords)) |
9892 (save-excursion | |
9893 (setq verilog-sk-signal v1) | |
9894 (verilog-beg-of-defun) | |
9895 (verilog-end-of-statement) | |
9896 (verilog-forward-syntactic-ws) | |
9897 (verilog-sk-def-reg) | |
9898 (message "signal at point is %s" v1)) | |
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|
9899 (message "object at point (%s) is a keyword" v1)))) |
79545 | 9900 |
9901 (define-skeleton verilog-sk-wire | |
9902 "Insert a wire definition." | |
9903 () | |
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9904 > "wire [" '(verilog-sk-datadef)) |
79545 | 9905 |
9906 (define-skeleton verilog-sk-reg | |
9907 "Insert a reg definition." | |
9908 () | |
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changeset
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9909 > "reg [" '(verilog-sk-datadef)) |
79545 | 9910 |
9911 (define-skeleton verilog-sk-assign | |
9912 "Insert a skeleton assign statement." | |
9913 () | |
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9914 > "assign " '(verilog-sk-prompt-name) " = " _ ";" \n) |
79545 | 9915 |
9916 (define-skeleton verilog-sk-while | |
9917 "Insert a skeleton while loop statement." | |
9918 () | |
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9919 > "while (" '(verilog-sk-prompt-condition) ") begin" \n |
79545 | 9920 > _ \n |
9921 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil)) | |
9922 | |
9923 (define-skeleton verilog-sk-repeat | |
9924 "Insert a skeleton repeat loop statement." | |
9925 () | |
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(verilog-sk-prompt-msb)
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9926 > "repeat (" '(verilog-sk-prompt-condition) ") begin" \n |
79545 | 9927 > _ \n |
9928 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil)) | |
9929 | |
9930 (define-skeleton verilog-sk-for | |
9931 "Insert a skeleton while loop statement." | |
9932 () | |
9933 > "for (" | |
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9934 '(verilog-sk-prompt-init) "; " |
c592638ac955
(verilog-sk-prompt-msb)
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diff
changeset
|
9935 '(verilog-sk-prompt-condition) "; " |
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(verilog-sk-prompt-msb)
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diff
changeset
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9936 '(verilog-sk-prompt-inc) |
79545 | 9937 ") begin" \n |
9938 > _ \n | |
9939 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil)) | |
9940 | |
9941 (define-skeleton verilog-sk-comment | |
9942 "Inserts three comment lines, making a display comment." | |
9943 () | |
9944 > "/*\n" | |
9945 > "* " _ \n | |
9946 > "*/") | |
9947 | |
9948 (define-skeleton verilog-sk-state-machine | |
9949 "Insert a state machine definition." | |
9950 "Name of state variable: " | |
9951 '(setq input "state") | |
9952 > "// State registers for " str | -23 \n | |
9953 '(setq verilog-sk-state str) | |
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9954 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n |
79545 | 9955 '(setq input nil) |
9956 > \n | |
9957 > "// State FF for " verilog-sk-state \n | |
9958 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n | |
9959 > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n | |
9960 > verilog-sk-state " = next_" verilog-sk-state ?; \n | |
9961 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil) | |
9962 > \n | |
9963 > "// Next State Logic for " verilog-sk-state \n | |
9964 > "always @ ( /*AUTOSENSE*/ ) begin\n" | |
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9965 > "case (" '(verilog-sk-prompt-state-selector) ") " \n |
79545 | 9966 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n ) |
9967 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil) | |
9968 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)) | |
9969 | |
9970 | |
9971 ;; | |
9972 ;; Include file loading with mouse/return event | |
9973 ;; | |
9974 ;; idea & first impl.: M. Rouat (eldo-mode.el) | |
9975 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el) | |
9976 | |
9977 (if (featurep 'xemacs) | |
9978 (require 'overlay) | |
9979 (require 'lucid)) ;; what else can we do ?? | |
9980 | |
9981 (defconst verilog-include-file-regexp | |
9982 "^`include\\s-+\"\\([^\n\"]*\\)\"" | |
9983 "Regexp that matches the include file.") | |
9984 | |
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9985 (defvar verilog-mode-mouse-map |
79545 | 9986 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map |
9987 (set-keymap-parent map verilog-mode-map) | |
9988 ;; mouse button bindings | |
9989 (define-key map "\r" 'verilog-load-file-at-point) | |
9990 (if (featurep 'xemacs) | |
9991 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ? | |
9992 (define-key map [mouse-2] 'verilog-load-file-at-mouse)) | |
9993 (if (featurep 'xemacs) | |
9994 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ? | |
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9995 (define-key map [S-mouse-2] 'mouse-yank-at-click)) |
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9996 map) |
79546 | 9997 "Map containing mouse bindings for `verilog-mode'.") |
9998 | |
79545 | 9999 |
10000 (defun verilog-colorize-include-files (beg end old-len) | |
10001 "This function colorizes included files when the mouse passes over them. | |
10002 Clicking on the middle-mouse button loads them in a buffer (as in dired)." | |
10003 (save-excursion | |
10004 (save-match-data | |
10005 (let (end-point) | |
10006 (goto-char end) | |
10007 (setq end-point (verilog-get-end-of-line)) | |
10008 (goto-char beg) | |
10009 (beginning-of-line) ; scan entire line ! | |
10010 ;; delete overlays existing on this line | |
10011 (let ((overlays (overlays-in (point) end-point))) | |
10012 (while overlays | |
10013 (if (and | |
10014 (overlay-get (car overlays) 'detachable) | |
10015 (overlay-get (car overlays) 'verilog-include-file)) | |
10016 (delete-overlay (car overlays))) | |
10017 (setq overlays (cdr overlays)))) ; let | |
10018 ;; make new ones, could reuse deleted one ? | |
10019 (while (search-forward-regexp verilog-include-file-regexp end-point t) | |
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10020 (let (ov) |
79545 | 10021 (goto-char (match-beginning 1)) |
79550
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10022 (setq ov (make-overlay (match-beginning 1) (match-end 1))) |
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10023 (overlay-put ov 'start-closed 't) |
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10024 (overlay-put ov 'end-closed 't) |
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10025 (overlay-put ov 'evaporate 't) |
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* progmodes/verilog-mode.el (verilog-mode-map)
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10026 (overlay-put ov 'verilog-include-file 't) |
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10027 (overlay-put ov 'mouse-face 'highlight) |
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10028 (overlay-put ov 'local-map verilog-mode-mouse-map))))))) |
79545 | 10029 |
10030 | |
10031 (defun verilog-colorize-include-files-buffer () | |
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10032 "Colorize an include file." |
79545 | 10033 (interactive) |
10034 ;; delete overlays | |
10035 (let ((overlays (overlays-in (point-min) (point-max)))) | |
10036 (while overlays | |
10037 (if (and | |
10038 (overlay-get (car overlays) 'detachable) | |
10039 (overlay-get (car overlays) 'verilog-include-file)) | |
10040 (delete-overlay (car overlays))) | |
10041 (setq overlays (cdr overlays)))) ; let | |
10042 ;; remake overlays | |
10043 (verilog-colorize-include-files (point-min) (point-max) nil)) | |
10044 | |
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10045 ;; ffap-at-mouse isn't useful for Verilog mode. It uses library paths. |
79545 | 10046 ;; so define this function to do more or less the same as ffap-at-mouse |
10047 ;; but first resolve filename... | |
10048 (defun verilog-load-file-at-mouse (event) | |
10049 "Load file under button 2 click's EVENT. | |
10050 Files are checked based on `verilog-library-directories'." | |
10051 (interactive "@e") | |
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10052 (save-excursion ;; implement a Verilog specific ffap-at-mouse |
79545 | 10053 (mouse-set-point event) |
10054 (beginning-of-line) | |
10055 (if (looking-at verilog-include-file-regexp) | |
10056 (if (and (car (verilog-library-filenames | |
10057 (match-string 1) (buffer-file-name))) | |
10058 (file-readable-p (car (verilog-library-filenames | |
10059 (match-string 1) (buffer-file-name))))) | |
10060 (find-file (car (verilog-library-filenames | |
10061 (match-string 1) (buffer-file-name)))) | |
10062 (progn | |
10063 (message | |
10064 "File '%s' isn't readable, use shift-mouse2 to paste in this field" | |
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10065 (match-string 1))))))) |
79545 | 10066 |
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10067 ;; ffap isn't useable for Verilog mode. It uses library paths. |
79545 | 10068 ;; so define this function to do more or less the same as ffap |
10069 ;; but first resolve filename... | |
10070 (defun verilog-load-file-at-point () | |
10071 "Load file under point. | |
10072 Files are checked based on `verilog-library-directories'." | |
10073 (interactive) | |
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10074 (save-excursion ;; implement a Verilog specific ffap |
79545 | 10075 (beginning-of-line) |
10076 (if (looking-at verilog-include-file-regexp) | |
10077 (if (and | |
10078 (car (verilog-library-filenames | |
10079 (match-string 1) (buffer-file-name))) | |
10080 (file-readable-p (car (verilog-library-filenames | |
10081 (match-string 1) (buffer-file-name))))) | |
10082 (find-file (car (verilog-library-filenames | |
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10083 (match-string 1) (buffer-file-name)))))))) |
79545 | 10084 |
10085 | |
10086 ;; | |
10087 ;; Bug reporting | |
10088 ;; | |
10089 | |
10090 (defun verilog-faq () | |
10091 "Tell the user their current version, and where to get the FAQ etc." | |
10092 (interactive) | |
10093 (with-output-to-temp-buffer "*verilog-mode help*" | |
10094 (princ (format "You are using verilog-mode %s\n" verilog-mode-version)) | |
10095 (princ "\n") | |
10096 (princ "For new releases, see http://www.verilog.com\n") | |
10097 (princ "\n") | |
10098 (princ "For frequently asked questions, see http://www.veripool.com/verilog-mode-faq.html\n") | |
10099 (princ "\n") | |
10100 (princ "To submit a bug, use M-x verilog-submit-bug-report\n") | |
10101 (princ "\n"))) | |
10102 | |
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10103 (autoload 'reporter-submit-bug-report "reporter") |
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10104 (defvar reporter-prompt-for-summary-p) |
79691
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10105 |
79545 | 10106 (defun verilog-submit-bug-report () |
10107 "Submit via mail a bug report on verilog-mode.el." | |
10108 (interactive) | |
10109 (let ((reporter-prompt-for-summary-p t)) | |
10110 (reporter-submit-bug-report | |
10111 "mac@verilog.com" | |
10112 (concat "verilog-mode v" verilog-mode-version) | |
10113 '( | |
10114 verilog-align-ifelse | |
10115 verilog-auto-endcomments | |
10116 verilog-auto-hook | |
10117 verilog-auto-indent-on-newline | |
10118 verilog-auto-inst-vector | |
10119 verilog-auto-inst-template-numbers | |
10120 verilog-auto-lineup | |
10121 verilog-auto-newline | |
10122 verilog-auto-save-policy | |
10123 verilog-auto-sense-defines-constant | |
10124 verilog-auto-sense-include-inputs | |
10125 verilog-before-auto-hook | |
10126 verilog-case-indent | |
10127 verilog-cexp-indent | |
10128 verilog-compiler | |
10129 verilog-coverage | |
10130 verilog-highlight-translate-off | |
10131 verilog-indent-begin-after-if | |
10132 verilog-indent-declaration-macros | |
10133 verilog-indent-level | |
10134 verilog-indent-level-behavioral | |
10135 verilog-indent-level-declaration | |
10136 verilog-indent-level-directive | |
10137 verilog-indent-level-module | |
10138 verilog-indent-lists | |
10139 verilog-library-flags | |
10140 verilog-library-directories | |
10141 verilog-library-extensions | |
10142 verilog-library-files | |
10143 verilog-linter | |
10144 verilog-minimum-comment-distance | |
10145 verilog-mode-hook | |
10146 verilog-simulator | |
10147 verilog-tab-always-indent | |
10148 verilog-tab-to-comment | |
10149 ) | |
10150 nil nil | |
10151 (concat "Hi Mac, | |
10152 | |
10153 I want to report a bug. I've read the `Bugs' section of `Info' on | |
10154 Emacs, so I know how to make a clear and unambiguous report. To get | |
10155 to that Info section, I typed | |
10156 | |
10157 M-x info RET m " invocation-name " RET m bugs RET | |
10158 | |
10159 Before I go further, I want to say that Verilog mode has changed my life. | |
10160 I save so much time, my files are colored nicely, my co workers respect | |
10161 my coding ability... until now. I'd really appreciate anything you | |
10162 could do to help me out with this minor deficiency in the product. | |
10163 | |
10164 If you have bugs with the AUTO functions, please CC the AUTOAUTHOR Wilson | |
10165 Snyder (wsnyder@wsnyder.org) and/or see http://www.veripool.com. | |
10166 You may also want to look at the Verilog-Mode FAQ, see | |
10167 http://www.veripool.com/verilog-mode-faq.html. | |
10168 | |
10169 To reproduce the bug, start a fresh Emacs via " invocation-name " | |
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|
10170 -no-init-file -no-site-file'. In a new buffer, in Verilog mode, type |
79545 | 10171 the code included below. |
10172 | |
10173 Given those lines, I expected [[Fill in here]] to happen; | |
10174 but instead, [[Fill in here]] happens!. | |
10175 | |
10176 == The code: ==")))) | |
10177 | |
79546 | 10178 (provide 'verilog-mode) |
10179 | |
79545 | 10180 ;; Local Variables: |
10181 ;; checkdoc-permit-comma-termination-flag:t | |
10182 ;; checkdoc-force-docstrings-flag:nil | |
10183 ;; End: | |
10184 | |
79552 | 10185 ;; arch-tag: 87923725-57b3-41b5-9494-be21118c6a6f |
79545 | 10186 ;;; verilog-mode.el ends here |