annotate arm/simple_idct_armv6.S @ 10893:2aafcafbe1f0 libavcodec

Replace cabac checks in inline functions from h264.h with constants. No benchmark because its just replacing variables with litteral constants (so no risk for slowdown outside gcc silliness) and i need sleep.
author michael
date Sat, 16 Jan 2010 05:41:33 +0000
parents db79dcbd5161
children 361a5fcb4393
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1 /*
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2 * Simple IDCT
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3 *
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4 * Copyright (c) 2001 Michael Niedermayer <michaelni@gmx.at>
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5 * Copyright (c) 2007 Mans Rullgard <mans@mansr.com>
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6 *
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7 * This file is part of FFmpeg.
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8 *
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9 * FFmpeg is free software; you can redistribute it and/or
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10 * modify it under the terms of the GNU Lesser General Public
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11 * License as published by the Free Software Foundation; either
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12 * version 2.1 of the License, or (at your option) any later version.
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13 *
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14 * FFmpeg is distributed in the hope that it will be useful,
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15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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17 * Lesser General Public License for more details.
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18 *
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19 * You should have received a copy of the GNU Lesser General Public
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20 * License along with FFmpeg; if not, write to the Free Software
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21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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22 */
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23
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24 #include "asm.S"
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25
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26 #define W1 22725 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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27 #define W2 21407 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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28 #define W3 19266 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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29 #define W4 16383 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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30 #define W5 12873 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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31 #define W6 8867 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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32 #define W7 4520 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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33 #define ROW_SHIFT 11
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34 #define COL_SHIFT 20
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35
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36 #define W13 (W1 | (W3 << 16))
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37 #define W26 (W2 | (W6 << 16))
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38 #define W42 (W4 | (W2 << 16))
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39 #define W42n (-W4&0xffff | (-W2 << 16))
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40 #define W46 (W4 | (W6 << 16))
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41 #define W57 (W5 | (W7 << 16))
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42
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43 .text
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44 .align
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45 w13: .long W13
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46 w26: .long W26
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47 w42: .long W42
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48 w42n: .long W42n
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49 w46: .long W46
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50 w57: .long W57
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51
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52 /*
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53 Compute partial IDCT of single row.
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54 shift = left-shift amount
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55 r0 = source address
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56 r2 = row[2,0] <= 2 cycles
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57 r3 = row[3,1]
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58 ip = w42 <= 2 cycles
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59
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60 Output in registers r4--r11
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61 */
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62 .macro idct_row shift
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63 ldr lr, w46 /* lr = W4 | (W6 << 16) */
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64 mov r1, #(1<<(\shift-1))
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65 smlad r4, r2, ip, r1
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66 smlsd r7, r2, ip, r1
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67 ldr ip, w13 /* ip = W1 | (W3 << 16) */
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68 ldr r10,w57 /* r10 = W5 | (W7 << 16) */
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69 smlad r5, r2, lr, r1
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70 smlsd r6, r2, lr, r1
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71
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72 smuad r8, r3, ip /* r8 = B0 = W1*row[1] + W3*row[3] */
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73 smusdx r11,r3, r10 /* r11 = B3 = W7*row[1] - W5*row[3] */
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74 ldr lr, [r0, #12] /* lr = row[7,5] */
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75 pkhtb r2, ip, r10,asr #16 /* r3 = W7 | (W3 << 16) */
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76 pkhbt r1, ip, r10,lsl #16 /* r1 = W1 | (W5 << 16) */
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77 smusdx r9, r2, r3 /* r9 = -B1 = W7*row[3] - W3*row[1] */
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78 smlad r8, lr, r10,r8 /* B0 += W5*row[5] + W7*row[7] */
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79 smusdx r10,r3, r1 /* r10 = B2 = W5*row[1] - W1*row[3] */
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80
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81 ldr r3, w42n /* r3 = -W4 | (-W2 << 16) */
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82 smlad r10,lr, r2, r10 /* B2 += W7*row[5] + W3*row[7] */
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83 ldr r2, [r0, #4] /* r2 = row[6,4] */
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84 smlsdx r11,lr, ip, r11 /* B3 += W3*row[5] - W1*row[7] */
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85 ldr ip, w46 /* ip = W4 | (W6 << 16) */
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86 smlad r9, lr, r1, r9 /* B1 -= W1*row[5] + W5*row[7] */
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87
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88 smlad r5, r2, r3, r5 /* A1 += -W4*row[4] - W2*row[6] */
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89 smlsd r6, r2, r3, r6 /* A2 += -W4*row[4] + W2*row[6] */
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90 smlad r4, r2, ip, r4 /* A0 += W4*row[4] + W6*row[6] */
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91 smlsd r7, r2, ip, r7 /* A3 += W4*row[4] - W6*row[6] */
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92 .endm
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93
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94 /*
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95 Compute partial IDCT of half row.
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96 shift = left-shift amount
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97 r2 = row[2,0]
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98 r3 = row[3,1]
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99 ip = w42
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100
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101 Output in registers r4--r11
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102 */
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103 .macro idct_row4 shift
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104 ldr lr, w46 /* lr = W4 | (W6 << 16) */
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105 ldr r10,w57 /* r10 = W5 | (W7 << 16) */
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106 mov r1, #(1<<(\shift-1))
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107 smlad r4, r2, ip, r1
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108 smlsd r7, r2, ip, r1
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109 ldr ip, w13 /* ip = W1 | (W3 << 16) */
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110 smlad r5, r2, lr, r1
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111 smlsd r6, r2, lr, r1
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112 smusdx r11,r3, r10 /* r11 = B3 = W7*row[1] - W5*row[3] */
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113 smuad r8, r3, ip /* r8 = B0 = W1*row[1] + W3*row[3] */
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114 pkhtb r2, ip, r10,asr #16 /* r3 = W7 | (W3 << 16) */
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115 pkhbt r1, ip, r10,lsl #16 /* r1 = W1 | (W5 << 16) */
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116 smusdx r9, r2, r3 /* r9 = -B1 = W7*row[3] - W3*row[1] */
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117 smusdx r10,r3, r1 /* r10 = B2 = W5*row[1] - W1*row[3] */
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118 .endm
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119
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120 /*
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121 Compute final part of IDCT single row without shift.
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122 Input in registers r4--r11
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123 Output in registers ip, r4--r6, lr, r8--r10
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124 */
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125 .macro idct_finish
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126 add ip, r4, r8 /* r1 = A0 + B0 */
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127 sub lr, r4, r8 /* r2 = A0 - B0 */
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128 sub r4, r5, r9 /* r2 = A1 + B1 */
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129 add r8, r5, r9 /* r2 = A1 - B1 */
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130 add r5, r6, r10 /* r1 = A2 + B2 */
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131 sub r9, r6, r10 /* r1 = A2 - B2 */
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132 add r6, r7, r11 /* r2 = A3 + B3 */
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133 sub r10,r7, r11 /* r2 = A3 - B3 */
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134 .endm
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135
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136 /*
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137 Compute final part of IDCT single row.
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138 shift = right-shift amount
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139 Input/output in registers r4--r11
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140 */
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141 .macro idct_finish_shift shift
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142 add r3, r4, r8 /* r3 = A0 + B0 */
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143 sub r2, r4, r8 /* r2 = A0 - B0 */
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144 mov r4, r3, asr #\shift
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145 mov r8, r2, asr #\shift
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146
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147 sub r3, r5, r9 /* r3 = A1 + B1 */
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148 add r2, r5, r9 /* r2 = A1 - B1 */
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149 mov r5, r3, asr #\shift
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150 mov r9, r2, asr #\shift
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151
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152 add r3, r6, r10 /* r3 = A2 + B2 */
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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153 sub r2, r6, r10 /* r2 = A2 - B2 */
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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154 mov r6, r3, asr #\shift
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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155 mov r10,r2, asr #\shift
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156
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157 add r3, r7, r11 /* r3 = A3 + B3 */
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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158 sub r2, r7, r11 /* r2 = A3 - B3 */
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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159 mov r7, r3, asr #\shift
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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160 mov r11,r2, asr #\shift
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161 .endm
765df9cbb2b3 ARMv6 SIMD IDCT
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162
765df9cbb2b3 ARMv6 SIMD IDCT
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163 /*
765df9cbb2b3 ARMv6 SIMD IDCT
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164 Compute final part of IDCT single row, saturating results at 8 bits.
765df9cbb2b3 ARMv6 SIMD IDCT
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165 shift = right-shift amount
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166 Input/output in registers r4--r11
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167 */
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168 .macro idct_finish_shift_sat shift
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169 add r3, r4, r8 /* r3 = A0 + B0 */
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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170 sub ip, r4, r8 /* ip = A0 - B0 */
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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171 usat r4, #8, r3, asr #\shift
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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172 usat r8, #8, ip, asr #\shift
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173
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174 sub r3, r5, r9 /* r3 = A1 + B1 */
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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175 add ip, r5, r9 /* ip = A1 - B1 */
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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176 usat r5, #8, r3, asr #\shift
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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177 usat r9, #8, ip, asr #\shift
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178
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179 add r3, r6, r10 /* r3 = A2 + B2 */
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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180 sub ip, r6, r10 /* ip = A2 - B2 */
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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181 usat r6, #8, r3, asr #\shift
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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182 usat r10,#8, ip, asr #\shift
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183
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184 add r3, r7, r11 /* r3 = A3 + B3 */
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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185 sub ip, r7, r11 /* ip = A3 - B3 */
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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186 usat r7, #8, r3, asr #\shift
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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187 usat r11,#8, ip, asr #\shift
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188 .endm
765df9cbb2b3 ARMv6 SIMD IDCT
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189
765df9cbb2b3 ARMv6 SIMD IDCT
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190 /*
765df9cbb2b3 ARMv6 SIMD IDCT
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191 Compute IDCT of single row, storing as column.
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192 r0 = source
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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193 r1 = dest
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194 */
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195 function idct_row_armv6
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196 push {lr}
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7a56dc39adef oops, revert accidental checkin
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197
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198 ldr lr, [r0, #12] /* lr = row[7,5] */
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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199 ldr ip, [r0, #4] /* ip = row[6,4] */
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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200 ldr r3, [r0, #8] /* r3 = row[3,1] */
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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201 ldr r2, [r0] /* r2 = row[2,0] */
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202 orrs lr, lr, ip
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0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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203 cmpeq lr, r3
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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204 cmpeq lr, r2, lsr #16
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c66326f1f635 optimize IDCT of rows with mostly zero coefficients
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205 beq 1f
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206 push {r1}
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207 ldr ip, w42 /* ip = W4 | (W2 << 16) */
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208 cmp lr, #0
7a56dc39adef oops, revert accidental checkin
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209 beq 2f
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765df9cbb2b3 ARMv6 SIMD IDCT
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210
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211 idct_row ROW_SHIFT
7a56dc39adef oops, revert accidental checkin
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212 b 3f
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213
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214 2: idct_row4 ROW_SHIFT
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215
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216 3: pop {r1}
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217 idct_finish_shift ROW_SHIFT
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218
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219 strh r4, [r1]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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220 strh r5, [r1, #(16*2)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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221 strh r6, [r1, #(16*4)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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222 strh r7, [r1, #(16*6)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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223 strh r11,[r1, #(16*1)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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224 strh r10,[r1, #(16*3)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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225 strh r9, [r1, #(16*5)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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226 strh r8, [r1, #(16*7)]
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227
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228 pop {pc}
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229
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230 1: mov r2, r2, lsl #3
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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231 strh r2, [r1]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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232 strh r2, [r1, #(16*2)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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233 strh r2, [r1, #(16*4)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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234 strh r2, [r1, #(16*6)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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235 strh r2, [r1, #(16*1)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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236 strh r2, [r1, #(16*3)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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237 strh r2, [r1, #(16*5)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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238 strh r2, [r1, #(16*7)]
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239 pop {pc}
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240 .endfunc
765df9cbb2b3 ARMv6 SIMD IDCT
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241
765df9cbb2b3 ARMv6 SIMD IDCT
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242 /*
765df9cbb2b3 ARMv6 SIMD IDCT
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243 Compute IDCT of single column, read as row.
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0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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244 r0 = source
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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245 r1 = dest
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246 */
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316762ae96a7 ARM: use new macros for assembler function labels
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247 function idct_col_armv6
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248 push {r1, lr}
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249
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250 ldr r2, [r0] /* r2 = row[2,0] */
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251 ldr ip, w42 /* ip = W4 | (W2 << 16) */
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252 ldr r3, [r0, #8] /* r3 = row[3,1] */
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253 idct_row COL_SHIFT
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254 pop {r1}
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765df9cbb2b3 ARMv6 SIMD IDCT
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255 idct_finish_shift COL_SHIFT
765df9cbb2b3 ARMv6 SIMD IDCT
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diff changeset
256
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0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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257 strh r4, [r1]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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258 strh r5, [r1, #(16*1)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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259 strh r6, [r1, #(16*2)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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260 strh r7, [r1, #(16*3)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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diff changeset
261 strh r11,[r1, #(16*4)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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262 strh r10,[r1, #(16*5)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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diff changeset
263 strh r9, [r1, #(16*6)]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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264 strh r8, [r1, #(16*7)]
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765df9cbb2b3 ARMv6 SIMD IDCT
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265
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266 pop {pc}
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267 .endfunc
765df9cbb2b3 ARMv6 SIMD IDCT
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268
765df9cbb2b3 ARMv6 SIMD IDCT
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269 /*
765df9cbb2b3 ARMv6 SIMD IDCT
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270 Compute IDCT of single column, read as row, store saturated 8-bit.
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271 r0 = source
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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272 r1 = dest
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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273 r2 = line size
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274 */
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275 function idct_col_put_armv6
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276 push {r1, r2, lr}
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765df9cbb2b3 ARMv6 SIMD IDCT
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277
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278 ldr r2, [r0] /* r2 = row[2,0] */
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279 ldr ip, w42 /* ip = W4 | (W2 << 16) */
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280 ldr r3, [r0, #8] /* r3 = row[3,1] */
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765df9cbb2b3 ARMv6 SIMD IDCT
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281 idct_row COL_SHIFT
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282 pop {r1, r2}
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283 idct_finish_shift_sat COL_SHIFT
765df9cbb2b3 ARMv6 SIMD IDCT
mru
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diff changeset
284
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diff changeset
285 strb r4, [r1], r2
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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diff changeset
286 strb r5, [r1], r2
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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diff changeset
287 strb r6, [r1], r2
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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diff changeset
288 strb r7, [r1], r2
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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diff changeset
289 strb r11,[r1], r2
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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diff changeset
290 strb r10,[r1], r2
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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diff changeset
291 strb r9, [r1], r2
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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diff changeset
292 strb r8, [r1], r2
4427
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diff changeset
293
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294 sub r1, r1, r2, lsl #3
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765df9cbb2b3 ARMv6 SIMD IDCT
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295
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296 pop {pc}
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297 .endfunc
765df9cbb2b3 ARMv6 SIMD IDCT
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298
765df9cbb2b3 ARMv6 SIMD IDCT
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299 /*
765df9cbb2b3 ARMv6 SIMD IDCT
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300 Compute IDCT of single column, read as row, add/store saturated 8-bit.
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diff changeset
301 r0 = source
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
302 r1 = dest
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
303 r2 = line size
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
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304 */
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316762ae96a7 ARM: use new macros for assembler function labels
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diff changeset
305 function idct_col_add_armv6
8578
db79dcbd5161 ARM: use push/pop pseudo-instructions in simple_idct_armv6.S
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diff changeset
306 push {r1, r2, lr}
4427
765df9cbb2b3 ARMv6 SIMD IDCT
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parents:
diff changeset
307
8575
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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diff changeset
308 ldr r2, [r0] /* r2 = row[2,0] */
8576
636dc45f4779 ARM: clean up pc-relative references in simple_idct_armv6.S
mru
parents: 8575
diff changeset
309 ldr ip, w42 /* ip = W4 | (W2 << 16) */
8575
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
310 ldr r3, [r0, #8] /* r3 = row[3,1] */
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765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
311 idct_row COL_SHIFT
8578
db79dcbd5161 ARM: use push/pop pseudo-instructions in simple_idct_armv6.S
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diff changeset
312 pop {r1, r2}
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765df9cbb2b3 ARMv6 SIMD IDCT
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313 idct_finish
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
314
8575
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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diff changeset
315 ldrb r3, [r1]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
316 ldrb r7, [r1, r2]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
317 ldrb r11,[r1, r2, lsl #2]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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diff changeset
318 add ip, r3, ip, asr #COL_SHIFT
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
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319 usat ip, #8, ip
8575
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
320 add r4, r7, r4, asr #COL_SHIFT
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
321 strb ip, [r1], r2
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
322 ldrb ip, [r1, r2]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
323 usat r4, #8, r4
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
324 ldrb r11,[r1, r2, lsl #2]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
325 add r5, ip, r5, asr #COL_SHIFT
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
326 usat r5, #8, r5
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
327 strb r4, [r1], r2
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
328 ldrb r3, [r1, r2]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
329 ldrb ip, [r1, r2, lsl #2]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
330 strb r5, [r1], r2
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
331 ldrb r7, [r1, r2]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
332 ldrb r4, [r1, r2, lsl #2]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
333 add r6, r3, r6, asr #COL_SHIFT
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
334 usat r6, #8, r6
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
335 add r10,r7, r10,asr #COL_SHIFT
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
336 usat r10,#8, r10
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
337 add r9, r11,r9, asr #COL_SHIFT
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
338 usat r9, #8, r9
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
339 add r8, ip, r8, asr #COL_SHIFT
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
340 usat r8, #8, r8
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
341 add lr, r4, lr, asr #COL_SHIFT
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765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
342 usat lr, #8, lr
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0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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diff changeset
343 strb r6, [r1], r2
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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diff changeset
344 strb r10,[r1], r2
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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diff changeset
345 strb r9, [r1], r2
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
346 strb r8, [r1], r2
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
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diff changeset
347 strb lr, [r1], r2
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765df9cbb2b3 ARMv6 SIMD IDCT
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parents:
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348
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0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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diff changeset
349 sub r1, r1, r2, lsl #3
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765df9cbb2b3 ARMv6 SIMD IDCT
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350
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db79dcbd5161 ARM: use push/pop pseudo-instructions in simple_idct_armv6.S
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351 pop {pc}
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765df9cbb2b3 ARMv6 SIMD IDCT
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352 .endfunc
765df9cbb2b3 ARMv6 SIMD IDCT
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353
765df9cbb2b3 ARMv6 SIMD IDCT
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parents:
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354 /*
765df9cbb2b3 ARMv6 SIMD IDCT
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355 Compute 8 IDCT row transforms.
765df9cbb2b3 ARMv6 SIMD IDCT
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356 func = IDCT row->col function
765df9cbb2b3 ARMv6 SIMD IDCT
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parents:
diff changeset
357 width = width of columns in bytes
765df9cbb2b3 ARMv6 SIMD IDCT
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358 */
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
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359 .macro idct_rows func width
765df9cbb2b3 ARMv6 SIMD IDCT
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diff changeset
360 bl \func
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0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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parents: 8359
diff changeset
361 add r0, r0, #(16*2)
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
362 add r1, r1, #\width
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
363 bl \func
8575
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
364 add r0, r0, #(16*2)
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
365 add r1, r1, #\width
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
366 bl \func
8575
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
367 add r0, r0, #(16*2)
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
368 add r1, r1, #\width
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
369 bl \func
8575
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
370 sub r0, r0, #(16*5)
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
371 add r1, r1, #\width
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
372 bl \func
8575
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
373 add r0, r0, #(16*2)
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
374 add r1, r1, #\width
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
375 bl \func
8575
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
376 add r0, r0, #(16*2)
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
377 add r1, r1, #\width
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
378 bl \func
8575
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
379 add r0, r0, #(16*2)
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
380 add r1, r1, #\width
4427
765df9cbb2b3 ARMv6 SIMD IDCT
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parents:
diff changeset
381 bl \func
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
382
8575
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
383 sub r0, r0, #(16*7)
4427
765df9cbb2b3 ARMv6 SIMD IDCT
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parents:
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384 .endm
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
385
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
386 /* void ff_simple_idct_armv6(DCTELEM *data); */
8069
316762ae96a7 ARM: use new macros for assembler function labels
mru
parents: 5220
diff changeset
387 function ff_simple_idct_armv6, export=1
8578
db79dcbd5161 ARM: use push/pop pseudo-instructions in simple_idct_armv6.S
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diff changeset
388 push {r4-r11, lr}
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
389 sub sp, sp, #128
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
390
8575
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
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parents: 8359
diff changeset
391 mov r1, sp
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
392 idct_rows idct_row_armv6, 2
8575
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
393 mov r1, r0
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
394 mov r0, sp
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
395 idct_rows idct_col_armv6, 2
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
396
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
397 add sp, sp, #128
8578
db79dcbd5161 ARM: use push/pop pseudo-instructions in simple_idct_armv6.S
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parents: 8577
diff changeset
398 pop {r4-r11, pc}
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
399 .endfunc
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
400
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
401 /* ff_simple_idct_add_armv6(uint8_t *dest, int line_size, DCTELEM *data); */
8069
316762ae96a7 ARM: use new macros for assembler function labels
mru
parents: 5220
diff changeset
402 function ff_simple_idct_add_armv6, export=1
8578
db79dcbd5161 ARM: use push/pop pseudo-instructions in simple_idct_armv6.S
mru
parents: 8577
diff changeset
403 push {r0, r1, r4-r11, lr}
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
404 sub sp, sp, #128
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
405
8575
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
406 mov r0, r2
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
407 mov r1, sp
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
408 idct_rows idct_row_armv6, 2
8575
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
409 mov r0, sp
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
410 ldr r1, [sp, #128]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
411 ldr r2, [sp, #(128+4)]
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
412 idct_rows idct_col_add_armv6, 1
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
413
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
414 add sp, sp, #(128+8)
8578
db79dcbd5161 ARM: use push/pop pseudo-instructions in simple_idct_armv6.S
mru
parents: 8577
diff changeset
415 pop {r4-r11, pc}
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
416 .endfunc
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
417
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
418 /* ff_simple_idct_put_armv6(uint8_t *dest, int line_size, DCTELEM *data); */
8069
316762ae96a7 ARM: use new macros for assembler function labels
mru
parents: 5220
diff changeset
419 function ff_simple_idct_put_armv6, export=1
8578
db79dcbd5161 ARM: use push/pop pseudo-instructions in simple_idct_armv6.S
mru
parents: 8577
diff changeset
420 push {r0, r1, r4-r11, lr}
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
421 sub sp, sp, #128
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
422
8575
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
423 mov r0, r2
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
424 mov r1, sp
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
425 idct_rows idct_row_armv6, 2
8575
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
426 mov r0, sp
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
427 ldr r1, [sp, #128]
0b9dff3a1ce2 ARM: use rX register names in simple_idct_armv6.S
mru
parents: 8359
diff changeset
428 ldr r2, [sp, #(128+4)]
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
429 idct_rows idct_col_put_armv6, 1
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
430
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
431 add sp, sp, #(128+8)
8578
db79dcbd5161 ARM: use push/pop pseudo-instructions in simple_idct_armv6.S
mru
parents: 8577
diff changeset
432 pop {r4-r11, pc}
4427
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
433 .endfunc