annotate armv4l/simple_idct_armv6.S @ 4434:cab2986ffc0b libavcodec

theoretically save one cycle
author mru
date Mon, 29 Jan 2007 22:25:54 +0000
parents 765df9cbb2b3
children c66326f1f635
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1 /*
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2 * Simple IDCT
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3 *
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4 * Copyright (c) 2001 Michael Niedermayer <michaelni@gmx.at>
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5 * Copyright (c) 2007 Mans Rullgard <mru@inprovide.com>
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6 *
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7 * This file is part of FFmpeg.
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8 *
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9 * FFmpeg is free software; you can redistribute it and/or
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10 * modify it under the terms of the GNU Lesser General Public
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11 * License as published by the Free Software Foundation; either
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12 * version 2.1 of the License, or (at your option) any later version.
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13 *
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14 * FFmpeg is distributed in the hope that it will be useful,
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15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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17 * Lesser General Public License for more details.
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18 *
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19 * You should have received a copy of the GNU Lesser General Public
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20 * License along with FFmpeg; if not, write to the Free Software
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21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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22 */
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23
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24 #define W1 22725 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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25 #define W2 21407 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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26 #define W3 19266 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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27 #define W4 16383 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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28 #define W5 12873 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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29 #define W6 8867 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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30 #define W7 4520 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
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31 #define ROW_SHIFT 11
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32 #define COL_SHIFT 20
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33
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34 #define W13 (W1 | (W3 << 16))
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35 #define W26 (W2 | (W6 << 16))
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36 #define W42 (W4 | (W2 << 16))
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37 #define W42n (-W4&0xffff | (-W2 << 16))
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38 #define W46 (W4 | (W6 << 16))
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39 #define W57 (W5 | (W7 << 16))
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40
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41 .text
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42 .align
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43 w13: .long W13
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44 w26: .long W26
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45 w42: .long W42
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46 w42n: .long W42n
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47 w46: .long W46
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48 w57: .long W57
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49
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50 /*
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51 Compute partial IDCT of single row.
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52 shift = left-shift amount
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53 a1 = source address
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54
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55 Output in registers v1--v8
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56 */
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57 .macro idct_row shift
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58 ldr a3, [a1] /* a3 = row[2,0] */
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59 ldr ip, [pc, #(w42-.-8)] /* ip = W4 | (W2 << 16) */
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60 ldr lr, [pc, #(w46-.-8)] /* lr = W4 | (W6 << 16) */
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61 ldr a4, [a1, #8] /* a4 = row[3,1] */
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62 mov a2, #(1<<(\shift-1))
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63 smlad v1, a3, ip, a2
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64 smlsd v4, a3, ip, a2
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65 ldr ip, [pc, #(w13-.-8)] /* ip = W1 | (W3 << 16) */
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66 ldr v7, [pc, #(w57-.-8)] /* v7 = W5 | (W7 << 16) */
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67 smlad v2, a3, lr, a2
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68 smlsd v3, a3, lr, a2
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69
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70 smuad v5, a4, ip /* v5 = B0 = W1*row[1] + W3*row[3] */
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71 smusdx fp, a4, v7 /* fp = B3 = W7*row[1] - W5*row[3] */
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72 ldr lr, [a1, #12] /* lr = row[7,5] */
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73 pkhtb a3, ip, v7, asr #16 /* a4 = W7 | (W3 << 16) */
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74 pkhbt a2, ip, v7, lsl #16 /* a2 = W1 | (W5 << 16) */
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75 smusdx v6, a3, a4 /* v6 = -B1 = W7*row[3] - W3*row[1] */
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76 smlad v5, lr, v7, v5 /* B0 += W5*row[5] + W7*row[7] */
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77 smusdx v7, a4, a2 /* v7 = B2 = W5*row[1] - W1*row[3] */
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78
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79 ldr a4, [pc, #(w42n-.-8)] /* a4 = -W4 | (-W2 << 16) */
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80 smlad v7, lr, a3, v7 /* B2 += W7*row[5] + W3*row[7] */
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81 ldr a3, [a1, #4] /* a3 = row[6,4] */
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82 smlsdx fp, lr, ip, fp /* B3 += W3*row[5] - W1*row[7] */
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83 ldr ip, [pc, #(w46-.-8)] /* ip = W4 | (W6 << 16) */
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84 smlad v6, lr, a2, v6 /* B1 -= W1*row[5] + W5*row[7] */
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85
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86 smlad v2, a3, a4, v2 /* A1 += -W4*row[4] - W2*row[6] */
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87 smlsd v3, a3, a4, v3 /* A2 += -W4*row[4] + W2*row[6] */
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88 smlad v1, a3, ip, v1 /* A0 += W4*row[4] + W6*row[6] */
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89 smlsd v4, a3, ip, v4 /* A3 += W4*row[4] - W6*row[6] */
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90 .endm
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91
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92 /*
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93 Compute final part of IDCT single row without shift.
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94 Input in registers v1--v8
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95 Output in registers ip, v1--v3, lr, v5--v7
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96 */
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97 .macro idct_finish
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98 add ip, v1, v5 /* a2 = A0 + B0 */
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99 sub lr, v1, v5 /* a3 = A0 - B0 */
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100 sub v1, v2, v6 /* a3 = A1 + B1 */
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101 add v5, v2, v6 /* a3 = A1 - B1 */
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102 add v2, v3, v7 /* a2 = A2 + B2 */
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103 sub v6, v3, v7 /* a2 = A2 - B2 */
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104 add v3, v4, fp /* a3 = A3 + B3 */
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105 sub v7, v4, fp /* a3 = A3 - B3 */
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106 .endm
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107
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108 /*
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109 Compute final part of IDCT single row.
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110 shift = right-shift amount
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111 Input/output in registers v1--v8
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112 */
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113 .macro idct_finish_shift shift
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114 add a4, v1, v5 /* a4 = A0 + B0 */
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115 sub a3, v1, v5 /* a3 = A0 - B0 */
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116 mov v1, a4, asr #\shift
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117 mov v5, a3, asr #\shift
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118
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119 sub a4, v2, v6 /* a4 = A1 + B1 */
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120 add a3, v2, v6 /* a3 = A1 - B1 */
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121 mov v2, a4, asr #\shift
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122 mov v6, a3, asr #\shift
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123
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124 add a4, v3, v7 /* a4 = A2 + B2 */
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125 sub a3, v3, v7 /* a3 = A2 - B2 */
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126 mov v3, a4, asr #\shift
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127 mov v7, a3, asr #\shift
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128
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129 add a4, v4, fp /* a4 = A3 + B3 */
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130 sub a3, v4, fp /* a3 = A3 - B3 */
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131 mov v4, a4, asr #\shift
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132 mov fp, a3, asr #\shift
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133 .endm
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134
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135 /*
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136 Compute final part of IDCT single row, saturating results at 8 bits.
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137 shift = right-shift amount
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138 Input/output in registers v1--v8
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139 */
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140 .macro idct_finish_shift_sat shift
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141 add a4, v1, v5 /* a4 = A0 + B0 */
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142 sub ip, v1, v5 /* ip = A0 - B0 */
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143 usat v1, #8, a4, asr #\shift
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144 usat v5, #8, ip, asr #\shift
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145
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146 sub a4, v2, v6 /* a4 = A1 + B1 */
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147 add ip, v2, v6 /* ip = A1 - B1 */
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148 usat v2, #8, a4, asr #\shift
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149 usat v6, #8, ip, asr #\shift
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150
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151 add a4, v3, v7 /* a4 = A2 + B2 */
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152 sub ip, v3, v7 /* ip = A2 - B2 */
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153 usat v3, #8, a4, asr #\shift
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154 usat v7, #8, ip, asr #\shift
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155
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156 add a4, v4, fp /* a4 = A3 + B3 */
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157 sub ip, v4, fp /* ip = A3 - B3 */
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158 usat v4, #8, a4, asr #\shift
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159 usat fp, #8, ip, asr #\shift
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160 .endm
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161
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162 /*
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163 Compute IDCT of single row, storing as column.
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164 a1 = source
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165 a2 = dest
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166 */
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167 .align
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168 .func idct_row_armv6
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169 idct_row_armv6:
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170 stmfd sp!, {a2, lr}
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171
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172 idct_row ROW_SHIFT
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173 ldr a2, [sp], #4
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174 idct_finish_shift ROW_SHIFT
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175
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
176 strh v1, [a2]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
177 strh v2, [a2, #(16*2)]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
178 strh v3, [a2, #(16*4)]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
179 strh v4, [a2, #(16*6)]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
180 strh fp, [a2, #(16*1)]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
181 strh v7, [a2, #(16*3)]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
182 strh v6, [a2, #(16*5)]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
183 strh v5, [a2, #(16*7)]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
184
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
185 ldr pc, [sp], #4
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
186 .endfunc
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
187
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
188 /*
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
189 Compute IDCT of single column, read as row.
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
190 a1 = source
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
191 a2 = dest
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
192 */
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
193 .align
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
194 .func idct_col_armv6
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
195 idct_col_armv6:
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
196 stmfd sp!, {a2, lr}
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
197
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
198 idct_row COL_SHIFT
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
199 ldr a2, [sp], #4
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
200 idct_finish_shift COL_SHIFT
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
201
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
202 strh v1, [a2]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
203 strh v2, [a2, #(16*1)]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
204 strh v3, [a2, #(16*2)]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
205 strh v4, [a2, #(16*3)]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
206 strh fp, [a2, #(16*4)]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
207 strh v7, [a2, #(16*5)]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
208 strh v6, [a2, #(16*6)]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
209 strh v5, [a2, #(16*7)]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
210
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
211 ldr pc, [sp], #4
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
212 .endfunc
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
213
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
214 /*
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
215 Compute IDCT of single column, read as row, store saturated 8-bit.
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
216 a1 = source
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
217 a2 = dest
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
218 a3 = line size
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
219 */
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
220 .align
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
221 .func idct_col_put_armv6
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
222 idct_col_put_armv6:
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
223 stmfd sp!, {a2, a3, lr}
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
224
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
225 idct_row COL_SHIFT
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
226 ldmfd sp!, {a2, a3}
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
227 idct_finish_shift_sat COL_SHIFT
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
228
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
229 strb v1, [a2], a3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
230 strb v2, [a2], a3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
231 strb v3, [a2], a3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
232 strb v4, [a2], a3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
233 strb fp, [a2], a3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
234 strb v7, [a2], a3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
235 strb v6, [a2], a3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
236 strb v5, [a2], a3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
237
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
238 sub a2, a2, a3, lsl #3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
239
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
240 ldr pc, [sp], #4
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
241 .endfunc
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
242
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
243 /*
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
244 Compute IDCT of single column, read as row, add/store saturated 8-bit.
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
245 a1 = source
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
246 a2 = dest
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
247 a3 = line size
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
248 */
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
249 .align
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
250 .func idct_col_add_armv6
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
251 idct_col_add_armv6:
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
252 stmfd sp!, {a2, a3, lr}
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
253
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
254 idct_row COL_SHIFT
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
255 ldmfd sp!, {a2, a3}
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
256 idct_finish
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
257
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
258 ldrb a4, [a2]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
259 ldrb v4, [a2, a3]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
260 ldrb fp, [a2, a3, lsl #2]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
261 add ip, a4, ip, asr #COL_SHIFT
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
262 usat ip, #8, ip
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
263 add v1, v4, v1, asr #COL_SHIFT
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
264 strb ip, [a2], a3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
265 ldrb ip, [a2, a3]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
266 usat v1, #8, v1
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
267 ldrb fp, [a2, a3, lsl #2]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
268 add v2, ip, v2, asr #COL_SHIFT
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
269 usat v2, #8, v2
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
270 strb v1, [a2], a3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
271 ldrb a4, [a2, a3]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
272 ldrb ip, [a2, a3, lsl #2]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
273 strb v2, [a2], a3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
274 ldrb v4, [a2, a3]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
275 ldrb v1, [a2, a3, lsl #2]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
276 add v3, a4, v3, asr #COL_SHIFT
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
277 usat v3, #8, v3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
278 add v7, v4, v7, asr #COL_SHIFT
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
279 usat v7, #8, v7
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
280 add v6, fp, v6, asr #COL_SHIFT
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
281 usat v6, #8, v6
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
282 add v5, ip, v5, asr #COL_SHIFT
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
283 usat v5, #8, v5
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
284 add lr, v1, lr, asr #COL_SHIFT
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
285 usat lr, #8, lr
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
286 strb v3, [a2], a3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
287 strb v7, [a2], a3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
288 strb v6, [a2], a3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
289 strb v5, [a2], a3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
290 strb lr, [a2], a3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
291
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
292 sub a2, a2, a3, lsl #3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
293
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
294 ldr pc, [sp], #4
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
295 .endfunc
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
296
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
297 /*
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
298 Compute 8 IDCT row transforms.
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
299 func = IDCT row->col function
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
300 width = width of columns in bytes
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
301 */
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
302 .macro idct_rows func width
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
303 bl \func
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
304 add a1, a1, #(16*2)
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
305 add a2, a2, #\width
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
306 bl \func
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
307 add a1, a1, #(16*2)
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
308 add a2, a2, #\width
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
309 bl \func
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
310 add a1, a1, #(16*2)
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
311 add a2, a2, #\width
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
312 bl \func
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
313 sub a1, a1, #(16*5)
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
314 add a2, a2, #\width
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
315 bl \func
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
316 add a1, a1, #(16*2)
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
317 add a2, a2, #\width
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
318 bl \func
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
319 add a1, a1, #(16*2)
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
320 add a2, a2, #\width
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
321 bl \func
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
322 add a1, a1, #(16*2)
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
323 add a2, a2, #\width
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
324 bl \func
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
325
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
326 sub a1, a1, #(16*7)
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
327 .endm
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
328
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
329 .align
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
330 .global ff_simple_idct_armv6
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
331 .func ff_simple_idct_armv6
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
332 /* void ff_simple_idct_armv6(DCTELEM *data); */
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
333 ff_simple_idct_armv6:
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
334 stmfd sp!, {v1, v2, v3, v4, v5, v6, v7, fp, lr}
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
335 sub sp, sp, #128
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
336
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
337 mov a2, sp
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
338 idct_rows idct_row_armv6, 2
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
339 mov a2, a1
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
340 mov a1, sp
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
341 idct_rows idct_col_armv6, 2
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
342
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
343 add sp, sp, #128
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
344 ldmfd sp!, {v1, v2, v3, v4, v5, v6, v7, fp, pc}
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
345 .endfunc
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
346
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
347 .align
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
348 .global ff_simple_idct_add_armv6
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
349 .func ff_simple_idct_add_armv6
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
350 /* ff_simple_idct_add_armv6(uint8_t *dest, int line_size, DCTELEM *data); */
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
351 ff_simple_idct_add_armv6:
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
352 stmfd sp!, {a1, a2, v1, v2, v3, v4, v5, v6, v7, fp, lr}
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
353 sub sp, sp, #128
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
354
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
355 mov a1, a3
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
356 mov a2, sp
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
357 idct_rows idct_row_armv6, 2
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
358 mov a1, sp
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
359 ldr a2, [sp, #128]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
360 ldr a3, [sp, #(128+4)]
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
361 idct_rows idct_col_add_armv6, 1
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
362
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
363 add sp, sp, #(128+8)
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
364 ldmfd sp!, {v1, v2, v3, v4, v5, v6, v7, fp, pc}
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
365 .endfunc
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
366
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
367 .align
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
368 .global ff_simple_idct_put_armv6
765df9cbb2b3 ARMv6 SIMD IDCT
mru
parents:
diff changeset
369 .func ff_simple_idct_put_armv6
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370 /* ff_simple_idct_put_armv6(uint8_t *dest, int line_size, DCTELEM *data); */
765df9cbb2b3 ARMv6 SIMD IDCT
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371 ff_simple_idct_put_armv6:
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372 stmfd sp!, {a1, a2, v1, v2, v3, v4, v5, v6, v7, fp, lr}
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373 sub sp, sp, #128
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374
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375 mov a1, a3
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376 mov a2, sp
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377 idct_rows idct_row_armv6, 2
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378 mov a1, sp
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379 ldr a2, [sp, #128]
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380 ldr a3, [sp, #(128+4)]
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381 idct_rows idct_col_put_armv6, 1
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382
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383 add sp, sp, #(128+8)
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384 ldmfd sp!, {v1, v2, v3, v4, v5, v6, v7, fp, pc}
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385 .endfunc